1.

Which of the following is NOT a component Memory Access (DMA) in embedded

of embedded system hardware? systems?
A. Processor A. It allows memory to be expanded
B. Power supply B. It enables the processor to access I/O
C. Device driver devices directly
D. Memory C. It frees up the processor during data
transfer between memory and I/O
2. Which of the following best describes a D. It increases clock speed
watchdog timer in embedded systems?
A. A timer to put the CPU into sleep mode 8. What is the primary function of an
B. A timer used for task scheduling emulator in embedded system
C. A timer to detect and recover from development?
system malfunctions A. Generate random test data
D. A hardware debugger B. Simulate hardware to run software
code
3. An In-Circuit Emulator (ICE) is mainly C. Compile embedded C code
used for: D. Replace real-time clocks
A. Power supply design
B. Circuit layout optimization 9. Which of the following is an example of a
C. Debugging embedded software on real real-time embedded system?
hardware A. Digital watch
D. Writing embedded applications B. Microwave oven
C. Industrial robotic controller
4. The primary function of the clock oscillator D. Handheld video game
in an embedded system is to:
A. Amplify signals 10. The CAN bus is mainly used in which
B. Convert analog signals to digital application area?
C. Provide timing signals to synchronize A. Mobile phones
system operations B. Automotive systems
C. Desktop computing
D. Store program instructions
D. Aerospace navigation
5. Which one of the following is not considered
a structural unit in a typical processor? 11. In cooperative scheduling with time
A. ALU slicing:
B. Registers
C. Oscillator A. Tasks are always preempted after a fixed
D. Control unit time
B. All tasks run to completion without
6. What is one of the most common interruption
solutions to shared data problems? C. Tasks must explicitly yield control
A. Ignoring task priorities D. The scheduler uses hardware interrupts
B. Using a Real-Time Clock
C. Disabling interrupts or using mutexes
12. What is a shared data problem in embedded
D. Increasing memory size systems?
A. When data is shared between users online
B. When two tasks try to access and modify the
7. What is the main advantage of Direct same data simultaneously
C. When a device shares its data wirelessly
D. When memory gets fragmented C. Complexity in managing shared data and
timing
13. Which synchronization mechanism is commonly
used to resolve shared data access issues?
A. DMA
B. Cache Memory
C. Semaphore
D. Timer Interrupt

14. Which of the following is TRUE about

cooperative round-robin scheduling?
A. Tasks are preempted based on priority
B. Each task runs until completion without
yielding
C. Tasks yield control voluntarily
D. It supports real-time constraints by
default

15. One of the following is not a component of and

embedded systems
A. Hardware
B. Application software
C. Processor
D. Real time operating system

16. In preemptive scheduling, the task that

runs is typically the one with:
A. The longest execution time
B. The highest priority
C. The lowest memory usage
D. The shortest deadline

17. The following things are considered when

choosing a processor except:
A. Instruction set
B Clock speed
C. Manufacturing date
D. Maximum bits in an operand

18. Which type of memory is commonly used

for storing firmware in embedded systems?
A. SRAM
B. DRAM
C. ROM / Flash
D. Cache

19. What is the main drawback of preemptive

scheduling?
A. It can only support one task
B. Tasks cannot be prioritized
Draw the components of an embedded system hardware and explain the following
i. Clock Oscillator and clocking unit
ii. Interrupt handler

Input device interfacing

Driver circuits
Power Supply, Reset and Oscillator Circuit

Program Memory

System Application Specific Circuits

Processor Data Memory

Parallel Comm.

Timers Ports

Serial Comm.

Interrupt Controller Ports

Output device interfacing

Driver circuits

Clock Oscillator and clocking unit

A processor needs a clock oscillator circuit. The clock controls the various clocking requirements in the CPU, of
the system timers and CPU machine cycle. Machine cycle:

i. Fetches the codes and data from memory and decoding and executing at the processor
ii. Transferring the result into memory.

The clock controls the time for executing an instruction.

The clock circuit uses either a crystal (external to the processor) or

a ceramic resonator (internally associated with the processor) or
an external oscillator IC attached to the processor.

The ceramic resonator gives the highest stability in frequency with temperature and drift in the circuit the
crystal in association with an appropriate resistance in parallel and a pair of series capacitance at both pins
resonates at the frequency, which is either double or single times the crystal frequency

b. The internal ceramic resonator, if available in a processor saves the use of external crystal and gives
reasonable though not very highly stable frequency.

c. The external IC based clock oscillator has a significantly higher power dissipation compared to the internal
processor resonator, it provides higher driving capabilities which is needed when the various circuits of the
embedded system are concurrently driven. For the processing unit, a highly stable oscillator is required and the
processor clock-out signal provides the clock for synchronizing all the system units.

ii. Interrupt handler

A system may possess a number of devices and the system processor has to control and handle the
requirements of each device by running an appropriate Interrupt Service Routine (ISR) for each.

An interrupt handling mechanism must exist in each system to handle interrupts from various processes in the
system, such as transfer of data from a keyboard or a printer.

There can be a number of interrupt sources and groups of interrupt sources in a processor. An interrupt may be
a hardware signal that indicates the occurrence of an event. An interrupt may also occur through timers,
through an interrupting instruction of the processor program or through an error during processing.

The system may prioritize the sources and service them accordingly .

Certain sources are not maskable and cannot be disabled.

Some are defined to the highest priority during processing The processor’s current program has to divert to a
service routine to complete that task on the occurrence of the interrupt.

There is a programmable unit on chip for the interrupt handling mechanism in a microcontroller

b) Explain the classification of embedded systems

1. Small Scale Embedded System – these systems are designed with a single 8 or 16 bit microcontroller; the
have little software and hardware complexities and involve board level design. They may even be battery
operated. When developing embedded software for these, an editor, assembler, specific to the microcontroller
or processor used are the main programming tools. Usually ‘C’ is used for developing these systems. ‘C’ program
compilation is done into the assembly, and executable codes are then appropriately located in the system
memory. The software has to fit within the available memory.

2. Medium Scale Embedded System: These systems are usually designed with a single or few 16 or 32 bit
microcontrollers or DSP or RISC. These have both hardware and software complexities. For complex software
design there are the following programming tools: RTOS, Source code engineering tool, simulator, debugger and
IDE. Software tools provides solutions to hardware complexities.

3. Sophisticated Embedded System: sophisticated embedded system have enormous hardware and software
complexities and may need scalable processors or configurable processors and programmable logic arrays. They
are used for cutting edge applications that need hardware and software co-design and integration in the final
system; however they are constrained by the processing speeds available in their hardware units. Certain
software functions such as encryption and deciphering algorithms, discreet cosine transformation and inverse
transformation algorithms. TCP/IP protocol stacking and network driver functions are implemented in the
hardware to obtain additional speeds by saving time

Briefly explain five goals of the operating system

Students are required to state and explain any of the unlisted OS goals

i. Facilitating easy sharing of resources as per schedule and allocations.

ii. Facilitating easy implementation

i. Optimally scheduling the processes on one (or more CPUs) by providing and appropriate context
switching mechanism.
ii. Maximizing the systems performance to let different processes (tasks or threads) share the
resource most efficiently with protection and without any security breach
iii. Providing management functions to the processes (tasks and threads), memory, I/O and other
functions for which it is designed
iv. Providing management and organization functions for the devices and files and files-like devices
v. Providing portability of the application on different hardware configurations
vi. Providing interoperability of the application on different networks

b) Is RTOS always necessary in Embedded Systems? List five ways to run and embedded

system without RTOS.

The answer is No. Not always. Software for large number of small scale embedded systems uses no
RTOS and these functions are incorporated into the application software.

The following methods are used

i. Instead of memory allocation and de-allocation function of RTOS, the ‘C’ function, melloc() and
ii. Instead of RTOS function for restricting memory access to various addresses, the use of C++
classes can provided data encapsulation feature and restrict the memory access address
iii. Instead of using RTOS kernel for scheduling tasks, function queues can be used. Coding can
similarly be done and code design is the simplest
iv. Software can handle the inter process (task) communication without recourse to the RTOS.
Software codes synchronize and send data from one function to another by effectively
managing shared memory access.
v. With a user designed device manager and device driver functions I/O management becomes
possible even in the absence of RTOS
vi. Instead of using the RTOS for file management, it can be done by standard ‘C’ functions, fopen(),
fread(), fwrite() and fclose().
 Draw the structural unit of a processor in an embedded system and explain the following;
vii. PFCU
viii. ALU
ix. PC
x. ARS
xi.AOU
xii.MAR
xiii.FRS
xiv. MDR
xv.I-cache and D-cache
xvi. FLPU

Prefetch Control Unit PFCU

It is a unit that controls the fetching of data into the I-cache and D-cache in advance from the memory
units. The instructions and data are delivered when needed to the processor’s execution units. The
processor does not have to fetch data just before executing the instructions.

Arithmetic and Logic Unit

It is a unit used to execute the arithmetic and logical operations according to the current instruction
present at the IR.
Program Counter PC

It generates the instruction cycle to fetch the address from the memory through the MAR. it auto
increments as the instructions are fetched regularly and sequentially. It is called instruction pointer in
80x86 processor.

Application Register Set ARS

It is a set of on-chip registers used during processing the instructions of the application program of the
user. A register window consist of subset of registers with each subset storing static variables of a
software routine. A register file is a file that associates a unit like ALU or FLPU

Atomic Operation Unit AOU

It lets a user or compiler instructions, when broken into number of processor instructions called atomic
operations, finish before an interrupt of a process occurs. This prevents problems from arising out of
shared data between various routines and tasks.

Memory Address Register MAR

It holds address of the byte or word to be fetched from external memories. Processor issues the address
of instructions or data to MAR before it initiates a fetch cycle.

Floating Point Register Set FRS

A register set dedicated for storing floating point numbers in a standard format and used by FLPU for its
data and stack.

Memory Address Register MDR

It holds the byte or word fetched (or to be sent) from (to) external memory or I/O address
Instruction Cache I-Cache

it sequentially stores, like and instruction queue , the instructions in FIFO mode. It lets the processor
execute instructions at great speed while, through PFCU; the processor accesses external system-
memories at relatively much slower speeds.
Data Cache D-cache

It stores the pre-fetched data from the external memory. A data cache generally holds both the key
(Address) and value (Word) together at a location. It also stores write-through data when configured.

Floating Point Processing Unit FLPU

It’s a unit separate from the ALU for floating point processing, which is essential in processing
mathematical functions fast in a microprocessor or DSP.

Explain the serial communication using the, CAN buses between a networked
multiple devices

I2C Bus
When there are number of devices circuits, some for measuring temperatures and some for measuring
pressures in a number of processes in a plant, how can these ICs mutually network through a common
bus? The I2C bus has become the standard bus for these circuits.

The I2C bus has two lines that carry its signals - one line is for the clock and one is for bidirectional data.
There is a protocol for the I2C bus.

Field and its length Explanation

First field of 1bit It is start bit like in UART

Second field of 7bits It called the address field. It defines the slave address, which is being sent
the data frame by the master

Third field of 1 control bit It defines whether a read or write cycle is in progress

Fourth field of 1 control bit It defines whether the present data is an acknowledgement

Fifth field of 8bits It is for IC device data byte

Sixth field of 1 bit It is a NACK bit( Negative Acknowledgement). If active then

acknowledgement after a transfer is not needed from the slave. Else
acknowledgement is expected from slave

Seventh field of 1 bit It’s a stop bit like in UART

I2C is a serial bus for interconnecting ICs. It has a start but and a stop bit. It has seven fields for start, 7-
bit address, defining a read or write, defining byte as acknowledgement byte, data byte, NACK and end
 IC1
Clock
Data

IC3
Clock

Clock
IC2
CAN Bus

The CAN bus is a standard bus for distributed network as in a car. It is mainly used in automative
electronics. It has serial line, which is bidirectional. It receives or sends a bit at an instant by operating at
the maximum rate of 1 Mbps. It employs a twisted pair connection to each node. The pair runs up to a
maximum length of 40m

xvii. CAN serial line is pulled to logic level 1 by a resistor between the line. Logic 1 means idle
stage also known as recessive stage
xviii. Each node has a buffer gate between an imput pin and a CAN serial line. A node gets the
input at any instance fron the line after sensing that instant when the line is pulled down to
0, also called the dominant state.
xix. Each node has a current driver circuit between an output pin and the serial line. A node
sends the output to the line at an instance by pulling the line to 0 by its driver
xx. A node sends the data bit as a data frame. Data frames always start with 1 and always end
with seven 0s. between two data frames, there is a minimum of three field.
xxi. CAN bus line usually interconnects to a CAN controller between line and host at the node. It
basically gives the input and get output between the physical and data link layer and the
host node. The CAN controller has the BIU
xxii. There is an arbitration method called CSMA/AMP (Carrier Sense Multiple Acces with
Arbitration Message Priority. A node stop transmitting on sensing a dominant bit, which
indicates that another node is transmitting.
Field and its length Explanation
First field of 12 bits It is called arbitration field. It contains the packet 11bit destination address and Remote
Transmission Request (RTR) bit. When this bit is one it means this packet is for the
destination address. If the bit is at 0, it means the packet is a request for the data from a
device

Second field of 6 bits Its called control field. The first bit is the identifier extension, the second bit is always 1.
The last 4 bits are code for data length

Third field of 0 to 64 bits It length depends on the data length code in the control field
Fourth field of 16 bit (third if It is a Cyclic Redundancy Check word for the receiver to check errors
data field has no bit present

Fifth field of 2bits First bit is the Acknowledgement slot. The sender sends it as and the receiver send
back 0 in this slot when the receiver detects and error in the reception. When the
sender sense 0 retransmits the data. The second is ACK delimiter bit signaling the end
of the ACK field

Sixth field of 7bits

It is for end of frame specification and has seven 0s