HI-3593

3.3V ARINC 429 Dual Receiver,

August 2013 Single Transmitter with SPI Interface

GENERAL DESCRIPTION PIN CONFIGURATIONS (Top View)

The HI-3593 from Holt Integrated Circuits is a CMOS
integrated circuit for interfacing a Serial Peripheral
Interface (SPI) enabled microcontroller to the ARINC 429

GND
GND
VDD
VDD

CN+
CP+

CN-
CP-
serial bus. The device provides two receivers, each with

V+

V-
-
-
-
-
-
-
-
-
-
-
-
user-programmable label recognition for any combination

44
43
42
41
40
39
38
37
36
35
34
of 256 possible labels, 32 x 32 Receive FIFO, 3 priority-
- 1 33 - AMPA
label quick-access double-buffered registers and analog RIN1A-40 - 2 32 - TXAOUT
line receiver. The independent transmitter has a 32 x 32 RIN1A - 3 31 - AMPB

Transmit FIFO and built-in line driver. The line driver

RIN1B
RIN1B-40
- 4
- 5
HI-3593PCI 30
29
-
-
TXBOUT

RIN2A-40 - 6 HI-3593PCT 28 - TFULL

operates from a single 3.3V supply and includes on-chip RIN2A - 7 27 - TEMPTY
RIN2B - 8
HI-3593PCM 26 - R1FLAG
DC/DC converter to generate the bipolar ARINC 429 RIN2B-40 - 9 25 - R1INT
differential voltage levels needed to directly drive the MR - 10 24 - R2FLAG
ACLK - 11 23 - R2INT
ARINC 429 bus. The status of the transmit and receive
FIFOs and priority-label buffers can be monitored using

12
13
14
15
16
17
18
19
20
21
22
-
-
-
-
-
-
-
-
-
-
-
the programmable external interrupt pins, or by polling the

CS
SI
SCK
SO
GND
MB1-1
MB1-2
MB1-3
MB2-1
MB2-2
MB2-3
HI-3593 Status Registers. Other features include a
programmable option of data or parity in the 32nd bit, and
the ability to switch the bit-signifiance of ARINC 429 labels.
Pins are available with different input resistance and 44 - Pin Plastic 7mm x 7mm
output resistance values which provides flexibility when Chip-Scale Package (QFN)
using external lightning protection circuitry.
The Serial Peripheral Interface minimizes the number of
host interface signals resulting in a small footprint device
that can be interfaced to a wide range of industry-standard

- GND
- GND
- VDD
- VDD

- CN+
- CP+

- CN-
- CP-

- V+
microcontrollers supporting SPI. Alternatively, the SPI

- V-
-
signals may be controlled using just four general purpose

34
35
36
37
38
39
40
41
42
43
44

I/O port pins from a microcontroller or custom FPGA. The

SPI and all control signals are CMOS and TTL compatible
and support 3.3V operation.
-1 33 - AMPA
The HI-3593 applies the ARINC 429 protocol to the RIN1A-40 - 2 32 - TXAOUT
RIN1A - 3 31 - AMPB
receivers and transmitter. ARINC 429 databus timing RIN1B - 4 HI-3593PQI 30 - TXBOUT
comes from a 1 MHz clock input, or an internal counter can RIN1B-40 - 5
HI-3593PQT 29 -
RIN2A-40 - 6 28 - TFULL
derive it from higher clock frequencies having certain fixed RIN2A - 7 HI-3593PQM 27 - TEMPTY
values, possibly the external host processor clock. RIN2B - 8 26 - R1FLAG
RIN2B-40 - 9 25 - R1INT
FEATURES MR - 10
ACLK - 11
24 - R2FLAG
23 - R2INT

· ARINC 429 specification compliant

· Single 3.3V power supply
MB2-3 - 22
MB2-2 - 21
MB2-1 - 20
MB1-3 - 19
MB1-2 - 18
MB1-1 - 17
GND - 16
SO - 15
SCK - 14
SI - 13
CS - 12

· On-chip analog line driver and receiver connect

directly to ARINC 429 bus
· Programmable label recognition for 256 labels
44 - Pin Plastic Quad Flat Pack (PQFP)
· 32 x 32 Receive FIFOs and Priority-Label buffers
· Independent data rates for Transmit and Receive
· 10MHz, four-wire Serial Peripheral Interface (SPI)
· Industrial & extended temperature ranges

HOLT INTEGRATED CIRCUITS

(DS3593 Rev. B) www.holtic.com 08/13
 HI-3593

BLOCK DIAGRAM

VDD (3.3V)

Transmitter ARINC 429

Line Driver
V+
5W
AMPA
ARINC 429 ARINC 429 37.5W
TXAOUT
Transmit Transmit
Data FIFO Formatter TXBOUT
37.5W
AMPB
5W
V-
TFULL
TEMPTY
Transmit Status Transmit Control
MR

V+ V+
SCK
CS SPI 47uF
Interface V-
SI V-
SO 47uF
3.3V DC / DC
Converter CP+
ARINC
Clock CP- 0.47uF
ACLK
Divider
CN+

CN- 2.2uF

Receiver 2

Receiver 1

R2FLAG

Label R2INT
Receive Status Receive Control
RIN2A Filter Flag / R1FLAG
Bit Map Interrupt
RIN2B Memory R1INT
RIN2B-40
RIN2A-40 ARINC 429
Line Receiver
40 KW ARINC 429 ARINC 429
RIN1A Valid word Label Received
40 KW
Checker Filter Data FIFO
RIN1B
(See fig. 3) (32 x 32)
RIN1B-40
RIN1A-40
Priority - Buffer P-L Reg 3
Label Buffer P-L Reg 2 MB2-3
Match (x3)
Buffer P-L Reg 1 MB2-2
MB2-1

MB1-3
MB1-2
MB1-1

GND

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 HI-3593

PIN DESCRIPTIONS
SIGNAL FUNCTION DESCRIPTION INTERNAL PULL UP / DOWN

RIN1A-40 INPUT Alternate ARINC receiver 1 positive input. Requires external 40K ohm resistor
RIN1A INPUT ARINC receiver 1 positive input. Direct connection to ARINC 429 bus
RIN1B INPUT ARINC receiver 1 negative input. Direct connection to ARINC 429 bus
RIN1B-40 INPUT Alternate ARINC receiver 1 negative input. Requires external 40K ohm resistor
RIN2A-40 INPUT Alternate ARINC receiver 2 positive input. Requires external 40K ohm resistor
RIN2A INPUT ARINC receiver 2 positive input. Direct connection to ARINC 429 bus
RIN2B INPUT ARINC receiver 2 negative input. Direct connection to ARINC 429 bus
RIN2B-40 INPUT Alternate ARINC receiver 2 negative input. Requires external 40K ohm resistor
MR INPUT Master Reset. A positive pulse clears Receive and Transmit data FIFOs and flags 50K ohm pull-down
ACLK INPUT Master timing source for the ARINC 429 receiver and transmitter 50K ohm pull-down
CS INPUT Chip Select. Data is shifted into SI and out of SO when CS is low. 50K ohm pull-up
SI INPUT SPI interface serial data input 50K ohm pull-down
SCLK INPUT SPI Clock. Data is shifted into or out of the SPI interface using SCK 50K ohm pull-down
SO OUTPUT SPI interface serial data output
GND POWER Chip 0V supply
MB1-1 OUTPUT Goes high when Receiver 1, Priority-Label Mail Box 1 contains a message
MB1-2 OUTPUT Goes high when Receiver 1, Priority-Label Mail Box 2 contains a message
MB1-3 OUTPUT Goes high when Receiver 1, Priority-Label Mail Box 3 contains a message
MB2-1 OUTPUT Goes high when Receiver 2, Priority-Label Mail Box 1 contains a message
MB2-2 OUTPUT Goes high when Receiver 2, Priority-Label Mail Box 2 contains a message
MB2-3 OUTPUT Goes high when Receiver 2, Priority-Label Mail Box 3 contains a message
R2INT OUTPUT Receiver 2 programmable Interrupt pin
R2FLAG OUTPUT Goes high as defined by Flag / Interrupt Assignment Register
R1INT OUTPUT Receiver 1 programmable Interrupt pin
R1FLAG OUTPUT Goes high as defined by Flag / Interrupt Assignment Register
TEMPTY OUTPUT Goes high when the Transmit FIFO is empty
TFULL OUTPUT Goes high when the Transmit FIFO contains the maximum 32 ARINC 429 words
TXBOUT OUTPUT ARINC line driver negative output. Direct connection to ARINC 429 bus
AMPB OUTPUT Alternate ARINC line driver negative output. Requires external 32.5 ohm resistor
TXAOUT OUTPUT ARINC line driver positive output. Direct connection to ARINC 429 bus
AMPA OUTPUT Alternate ARINC line driver positive output. Requires external 32.5 ohm resistor
V- CONVERTER DC/DC negative voltage output
CN- CONVERTER DC/DC converter fly capacitor for V-
CN+ CONVERTER DC/DC converter fly capacitor for V-
V+ CONVERTER DC/DC positive voltage output
CP- CONVERTER DC/DC converter fly capacitor for V+
CP+ CONVERTER DC/DC converter fly capacitor for V+
VDD POWER Chip 3.3V supply

INSTRUCTIONS
Instruction op codes are used to read, write and configure the HI- SPI Instructions are of a common format. The first bit specifies
3593. When CS goes low, the next 8 clocks at the SCK pin shift an whether the instruction is a write “0” or read “1” transfer. The next
instruction op code into the decoder, starting with the first rising five bits specify the source or destination of the associated data
edge. The op code is fed into the SI pin, most significant bit first. byte(s), and the last two bits are “don’t care”.

For write instructions, the most significant bit of the data word must
immediately follow the instruction op code and is clocked into its
register on the next rising SCK edge. Data word length varies Source /
depending on word type written: 8-bit Control Register writes, 32- Destination
/W
R

bit ARINC label writes or 256-bit writes to a channel’s label-

matching enable/disable memory. X X
MSB 7 6 5 4 3 2 1 0 LSB
For read instructions, the most significant bit of the requested data
word appears at the SO pin after the last op code bit is clocked into SPI INSTRUCTION FORMAT
the decoder, at the next falling SCK edge. As in write instructions,
the data field bit-length varies with read instruction type.

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 HI-3593

TABLE 1. DEFINED INSTRUCTIONS

Op-Code R/W # Data DESCRIPTION

bytes
0x00 W 0 Instruction not implemented. No operation.

0x04 W 0 Software controlled Master Reset

0x08 W 1 Write Transmit Control Register

0x0C W 4 Write ARINC 429 message to Transmit FIFO

0x10 W 1 Write Receiver 1 Control Register

0x14 W 32 Write label values to Receiver 1 label memory. Starting with label 0xFF, consecutively set or reset each
label in descending order. For example, if the first data byte is programmed to 10110010 then labels FF,
FD FC and F9 will be set and FE, FB, FA and F8 will be reset.

0x18 W 3 Write Receiver 1 Priority-Label Match Registers. The data field consists of three eight-bit labels. The first data
byte is written to P-L filter #3, the second to P-L filter #2, and the last byte to filter #1

0x24 W 1 Write Receiver 2 Control Register

0x28 W 32 Write label values to Receiver 2 label memory. Starting with label 0xFF, consecutively set or reset each
label in descending order. For example, if the first data byte is programmed to 10110010 then labels FF,
FD FC and F9 will be set and FE, FB, FA and F8 will be reset.

0x2C W 3 Write Receiver 2 Priority-Label Match Registers. The data field consists of three eight-bit labels. The first
eight bits is written to P-L filter #3, the second to P-L filter #2, and the last byte to filter #1

0x34 W 1 Write Flag / Interrupt Assignment Register

0x38 W 1 Write ACLK Division Register

0x40 W 0 Transmit current contents of Transmit FIFO if Transmit Control Register bit 5 (TMODE) is a “0”

0x44 W 0 Software Reset. Clears the Transmit and Receive FIFOs and the Priority-Label Registers

0x48 W 0 Set all bits in Receiver 1 label memory to a “1”

0x4C W 0 Set all bits in Receiver 2 label memory to a “1”

0x80 R 1 Read Transmit Status Register

0x84 R 1 Read Transmit Control Register

0x90 R 1 Read Receiver 1 Status Register

0x94 R 1 Read Receiver 1 Control Register

0x98 R 32 Read label values from Receiver 1 label memory.

0x9C R 3 Read Receiver 1 Priority-Label Match Registers.

0xA0 R 4 Read one ARINC 429 message from the Receiver 1 FIFO

0xA4 R 3 Read Receiver 1 Priority-Label Register #1, ARINC429 bytes 2,3 & 4 (bits 9 - 32)

0xA8 R 3 Read Receiver 1 Priority-Label Register #2, ARINC429 bytes 2,3 & 4 (bits 9 - 32)

0xAC R 3 Read Receiver 1 Priority-Label Register #3, ARINC429 bytes 2,3 & 4 (bits 9 - 32)

0xB0 R 1 Read Receiver 2 Status Register

0xB4 R 1 Read Receiver 2 Control Register

0xB8 R 32 Read label values from Receiver 2 label memory.

0xBC R 3 Read Receiver 2 Priority-Label Match Registers.

0xC0 R 4 Read one ARINC 429 message from the Receiver 2 FIFO

0xC4 R 3 Read Receiver 2 Priority-Label Register #1, ARINC429 bytes 2,3 & 4 (bits 9 - 32)

0xC8 R 3 Read Receiver 2 Priority-Label Register #2, ARINC429 bytes 2,3 & 4 (bits 9 - 32)

0xCC R 3 Read Receiver 2 Priority-Label Register #3, ARINC429 bytes 2,3 & 4 (bits 9 - 32)

0xD0 R 1 Read Flag / Interrupt Assignment Register

0xD4 R 1 Read ACLK Division Register

0xFF R 0 Instruction not implemented. No operation.

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 HI-3593

REGISTER DESCRIPTIONS

RECEIVE CONTROL REGISTER

O C
LA ITY
PL E
PA N
SD IP

R N
BR

E
SD 0
O
R
9
1

AT
FL

SD
R
(Receiver 1 Write, SPI Op-code 0x10)
(Receiver 1 Read, SPI Op-code 0x94)
(Receiver 2 Write, SPI Op-code 0x24) 7 6 5 4 3 2 1 0
(Receiver 2 Read, SPI Op-code 0xB4) MSB LSB

Bit Name R/W Default Description

7 RFLIP R/W 0 Setting this bit reverses the bit order of the first 8 bits of each ARINC 429 message received.
See figure 1 for details.
6 SD9 R/W 0 If the receiver decoder is enable by setting the SDON bit to a “1”, then ARINC 429 message
bit 9 must match this bit for the message to be accepted.
5 SD10 R/W 0 If the receiver decoder is enable by setting the SDON bit to a “1”, then ARINC 429 message
bit 10 must match this bit for the message to be accepted.
4 SDON R/W 0 If this bit is set, bits 9 and 10 of the received ARINC 429 message must match SD9 and SD10
3 PARITY R/W 0 Received word parity checking is enabled when this bit is set. If “0”, all 32 bits of the received
ARINC 429 word are stored without parity checking.
2 LABREC R/W 0 When “0”, all received messages are stored. If this bit is set, incoming ARINC message label
filtering is enabled. Only messages whose corresponding label filter table entry is set to a “1”
will be stored in the Receive FIFO.
1 PLON R/W 0 Priority-Label Register enable. If PLON = “1” the three Priority-Label Registers are enabled
and received ARINC 429 messages with labels that match one of the three pre-programmed
values will be capured and stored in the corresponding Prioty-Label Mail Boxes. If PLON = “0”
the Priority-Label matching feature is turned off and no words are placed in the mail boxes.
0 RATE R/W 0 If RATE is “0”, ARINC 429 high-speed data rate is selected. RATE = “1” selects low-speed
ARINC 429 data rate (high-speed / 8).
TP EV T
AR EN

TRANSMIT CONTROL REGISTER

D S

Y
O TE
SE DE

X IT
TM P

E
LF
O
LI

AT
IZ

D
TF

R
H

(Write, SPI Op-code 0x08)

(Read, SPI Op-code 0x84)
7 6 5 4 3 2 1 0
MSB LSB

Bit Name R/W Default Description

7 HIZ R/W 0 Setting this bit puts the on-chip line driver outputs to a high-impedance state.
6 TFLIP R/W 0 Setting this bit reverses the bit order of the first 8 bits of each ARINC 429 message transmitted.
See figure 1 for details.
5 TMODE R/W 0 If TMODE is “0”, data in the transmit FIFO is sent to the ARINC 429 bus only upon receipt of an
SPI op-code 0x40, transmit enable, command. If TMODE is a “1”, data is sent as soon as it is
available.
4 SELFTEST R/W 0 Setting SELFTEST causes an internal connection to be made looping-back the transmitter
outputs to both receiver inputs for self-test purposes. When in self-test mode, the HI-3593
ignores data received on the two ARINC 429 receive channels and holds the on-chip line driver
outputs in the NULL state to prevent self-test data being transmitted to other receivers on the
bus.
3 ODDEVEN R/W 0 If the TPARITY bit is set, the transmitter inserts an odd parity bit if ODDEVEN = “0”, or an even if
ODDEVEN = “1”.
2 TPARITY R/W 0 If TPARITY = “0”, no parity bit is inserted and the 32nd transmitted bit is data. When TPARITY is
a “1” a parity bit is substituted for bit 32 according to the ODDEVEN bit value.
1 X R/W 0 Not used.
0 RATE R/W 0 If RATE is “0”, ARINC 429 high-speed data rate is selected. RATE = “1” selects low-speed
ARINC 429 data rate (high-speed / 8).

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 HI-3593

Y
RECEIVE STATUS REGISTER

PT
FF LL
FF ALF
EM
FU
H
2
1
3
PL
PL
FF
PL
X
X
(Receiver 1 Read, SPI Op-code 0x90)
(Receiver 2 Read, SPI Op-code 0xB0) 0 0
7 6 5 4 3 2 1 0
MSB LSB

Bit Name R/W Default Description

7 X R 0 Not used. Always reads “0”
6 X R 0 Not used. Always reads “0”
5 PL3 R 0 This bit is set when a message is received by Priority Label filter #3
4 PL2 R 0 This bit is set when a message is received by Priority Label filter #2
3 PL1 R 0 This bit is set when a message is received by Priority Label filter #1
2 FFFULL R 0 This bit is set when the Receive FIFO contains 32 ARINC 429 messages
1 FFHALF R 0 This bit is set when the Receive FIFO contains at least 16 ARINC 429 messages
0 FFEMPTY R 1 This bit is set when the Receive FIFO is empty

Y
TRANSMIT STATUS REGISTER

PT
TF LL
TF ALF
EM
FU
H
TF
X
X

X
X
X

(Read, SPI Op-code 0x80)

0 0 0 0 0
7 6 5 4 3 2 1 0
MSB LSB

Bit Name R/W Default Description

7 X R 0 Not used. Always reads “0”
6 X R 0 Not used. Always reads “0”
5 X R 0 Not used. Always reads “0”
4 X R 0 Not used. Always reads “0”
3 X R 0 Not used. Always reads “0”
2 TFFULL R 0 This bit is set when the Transmit FIFO contains 32 ARINC 429 messages
1 TFHALF R 0 This bit is set when the Transmit FIFO contains at least 16 ARINC 429 messages
0 TFEMPTY R 1 This bit is set when the Transmit FIFO is empty

ACLK DIVISION REGISTER

D 3]
D 2]
D 1]
X 0]
[
[
[
[
IV
IV
IV
IV
D
X
X
X

(Write, SPI Op-code 0x38)

(Read, SPI Op-code 0xD4) 0 0 0 0
7 6 5 4 3 2 1 0
MSB LSB

Bit Name R/W Default Description

7 X R/W 0 Not used.
6 X R/W 0 Not used.
5 X R/W 0 Not used.
4 - 1 DIV[3:0] R/W 0 The value programmed in DIV[3:0] sets the ACLK division ratio (see table 2)
0 X R/W 0 Not used.

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 HI-3593

]
N [0]
R LAG ]

LA 1]
[0
1
FLAG / INTERRUPT ASSIGNMENT REGISTER

2F [

1F [
2I [1]
2F ]

N ]
1F ]

G
R LAG

R LAG
R T[0

R T[1
R T[0
T
N
N
2I

1I
1I
R
R
(Write, SPI Op-code 0x34)
(Read, SPI Op-code 0xD0)
7 6 5 4 3 2 1 0
MSB LSB

Bit Name R/W Default Description

7-6 R2INT[1:0] R/W 0 The value of R2INT[1:0] defines the function of the R2INT output pin, as follows:
00 R2INT pulses high when a valid message is received and
placed in the Receiver 2 FIFO or any of the Receiver 2 Priority-
Label mail boxes
01 R2INT pulses high when a message is received in Receiver 2
Priority-Label mail box #1
10 R2INT pulses high when a message is received in Receiver 2
Priority-Label mail box #2
11 R2INT pulses high when a message is received in Receiver 2
Priority-Label mail box #3

5-4 R2FLAG[1:0] R/W 0 The value of R2FLAG[1:0] defines the function of the R2FLAG output pin, as follows:
00 R2FLAG goes high when Receiver 2 FIFO is empty
01 R2FLAG goes high when Receiver 2 FIFO contains 32 ARINC
429 words (FIFO is full)
10 R2FLAG goes high when Receiver 2 FIFO contains at least
sixteen ARINC 429 words (FIFO is half-full)
11 R2FLAG goes high when Receiver 2 FIFO contains one or more
words (FIFO is not empty)
3-2 R1INT[1:0] R/W 0 The value of R1INT[1:0] defines the function of the R1INT output pin, as follows:
00 R1INT pulses high when a valid message is received and
placed in the Receiver 1 FIFO or any of the Receiver 1 Priority-
Label mail boxes
01 R1INT pulses high when a message is received in Receiver 1
Priority-Label mail box #1
10 R1INT pulses high when a message is received in Receiver 1
Priority-Label mail box #2
11 R1INT pulses high when a message is received in Receiver 1
Priority-Label mail box #3
1-0 R1FLAG[1:0] R/W 0 The value of R1FLAG[1:0] defines the function of the R1FLAG output pin, as follows:
00 R1FLAG goes high when Receiver 1 FIFO is empty
01 R1FLAG goes high when Receiver 1 FIFO contains 32 ARINC
429 words (FIFO is full)
10 R1FLAG goes high when Receiver 1 FIFO contains at least
sixteen ARINC 429 words (FIFO is half-full)
11 R1FLAG goes high when Receiver 1 FIFO contains one or more
words (FIFO is not empty)

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 HI-3593

ARINC 429 BIT ORDERING

ARINC 429 messages consist of a 32-bit sequence as shown ARINC 429 specifies the MSB of the label as ARINC bit 1.
below. The first eight bits that appear on the ARINC 429 bus are Conversely, the data field MSB is bit 31. So the bit significance of
the label byte. The next twenty three bits comprise a data field the label byte and data fields are opposite.
which presents data in a variety of formats defined in the ARINC
429 specification. The last bit transmitted is an odd parity bit. The HI-3593 may be programmed to “flip” the bit ordering of the
label byte as soon as it is received and immediately prior to
ARINC 429 data is transmitted between the HI-3593 and host transmission. This is accomplished by setting the TFLIP bit to a “1”
microcontroller using the four-wire Serial Peripheral Interface in the Transmit Control Register and/or the RFLIP bit in the
(SPI). A read or write operation consists of a single-byte op-code Receive Control Registers. The RFLIP bit does not control Priority
followed by the data. When writing to the transmit FIFO or reading Label Match Registers.
from the receive FIFOs, the SPI data field is four bytes. Figure 1
shows how the SPI data bytes are mapped to the ARINC 429 Note that when reading ARINC 429 messages from the Priority-
message. Label Registers the label byte is omitted to permit a faster read
time. The label value will match the value loaded into the Match
Register and therefore does not need to be output each time a
message is read.

ARINC 429 Message as received / transmitted on the ARINC 429 serial bus

Y
IT
MSB LABEL LSB LSB DATA MSB

R
SDI
I
SD

PA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

time

ARINC 429 Message as transferred on the SPI bus

Y
IT

SPI Op-Code MSB DATA LSB LSB LABEL MSB

R

SDI
I
SD
PA

0 0 0 0 1 1 0 0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Example 1. Write Transmit FIFO (Op-Code 0x0C) with TFLIP bit = “0”.
Y
IT

SPI Op-Code MSB DATA LSB MSB LABEL LSB

R

SDI
I
SD
PA

1 0 1 0 0 0 0 0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8

Example 2. Read Receiver 1 FIFO (Op-Code 0xA0) with RFLIP bit = “1”.
Y
IT

SPI Op-Code MSB DATA LSB

R

SDI
I
SD
PA

1 1 0 0 1 1 0 0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Example 3. Read Receiver 2 Priority-Label Register #3 (Op-Code 0xCC).

SPI Op-Code MSB LABEL #3 LSB MSB LABEL #2 LSB MSB LABEL #1 LSB

0 0 1 0 1 1 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

Example 4. Write Receiver 2 Priority-Label Match Registers (Op-Code 0x2C)with RFLIP bit = “1” or “0”.

FIGURE 1. ARINC 429 & SPI BIT ORDERING

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 HI-3593

FUNCTIONAL DESCRIPTION
INITIALIZATION ARINC 429 RECEIVERS
The HI-3593 may be initialized using the Master Reset (MR) pin or The HI-3593 has two completely independent ARINC 429 receive
under software control by executing SPI op-code 0x04. MR must channels. Each channel has an on-chip analog line receiver for
be pulsed high for 1 µs to bring the part to its completely reset connection to the ARINC 429 incoming data bus. The ARINC 429
state. MR clears all three FIFOs, all six Priority-Label Mail Boxes, specification requires the following detection levels:
clears the Filter memories and Match registers and sets all other
internal registers to their default state. STATE DIFFERENTIAL VOLTAGE
ONE +6.5 Volts to +13 Volts
Software Reset is performed using SPI op-code 0x44. Software
NULL +2.5 Volts to -2.5 Volts
Reset clears all three FIFOs and all six Priority-Label Mail Boxes,
ZERO -6.5 Volts to -13 Volts
but does not affect the values stored in the filter memories,
Priority-Label Match registers or other writeable registers. The
The HI-3593 guarantees recognition of these levels with a common
Transmit and Receive Status Registers will reflect the state of the
mode voltage with respect to GND less than ±30V for the worst case
post-software reset device.
condition (3.15V supply and 13V signal level).
CLOCK FREQUENCY SELECTION
Design tolerances guarantee detection of the above levels, so the
For correct ARINC 429 data rate transmission and reception, and actual acceptance ranges are slightly larger. If the ARINC signal
bit timing, the HI-3593 transmit and receive logic requires a 1 MHz (including nulls) is outside the differential voltage ranges, the HI-
+/- 1% reference clock source. The clock is input at the ACLK pin 3593 receiver rejects the data.
and must be 1 MHz or any even multiple of 1 MHz up to 30 MHz. If
a clock source greater than 1 MHz is used, then the ACLK Division BIT TIMING
Register must be programmed with the appropriate scaling value.
The ARINC 429 specification defines the following timing toler-
Note that the least significant bit of the ACLK Division Register is ances for received data:
fixed at “0” allowing only even numbers to be programmed.
Similarly the three most significant bits are also fixed at “0” limiting HIGH SPEED LOW SPEED
the maximum value to 0x1E. The ACLK Division Register is
cleared to 0x00 after Master Reset and is unaffected by Software (RATE = “0”) (RATE = “1”)
Reset. When programmed to 0x00, the ACLK division ratio is one, BIT RATE 100K BPS ± 1% 12K -14.5K BPS
and a 1 MHz clock should be applied to ACLK. The ACLK Division PULSE RISE TIME 1.5 ± 0.5 µsec 10 ± 5 µsec
Register is loaded using SPI Op-Code 0x38 and read using Op- PULSE FALL TIME 1.5 ± 0.5 µsec 10 ± 5 µsec
Code 0xD4. PULSE WIDTH 5 µsec ± 5% 34.5 to 41.7 µsec

The following table provides examples of ACLK frequency and

ACLK Division Register values for correct ARINC 429 operation: The HI-3593 accepts signals within these tolerances and rejects
signals outside these tolerances. Receiver logic achieves this as
described below:
ACLK Division Register value External Clock
1. An accurate 1MHz clock source is required to validate the
0x00 1 MHz receive signal timing.
0x02 2 MHz
0x04 4 MHz 2. The receiver uses three separate 10-bit sampling shift reg-
0x06 6 MHz isters for Ones detection, Zeros detection and Null detection.
0x08 8 MHz When the input signal is within the differential voltage range
0x0A 10 MHz for any shift register’s state (One, Zero or Null) sampling
“ “ clocks a “1” into that register. When the receive signal is out-
“ “ side the differential voltage range defined for any shift regis-
0x1C 28 MHz ter, a “0” is clocked. Only one shift register can clock a “1” for
0x1E 30 MHz any given sample. All three registers clock zeros if the differ-
ential input voltage is between defined state voltage bands.
TABLE 2. ACLK DIVISION
Valid data bits require at least three consecutive One or Zero
samples (three “1’s”) in the first five positions of the Ones or
CONFIGURATION Zeros sampling shift register, and at least three consecutive
Null samples (three “1’s”) in the second five positions of the
The Transmit Control Register and Receiver Control Registers are Null sampling shift register within the data bit interval.
used to configure the ARINC 429 transmission channel and two
ARINC 429 receive channels. The registers may be written or read A word gap Null requires at least three consecutive Null sam-
at any time. They are reset to 0x00 following Master Reset and are ples in the first half of the Null sampling shift register and at
unchanged by Software Reset. Refer to the Receiver Control least three consecutive Null samples in the second half of the
Register and Transmit Control Register descriptions for detailed Null sampling shift register. This guarantees the minimum
information. pulse width.

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9
 HI-3593

FUNCTIONAL DESCRIPTION (cont.)

3. To validate the receive data bit rate, each bit must follow its All three Priority-Label Match Registers are loaded using SPI op-
preceding bit by not less than 8 samples and not more than 12 code 0x18 (Receiver 1) or 0x2C (Receiver 2), followed by three label
samples. With exactly 1MHz input clock frequency, the match values. The first byte is the match value for Priority-Label
acceptable data bit rates are: Register #3, the second for Priority-Label Register #2 and the third
for Priority-Label #1. The match values may be checked by reading
the Priority-Label Match Registers using SPI op-code 0x9C
HIGH SPEED LOW SPEED
(Receiver 1) or 0xBC (Receiver 2).
DATA BIT RATE MIN 83K BPS 10.4K BPS
DATA BIT RATE MAX 125K BPS 15.6K BPS When using the Priority-Label feature, all three Priority-Label Match
Registers must be loaded to avoid unintended matches occurring on
un-programmed Priority-Label Match Register random values. If
4. Following the last data bit of a valid reception, the Word less than three Priority-Labels are required for a particular
Gap timer samples the Null shift register every 10 input application, duplicate copies of the same match value should be
clocks (every 80 clocks for low speed). If a Null is present, stored in two (or three) registers.
the Word Gap counter is incremented. A Word Gap count of
3 enables the next reception.
Note that Priority-Label Registers (mail boxes) are only 24 bits long.
RECEIVER PARITY Because the ARINC 429 label byte value is pre-programmed for
each register it is not necessary to store it when words are received.
Receiver parity checking is enabled by setting the Receive Control This allows a shorter and faster access of the data field using SPI
register PARITY bit to a “1”. When enabled, the receiver parity Op-Codes 0xA4, 0xA8 and 0xAC (Receiver 1 Priority-Label
circuit counts Ones received, including the parity bit. If the result is Registers #1, #2 and #3) or 0xC4, 0xC8 and 0xCC (Receiver 2
odd, a "0" is stored in the 32nd bit position, overwriting the received Priority-Label Registers #1, #2 and #3).
parity bit. The “0” indicates a parity bit check pass.
The Receive Status Register bits PL1, PL2 and PL3 indicate when
If receive parity is enabled and a word is received with bad odd Priority-Label data is available in the Priority-Label Registers. Six
parity, the 32nd bit is overwritten with a “1” indicating a parity check status output pins MB1-1 through MB2-3 also indicate when data is
fail. available at each of the six Priority-Label Registers. The R1INT and
R2INT interrupt pins can also be triggered when Priority Labels are
When the Receiver Control Register PARITY bit is a “0”, no parity captured by programming bits 7, 6, 3 and 2 of the Flag / Interrupt
checking takes place and all 32 bits of the received word remain Assignment Register.
unaltered.
LABREC ARINC word SDON ARINC word FIFO
RECEIVED DATA ACCEPTANCE AND STORAGE matches bits 10, 9
Enabled match
The HI-3593 subjects incoming ARINC 429 messages to three label SD10, SD9
different data filter checks before data is accepted. First all words are 0 X 0 X Load FIFO
filtered for matching S/D bits, if enabled. Secondly, the word label
1 No 0 X Ignore data
byte must match one of the three programmed Priority-Label Match
Register Values for the word to be stored in a Priority-Label Register, 1 Yes 0 X Load FIFO
and/or the label memory filter bit corresponding to the label must be 0 X 1 No Ignore data
set to a “1” for the word to be stored in the Receiver FIFO.
0 X 1 Yes Load FIFO

S/D FILTERING 1 Yes 1 No Ignore data

1 No 1 Yes Ignore data
S/D filtering is enabled by setting the Receive Control Register 1 No 1 No Ignore data
SDON bit to a “1”. When enabled, bits 9 and 10 of the incoming
ARINC 429 word are compared with Receive Control Register bits 1 Yes 1 Yes Load FIFO
SD9 and SD10. If they match, the word is accepted for the next TABLE 3. FIFO LOADING CONTROL
phase of filtering. If the bits do not match, the word is discarded and
never stored. The S/D filtering function may be disabled by
programming the SDON bit to a “0”. When disbled, all incoming DIFFERENTIAL COMPARATORS
VDD AMPLIFIERS
words are accepted for subsequent filtering. RINA-40

ONE
PRIORITY LABELS RINA

The three Priority Label Registers store received data if the Priority GND NULL
Label feature is enabled, and the incoming ARINC 429 word’s label VDD
byte matches the value stored in Pririty-Label Match Register #1, # 2
ZERO
or #3. RINB

Priority-Label capture is enabled by setting the Receive Control RINB-40

Register PLON bit to “1”. When PLON = “0” the Priority-Label feature GND
is disabled and no ARINC 429 words are stored in the Priority-Label
Registers. FIGURE 2. ARINC RECEIVER INPUT

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 HI-3593

FUNCTIONAL DESCRIPTION (cont.)

RECEIVED ARINC 429 WORD

TO FILTERS (S/D, LABEL, PRIORITY-LABEL)

DATA
PARITY 32 BIT SHIFT REGISTER
CHECK

WORD
WORD GAP GAP
ONES SHIFT REGISTER TIMER
END EOS
BIT BIT NEW WORD
CLOCK COUNTER
1MHz SEQUENCE AND
CONTROL END OF 32ND
START SEQUENCE BIT
NULL SHIFT REGISTER

1MHz 1MHz

ZEROS SHIFT REGISTER

ERROR ERROR
DETECTION

1MHz

FIGURE 3. RECEIVER BLOCK DIAGRAM

RECEIVE DATA FIFO RETRIEVING DATA

Following S/D Filtering, accepted ARINC 429 words are Each time a valid ARINC 429 word is loaded into the FIFO, the
conditionally stored in the Receive FIFO. If label filtering is Receive FIFO Status Register FFEMPTY, FFHALF and FFFULL bits
disabled, all words are stored. If label filtering is enabled, the are updated. When the FIFO is EMPTY, the FFEMPTY bit is a “1” and
incoming ARINC429 word’s label byte value is checked against its FFHALF and FFFULL are “0”. Once the first received and accepted
corresponding bit in the pre-programmed label look-up table. If the ARINC 429 word is loaded into the FIFO, FFEMPTY goes low. Each
bit is set to a “1” the word is stored in the FIFO. If the bit is a “0” the received ARINC 429 word is retrieved via the SPI interface using SPI
word is not stored in the FIFO. Op-Code 0xA0 (Receiver 1) or 0xC0 (Receiver 2).

LABEL RECOGNITION Up to 32 ARINC 429 words may be held in the Receive FIFO.
FFFULL goes high when the Receive FIFO is full. Failure to unload
The user loads the 256-bit label look-up table to specify which 8-bit the Receive FIFO when full causes additional valid ARINC 429
incoming ARINC labels are stored in the Receive FIFO, and which words to overwrite Receive FIFO location 32.
are not. Setting a “1” in the look-up table enables processing of
received ARINC words containing the corresponding label. A “0” A FIFO half-full flag (FFHALF) is high whenever the Receive FIFO
in the look-up table causes discard of received ARINC words contains 16 or more words. The FFHALF bit provides a useful
containing the label. The 256-bit look-up table is loaded using SPI indicator to the host CPU that a sixteen word data retrieval routine
Op-Codes 0x14 (Receiver 1) and 0x28 (Receiver 2), as described may be performed.
in Table 1. After the look-up table is initialized, the Control Register
bit LABREC must be set to enable label recognition. The FFEMPTY, FFHALF or FFFULL status bits can also be output on
the R1FLAG (Receiver 1) and R2FLAG (Receiver 2) pins. Flag /
All four bytes of the incoming ARINC429 word are stored in the Interrupt Assignment Register bits 5, 4, 1 and 0 select which flag
FIFO. appears. Additionally, a FIFO not empty option may be programmed
for the R1FLAG / R2FLAG pins causing the pin to go high any time at
Table 3. defines the rules for Receive FIFO loading. least one word is available in the FIFO.

READING THE LABEL LOOK-UP TABLE

The contents of the Label Look-up table may be read via the SPI
interface using Op-Code 0x98 (Receiver 1) or 0xB8 (Receiver 2) as
described in Table 1.

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 HI-3593

FUNCTIONAL DESCRIPTION (cont.)

TRANSMITTER SELF TEST

FIFO OPERATION If Transmit Control Register bit SELFTEST is equal ”1”, the
transmitter serial output data is internally looped-back into the
Figure 4 shows a block diagram of the HI-3593 transmitter. The receiver 1. The data will appear inverted (compliment) on receiver 2.
Transmit FIFO is loaded with ARINC 429 words awaiting Data passes unmodified from transmitter to receiver 1. Setting
transmission. SPI op-code 0x0C writes each ARINC 429 word into Transmit Control register bit SELFTEST to ”1” forces TXAOUT and
the FIFO, at the next available FIFO location. If Transmit Status TXBOUT to the Null state to prevent self-test data from appearing on
Register bit TFEMPTY equals “1” (FIFO empty), then up to 32 words the ARINC 429 bus.
(32 bits each) may be loaded. If Transmit Status Register bit
TFEMPTY equals “0” then only the available positions may be SYSTEM OPERATION
loaded. If all 32 positions are full, Transmit Status Register bit
TFFULL is asserted. Further attempts to load the Transmit FIFO are The receivers are independent of the transmitter. Therefore,
ignored until at least one ARINC 429 word is transmitted. control of data exchanges is strictly at the option of the user. The
only restrictions are:
The Transmit FIFO half-full flag (Transmit Status Register bit
TFHALF) equals “0” when the Transmit FIFO contains less than 16 1. The received data will be overwritten if the Receive FIFO is
words. When TFHALF equals “0”, the system microprocessor can full and at least one location is not retrieved before the next
safely initiate a 16-word ARINC 429 write sequence. complete ARINC 429 word is received.
In normal operation (Transmit Control Register bit TPARITY = ”1”), 2. The Transmit FIFO can store 32 words maximum and
the 32nd bit transmitted is an odd parity bit. If Transmit Control ignores attempts to load additional data when full.
Register bit PARITY equals “0”, all 32 bits loaded into the Transmit
FIFO are treated as data and are transmitted.

The Transmit and Receive FIFOs may be cleared using Software

DC/DC CONVERTER
Reset (SPI op-code 0x44). The Transmit FIFO should be cleared
after a self-test before starting normal operation to avoid inadvertent The HI-3593 requires only a single +3.3V power supply. An
transmission of test data. integrated inverting / non-inverting voltage doubler generates the
rail voltages (+/- 6.6V) which then power the line driver to produce
the required +/- 5V ARINC 429 signal levels.
DATA TRANSMISSION
The internal dual-polarity charge pump requires four external
If Transmit Control Register bit TMODE equals “1”, ARINC 429 data capacitors, two for each polarity generated by the doubler. Pins
is transmitted immediately following the CS rising edge of the SPI CP+ and CP- connect the external “fly” capacitor, CFLY, to the
instruction that loaded data into the Transmit FIFO. Writing Transmit positive portion of the doubler, resulting in twice VDD at the V+
Control Register bit TMODE to “0” allows the software to control pin. An output “hold” capacitor, COUT, is placed between V+ and
transmission timing; each time an SPI op-code 0x40 is executed, all GND. COUT should be ten times the size of CFLY. The inverting
loaded Transmit FIFO words are transmitted. If new words are negative portion of the converter works in a similar fashion, with
loaded into the Transmit FIFO before transmission stops, the new CFLY and COUT placed between CN+ / CN- and V- / GND
words will also be output. Once the Transmit FIFO is empty and respectively (see block diagram page 2). Note that low ESR
transmission of the last word is complete, the FIFO can be loaded capacitors rated for at least 10V should be used.
with new data which is held until the next SPI 0x40 instruction is
executed. Once transmission is enabled, the FIFO positions are
incremented with the top register loading into the data transmission
Recommended Values:
shift register. Within 2.5 data clocks the first data bit appears at V+ / GND = 47µF
TXAOUT and TXBOUT. The 31 or 32 bits in the data transmission V- / GND = 47µF
shift register are presented sequentially to the outputs in the ARINC CP+ / CP- = 0.47µF
429 format with the following timing: CN+ / CN- = 2.2µF
HIGH SPEED LOW SPEED LINE DRIVER OPERATION
ARINC DATA BIT TIME 10 Clocks 80 Clocks
DATA BIT TIME 5 Clocks 40 Clocks The line driver in the HI-3593 directly drives the ARINC 429 bus.
NULL BIT TIME 5 Clocks 40 Clocks The two ARINC 429 outputs (TXAOUT and TXBOUT) provide a
WORD GAP TIME 40 Clocks 320 Clocks differential voltage to produce a +10V One, a -10V Zero, and a 0 Volt
Null. Transmit Control Register bit RATE controls both the
A word counter detects when all loaded positions have been transmitter data rate and the slope of the differential output signal.
transmitted and sets the Transmit Status Register TFEMPTY bit No additional hardware is required to control the slope.
high.
Writing Transmit Control Register bit RATE to “0” causes a 100
TRANSMITTER PARITY Kbit/s data rate and a slope of 1.5 µs on the ARINC 429 outputs.
Setting RATE to “1” causes a 12.5 Kbit/s data rate and a slope of
The parity generator counts the Ones in the 31-bit word. The 32nd 10µs. Slope rate is set by an on-chip resistor and capacitor and
bit transmitted will make parity odd. Setting Transmit Control tested to be within ARINC 429 specification requirements.
Register bit TPARITY to “0” bypasses the parity generator, and
allows 32 bits of data to be transmitted.

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 HI-3593

FUNCTIONAL DESCRIPTION (cont.)

LINE DRIVER OUTPUT PINS must be connected through a 40K ohm series resistor in order for
the chip to detect the correct ARINC 429 levels. The typical 10 Volt
The HI-3593 TXAOUT and TXBOUT pins have 37.5 Ohms in series differential signal is translated and input to a window comparator
with each line driver output, and may be directly connected to an and latch. The comparator levels are set so that with the external
ARINC 429 bus. The alternate AMPA and AMPB pins have 5 Ohms 40K ohm resistors, they are just below the standard 6.5 volt mini-
of internal series resistance and require external 32.5 ohm resistors mum ARINC 429 data threshold and just above the standard 2.5
at each pin. AMPA and AMPB are for applications where external volt maximum ARINC 429 null threshold.
series resistance is applied, typically for lightning protection
devices. Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
The line driver outputs TXAOUT, TXBOUT, AMPA and AMPB may line drivers and line receivers.
be programmed to a high impedance state, allowing multiple line
drivers to be connected to a single ARINC 429 bus. To tri-state the MASTER RESET (MR)
outputs bit HIZ in the Transmit Control Register must be
programmed to a “1”. Note that all other functions of the HI-3593 Application of a Master Reset from the MR pin or execution
continue to operate as usual even though the outputs are tri-stated. of Opcode (0x04) causes immediate termination of data
transmission and reception and clears the receive control
LINE RECEIVER INPUT PINS registers, transmit control register, ACLK and Flag/Interrupt
Registers to the default states. All FIFOs will be emptied and
The HI-3593 has two sets of Line Receiver input pins for each of
status flags are set to the default state (TFULL is reset,
the two receivers, RINxA/B and RINxA/B-40. Only one pair may
be used to connect to the ARINC 429 bus. The unused pair must TEMPTY is set). NOTE: Reading an EMPTY FIFO may
be left floating. The RINxA/B pins may be connected directly to the result in invalid data.
ARINC 429 bus. The RINxA/B-40 pins require external 40K ohm
resistors in series with each ARINC input. These do not affect the SOFTWARE RESET
ARINC receiver thresholds. By keeping excessive voltage outside
the device, this option is helpful in applications where lightning pro- Opcode (0x044) clears the transmit and receive FIFOs and
tection is required. the Priority-Label Registers only. All other registers are
unaffected by Software Reset.
When using the RINxA/B-40 pins, each side of the ARINC 429 bus

TPARITY

DATA AND TXAOUT

32 BIT PARALLEL PARITY NULL TIMER LINE DRIVER
BIT CLOCK GENERATOR TXBOUT
LOAD SHIFT REGISTER SEQUENCER

HIZ

BIT
AND
WORD CLOCK WORD GAP
COUNTER

START
SEQUENCE
32 x 32 FIFO ADDRESS
TFFULL
WORD COUNTER
AND TFHALF
LOAD FIFO CONTROL
TFEMPTY
INCREMENT
WORD COUNT

FIFO
LOADING
SEQUENCER
SCK SPI COMMANDS
CS SPI COMMANDS
SPI INTERFACE
SI
DATA
SO CLOCK DATA CLOCK
ACLK
DIV[3:0] DIVIDER

FIGURE 4. TRANSMITTER BLOCK DIAGRAM

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 HI-3593

SERIAL PERIPHERAL INTERFACE

SERIAL PERIPHERAL INTERFACE (SPI) BASICS The SPI protocol transfers serial data as 8-bit bytes. Once
CS chip select is asserted, the next 8 rising edges on SCK
The HI-3593 uses an SPI synchronous serial interface for latch input data into the master and slave devices, starting
host access to internal registers and data FIFOs. Host with each byte’s most-significant bit. The HI-3593 SPI can
serial communication is enabled through the Chip Select be clocked at 10 MHz.
(CS) pin, and is accessed via a three-wire interface
consisting of Serial Data Input (SI) from the host, Serial Multiple bytes may be transferred when the host holds CS
Data Output (SO) to the host and Serial Clock (SCK). All low after the first byte transferred, and continues to clock
read / write cycles are completely self-timed. SCK in multiples of 8 clocks. A rising edge on CS chip
select terminates the serial transfer and reinitializes the
The SPI (Serial Peripheral Interface) protocol specifies HI-3593 SPI for the next transfer. If CS goes high before a
master and slave operation; the HI-3593 operates as an full byte is clocked by SCK, the incomplete byte clocked
SPI slave. into the device SI pin is discarded.

The SPI protocol defines two parameters, CPOL (clock In the general case, both master and slave simultaneously
polarity) and CPHA (clock phase). The possible CPOL- send and receive serial data (full duplex), per Figure 5
CPHA combinations define four possible "SPI Modes". below. However the HI-3593 operates half duplex,
Without describing details of the SPI modes, the HI-3593 maintaining high impedance on the SO output, except
operates in mode 0 where input data for each device ( when actually transmitting serial data. When the HI-3593
master and slave) is clocked on the rising edge of SCK, is sending data on SO during read operations, activity on
and output data for each device changes on the falling its SI input is ignored. Figures 6 and 7 show actual
edge (CPHA = 0, CPOL = 0). Be sure to set the host SPI behavior for the HI-3593 SO output.
logic for mode 0.

As seen in Figure 5, SPI Mode 0 holds SCK in the low state

when idle.

SCK (SPI Mode 0) 0 1 2 3 4 5 6 7

SI MSB LSB

High Z High Z
SO MSB LSB

CS

FIGURE 5. Generalized Single-Byte Transfer Using SPI Protocol Modes 0

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 HI-3593

HOST SERIAL PERIPHERAL INTERFACE, cont.

HI-3593 SPI COMMANDS
Multiple byte read or write cycles may be performed by
For the HI-3593, each SPI read or write operation begins transferring more than one byte before CS is negated.
with an 8-bit command byte transferred from the host to the Table 1. defines the required number of bytes for each
device after assertion of CS. Since HI-3593 command byte instruction.
reception is half-duplex, the host discards the dummy byte
it receives while serially transmitting the command byte. Note: SPI Instruction op-codes not shown in Table 1 are
“reserved” and must not be used. Further, these op-codes
Figures 6 and 7 show read and write timing as it appears will not provide meaningful data in response to read
for a single-byte and dual-byte register operation. The commands.
command byte is immediately followed by a data byte
comprising the 8-bit data word read or written. For a single Two instruction bytes cannot be “chained”; CS must
register read or write, CS is negated after the data byte is be negated after the command, then reasserted for the
transferred. following Read or Write command.

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
SCK

MSB LSB

SI

Op-Code Byte MSB LSB MSB

High Z High Z
SO

Data Byte

CS

Host may continue to assert CS

here to read sequential word(s)
when allowed by the instruction.
Each word needs 8 SCK clocks.
FIGURE 6. Single-Byte Read From a Register

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
SCK
SPI Mode 0
MSB LSB MSB LSB MSB LSB

SI

Op-Code Byte Data Byte 0 Data Byte 1

High Z
SO

CS

Host may continue to assert CS

here to write sequential byte(s)
when allowed by the SPI instruction.
Each byte needs 8 SCK clocks.

FIGURE 7. 2-Byte Write example

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 HI-3593

TIMING DIAGRAMS

SERIAL INPUT TIMING DIAGRAM

t CPH
t CYC
CS
tCHH
t CES t SCKF t CEH
SCK
t DS t DH t SCKR
SI MSB LSB

SERIAL OUTPUT TIMING DIAGRAM

t CPH
t CYC
CS

t SCKH tSCKL
SCK

t DV t CHZ
SO
MSB LSB
Hi Impedance Hi Impedance

DATA RATE - EXAMPLE PATTERN

TXAOUT

ARINC BIT

TXBOUT

DATA NULL DATA NULL DATA NULL

BIT 1
BIT 31 BIT 32 WORD GAP
BIT 30 NEXT WORD

RECEIVER OPERATION

ARINC DATA BIT 31 BIT 32

FLAGS (1)

tINTW
R1INT / R2INT
tRFLG tRXR tSPIF

CS

SPI INSTRUCTION (E.g. 0xA0)

SI

ARINC ARINC ARINC ARINC

BIT 32 BIT 31 BIT 30 BIT 1
SO

(1) Receiver status flag outputs: R1FLAG, R2FLAG, MB1-1, MB1-2, MB1-3, MB2-1, MB2-2, MB2-3

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 HI-3593

TIMING DIAGRAMS (cont.)

OUTPUT WAVEFORMS

ARINC BIT ARINC BIT ARINC BIT

DATA DATA
BIT 1 BIT 2 DATA
BIT 32
+5V +5V

AOUT

-5V

+5V

BOUT

-5V -5V

tfx
+10V +10V
V 90%
DIFF
(AOUT - BOUT)
tfx trx
10%

trx 10%

one level zero level 90% null level

-10V

TRANSMITTING DATA

CS

SPI INSTRUCTION 0x0C SPI INSTRUCTION 0x40

SI

TEMPTY /
TFULL

t TFLG t DATT

AOUT

t SDAT

BOUT

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 HI-3593

HEAT SINK - CHIP-SCALE PACKAGE ONLY

The HI-3593PCx uses a 44-pin plastic chip-scale package. soldered to matching circuit board pad.
This package has a metal heat sink pad on its bottom
surface. This heat sink is electrically isolated from the die.
To enhance thermal dissipation, the heat sink can be

ABSOLUTE MAXIMUM RATINGS

Supply Voltages VDD ......................................... -0.3V to +5.0V Power Dissipation at 25°C
V+ ......................................................... +7.0V Plastic Quad Flat Pack ............... 1.5 W, derate 10mW/°C
V- ......................................................... -7.0V

Voltage at pins RINxx-xx .................................. -120V to +120V DC Current Drain per digital input pin ........................... ±10mA

Voltage at pins TXAOUT, TXBOUT, AMPA, AMPB ......... V- to V+ Storage Temperature Range ........................ -65°C to +150°C

Voltage at any other pin ............................... -0.3V to VDD +0.3V Operating Temperature Range (Industrial): ..... -40°C to +85°C
(Extended): ..... -55°C to +125°C

Solder temperature (Reflow).............................................. 260°C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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 HI-3593

DC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, TA = Operating Temperature Range (unless otherwise specified).

LIMITS
PARAMETER SYMBOL CONDITIONS UNIT
MIN TYP MAX

ARINC 429 INPUTS - Pins RIN1/2A, RIN1/2B, RIN1/2A-40 (with external 40KOhms), RIN1/2B-40 (with external 40KOhms)

Differential Input Voltage: ONE VIH Common mode voltages 6.5 10.0 13.0 V
(RIN1A to RIN1B, RIN2A to RIN2B) ZERO VIL less than ±25V with -13.0 -10.0 -6.5 V
NULL VNUL respect to GND -2.5 0 2.5 V

Input Resistance: Differential RI - 140 - KW

To GND RG - 140 - KW
To VDD RH - 100 - KW

Input Current: Input Sink IIH 200 µA

Input Source IIL -450 µA

Input Capacitance: Differential CI (RINxA to RINxB) 20 pF

(Guaranteed but not tested) To GND CG 20 pF
To VDD CH 20 pF

LOGIC INPUTS

Input Voltage: Input Voltage HI VIH 80% VDD V

Input Voltage LO VIL 20% VDD V

Input Current: Input Sink IIH 1.5 µA

Input Source IIL -1.5 µA
Pull-down Current (MR, SI, SCK, ACLK pins) IPD 60 µA
Pull-up current (CS pin) IPU -60 µA

ARINC 429 OUTPUTS - Pins TXAOUT, TXBOUT, (or AMPA, AMPB with external 32.5 Ohms)

ARINC output voltage (Ref. To GND) One or zero VDOUT No load and magnitude at pin, 4.50 5.00 5.50 V
Null VNOUT -0.25 0.25 V

ARINC output voltage (Differential) One or zero VDDIF No load and magnitude at pin, 9.0 10.0 11.0 V
Null VNDIF -0.5 0.5 V

ARINC output current IOUT Momentary short-circuit current 80 mA

LOGIC OUTPUTS

Output Voltage: Logic "1" Output Voltage VOH IOH = -100µA 90%VDD V
Logic "0" Output Voltage VOL IOL = 1.0mA 10% VDD V

Output Current: Output Sink IOL VOUT = 0.4V 1.6 mA

Output Source IOH VOUT = VDD - 0.4V -1.0 mA

Output Capacitance: CO 15 pF

OPERATING VOLTAGE RANGE

VDD 3.15 3.45 V

OPERATING SUPPLY CURRENT

Transmitting Data in High-Speed Mode. IDD Outputs Unloaded 50 mA

Transmitting Data in High-Speed Mode. IDDL 400 Ohm Differential Output Load 75 mA

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 HI-3593

AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, TA = Operating Temperature Range and fclk=1MHz +0.1%
LIMITS
PARAMETER SYMBOL UNITS
MIN TYP MAX
SPI INTERFACE TIMING
SCK clock period tCYC 100 ns
CS active after last SCK rising edge tCHH 10 ns
CS setup time to first SCK rising edge tCES 10 ns
CS hold time after last SCK falling edge tCEH 10 ns
CS inactive between SPI instructions tCPH 55 ns
SPI SI Data set-up time to SCK rising edge tDS 10 ns
SPI SI Data hold time after SCK rising edge tDH 10 ns
SCK rise time tSCKR 10 ns
SCK fall ime tSCKF 10 ns
SCK pulse width high tSCKH 20 ns
SCK pulse width low tSCKL 25 ns
SO valid after SCK falling edge tDV 35 ns
SO high-impedance after SCK falling edge tCHZ 30 ns
MR pulse width tMR 50 ns

RECEIVER TIMING

Delay - Last bit of received ARINC word to Receive Flag change - Hi Speed tRFLG 16 µs
Delay - Last bit of received ARINC word to Receive Flag change - Lo Speed tRFLG 126 µs
Received data available to SPI interface. RxFLAG to CS active tRXR 0 ns
SPI receiver read FIFO instruction to RxFLAG tSPIF 0 tCYC ns
RxINT pulse width tINT 500 ns
TRANSMITTER TIMING

SPI transmit data write (FIFO Flag Empty or Full) tTFLG 0 ns

FIFO Flag delay after enable transmit instruction - Hi Speed tDATT 2 µs
FIFO Flag delay to ARINC 429 data output - Hi Speed tSDAT 40 µs
FIFO Flag delay to ARINC 429 data output - Lo Speed tSDAT 320 µs
Line driver transition differential times:
High Speed high to low tfx 1.0 1.5 2.0 µs
low to high trx 1.0 1.5 2.0 µs
Low Speed high to low tfx 5.0 10 15 µs
low to high trx 5.0 10 15 µs

CONVERTER CHARACTERISTICS
VDD = +3.3V, TA = Operating Temperature (unlesss otherwise stated)
LIMITS
PARAMETER SYMBOL TEST CONDITIONS UNITS
MIN TYP MAX
Start-up transient (V+, V-) tSTART - - 10 ms
Operating Switching Frequency fSW - 650 - kHz
Worst case maximum voltage doubler output VDD2+(max) VDD = 3.6V T= -55C Open load - 6.93 V
DC/DC converter capacitor recommendations.
For optimum performance use typical (not min.) values. For EMC compliance, see AN-135. CFLY and COUT caps are Ceramic or Tantalum,
preferably multilayer, non polarized dielectric XR7, 10V minimum. CSUPPLY cap is Tantalum 10V minimum.
Ratio of bulk storage to fly-back capacitors COUT / CFLY 2.2 10
Fly-back capacitor CFLY COUT / CFLY >= 10 1.0 4.7 - µF
CFLY(ESR) [0.5, 1.0] Mhz 500 mW
Bulk storage capacitor COUT COUT / CFLY >= 10 2.2 4.7 - µF
COUT(ESR) [0.5, 1.0] Mhz 300 mW
By-pass capacitor CSUPPLY CSUPPLY >= COUT (connect from VDD to GND)

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 HI-3593

ORDERING INFORMATION
HI - 3593 xx x x PART LEAD
NUMBER FINISH
Blank Tin / Lead (Sn / Pb) Solder
F 100% Matte Tin (Pb-free, RoHS compliant)

PART TEMPERATURE BURN

NUMBER RANGE FLOW IN
I -40°C TO +85°C I No
T -55°C TO +125°C T No
M -55°C TO +125°C M Yes

PART PACKAGE
NUMBER DESCRIPTION
PC 44 PIN PLASTIC CHIP-SCALE, QFN (44PCS)
PQ 44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PTQS)

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 HI-3593

REVISION HISTORY

P/N Rev Date Description of Change

DS3593 NEW 02/03/08 Initial Release
A 08/11/11 Modified AC Electrical Characteristics for 10 MHZ SPI operation.
B 08/13/13 Updated DC/DC converter section. Added Converter Characteristics section to AC Electrical
Characteristics. Corrected description for op codes 0x14 and 0x28 in Table 1. Clarified
Solder Reflow Temperature.

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 HI-3593 PACKAGE DIMENSIONS

44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) inches (millimeters)

Package Type: 44PCS

.276 .203 ± .006

BSC
(7.00) (5.15 ± .15)

.020 BSC
(0.50)

.276 Top View .203 ± .006 Bottom

BSC
(7.00) (5.15 ± .15) View
.010
(0.25) typ

.016 ± .002
.039 (0.40 ± .05)
max .008 typ
(1.00)
(0.2)

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)

44-PIN PLASTIC QUAD FLAT PACK (PQFP) inches (millimeters)

Package Type: 44PTQS
.006 MAX.
(.15)

.0315
BSC
(.80)
.547 ± .010 .394 ± .004
(13.90 ± .25) (10.0 ± .10)
SQ. SQ. .014 ± ..002
(.35 ± .05)

.035 ± .006
(.88 ± .15)

.012
R MAX.
See Detail A (.30)
.055 ± .002
.063 (1.4 ± .05)
MAX.
(1.6) 0° £ Q £ 7°
.005
R MIN. Detail A
(.13)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)

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