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Third Edition

EMBEDDED
SYSTEM DESIGN

SANTANU CHATTOPADHYAY
EmbEddEd SyStEm dESign
THIRD EDITION

SANTANU CHATTOPADHYAY
Professor
Department of Electronics and Electrical Communication Engineering
Indian Institute of Technology Kharagpur

Delhi-110092
2023
 To
SANTANA, MY WIFE
My inspiration
and
SAYANTAN, OUR SON
Our hope
 Contents

Preface..........................................................................................................................................................................................xi
Preface to the First Edition............................................................................................................................................. xiii
Acknowledgements............................................................................................................................................................. xvii

1. Introduction...................................................................................................................................... 1–7
1.1 Features of Embedded Systems 2
1.2 Design Metrics 3
1.3 Embedded System Design Flow 4
1.4 Conclusion 6
Exercises 7

2. ARM: An Advanced Microcontroller.......................................................................................8–32

2.1 ARM Microcontroller 9
2.2 A Brief History 9
2.3 Structure of ARM7 11
2.3.1 Control and Status Signals in ARM7 12
2.4 ARM Pipeline 14
2.4.1 3-stage Pipeline 15
2.4.2 5-stage Pipeline 15
2.4.3 6-stage Pipeline 15
2.4.4 8-stage Pipeline 15
2.5 Instruction Set Architecture (ISA) 16
2.5.1 Registers 16
2.5.2 Data Processing Instructions 19
2.5.3 Data Transfer Instructions 19
2.5.4 Multiplication Instructions 23
2.5.5 Software Interrupt 24
2.5.6 Conditional Execution 24
2.5.7 Branch Instruction 25
2.5.8 Swap Instruction 25
2.5.9 Modifying Status Registers 26
2.6 THUMB Instructions 26
vi   Contents

2.7 Exceptions in ARM 29

2.8 Programming Examples 30
2.8.1 Finding the Maximum of a Set of Numbers 30
2.8.2 Comparing Two Null-terminated Strings 30
2.9 Conclusion 31
Exercises 31

3. Digital Signal Processors......................................................................................................... 33–47

3.1 Architecture of Digital Signal Processors 34
3.2 High-speed Data Access 35
3.2.1 Memory Architecture Design 35
3.2.2 Address Generation Units and Special Addresing Modes 36
3.2.3 Direct Memory Access (DMA) Controllers 38
3.3 Fast Computation 40
3.3.1 Arithmetic Processing 40
3.3.2 Instruction Pipelining 40
3.3.3 Parallel Architectures 40
3.4 Higher Accuracy 41
3.5 Fast Execution Control 42
3.6 C6000 Family of DSPs 42
3.6.1 C6000 DSP Core 43
3.6.2 C6000 Pipeline 44
3.6.3 Software Pipelining 44
3.6.4 Software Pipelined Loop (SPLOOP) Buffer 46
3.7 Conclusion 46
Exercises 47

4. Field Programmable Gate Arrays......................................................................................... 48–56

4.1 Field Programmable Devices 48
4.2 Programmability of FPGA 50
4.3 FPGA Logic Block Variations 52
4.4 FPGA Design Flow 54
4.5 Modern FPGAs 55
4.6 Conclusion 55
Exercises 56

5. Interfacing..................................................................................................................................... 57–81
5.1 Serial Peripheral Interface (SPI) 57
5.2 Inter-Integrated Circuit (IIC, I2C) 60
5.3 RS-232C 62
5.4 RS-422 63
5.5 RS-485 63
5.6 Universal Serial Bus (USB) 64
5.6.1 Physical Interface 68
5.6.2 USB Connectors 68
5.7 Infrared Communication—IrDA 71
 Contents   vii

5.8 Controller Area Network—CAN 74

5.9 Bluetooth 78
5.10 Conclusion 80
Exercises 81

6. Sensors and Actuators...........................................................................................................82–104

6.1 Sensors 82
6.1.1 Parameters of Sensors 83
6.1.2 Classification of Sensors 84
6.1.3 Linear and Rotational Sensors 87
6.2 Actuators 102
6.2.1 Classification of Actuators 102
6.3 Conclusion 104
Exercises 104

7. Real-time Operating System..............................................................................................105–131

7.1 Types of Real-time Tasks 105
7.1.1 Hard Real-time Tasks 105
7.1.2 Firm Real-time Tasks 106
7.1.3 Soft Real-time Tasks 106
7.2 Task Periodicity 107
7.2.1 Periodic Tasks 107
7.2.2 Sporadic Tasks 108
7.2.3 Aperiodic Tasks 108
7.3 Task Scheduling 109
7.4 Classification of Scheduling Algorithms 109
7.5 Clock Driven Scheduling 110
7.5.1 Table Driven Scheduling 110
7.5.2 Cyclic Scheduling 111
7.6 Event Driven Scheduling 114
7.6.1 Foreground–background Scheduling 114
7.6.2 Rate Monotonic Scheduling 114
7.6.3 Earliest Deadline First Scheduling 119
7.7 Resource Sharing 123
7.7.1 Priority Inheritance Protocol 123
7.8 Other Features of RTOS 125
7.9 Commercial RTOS 126
7.9.1 General Purpose Operating Systems—Real-time Extensions 127
7.9.2 Windows CE 128
7.9.3 LynxOS 128
7.9.4 VxWorks 128
7.9.5 Jbed 128
7.9.6 pSOS 129
7.10 Conclusion 130
Exercises 130
viii   Contents

8. Specification Techniques....................................................................................................132–163
8.1 Introduction 132
8.2 StateChart 133
8.2.1 Modelling Hierarchy 134
8.3 Specification and Description Language (SDL) 139
8.3.1 Signal Communication 142
8.3.2 Timer 144
8.4 Petri Nets 144
8.4.1 Basic Petri Nets 145
8.4.2 Properties of a Petri Net 149
8.4.3 Extensions to Petri Nets 150
8.4.4 Embedded System Modelling with Petri Nets 151
8.5 Unified Modelling Language (UML) 154
8.5.1 Activity Diagram 155
8.5.2 Class Diagram 155
8.5.3 Communication/Collaboration Diagram 157
8.5.4 Component Diagram 157
8.5.5 Use Case Diagram 158
8.5.6 Sequence Diagram 158
8.5.7 Other Diagrams 159
8.5.8 UML Specification of an Elevator Control System 160
8.6 Conclusion 162
Exercises 162

9. Hardware–Software Cosimulation..................................................................................164–172
9.1 Dimensions in Cosimulation 165
9.2 Cosimulation Approaches 166
9.3 A Typical Cosimulation Environment 167
9.3.1 Abstract-level Cosimulation 168
9.3.2 Detailed-level Cosimulation 169
9.3.3 Interface Issues 169
9.3.4 Automatic Interface Generation 170
9.4 Conclusion 171
Exercises 171

10. Hardware–Software Partitioning.....................................................................................173–202

10.1 Partitioning Using Integer Programming 173
10.2 Extended Kernighan-Lin Heuristic 177
10.2.1 The Kernighan-Lin Heuristic 178
10.2.2 Extending KL-Heuristic for Hardware–Software Partitioning 181
10.3 Partitioning Using Genetic Algorithm 185
10.4 Partitioning Using Particle Swarm Optimization (PSO) 185
10.5 Extended Partitioning Problem 187
10.5.1 Binary Partitioning 188
10.5.2 Extended Partitioning 194
 Contents   ix

10.6 Power Aware Partitioning on Reconfigurable Hardware 196

10.6.1 Single Application Partitioning 197
10.6.2 Multiple Application Partitioning 199
10.7 Conclusion 200
Exercises 201

11. Functional Partitioning and Optimization...................................................................203–217

11.1 Functional Partitioning 203
11.1.1 Model 204
11.1.2 Partitioning Methodology 205
11.2 High-level Optimizations 208
11.2.1 Loop Optimizations 208
11.2.2 Floating to Fixed Point Conversion 211
11.3 Conclusion 216
Exercises 216

12. Security in Embedded Systems........................................................................................218–232

12.1 Vulnerabilities 219
12.2 Security Requirements of Embedded Systems 219
12.3 Common Network Security Solutions 221
12.4 Design Challenges for Secure Embedded Systems 221
12.5 Security-Processing Architectures 222
12.6 Security Attacks 223
12.6.1 Logical Attacks 224
12.6.2 Physical and Side-Channel Attacks 225
12.7 Smart Card Security—A Case Study 227
12.7.1 Operating System and Logical Files 229
12.7.2 Attacks on Smart Card 230
12.8 Conclusion 231
Exercises 232

13. Low Power Embedded System Design..........................................................................233–243

13.1 Sources of Power Dissipation 233
13.1.1 Dynamic Power Dissipation 234
13.1.2 Static Power Dissipation 234
13.2 Power Reduction Techniques 235
13.2.1 Algorithmic Power Minimization 235
13.2.2 Architectural Power Minimization 236
13.2.3 Logic and Circuit Level Power Minimization 237
13.2.4 Control Logic Power Minimization 239
13.3 System Level Power Management 240
13.3.1 Advanced Configuration and Power Interface (ACPI) 241
13.4 Conclusion 242
Exercises 242

Bibliography.......................................................................................................................................... 245–249
Index......................................................................................................................................................... 251–257
 Preface

The third edition of the book incorporates two new chapters—Sensors and Actuators and
Security in Embedded Systems. As embedded systems are interacting more and more with the
environment, different types of sensors are being used by them to get the input parameters. An
embedded system professional must possess good knowledge about the types of these sensors,
their working principles, cost, etc., and should be able to choose the right one from various
alternatives available—for an application design. A full chapter has been devoted for the same
in this new edition. It starts with the parameters of sensors and their classification, followed
by discussion on linear and rotational position sensors, strain sensors, temperature sensors,
acceleration sensors, proximity sensors, Hall-effect sensors, etc. Several types of actuators have
also been enumerated. Chapter 12 of this book discusses the security concerns for embedded
system design. As embedded systems are battery operated and the battery technology is not
advancing at the same rate as computing technology, a battery gap is being felt increasingly
by the system designers. As embedded systems are mostly resource constrained, it is often
difficult to implement rigorous security protocols in them, unlike other computing systems.
On the other hand, increasing use of embedded systems in safety-critical operations, often
dealing with confidential information, has made security a very important aspect. The chapter
discusses the vulnerabilities faced by such a system. Different levels of the system design and
usage may have varying security concerns. Design challenges of a secure embedded system
have been enumerated. Different types of security attacks that may happen on an embedded
system and their probable prevention strategies have also been detailed. A case study on Smart
Card security concerns has been included for better understanding of the topic.
With the inclusion of these two chapters, the book now comprises thirteen chapters, which
make the book complete and more informative. I believe the new edition will be great value to
the students and working professionals in the domain of Embedded Systems. Like the previous
editions, the present edition is also expected to receive wide acceptance in the academic and
professional world.

Santanu Chattopadhyay
 Preface to the First Edition

Embedded Systems are foreseen to be present in almost every electrical/electronic system,

in the form of computing engine embodied within them, often unnoticed by the users of the
systems. Because of this, the future electronic engineers need to be equipped with the design
methodology of such systems. Expertise in just only one or few domains, such as hardware,
software, networking, etc. may not be sufficient to enable the designer to take wise decisions
regarding the implementation platforms and design techniques to be utilized for cost‑effective
solutions to the design problems. An overall knowledge of all the fields with pros and cons
of design alternatives is essential for designing such systems. As a subject, embedded system
is an amalgamation of the fields, such as computer architecture, operating systems, modelling
real-world environment, interfacing standards, networking, algorithms, and so on. This book
is an effort to encompass the essentials of all these fields particularly in relation to the design
of real-time embedded systems. The volume of the book has been kept to reasonable size so
that the contents can be covered within a single semester. The book has been organized into
ten chapters.
Chapter 1 introduces the notion of embedded system and enumerates its features to
distinguish it from desktop and other computing platforms. It carefully examines the
characteristics of such a system and the common design metrics. The design flow of such a
system is explained, bringing out the list of tools and libraries to be used at various stages.
Chapter 2 presents one of the most widely used platforms for embedded system
realization—the microcontrollers. After introducing the basic features of microcontrollers, it
discusses in detail one of the most advanced embedded processor—the ARM processor. First,
its history is presented. It is followed by the various attractive architectural features of ARM
accounting for its popularity. Its instruction set is discussed in detail. Both ARM and THUMB
instruction sets are presented. Some sample assembly language programs are also given as
examples.
Chapter 3 presents an overview of other hardware platforms for embedded system
realization. These include FPGA, DSP, ASIC, etc. A very detailed discussion of these is outside
the scope of this book. Hence, the important features are presented for FPGA and DSP that
will enable the designer to take decisions about the design platform.
Chapter 4 enumerates the interfacing standards commonly used in embedded system
design. It begins with the discussion on simple strategies, such as Serial Peripheral Interfaces
xiv   Preface to the First Edition

(SPI), Inter-Integrated Circuits (IIC), RS-232C, etc. The advanced versions, such as RS-
422 and RS-485 are also presented. It is followed by a detailed discussion on USB. The
physical, electrical and communication standards of USB are presented. Next, the wireless
communication techniques, such as IrDA and Bluetooth have been dealt with. Many of the
embedded applications, particularly in the automotives, utilize the Controller Area Networking
(CAN) for information exchange between subsystems. It has also been discussed.
Chapter 5 is on specification techniques for embedded systems. This enables the readers
to get familiar with the modelling techniques for the real-world systems. It begins with the
discussion on StateChart, a modified version of finite state machines. Several examples have been
included to illustrate the specification methodology. It is followed by another strategy, called
SDL, particularly suitable for describing distributed systems. A very powerful mathematical
technique for describing the behaviour of asynchronous systems is the PetriNets. The basic
PetriNet structure has also been extended in several ways to handle real-time systems. All
these have been discussed with a good number of illustrations. A graphical object-oriented
method for embedded system specification is the UML. It consists of a set of diagrams that
can be utilized to describe a system hierarchically. Suitable illustrations have been included to
illustrate the specification process.
Chapter 6 deals with real-time operating systems. This forms the kernel of any moderate‑to-
large sized real-time embedded system. First, the tasks have been classified into several
categories, such as soft, firm, and hard real-time tasks. Different scheduling algorithms have
been presented, beginning with the very simple table-driven ones to the complex ones, such as
rate-monotonic scheduling, earliest-deadline first scheduling, etc. The schedulability conditions
for a set of tasks have been described. The pros and cons of the major scheduling strategies
have been discussed. The problems related to priority-based scheduling algorithms have been
presented. These include priority inversion and associated deadlock problems. The solutions
to these have also been dealt with. The other general features of real-time operating systems
have been enumerated. A number of such real-time operating systems have been studied and
their features have been compared.
Chapter 7 presents the details of hardware–software co-simulation. It addresses the
problem of verifying the correctness of the system at every stage of development. The concept
of co-simulation is presented—its categories are discussed. The techniques for homogeneous
and heterogeneous co-simulation have been presented. It also discusses the important issue of
automated interface generation that enables the completion of hardware–software co-synthesis.
Chapter 8 deals with the issues related to hardware–software partitioning of the tasks
belonging to one or more applications for a system realization. The partitioning problem
takes as input a specification, most conveniently represented as a task graph with nodes
representing individual tasks and the edges representing the amount of interactions and
dependencies between the tasks. There exist a good number of algorithms to solve this
partitioning problem targeted to architecture. These include techniques based on Integer
Linear Programming (ILP), heuristic approaches (such as Kernighan-Lin algorithm), meta-
search techniques (such as, Genetic Algorithm, Particle Swarm Optimization etc.). Each of
these categories has been discussed. The problem has been extended further to combine with
scheduling and implementation bin selection (to select among the hardware alternatives for
nodes mapped onto to hardware, and similarly for software). Another important aspect of
today’s system design is honouring the power constraints. Some power constrained mapping
solutions have also been presented.
 Preface to the First Edition   xv

Chapter 9 discusses the functional partitioning and optimization of task graph for an
application. The problem of functional partitioning is to reconsider a given specification and
come up with better grouping or refining the procedures within it so that the improved task
graph can be fed as input to the partitioning process to result in better solutions. It includes
steps like granularity selection, pre-clustering and N-way assignment. On the optimization
side, the chapter enumerates different loop-optimization techniques, floating-to-fixed-point
conversion algorithms, etc. The overall idea is to refine the manual specification into a form
that can lead to a better final implementation.
Chapter 10 presents discussions on low-power techniques commonly followed in embedded
system design. After presenting the basic power dissipation techniques in an electronic
system, it discusses the power reduction approaches. The power can be saved at various
levels—algorithm, architecture, logic, device, etc. For an embedded system designer, it is most
appropriate to address the power issues at algorithm and/or architectural levels. Hence, these
have been discussed in detail. The issues related to dynamic power management have been
enumerated. The shutdown prediction mechanisms have been presented for periodic real-time
tasks. The ACPI standards for power management have also been discussed.
This book is an attempt to bridge various domains of knowledge needed by an embedded
system designer. It is estimated to be covered in a single semester undergraduate/postgraduate
course on Embedded Systems. If the book can be fruitfully utilized by the students, for whom
it has been written, I will consider my efforts to be successful. All constructive suggestions for
improving the content will be welcomed.

Santanu Chattopadhyay
 Acknowledgements

I must acknowledge the contribution of my teachers who taught me the subjects such as Digital
Logic, Computer Architecture, Operating Systems, Programming Languages and Semantics,
Algorithms, Networking, Compilers, VLSI Design, and so forth. The clear discussions in those
classes helped me to consolidate my knowledge in these domains and combine them properly
in framing the contents of the book. The various design problems introduced in the book have
their roots in those class lectures. I feel deeply blessed to have such a nice group of teachers.
I am also thankful to all my students, whom I have taught this subject. They all helped me to
identify the gaps and mistakes in the manuscript.
My source of inspiration for writing this book is my wife Santana, whose relentless wish
and pressure forced me to bring the book in its present shape. Over this long period, she has
sacrificed a lot in the family front to allow me to have time to continue writing, taking all other
responsibilities onto herself. I am also thankful to my son, Sayantan, for his cute comments
that kept the charm of writing rolling.
I acknowledge the authors of the books and research papers, which have been referenced
for writing this book. A detailed list has been provided in the Bibliography.
Thanks are also due to the publishers, PHI Learning, its editorial and production teams for
providing me with the necessary support to see my thoughts in the form of a book.

Santanu Chattopadhyay
 1
CHAPTER

Introduction

Information processing is the heart of any modern electrical/electronic equipment. While

in eighties and early nineties, the task of information processing was accomplished via large
mainframe, mini, and personal computers, the trend has changed significantly to put the
computation inside the new electronic gadgets being developed in every front of life. These
computational units lying totally inside the bigger device often go unnoticed by the users
of the system. This continual effort to embed computational elements into bigger systems
has given rise to a new class of systems, named aptly as embedded systems. The design goals
of such systems vary significantly from the general computational systems in the sense that
they often have a set of very strict performance requirements, at the same time, meeting
many other design constraints. Thus, an embedded system can be defined to be a computing
system embedded within a larger electronic device, performing a single (or a small set of)
function(s) repeatedly, and often going unnoticed by the device’s user. This definition, being a
bit non-technical, may not be very precise. However, it should be noted that giving a precise
definition of embedded system is quite difficult. In some sense, it can be thought to be the
computing systems other than desktops and other computers with higher configurations.
Embedded systems can be found in almost every walk of life. The gadgets around us have
some embedded processors in almost all of them. It is predicted that each and every electrical
device will have some computational component put into it (if not already there), in the near
future. Application domains of embedded systems are varied and wide. To mention a few,
◆ consumer electronics (cell-phone, pager, video camera, calculator, etc.)
◆ automobiles (anti-lock brake, fuel injection control, etc.)
◆ home appliances (refrigerator, washing machine, microwave oven, etc.)
◆ office automation equipments (fax, scanner, printer, EPBX, etc.)
In fact, the list is very long. With the newer and newer electronic gadgets reaching the
market everyday, the range of applications are also increasing at a rapid pace. These systems
have got varied operational principles, design philosophies, and maintenance techniques. Thus
bringing these heterogeneous systems under the common umbrella of embedded systems is a
challenging task. In the following section, we identify a set of features commonly found
in such embedded systems.
2   Embedded System Design

1.1 FEATURES OF EMBEDDED SYSTEMS

There are several features common to many embedded systems, whereas, it is also not
mandatory that all features will be supported by all the embedded systems.
The following are the important features exhibited by embedded systems.
1. Single functioned system: Most embedded systems perform a single job repetitively.
For example, a washing machine has an embedded controller that can take user
inputs in terms of knob settings and perform the job of washing. A cell-phone can
receive and transmit signals to enable communication between two people. A general
purpose system (like a desktop) on the other hand is capable of doing a lot many
operations. An embedded system will do the single function efficiently as compared
to a general purpose computational system. However, it should be kept in mind that
all embedded systems are not single functioned. For example, the cell-phone, as other
features, may be able to send/receive SMSs, take photograph with add-on camera,
tune to a radio station, play music, connect to the Internet and so on. But it cannot
be utilized to perform complex scientific computation—unlike a desktop, it cannot
be programmed for this purpose.
2. Interaction with the physical environment: Most embedded systems interact with
the physical environment around them. Data are collected from the environment
using sensors while actuators are used to control some of the parameters of the
environment. A room temperature monitoring system may have number of temperature
sensors fitted at various locations in the room. Depending upon the temperature
readings, it can actuate a number heating/cooling instruments distributed in the
room.
3. User interface: Unlike the common user interfaces like keyboard, mouse, screen,
etc. in general computing systems, embedded systems often contain dedicated user
interfaces consisting of push buttons, Light Emitting Diodes (LEDs), steering wheels,
etc. This gives an impression of the absence of computers and thus, information
processing to the general users.
4. Dependable system: Embedded systems are often used in safety-critical applications,
like nuclear power plants, medical instrumentation, etc. This demands a high
degree of dependability on such systems. It is more so, because embedded systems
often work in autonomous mode, interacting with the environment and impacting
upon it directly. Apart from system reliability, a dependable system must ensure
easy maintainability, good availability, high degree of safety to the environment and
security of information it processes. For example, a smart card reader should not
release the card information to any undesired agency.
5. Tightly constrained system: Embedded system design is often constrained from several
angles. For example, it should be a low-cost solution to the problem so that the overall
system is cheap. Size of the embedded system, its performance and power budget also
put severe constraint on the choice of the target implementation. For the battery to
last long and reduced battery-pack size, the system must be a low-power one. These
constraints, though present in other computing systems, may not be that stringent
there.
 Introduction   3

6. Real-time system: Most embedded systems are real-time in nature. They must respond
to a request from the environment within a finite and fixed amount of time.
Failure to do so may lead to a catastrophic situation. For example, failure to activate
fire extinguishers immediately after getting a fire alarm through sensors, may destroy
the entire plant. Such systems are called hard real-time systems. On the other
hand, if the effect is not that serious, the system is a soft real-time system. For
example, failure to process the image frame just arrived may just create some noise
in the display of the image for some time.
7. Hybrid systems: Many of the real-time systems are hybrid in nature, as they include
both analog and digital components.
8. Reactive systems: Reactive systems have continual interaction with the environment.
The behaviour of the system is very much dependent on the events occurring
in the environment. This type of systems normally have a set of states. Depending
upon the occurrence of events, state transitions in the system take place. On the other
hand, a proactive system may not be interactive in nature. Once initiated, a proactive
system may work on its own to produce output.

1.2 DESIGN METRICS

The design metrics are the optimization goals that an embedded system designer wants
to achieve. The commonly used metrics are the following:
1. System cost: It consists of two types of costs, namely the non-recurring engineering
(NRE) cost and the recurring cost. The NRE cost is one time—the expenditure
incurred in the design stage of the system. Once the system has been designed,
extra units can be produced at a much lesser cost. This type of situation occurs
commonly in designing VLSI chips. The NRE cost is very high as it includes the
process of generating masks. However, once the mask preparation has been done, it
can be replicated over a large silicon die to produce a large number of similar chips,
reducing the per unit cost.
2. Size: Size of the system is very important. The size may be measured in silicon
area for hardware, whereas it refers to the code size for the software portion of the
embedded system. The code size affects the memory space requirement, increasing
the overall chip/board size.
3. Performance: It refers to the speed of the designed system. Normally, the specification
of the system will have some performance requirements to be met by the design. This
is one of the vital factors influencing the decision regarding the final implementation.
For example, the same functionality implemented in software will have lesser speed
than a hardware realization. In the hardware realization also, an application specific
integrated circuit (ASIC) will have better performance as compared to Field
Programmable Gate Arrays (FPGAs) or other general purpose processors.
4. Power requirement: This is the other most important design metric, particularly
because the embedded systems are expected to have light weight, long battery
life. This necessitates plastic packaging, absence of cooling fans, etc. Thus, power
requirement and the associated heat dissipation of the system should be very low.
4   Embedded System Design

5. Design flexibility: It refers to the effort needed to modify a system if the specification
changes to some extent later. While a software implementation is very flexible, ASIC
is the least flexible one, with FPGAs lying at an intermediary stage. The main problem
in the design change is the repetition of the NRE cost which is the minimum for
software.
6. Design turnaround time: This is the time needed to complete the design starting from
specification upto taking it to the market. Due to the very high rate of obsolesence
of electronic goods, it is imperative that this time be small. The requirement often
forces the designers to use off-the-shelf components, rather than doing a costly
redesign of system components. Design reuse is the key term here.
7. System maintainability: This refers to the ease of maintaining and monitoring the
health of the system after it has been put into the field. A good design is well
documented such that even designers excepting those who designed the system
originally, can modify the system, if necessary.
8. Testing and verification of functionality: It refers to the ability to check the system
functionality and get confidence regarding the correct operation of it. It may be
noted that in the system life-cycle, verification is generally carried out after the
design has been completed. The goal of design verification is to see whether all the
system features have been designed properly or not. There is no physical system
available at this point of time. On the other hand, testing is needed to check for
correct functioning of each unit produced. Thus, verification comes as an NRE cost
while testing comes as a part of unit cost.

1.3 EMBEDDED SYSTEM DESIGN FLOW

Having understood what an embedded system is, its essential features and design parameters,
now we will have a look into the embedded system design methodology. It consists of several
stages as discussed next.
1. System specification: Design of any system starts at its specification. Specification
uses a language, which may be simple English, some programming language like C
(for example), or it may be some formal technique using PetriNets, StateChart,
UML chart and so on. Different specification techniques have been detailed in
Chapter 7. As will be noted later, ideally a specification should be executable, so
that we can check whether the desired input–output behaviour has been modelled
correctly or not. Also, it is desirable that some automated tool be able to convert the
system specification into a design. These necessitate having a formal specification of
the system. The type of tools doing this transformation of converting an abstract
system specification into a set of sequential programs are commonly known as system
synthesis tools. The processes do interact between themselves to realize the overall
functionality of the system. An individual process can be realized by general purpose
processor or through dedicated processor. It should be noted that any task can be
implemented by either type of the processors, however, the speed will vary. A general
purpose processor will have a software implementation of the task, while a dedicated
processor can be implemented on FPGA (Field Programmable Gate Array) or ASIC
 Introduction   5

(Application Specific Integrated Circuit) to have better performance. However, the

decision regarding hardware or software implementation is also often determined by
the availability of pre-designed modules. Such modules form the system level library
consisting of complete system solutions to previous problems. System specifications
are normally verified by using some formal tools known as model simulators/checkers.
These tools prepare a model of the entire system using some mathematical logic. A
set of desired behaviour of the system is also specified as logic formula. The tool
then checks whether those formula hold on the model or not. In case a formula
fails, the tool often generates an example of such failure. This may help the designer
to rectify the error.
2. Behavioural specification: System specification refines to behavioural specification by
the system synthesis tools. For each of the processes, a behavioural specification
is obtained. As noted earlier, some of these processes are marked for software
implementation on general purpose processor, while some others are on dedicated
hardware. Behavioural specification is verified by hardware–software cosimulation.
Individual simulation of only hardware or only software cannot bring out the total
picture of the system. Thus, a joint simulation strategy is needed.
3. Register transfer (RT) specification: This is achieved through the refinement of behavioural
specification. For the processes mapped onto general purpose processor, the software
code is translated to the assembly/machine language instructions. It may be
noted that a processor defines operation at register-transfer level only. On the other
hand, for dedicated hardware realization, synthesis tools (commonly known as high
level sysnthesis tools) convert the behavioural specification into a netlist of library
components. This library includes description about RT components that may be
used in the design at RT level. For example, registers, counters, ALUs, etc. The RT-
specification can be verified by using RTL simulators normally available to simulate
descriptions in hardware description languages, such as VHDL, Verilog, etc.
4. Logic specification: The specification of the dedicated processors is converted to logic
specification. The logic specification consists of Boolean equations. The equations
can now be converted to final implementation in some target technology. It may
be noted that for the processes mapped onto general purpose processor, for which
software code has been generated, no refinement is needed at this stage. Gate level
simulators can be used to simulate the logic specification in terms of gates present
in the circuit.
It should be noted that at each stage, it is highly necessary to verify the correctness
of the refinement. This is done by simulating the specification at that stage and matching the
simulated response with the desired one. At system level, a model simulator simulates the
specification. It uses an abstract computational model, independent of the target processor
technology, to verify the correctness and completeness of the specification. While the correctness
ensures that all the desired functionalities have been specified correctly, the completeness issue
ascertains that nothing extra is done by the system which may lead to undesirable system
states. At the behavioural level, HDL (Hardware Description Language) simulators can be
used to simulate the behaviour of the system partitions mapped onto dedicated processor.
The software portion can be simulated by using a general purpose processor simulator. A
6   Embedded System Design

cosimulator connects these two types of simulators (hardware and software) to perform the
overall simulation of the system at its behavioural level. At RT-level, a structural-level HDL
simulator can be used to simulate the RT-specification of the hardware components, whereas,
the code corresponding to the general-purpose processor can be compiled and run. Again the
cosimulator can utilize these two types of information to have a RT-level simulation of the
system. At logic level, a gate-level simulator can be used to produce the output waveforms from
the given input waveforms. The general-purpose processor simulators execute the program
code mapped onto it. The co-simulator now checks the output of both of them to produce the
final output of the system simulation. Thus the overall design methodology can be expressed
in the form of a diagram shown in Fig. 1.1.

FIGURE 1.1 Embedded system design methodology.

1.4 CONCLUSION
In this chapter, we had an overview of the embedded systems, their features, design metrics,
overall design flow and the synthesis techniques. To be a successful system designer, one must
have thorough knowledge about the following:
◆ Specification techniques to be able to specify the system behaviour in a formal fashion.
◆ Hardware platforms available to realize the functionalities mapped onto hardware. This
requires us to know about the general purpose processors, Field Programmable Gate
Arrays (FPGAs), microcontrollers, digital signal processors and so on.
◆ Interfaces that are commonly used, like RS232C, USB, I 2 C, SPI, UART, CAN, IrDA,
Bluetooth, etc.
 Introduction   7

◆ Sensors and actuators that can be used to interface with the environment.
◆ For efficient software design, we need knowledge about the real-time operating systems.
◆ Methodologies for hardware and software partitioning and synthesis.
◆ Automated synthesis of the interface between the system components.
In subsequent chapters we will go through discussions on each of these topics in detail.
To start with, in next two chapters we will look into the available processor architectures
that can be used in embedded system design.

EXERCISES
1.1 What is embedded system? Give as many different definitions (with justification) that
you can think of.
1.2 Identify a few embedded systems around us and justify their classification as embedded
system.
1.3 Differentiate between single-functioned and multi-functioned embedded systems. Give
examples for each of them. How do you distinguish between a multifunction embedded
system and a general desktop?
1.4 Identify a few instruments that can be part of an embedded system interacting with
the environment.
1.5 Explain the terms dependability, safety, criticality, reliability, availability with respect
to an embedded system.
1.6 What is a tightly constrained system. What are the different types of constraints
that we can encounter in embedded system design?
1.7 Distinguish between proactive and reactive systems. Give examples.
1.8 Explain the main features of embedded systems.
1.9 What is meant by design metric? Mention the various design metrics that need to be
considered in embedded system design.
1.10 What are the components of the metric system cost? How does the contribution of
the components change as we go from general processor-based design to application
specific design?
1.11 How is the performance of a system expected to change in different implementation
strategies?
1.12 What are the compelling factors that make power an important issue?
1.13 What is design turnaround time and why should it be as small as possible?
1.14 Enumerate the various steps of embedded system design.
1.15 What are the various categories of synthesis tools needed in the embedded system
design cycle? Identify some potential tools (name of the tool, manufacturer, etc.) in
each of these categories.
1.16 What do you mean by the RTL specification of software processes?
1.17 What are simulators? Mention different categories of simulators in embedded system
design with examples of actual tools (name of the tool, manufacturer, etc.) for each
category.
 2
CHAPTER

ARM: An Advanced
Microcontroller

Microcontrollers are single-chip computers. In a single chip it combines a relatively simple CPU,
with supports, such as timers, serial/parallel, digital/analog, input/output lines, etc. Program
memory is generally included on-chip. Also, a typically small read/write memory (commonly
known as scratch-pad) is included in the chip. To extend program and data memory further,
proper interfacing facilities are provided.
While microprocessors are used in personal computers and other high-performance appli-
cations, microcontrollers are targeted towards small applications. The operating frequency
may be as low as 32 kHz, though there exist many high speed microcontrollers. The major
requirement of such small systems is the reduced power consumption (as noted in Chapter 1).
The next important issue is of course cost. Apart from the integration of various system com-
ponents into a single chip with reduced power consumption and cost, some of the important
features that embedded system designers look for in microcontrollers are the following:
1. Whether the highest available speed of the microcontroller is sufficient for the
application in hand.
2. The size of the chip, for example, 40-pin DIP (dual inline package), QFP (quad flat
package). This determines the size of the system and thus the device.
3. Amount of on-chip ROM/RAM space should be sufficient to hold program code.
Depending upon the design constraints, external memory may or may not be utilized.
4. Cost of a single chip, as it is going to determine the cost of the overall system.
5. The development platform should be good enough so that the design time is reduced.
It is also advisable to have on-chip debugging facility (through JTAG port) and debug
software.
6. Availability of the microcontroller chips is also another determining factor.
Various types of microcontrollers are available in the market. Some of the important ones
are—68HC11, 8051, ARM, Atmel (AVR8, AVR32), Freescale (CF, S08), Hitachi (H8, SuperH),
MIPS, NEC, PIC, PowerPC, TI MSP430, Toshiba TLCS-870, Zilog (eZ8, eZ80). In the following
section, we look into the ARM processor architecture that has many nice features supporting
embedded computation, and is, in particular, low power.
 ARM: An Advanced Microcontroller   9

2.1 ARM MICROCONTROLLER

ARM is a 32-bit RISC (Reduced Instruction Set Computer) processor architecture developed
by the ARM Corporation. It was previously known as Advanced RISC Machine, and prior to that
Acron RISC Machine. The ARM architecture is licensed to companies that want to manufacture
ARM-based CPUs or system-on-a-chip products. This enables the licensees to develop their
own processors compliant with the ARM instruction set architecture. ARM processors possess
a unique combination of features that makes ARM the most popular embedded architecture
today.
1. ARM cores are very simple, compared to other general-purpose processors available in
the market. This implies that the ARM processors will need relatively lesser number
of transistors, leaving enough space on the die to realize other functionalities on the
silicon.
2. The instruction set architecture and the pipeline design of ARM are aimed at
minimizing the energy consumption—a critical requirement in mobile embedded
systems. In spite of being a 32-bit microcontroller, it is capable of running 16-bit
instruction set, known as “THUMB”. This helps to achieve greater code density and
enhanced power saving.
3. While being small and low-power, ARM processors provide high performance.
4. ARM architecture is highly modular—the only mandatory component of an ARM
processor is the integer pipeline. All other components including caches, memory
management unit (MMU), floating point and other co-processors are optional. This
gives a lot of flexibility in building application specific ARM-based processors.
5. To assist the developer, the ARM core has a built-in JTAG debug port and on-chip
“embedded ICE (In-Circuit Emulator)” that allows programs to be downloaded and
fully debugged in-system.

2.2 A BRIEF HISTORY

The first ARM processor was designed by the Acron Computers Limited of Cambridge, England
between 1983 and 1985. While looking for a new processor for the next generation desktop,
they found that the existing commercial microprocessors were not suitable for their purpose,
mainly because of the following two reasons.
◆ These processors were slower than the existing memory parts.
◆ Complex instruction set, including instructions requiring hundreds of cycles to execute,
leading to high interrupt latencies.
Thus, the requirement of designing a new processor was felt. However, designing a complex
processor used to take many years even for large companies with expertise available for pro-
cessor design. The solution was found in the Berkeley RISC 1 project which had established
that it was possible to build a very simple processor with performance comparable to the most
advanced CISC processors of the time. Acron designed their first 26-bit Acron RISC Machine
(ARM) processor in 1985, based upon the Berkeley project. It used less than 25,000 transistors
and still performed like (or better than) Intel 80286 processor that came out at about the
same time. This architecture has later been referred to as ARM version 1 architecture. It was
followed by the second processor in 1987. This
10   Embedded System Design

was extended with on-chip cache in ARM 3 processor. The third version of ARM architecture,
developed in 1992 had features like 32-bit addressing, support for Memory Management Unit
(MMU) and 64-bit multiply-accumulate instructions. It was implemented in ARM 6 and ARM 7
cores. Prior to this, in 1990, Apple took a decision to use ARM processor in their Newton PDA.
A joint venture called ARM (Advanced RISC Machines) was launched. ARM entered into the
embedded market with the release of these processors and the Apple Newton PDA in 1992. The
4th generation ARM processor came out in 1996 with the special feature of THUMB—16-bit
compressed instruction set. Though THUMB is slightly less efficient compared to the regular
32-bit ARM instruction set, it takes 40% less space. The most prominent representative of
the 4th generation ARM is the ARM7TDMI core, which is till now the most popular ARM
product. It has been used in most Apple iPod players, including the video iPod. Another
popular implementation of ARMv4 core is the Intel StrongARM processor. The 5th generation
of ARM architecture introduced in 1999 has digital signal processing capability and Java
byte code extensions to the ARM instruction set. Intel XScale processor is the most popular
implementation of the 5th generation ARM core. It is used in a number of embedded devices,
network processors, smart phones and PDAs. ARMv6 architecture anounced in 2001 features
improvements in many areas covering the memory system, improved exception handling
and better support for multiprocessing environments. It also includes media instructions to
support Single Instruction Multiple Data (SIMD) software execution. THUMB-2, an improved
THUMB instruction set defining a new set of 32-bit instructions that execute along-side
16-bit instructions in THUMB state, was introduced. It provides better support for two separate
address spaces, such that code executing in the non-secure world cannot gain access to any
address space marked as secured. The protection provided by the technology is necessary for
consumer privacy and extending a range of services such as, mobile banking and multimedia
entertainment, to widespread consumer adoption and use. The next generation ARMv7 cores
have been introduced in 2005. They come with three different processor profiles. The ‘A’
profile is for sophisticated virtual memory based OS and user applications. The ‘R’ profile
is for real-time systems, and the ‘M’ profile is optimized for microcontrollers and low-cost
applications. The ARMv7A architecture has the option of NEON technology designed to address
the next generation high performance, media intense, low-power mobile hand-held devices. It
is a 64/128-bit hybrid SIMD architecture developed by ARM to accelerate the performance of
multimedia and signal processing applications. The Vector Floating Point (VFP) coprocessor
support is also an architectural option. It supports single and double precision floating point
arithmetic, and is fully IEEE 754 compliant with suitable software library. Table 2.1 summarizes
the discussion.

TABLE 2.1 ARM architecture summary

Version Year Features Implementation
v1 1985 The first commercial RISC (26-bit) ARM1
v2 1987 Coprocessor support ARM2, ARM3
v3 1992 32-bit, MMU, 64-bit MAC ARM6, ARM7
v4 1996 THUMB ARM7TDMI, ARM8, ARM9TDMI,
StrongARM
v5 1999 DSP and Jazelle extensions ARM10, XScale
v6 2001 SIMD, THUMB-2, TrustZone, Multiprocessing ARM11, ARM11 MPCore
v7 2005 Three profiles, NEON, VFP
 ARM: An Advanced Microcontroller   11

2.3 STRUCTURE OF ARM7

Figure 2.1 shows a block diagram of ARM7 processor. The major components of ARM7 processor
are described next:

FIGURE 2.1 ARM7 block diagram.

1. Instruction Pipeline and Read Data Register: It gets the content of memory location
pointed to by the address bus lines A[31 : 0], of Address Register. The external 32-bit
data-in lines DATA[31 : 0] put the content into this register.
2. Instruction Decoder and Control Logic: It has a number of control inputs determining
the operation policy of the processor. Also, it outputs a number of control signals
useful for interfacing the processor with other peripherals. The various control signals
are explained later.
3. Address Register: It holds the address of the next instruction/data to be fetched.
Address bus A[31 : 0] originates from it. The input signal ALE determines the time
12   Embedded System Design

upto which the register’s content will remain available on the A[31 : 0] lines. Content
is available as long as ALE remains low.
4. Address Incrementer: It increments the Address Register’s value by an appropriate
amount to point to the next instruction/data.
5. Register Bank: It contains 31, 32-bit registers accessible in different modes of operation
of the processor (detailed later). It also contains 6 status registers, each of size 32-bits.
6. Booth’s Multiplier: It is used in the multiplication instructions.
7. Barrel Shifter: One of the operands of data processing instructions can be shifted by a
few bit positions. The barrel shifter located at the input of ALU performs this function.
8. ALU: A 32-bit ALU performs the arithmetic and logic functions.
9. Write Data Register: It holds the value to be written into the memory. The 32-bit
value is available in the DOUT [31 : 0]. The associated signals DBE and nENOUT have
been elaborated later.

2.3.1 Control and Status Signals in ARM7

We will next elaborate the control and status signals used in ARM7 processor. Figure 2.2 shows
a functional diagram of ARM7 CPU. The signals can be grouped as per their functionality. Based
on this, the signals can be grouped as:
◆ Processor mode: includes the signals nM[4 : 0].
◆ Memory interface: A[31 : 0], DATA[31 : 0], DOUT [31 : 0], nENOUT, nMREQ, SEQ, nRW,
nBW, LOCK.
◆ Memory management interface: nTRANS, ABORT.
◆ Clock signals: MCLK and nWAIT.
◆ Configuration signals: PROG32, DATA32, BIGEND.
◆ Interrupts: nIRQ, nFIQ.
◆ Bus control signals: ALE, DBE.
◆ Power lines: VDD and VSS.
◆ Special signals: nEXEC and nRESET.

Processor mode signals nM [4 : 0]

These status signals identify the mode of the processor. The output bits are the inverses of the
internal status bits indicating processor operation mode (detailed later).

Clock signals MCLK and nWAIT

MCLK is the master clock input to the ARM processor. It has two phases. In phase 1 MCLK is
low and in phase 2 it is high. The clock may be stretched in either phase to interface slower
devices. Alternatively, nWAIT can be used. ARM7 can be made to wait for an integer number
of MCLK cycles by holding nWAIT low. nWAIT is internally ANDed with MCLK and must only
change when MCLK is low.
 ARM: An Advanced Microcontroller   13

FIGURE 2.2 ARM7 functional diagram.

Memory interface signals A[31 : 0], DATA[31 : 0], DOUT[31 : 0], nENOUT, nMREQ, SEQ, nRW,
nBW, LOCK
A[31 : 0] are the address lines constituting the processor address bus. If ALE is high, address
becomes valid during the phase 2 of the previous instruction cycle. This address is used in
phase 1 of the referenced cycle. The stable period may be controlled by ALE as discussed later.
DATA[31 : 0] is the input data bus. During read cycles (identified by nRW = 0), input must
be valid before the end of phase 2 of the transfer cycle. DOUT[31 : 0] is the output data bus.
During write cycles (nRW = 1), output data becomes valid during phase 1 and remain so for
the entire phase 2 of the transfer cycle. nENOUT is a status signal which is activated (made
low) by the processor when DOUT contains a valid data to be written into the memory. This
nENOUT signal can be utilized to create a bidirectional bus with DATA for the memory. nMREQ
is a status signal indicating (when low) that the processor requires memory access during the
following cycle. The signal becomes valid during phase 1, remaining valid through phase 2 of
the cycle preceding that to which it refers. SEQ active-high signal indicates that the address used
in the following cycle is either the same as the last memory address, or is 4 greater (i.e., the
next word address). It becomes valid during phase 1 and remains valid throughout phase 2 of
the cycle before the one to which it refers. The two signals nMREQ and SEQ together indicate
burst activity one cycle advance. nRW is another status signal.
14   Embedded System Design

For a read cycle, the signal is low, for a write cycle, it is high. nBW is high for a word
transfer and low for a byte transfer. The signal LOCK is used for locked memory access. When
LOCK is high, the memory controller should not allow any other device to access memory till
LOCK becomes low. It is used, in particular, in swap instruction.

Memory management interface nTRANS, ABORT

nTRANS signal indicates when to translate the address. nTRANS = 0 indicates that processor
is in user mode and address translation should be turned on. The timing of the signal may be
modified by ALE, as discussed later. The signal ABORT is an input to the processor. This allows
the memory system to tell the processor that the requested access is not allowed.

Configuration signals PROG32, DATA32, BIGEND

PROG32 is for 32-bit program configuration. When high, it makes the processor to fetch from
32-bit address space. When low, the processor fetches instructions from a 26-bit address space.
DATA32 is for 32-bit data configuration. When high, the processor uses 32-bit address for data
fetch. When low, data is fetched from a 26-bit address space. BIGEND = 1 instructs the processor
to utilize big-endian convention. When low, little-endian format is assumed.

Interrupts nIRQ, nFIQ

nFIQ is an asynchronous interrupt to the processor. The signal is low-level sensitive and must
be held low till an action is received from the processor. This is responded the fastest. On the
other hand, nIRQ is of lower priority.

Bus control signals ALE, DBE

ALE is the address latch enable, an input signal to ARM7 to extend the stable address on the
address lines till end of phase 2 of MCLK. By default (ALE being 1), address changes during
phase 2 of MCLK to the value needed in the next cycle. Setting ALE to 0 also extends the
following signals—nBW, nRW, LOCK, nOPC, nTRANS. DBE is data bus enable. It facilitates data
bus sharing for DMA mode of operation.

Special signals nEXEC and nRESET

nEXEC is high when the instruction in the execution unit is not being executed, for example, it
has failed its condition code check. nRESET is low-level sensitive reset signal for the processor.

2.4 ARM PIPELINE

One important feature of ARM architecture is its pipelined organization. There are various
versions of this pipeline used in different ARM architectures. These are:
◆ 3-stage pipeline (ARM7TDMI and earlier).
◆ 5-stage pipeline (ARMS, ARM9TDMI).
◆ 6-stage pipeline (ARM10TDMI).
◆ 8-stage pipeline (ARM11).
 ARM: An Advanced Microcontroller   15

2.4.1 3-stage Pipeline

The 3-stage pipeline is the classical fetch–decode–execute pipeline. The first pipeline stage reads
an instruction from memory and increments the value in the instruction address register. The
value is also stored in the program counter (PC). The next stage decodes the instruction and
prepares control signals required to execute it on. The third stage does all the actual work:
reading operands from the register file, performing ALU operations by fetching or writing to
the memory the temporary data (if necessary), and finally writing back the modified register
values. In the case of data processing instructions, the result from ALU is directly written into
the register file, thus completing the execution stage of the instruction in one cycle, while for
load/store type of instructions, the address computed by the ALU is placed on the address bus
and the actual memory access is performed during the second cycle of the execution stage.

2.4.2 5-stage Pipeline

The problem with 3-stage pipeline is the pipeline stall caused by every data transfer
instruction—the next instruction cannot be fetched while memory is being read/written. To
circumvent this problem, in ARM9TDMI and later architectures, instruction and data memory
have been separated. To make the pipeline balanced, the following measures have been taken.
◆ The register read step is moved to the decode stage.
◆ Execute stage is split into three stages. The first stage performs arithmetic computations,
the second stage performs memory access, while the third stage writes the result back to
the register file. It may be noted that the second stage will remain idle when executing
data processing instructions.
This modification balances the pipeline, reducing the CPI (average number of Clocks Per
Instruction). However, there is a new complication—we need to forward data between pipeline
stages to resolve data dependencies between the stages without stalling the pipeline.

2.4.3 6-stage Pipeline

In ARM10 core, the instruction decode stage is split into two pipeline stages—the decode
stage and the register stage. This creates a 6-stage pipeline. While the decode stage performs
the decoding operation, register stage reads the register to be used. The major advancements
introduced are in the width of the instruction and data buses, both of which are made 64-bit.
Thus, fetch stage can fetch two instructions simultaneously. A static branch predictor module
has been introduced. A separate adder has been introduced in the execution unit to take care
of multiply–accummulate instructions.

2.4.4 8-stage Pipeline

Two major changes have been introduced in ARM11 cores creating an eight-stage pipeline.
◆ Shift operation has been separated into a separate pipeline stage.
◆ Both instruction and data accesses are distributed across two pipeline stages.
16   Embedded System Design

The execution unit is split into three different pipelines that can operate concurrently and
commit instructions out-of-order also.

2.5 INSTRUCTION SET ARCHITECTURE (ISA)

ARM, in most respects, is a typical RISC architecture. However, several enhancements to it
have been introduced to improve the performance further. The RISC features present in ARM
are as follows:
◆ Large uniform register file with 16 general-purpose registers.
◆ Load/store architecture. The instructions that process data operate only on registers
and are separate from instructions that access memory.
◆ Simple addressing modes.
◆ Uniform and fixed-length instruction fields. All ARM instructions are 32-bit long and
most of them have a regular three-operand encoding.
These features help in the implementation of pipelining in the ARM architecture. However,
in order to keep the architecture simple and improve performance, a number of other (non-
RISC) features have been introduced.
◆ Each instruction controls the ALU and the shifter. Thus, making the instructions more
powerful.
◆ Auto-increment and auto-decrement addressing modes have been incorporated. This
increments or decrements the value of an index register while a load or store operation
is in progress.
◆ Multiple load/store instructions that allow to load or store up to 16 registers at once
have been introduced. While violating the one cycle per instruction principle, they
significantly speed up performance-critical operations, such as procedure invocation
and bulk data-transfers, and lead to more compact code.
◆ Conditional execution of instructions has been introduced. In the machine code of an
instruction, opcode is preceded by a 4-bit condition code. For the instruction to execute,
the condition stated must be met. This goes a long way to eliminate small branches in
the program code and eliminating stalls in the pipeline.
All these features have resulted in high performance, low code size, low power consumption,
and low silicon area in ARM.

2.5.1 Registers
The ARM ISA has 16 general-purpose registers, R0–R15, in the user mode. Out of these, register
R15 is the program counter which may also be manipulated as a general-purpose register.
Registers R13 and R14 also have special functions; R13 is used as the stack pointer, though this
has only been defined as a programming convention. Unusually, the ARM instruction set does
not have PUSH and POP instructions, so stack handling is done via a set of instructions that
allow loading and storing multiple registers in a single operation. R14 has special significance
and is called the link register. When a procedure call is made, the return address is automatically
placed into this register (and not in the stack, as usually done in other processors). A return
 ARM: An Advanced Microcontroller   17

from the procedure can thus be implemented by moving the content of R14 to R15. Another
important register, the current program status register (CPSR) contains four 1-bit condition
flags (namely, negative, zero, carry, and overflow) and four fields representing the execution
state of the processor. The ‘I’ and ‘F’ flags enable normal and fast interrupts, respectively. The
‘T’ field is used to switch between ARM and THUMB instruction sets. The mode field selects
one of the six execution modes as follows:
1. User mode is used to run the application code. Once in user mode, the CPSR cannot
be written to. Mode can only be changed when an exception is generated.
2. Fast interrupt processing mode (FIQ) supports high speed interrupt handling. Generally
it is used for a single critical interrupt source in a system.
3. Normal interrupt processing mode (IRQ) supports all other interrupt sources in a
system.
4. Supervisor mode (SVC) is entered when the processor encounters a software interrupt
instruction. These are standard ways to invoke operating system services. Upon reset,
ARM enters into this mode.
5. Undefined instruction mode (UNDEF) is entered if the fetched opcode is not an ARM
instruction or a coprocessor instruction.
6. Abort mode is entered in response to memory fault, for example, an instruction or
data fetched from an invalid memory region.
The user registers R0 to R7 are common to all operating modes. However, FIQ mode has
its own R8 to R14 registers that replace the user registers when FIQ mode is entered. Similarly,
each of the other modes have their own R13 and R14 registers so that each mode has its own
stack pointer and link register. The CPSR is also common to all the modes. However, in each
of the exception modes, an additional register—the saved program status register (SPSR) is
added. SPSR registers store a copy of the value of the CPSR register before an exception was
raised. Figure 2.3(a) shows all the user accessible registers while Figure 2.3(b) shows the
structure of the CPSR.

Data types
The ARM instruction set supports six different data types, namely, 8-bit signed and unsigned,
16-bit signed and unsigned, 32-bit signed and unsigned. The ARM processor instruction set
has been designed to support these data types in little- or big-endian format. However, most
of the ARM silicon implementations use the little-endian format.
In the following we give a brief overview of different types of ARM instructions. ARM has
got two instruction sets:
◆ ARM:
— Standard 32-bit instruction set
— It consists of the following types of instructions as shown in Figure 2.4.
∗ Data processing
∗ Data transfer
∗ Block transfer
∗ Branching
∗ Multiply
∗ Conditional
∗ Software interrupts
18   Embedded System Design

FIGURE 2.3 User accessible registers and CPSR.

FIGURE 2.4 ARM instruction set.

 ARM: An Advanced Microcontroller   19

◆ THUMB
— 16-bit compressed form
— Code density better than most CISC
— Dynamic decompression in pipeline

2.5.2 Data Processing Instructions

The ARM architecture provides a range of arithmetic operations, such as addition, subtraction,
multiplication, etc., and a set of bit-wise logical operations. All these instructions take two 32-
bit operands and return a 32-bit result. The multiplication instruction can return a 32- or 64-bit
value. All these operands and results can be specified independently. Out of the three, the first
operand and the result must be registers, while the second operand can be either a register
or an immediate value. If the second operand is a register, it can be shifted or rotated before
being sent to the ALU. On the other hand, for immediate operand, it must be a 32-bit value.
However, all 32-bit constants cannot be specified here. This is due to the limited space available
for operand specification inside the 32-bit instruction. An immediate operand should be a
32-bit binary number where all the binary 1s fall within a group of eight adjacent bit positions on
a 2-bit boundary. More formally, a valid immediate operand n satisfies the following equation:
n = i ROR (2 ∗ r)
where i is a number between 0 and 255 (inclusive), r is between 0 and 15 (inclusive) and ROR
is the rotate right operation. Examples of such numbers are 255 (i = 255, r = 0), 256 (i = 1,
r = 12), hexadecimal number FF000000 (i = 255, r = 4), etc.
One interesting feature of the ARM architecture is that the modification of condition flags
by arithmetic instructions is optional. This adds flexibility to the programming in the sense that
flags do not need to be checked right after the instruction that set them, but can be done later
in the instruction stream, provided that other intermediate instructions do not change the flags.
Some examples of data processing instructions are,
ADD R1, R2, R3; R1 = R2 + R3.
ADD R1, R2, R3, LSL #2; R1 = R2 + (R3 × 4).
ADDS R1, R2, R3, LSL #2; R1 = R2 + (R3 × 4) and set condition code flags.

2.5.3 Data Transfer Instructions

ARM supports two types of data transfer instructions: single register transfers and multiple
register transfers. Single register transfer instructions can be used to transfer 1, 2, or 4-bytes
of data between a register and a memory location. On the other hand, multiple register load/
store operations can be carried out via multiple register transfer instructions. The addressing
mode to be used for multiple register transfer is base–plus–offset addressing. Value in the base
register is added to the offset stored in a register or passed as an immediate value to form the
memory address. An auto-indexed addressing mode can also be used which writes the value
of the base register incremented by the offset back to the base register. It helps in accessing
the next memory location in the next instruction without wasting an additional instruction to
20   Embedded System Design

increment the register. Two different auto-indexed addressing modes are supported—the pre-
indexed mode uses the computed address for the load/store operation, and then updates the
base register to the computed value. The post-indexed mode uses the unmodified base register
for the transfer and then updates the base register. Multiple register transfer instructions also
support auto-indexed addressing. Multiple register transfer instructions are particularly useful
while entering or exiting a procedure to pass parameters or return values. The following points
may be noted regarding the offset and the indexing.
◆ The offset can be
— An unsigned 12-bit immediate value (that is, 0 to 4095 bytes)
— A register, optionally shifted by an immediate value
◆ Either added or subtracted from the base register
— Prefix the offset value or register with ‘+’ (default) or ‘−’
◆ Applied
— before the transfer is made: Pre-indexed addressing (optionally auto-incrementing
the base register by postfixing the instruction with an ‘!’)
— after the transfer is made: Post-indexed addressing, causing the base register to
be auto-incremented.
Some examples of data
transfer instructions are,
LDR R0, [R8] load content of memory location pointed to by R8 into R0
LDR R0, [R1, –R2] load content of memory location pointed to by R1 – R2 into R0
LDR R0, [R1, +4] load content of memory location pointed to by R1 + 4 into R0
LDR R0, [R1, +4]! load content of memory location pointed to by R1 + 4 into R0,
R1 is also incremented by 4
LDR R0, [R1], +16 Loads R0 from memory location pointed to by R1, then adds
16 to R1

LDR Load word STR Store word

LDRH Load half word STRH Store half word
LDRSH Load signed half word STRSH Store signed half word
LDRB Load byte STRB Store byte
LDRSB Load signed byte STRSB Store signed byte

As discussed earlier, ARM supports both little-endian and big-endian formats for data
access. In the little-endian format, the least significant byte of a word is stored in bits 0–7 of
an addressed word, whereas, in the big-endian format, the least significant byte is stored in
bits 24–31. It may be noted that this has got significance only when the data is stored as words
and then accessed as bytes or halfwords. Figure 2.5 gives an example of the same.
Block data transfer
The Load and Store multiple instructions (LDM/STM) allow between 1 and 16 registers to be
transferred to or from memory. The transferred registers can be either:
◆ Any subset of the current bank of registers (default)
◆ Any subset of the user mode bank of registers when in a privileged mode (postfix
instruction with a ˆ symbol).
 ARM: An Advanced Microcontroller   21

FIGURE 2.5 Big-endian vs. Little-endian.

Like single register transfer operations, in this case also the base register is used to
determine where memory access should occur. Auto-increment and auto-decrement are also
supported for the base register. Lowest register number is always transferred to/from the
lowest memory location accessed. The block transfer instructions have got efficient utilization in
◆ implementing stack for saving and restoring context
◆ moving large blocks of data around memory
1. Stack operation: Though traditionally a stack grows down in memory with the last
pushed value at the lowest address, ARM can be made to implement “ascending stack”
also, where the stack grows up through memory. The value of the stack pointer can
be either:
• Point to the last occupied address (Full stack), and thus needs pre-decrementing
before the push
• Point to the next occupied address (Empty stack), and thus needs post-decrementing
after the push
The stack type to be used is given by the postfix to the instruction as follows:
• STMFD/LDMFD: Full descending stack
• STMFA/LDMFA: Full ascending stack
• STMED/LDMED: Empty descending stack
• STMEA/LDMEA: Empty ascending stack
22   Embedded System Design

For example, Figure 2.6 shows four stack examples. It may be noted that the sequence of
registers within an instruction does not affect the order in which the registers are saved. ARM
follows the strategy that the lowest register number is always stored at the lowest address.
Thus, instead of writing the sequence as R0, R1, R3 − R5 specifying it as R1, R0, R5, R4, R3 or
R5, R0 − R1, R3 − R4 have the same effect.

FIGURE 2.6 Example stack.

2. Moving a large data block: We can best explain it with the help of an example.
Suppose, we have to copy a block of memory of size equal to an exact multiple of 12
words from the location pointed to by register R12 to the location pointed to by R13.
R14 points to the end of the block to be copied. The following versions of LDM/STM
instructions can be utilized for this purpose:
• STMIA/LDMIA: Increment after
• STMIB/LDMIB: Increment before
• STMDA/LDMDA: Decrement after
• STMDB/LDMDB: Decrement before
The exact code to perform the task may be as follows:
; R12 points to the start of the source data
; R14 points to the end of the source data
; R13 points to the start of the destination data
loop LDMIA R12!, {R0-R11} ; load 48 bytes
STMIA R13!, {R0-R11} ; and store them
CMP R12, R14 ; check for the end
BNE loop ; and loop until done
 ARM: An Advanced Microcontroller   23

2.5.4 Multiplication Instructions

ARM provides several versions of multiplications. These are:
◆ Integer multiplication (32-bit result)
◆ Long integer multiplication (64-bit result)
◆ Multiply accumulate instruction—particularly useful in signal processing applications,
for example, digital filtering.
Accordingly, there are several versions of the multiplication instruction.
MUL Multiply 32-bit result
MULA Multiply accumulate 32-bit result
UMULL Unsigned multiply 64-bit result
UMLAL Unsigned multiply accumulate 64-bit result
SMULL Signed multiply 64-bit result
SMLAL Signed multiply accumulate 64-bit result
For example,
MUL R0, R1, R2 R0 gets R1 ∗ R2
MULA R0, R1, R2, R3 R0 gets R1 ∗ R2 + R3
However, there are a few restrictions regarding the source and destination.
1. Destination and the first operand cannot be in the same register.
2. PC (R15) cannot be used for multiplication.
ARM uses the Booth’s Algorithm to perform integer multiplication. In some variants of
ARM processors, multiplication proceeds as follows:
◆ For each pair of bits, it takes 1 cycle. One more cycle is needed to start the instruction.
The multiplication continues till the source register has some 1’s left in it. Otherwise,
the algorithm early-terminates. For example, to multiply 18 (00000000000000000000
000000010010 in binary) and –1 (11111111111111111111111111111111 in binary),
if the source register content is 18, it will take 4 cycles, whereas, if the source register
holds –1, number of cycles needed is 17. Generally, the language compilers take care
of such issues.
In some other variants containing extended multiplication hardware, the following
enhancements have been performed.
◆ An 8-bit Booth’s algorithm is used, which makes the multiplication faster (maximum
standard instruction is now 5 cycles).
◆ Early termination method is improved in the sense that the multiplication completes
when all the remaining bit sets contain either all 0s, or all 1s.
◆ 64-bit results can be produced from 32-bit operands, this provides higher accuracy. A
pair of registers is used to hold the result.
24   Embedded System Design

2.5.5 Software Interrupt

The software interrupt (SWI) instruction forces the CPU into supervisor mode. Its format is,
SWI #n
The execution of the instruction causes an exception trap to the SWI hardware vector
(forcing the mode change and an associated state saving), thus causing the SWI exception
handler to be called. The handler can now analyse the value of n to determine which action
to perform. It should be noted that the processor completely ignores n, and it is the software
interrupt handler that may analyse the value of n to perform the desired job. This is very
suitable for an operating system to implement a set of privileged operations which applications
running in user mode can request. Such requests are commonly known as system calls. The
value of n is 24-bits, thus providing facility for a maximum of 224 calls. Unlike many other
processors (such as, Intel processors), the hardware does not attempt to distinguish between
these 224 cases. If separate addresses are to be maintained for them, a total of 224 × 4 (address
bus is 32 bits = 4 bytes) = 226 bytes of memory will be needed.

2.5.6 Conditional Execution

This is an interesting feature of ARM instruction set. While most of the existing architectures
allow only branches to be executed conditionally, ARM allows all instructions to be executed
conditionally. The most significant four bits of each instruction are reserved to hold the 16
condition codes. As it may be noted, there are four flags N, Z, C, and V. The following are the
interpretations of these four-bit settings.
0000 : EQ – (Equal)
0001 : NE – (Not equal)
0010 : HS/CS – (Unsigned higher or same)
0011 : LO/CC – (Unsigned lower)
0100 : MI – (Negative)
0101 : PL – (Positive or zero)
0110 : VS – (Overflow)
0111 : VC – (No overflow)
1000 : HI – (Unsigned higher)
1001 : LS – (Set unsigned lower or same)
1010 : GE – (Greater or equal)
1011 : LT – (Lower)
1100 : GT – (Greater)
1110 : AL – (Always)
1111 : NV – (Reserved)

We have already seen how to set the conditional flags in instruction execution. For example,
the use of mnemonic ADDS in place of ADD sets the flags, whereas the basic ADD instruction
does not affect any of the flags. Now, to execute an instruction conditionally, we have to use
mnemonics like EQADD. For example:
 ARM: An Advanced Microcontroller   25

EQADD R0, R1, R2 perform R0 = R1 + R2 only if zero flag is set.

EQADDS R1, R2, R3, LSL #2 perform R1 = R2 + (R3 × 4) only if zero flag is set,
and set condition code flags.

2.5.7 Branch Instruction

In ARM processor, the following features of branch instructions can be noted:
1. All branches are relative to the program counter.
2. Jump is always within a limit of ±32 MB.
3. Conditional branches are formed by using the condition codes as discussed earlier.
4. Subroutine call instruction is also modelled as a variant of branch instruction.
There are two opcodes reserved for branching—B (standard branch) and BL (branch with
link, current value of PC+4 is saved in link register R14). The BL version can be used to call
subroutine. The return from subroutine can be affected by copying the content of R14 back to
PC. The branch instruction structure is as shown in Figure 2.7.

FIGURE 2.7 Branch instruction format.

In the coding of a branch instruction, to get the offset, first a 26-bit difference is computed
between the current PC value and the target. It is then right shifted by two bits (as the
instructions are always word-aligned, least significant two bits are always 0s), and stored in
the instruction encoding. This provides a branch range of ±32 MB. While executing the branch,
the processor shifts the offset left by two bits, sign extends it to 32-bits, and adds it to the
PC to get the branch target. The instruction pipeline is filled by getting instructions from the
target address, and the execution resumes.
Another very important class of branch instructions is the Branch exchange—BX and
BLX. These are similar to B and BL instructions, however, it also performs the exchange of
instruction set between ARM instructions and THUMB instructions. This is the only way to
swap instruction sets.

2.5.8 Swap Instruction

A careful look into the ARM instructions will reveal that a single instruction can read/write at
the most one memory location. The swap instruction is an exception to this. Swap is an atomic
operation in which a memory read is followed by a memory write which moves byte or word
between registers and memory. Its format is,
SWP Rd, Rm, [Rn]
SWPB Rd, Rm, [Rn]
26   Embedded System Design

The execution proceeds as follows (as depicted in Figure 2.8).

1. It is a two-cycle operation.
2. Content of memory location pointed to by register Rn is copied into a temporary space.
3. Content of register Rm is copied into the memory location.
4. Content of the temporary space is copied into the register Rd.
Thus, to effect an interchange between the registers Rd and Rm, they should be made
the same register. In that case, content of the memory location is swapped with the register
in an atomic operation. This can be exploited to implement the semaphore operations of the
operating system.

FIGURE 2.8 Swap instruction execution.

2.5.9 Modifying Status Registers

The status registers (that is, CPSR and SPSR) can only be modified indirectly. The instruction
MSR moves content from CPSR/SPSR to the selected general purpose register, whereas the
MRS moves content of selected GPR to CPSR/SPSR. The instructions can only be executed in
the privileged modes.

2.6 THUMB INSTRUCTIONS

As we have noted earlier, the ARM processor supports two different instruction sets—ARM
and THUMB. While the ARM instruction set has got 32-bit instructions, THUMB instructions
are 16-bit in length. These instructions are stored in a compressed form. The instructions are
decompressed into ARM instructions and then executed by the processor. Figure 2.9 shows
the THUMB instruction processing. Figure 2.10 shows the THUMB instruction decompressor.

FIGURE 2.9 THUMB instruction processing.

 ARM: An Advanced Microcontroller   27

FIGURE 2.10 THUMB instruction decompressor.

THUMB instruction set must always be entered by running a BX/BLX instruction. These
instructions are similar to their ARM counterparts, with a few exceptions.
1. THUMB instructions are executed unconditionally, excepting the branch instructions.
2. THUMB instructions have unlimited access to registers R0–R7 and R13–R15. A reduced
number of instructions can access the full register set. As shown in Figure 2.11, only
a few instructions can access registers R8–R12.
3. The instructions look more like a conventional processor’s instructions. For example,
instructions like PUSH and POP are present for stack manipulation, though the final
implementation is via the ARM multibyte transfer instructions. It implements a
descending stack with the stack pointer hardwired to R13.
4. No MSR and MRS instructions.
5. The maximum number of SWI calls is restricted to 256.
6. On RESET and on raising of an exception, the processor always enters into the ARM
instruction set mode.
7. Similarities and differences between ARM and THUMB instruction sets have been
detailed in Table 2.2.
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