Topic 2

DC Biasing of Bipolar Transistors

2.1 Introduction
The analysis or design of a transistor amplier requires a knowledge of both the dc and the ac
response of the system. Biasing a transistor is connecting passive components to the terminals
of the transistor so that it operates within its limits of operation. The term biasing means the
application of dc voltages to establish a desired level of current and voltage. The dc level of
operation of a transistor is controlled by a number of factors, including the range of possible
operating points on the device characteristics. Once the desired dc current and voltage levels have
been dened, a network must be constructed that will establish the desired operating point. We
shall simply examine the common-emitter (CE) conguration of a BJT. The equations below can
be used for biasing are:

VBE ' 0.7 V (2.1)

IC = βIB (2.2)
IE = (β + 1)IB (2.3)

Fig. 2.1 shows the possible locations for an operating point. Note that the operating point can
be anywhere within the region of operation, so points like B, C and D are all possible but some
are better than others for reasons that will become clear later. For example, point B is a better
choice than C and D because it allows for adequate current and voltage swing to the left, right,
above and below it when the signal is fed into the amplier. For the BJT to be biased in its linear
or active operating region the following must be true:

(a) The baseemitter (BE) junction must be forward-biased (B more positive than E), with a
resulting forward-bias voltage VBE of about 0.6 V to 0.8 V or ' 0.7 V (for Si BJT)

(b) The basecollector (BC) junction must be reverse-biased (C more positive than B), with the
reverse-bias voltage being any value within the maximum limits of the device.

(c) The operating point must lie within the dashed lines in Fig. 2.1(a) and above the IB =
0 µA characteristic. This last condition applies only to amplication and not switching
applications of a BJT.

2.1.1 CE xed-bias BJT Amplier

Fig. 2.2(a) is a BJT xed-bias CE amplier. The signal enters through capacitor C1 and exits
through C2 after amplication. For biasing, we are only interested in DC conditions, so we consider

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 Figure 2.1: Limits of BJT operation

only the DC equivalent circuit shown in Fig. 2.2(b). The operating point is specied by three
parameters - the base current IB , the collector current IC and the collector-emitter voltage, VCE -
these are normally further subscripted using Q as IBQ , ICQ , VCEQ where Q stands for the Q-point
(quiescent point or operating point).

We apply Kircho's voltage law at the input side of the amplier in Fig. 2.2(c):
VCC = IB RB + VBE
The base current IB is given by
VCC − VBE
IBQ = (2.4)
RB

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 Figure 2.2: Fixed-bias BJT analysis

For the output side, using Fig. 2.2(d):

VCC = IC RC + VCE
and the collector emitter voltage is
VCEQ = VCC − ICQ RC (2.5)
Using Eqn. 1.6, i.e. IC = βIB , we get
ICQ = βIBQ (2.6)

Equation (2.5) may also be written as

VCEQ = VCC − βIBQ RC (2.7)
This establishes the operating point for this xed-bias amplier. The Q-point for this amplier
depends too closely upon the value of β and this can heavily depend upon the temperature of the
device. This is not good as devices tend to heat up during operation.

Example

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Load line Analysis
For any values of VCE and IC , Equation (2.5) is

VCE = VCC − IC RC
1 VCC
⇒ IC = − VCE + (2.8)
RC RC
Eqn. (2.8) is an equation of a straight line with gradient −1/RC and vertical intercept VCC /RC .
The horizontal axis intercept is obtained by inserting IC = 0 in Eqn. (2.8) to get VCE = VCC .
This line is plotted in Fig. 2.3 and is called the DC load line. The Q-point lies on the DC load
line and is given by the coordinates (VCEQ , ICQ ). Suppose that the signal at the base is ± iB . This
signal results in a signal iC = ± βiB at the collector. The signal is always superimposed on the
dc Q-point values already calculated using equations in Section (2.1.1). This aects the Q-point.
For this signal, the value of ICQ changes as

ICQ → ICQ ± βiB (2.9)

Similarly, VCEQ is aected:

VCEQ → VCC − (ICQ ± βiB )RC (2.10)

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 Figure 2.3: Showing the DC Load-line

Equations (2.9) and (2.10) indicate that the Q-point moves up (towards point A in Fig. 2.3) and
down (towards point B) along the dc load line if a signal is fed into the amplier. The amplier
designer must make sure that this movement of the Q-point does not drive the point up beyond
point A (into saturation) or below point B (cuto).

Example

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2.1.2 Emitter-bias Conguration
The dc bias network of Fig. 2.4 contains an emitter resistor
to improve the stability level over that of the xed-bias con-
guration seen earlier. The more stable a conguration, the
less its response will change due to undesireable changes in
temperature and parameter values. Fig. 2.5(a) shows the
DC equivalent circuit for the emitter-bias amplier of Fig.
2.4. Fig. 2.5(b) shows the base-emitter loop to be used
for analysis. We apply Kircho's voltage law to the loop
shown:

+VCC − IB RB − VBE − IE RE = 0
but IE = (1 + β)IB
thus VCC − IB RB − VBE − (1 + β)IB RB = 0
Figure 2.4:
VCC − VBE
⇒ IB = (2.11)
RB + (1 + β)RE
Note that in Fig. 2.5(c) as compared to Fig. 2.5(b), this result is equivalent to replacing the

Figure 2.5: For analysing emitter-bias congured BJT.

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emitter resistor RE by (1 + β)RE .

The output side of the amplier may be redrawn in the form shown in Fig. 2.6. Again applying
Kircho's voltage law to the loop shown gives

VCE = VCC − IC (RC + RE ) (2.12)

The collector current IC is given by

IC = βIB (2.13)

Equations (2.11), (2.12) and (2.13) specify the operat-

ing or Q-point of the emitter-bias amplier - we can
put them all together using the subscript Q as be-
fore:
Figure 2.6: Output
VCC − VBE
IBQ = (2.14a)
RB + (1 + β)RE
ICQ = βIBQ (2.14b)
VCEQ = VCC − ICQ (RC + RE ) (2.14c)

Example

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Saturation and Load line Analysis
Transistor saturation occurs if VCE ' 0. If this condition is inserted into Equation (2.12), we have

VCE = VCC − IC (RC + RE ) = 0 (2.15)

VCC
⇒ IC = (2.16)
RC + RE
VCC
The saturation current is ICSAT = IC = (2.17)
VCE=0 RC + RE
The eect on the DC load line of including an emitter resistance RE is shown in Fig. 2.7 - basically
the load ICSAT is lowered since
VCC VCC
without RE , ICSAT = > with RE
RC RC + RE

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 Figure 2.7: DC load-line for emitter-bias conguration

Example

Figure 2.8:

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Figure 2.9:

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2.1.3 Voltage-Divider Bias Conguration
In the previous bias congurations the bias collector current ICQ and voltageVCEQ were a function
of the forward current gain β of the transistor. However, because β is temperature sensitive,
especially for silicon transistors, and the actual value of β is usually not precisely known, it would
be desirable to develop a bias circuit that is less dependent on, or in fact is independent of, the
transistor's β . The voltage-divider bias conguration of Fig. 2.10(a) is such a network. Fig.
2.10(b) shows the Q point and DC load-line on the output characteristics. The DC equivalent

Figure 2.10: (a) Voltage-divide bias network (b) output characteristics

circuit for the voltage-divider bias circuit of Fig. 2.10(a) is shown in Fig. 2.11(a). We apply

Figure 2.11: Voltage-divider (a) circuit (b) Thevenin equivalent circuit of input (c)
circuit of output
Thevenin's theorem to reduce the circuit to a series combination of source ET h and equivalent

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resistance RT h as in Fig. 2.11(b) where

R1 R2
RT h = R1 ||R2 = (2.18a)
R1 + R2
R2
ET h = VCC (2.18b)
R1 + R2

The base current IB may be calculated using Fig. 2.11(b) as follows:

ET h − IB RT h − VBE − IE RE = 0
but IE = (1 + β) IB
⇒ ET h − IB RT h − VBE − (1 + β) IB RE = 0

so that
ET h − VBE
IB = (2.19)
RT h + (1 + β)RE
The output side of the amplier may be analysed using Fig. 2.11(c). We apply Kircho's
voltage law to the loop:

VCC − IC RC − VCE − IE RE = 0
1+β
but IE = IC
β
1+β
⇒ VCC − IC RC − VCE − IC RE = 0
β
The collector-emitter voltage VCE is then given by
" ! #
1+β
VCE = VCC − IC RC + RE (2.20)
β

Provided that β  1, which is normally the case, Equation 2.20 may be written as
 
VCE = VCC − IC RC + RE (2.21)

Eqn. (2.21) is exactly the same as that obtained for VCE (Eqn. (2.12)) for the emitter-bias
conguration. This is expected as the output circuit for both is exactly the same. The Q-point
parameters for the voltage-divider conguration are summarised, using the Q subscript as

ET h − VBE
IBQ = (2.22a)
RT h + (1 + β)RE
ICQ = βIBQ (2.22b)
VCEQ = VCC − ICQ (RC + RE ) (2.22c)

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Example

24
Approximate Biasing for Voltage-Divider
We consider Fig. 2.10(a) again. The potential at the base is assumed to be

R2
VB = (2.23)
R1 + R2
since R1 and R2 are assumed to be in series. The voltage-divider may be redrawn as shown in
Fig. 2.12 where Ri is the input impedance of the rest of the amplier (everything to the right of
the base, B). R1 and R2 are therefore not in series. Some current must ow through Ri .

A base current IB ows into the rest of amplier through a

resistance Ri . The current IB depends upon Ri and ideally,
this current must be very small in order that the potential
at B remains xed i.e. R1 and R2 appear to be in series.
So IB << I1 and I2 or I1 ' I2 . This will only be the case
if Ri is much larger than either of R1 and R2 . Because
Ri = (1 + β)RE ' βRE , the condition for the potential-
divider assumption is

βRE ≥ 10R2 (2.24)

As we have see earlier, the emitter and collector currents are

related by IE = (1 + β)IC but as we also know, values of β
range from 50 to 300, so the assumption β  1 is justied. Figure 2.12:
In this case, we can use the approximation

IE ' IC (2.25)

in all biasing designs.

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26
27
2.2 Emitter-follower Conguration
Fig. 2.13(a) shows yet another manner in which a BJT can be congured, called the emitter-
follower or common-collector conguration. Note that the collector terminal is common to both
input vi and output vo . Fig. 2.13(b) is the DC equivalent circuit of the circuit of Fig. 2.13(a)
which we shall now use for analysis. Applying Kircho's voltage law to the inout side, we have

−IB Rb − VBE − IE RE + VEE = 0

but IE = (1 + β)IB
so that − IB RB − VBE − (1 + β)IB RE + VEE = 0

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 Figure 2.13:

VEE − VBE
⇒ IB = (2.26)
RB + (1 + β)RE
On the output side,
−VEE − IE RE + VEE = 0 (2.27)

⇒ VCE = VEE − IE RE (2.28)

As before,
⇒ IC = βIB (2.29)
The three equations 2.26, e.28 and 2.29 are the basic biasing equations for the emitter-follower,
and specify the Q-point for the congurations:
VEE − VBE
IBQ = (2.30a)
RB + (1 + β)RE
ICQ = βIBQ (2.30b)
VCEQ = VEE − (β + 1)IBQ RE (2.30c)

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2.3 Multistage Ampliers
Amplier circuits so far considered have been single stage ampliers. In practice, ampliers may
have many similar stages, forming what is called multistage ampliers.

2.3.1 RC Coupled Voltage-Divider Amplier

Fig. 2.14(a) is a two-stage RC coupled voltage-divider amplier and Fig. 2.14(b) is its dc equiv-
alent circuit. The term RC coupled is used to indicate that an RC network is used to couple
the two stages. The rst stage is a voltage-divider amplier based around transistor Q1 and the
second stage is exactly the same but based around transistor Q2 . The two stages are connected or
coupled through an Rc network formed using resistor RC and capacitor CC . Stage 2 ends at the
second capacitor CC . The output signal vo is coupled to the load RL through second capacitor
CC .
Fig. 2.14(b) is the DC equivalent circuit of Fig. 2.14(a). Note that there are no capacitors (the
are open circuited) and no AC signals, such as vs and vo that appear in Fig. 2.14(a). The analysis
of each stage follows the same method used for single stage amplier considered in Section 2.2.

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Figure 2.14: Two-stage RC coupled voltage-divider amplier (a) circuit (b) DC equiv-
alent

2.3.2 Darlington BJT conguration

The use of multistage ampliers is primarily to get more gain. Instead of using such multistage
ampliers, one may use a special connection called the Darlington conguration. Fig. 2.15(a) is a
base-bias amplier using the Darlington conguration. For dc, capacitors Cs and CC cut RS and
RL out and we end up with the dc equivalent circuit of Fig. 2.15(b). Note that the emitter of Q1
is connected to the base if Q2 and the collectors of both Q1 and Q2 are connected together. This
eectively forms one composite transistor with input current base current IB1 and collector current
IC2 . We let the forward current amplication ratios for Q1 and Q2 be β1 and β2 respectively. Note
that for this connection, IE1 = IB2 . The gain of the combined transistors is

βD = IC2 /IB1
but IC2 = β2 IB2 = β2 IE1 = β2 (1 + β1 ) IB1
⇒ βD = IC21 /IB1 = β2 (1 + β1 )

If β1  1 as is usually the case, then (1 + β1 ) ' β1 and

βD ' β1 β2 (2.31)

Eqn. 2.31 gives the eective amplication of two transistors connected as a Darlington pair. For
the 2N4123 featured in Chapter 1 for example, the data sheet gives β = hf e from 50 to 200.
Using two such transistors connected as a Darlington pair would produce an eective βD from a
minimum of 2500 to a maximum of 40,000 - which is a phenomenal amplication! Further analysis

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 Figure 2.15: Darlingtom BJT (a) amplier (b) its DC equivalent circuit.

shows that
VCC − VBE1 − VBE2
IB1 =
RB + (1 + βD )RE
Let VBED = VBE1 + VBE2

VCC − VBED
IB1 = (2.32)
RB + (1 + βD )RE
Eqn. 2.32 is similar to that for a single stage amplier (for example Eqn. 2.19), with the exception
that βD replaces β . For the currents

IC2 ' IE2 = βD IB1 (2.33)

and the dc voltage at the emitter is

VE2 = IE2 RE

The collector voltage is equal to the supply voltage VCC

VC2 = VCC (2.34)

and the voltage across the transistor output is

VCE2 = VC2 − VE2 (2.35)

and
VCE2 = VCC − VE2 (2.36)

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Eqns. 2.32, 2.33 and 2.36 may be taken as the Q-point values for this conguration.

VCC − VBED
IBQ = (2.37a)
RB + (1 + βD )RE
ICQ = IC2 ' IE2 = βD IBQ (2.37b)
VCEQ = VCC − VE2 = VCC − ICQ RE (2.37c)

since VE2 = IE2 RE ' IC2 RE = βD IBQ RE as IE2 ' IC2 . Eqns. (2.37) dene the Q-point for the
amplier of Fig.2.15.

2.3.3 The Cascode Congured Amplier

Another important multistage transistor conguration for amplier design is the Cascode cong-
uration. Again this uses two transistors. Fig. 2.16(a) is one such design, showing the biasing
aspects. Note that the emitter of transistor Q1 feeds into the collector of transistor Q2 . The input
is at the base of Q2 through capacitor Cs . Fig. 2.16(b) is the dc equivalent circuit for analysis.
A basic assumption of the analysis of this circuit is that the current that ows down from VCC

Figure 2.16: Cascode conguration: (a) circuit (b) dc equivalent circuit

through resistors R1 , R2 and R3 is much larger than that which ows into the bases of Q1 and
Q2 . R1 , R2 and R3 therefore form a 3-section voltage divider. R2 + R3 set the potential at the
base of Q1 at
R2 + R3
VB1 = VCC (2.38)
R1 + R2 + R3
and R3 sets the voltage at the base of Q2 at

R3
VB2 = VCC (2.39)
R1 + R2 + R3

The emitter potentials are

VE1 = VB1 − VBE1 (2.40a)
VE2 = VB2 − VBE2 (2.40b)

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For the collector currents
VB1 − VBE1
IC2 ' IE2 ' IC1 = (2.41)
RE1 + RE2
The collector voltages are given by

VC1 = VB2 − VBE2 (2.42a)

VC2 = VCC − iC2 RC (2.42b)

The current through the biasing resistors is given by

VCC
IR1 ' IR2 ' IR3 = (2.43)
(R + 1 + R2 + R3 )

and the base currents are given by

IB1 = IC1 /β1 (2.44)

IB2 = IC2 /β2 (2.45)

2.3.4 Feedback Congured Amplier

The amplier of Fig. 2.17(a) used the feedback transistor conguration between transistors Q1
and Q2 . Note that the collector of Q2 feeds back into the emitter of Q1 .Fig. 2.17(b) is the dc
equivalent circuit to be used for analysis. For transistor Q2 , the base and collector currents are

IB2 = IC1 = β1 IB1 , IC2 = β2 IB2

so that
IC2 ' IE2 = β1 β2 IB1 (2.46)
The collector current IC is

IC = IE1 + IE2 ' β1 IB1 + β1 β2 IB1

= β1 (1 + β2 )IB1

⇒ IC ' β1 β2 IB1 (2.47)

We may apply Kircho's law from the supply VCC to ground on the input side of the amplier,
Fig. 2.17(b):

VCC − IC RC − VEB1 − IB1 RB = 0

or VCC − VEB1 − β1 β2 IB1 RB = 0

so that
VCC − VEB1
IB1 = (2.48)
RB + β1 β2 RC
The base voltages are
VB1 = IB1 RB (2.49a)
VB2 = VBE2 (2.49b)
The collector voltage VC2 = VE1 and

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 Figure 2.17: Feedback congured amplier: (a) circuit (b) dc equivalent of (a)

VC2 = VCC − IC RC (2.50a)

VC1 = VBE2 (2.50b)
For this case,
VCE2 = VC2 as E2 is grounded (2.51a)
VEC1 = VE1 − VC1 (2.51b)
⇒ VEC1 = VC2 − VBE2 (2.51c)

2.3.5 Direct Coupled Amplier

A Direct Coupled amplier such is shown in Fig.2.18(a). Note that in comparison with the RC-
coupled amplier of subsection 2.3.1, there is no capacitor between the collector of Q1 and the
base of Q2 . The purpose of coupling capacitors is to isolate the dc components of each stage. For
this amplier, the dc levels in one stage will directly aect the dc levels in succeeding stages. The
benet is that the coupling capacitor (like Cc in Fig. 2.14(a)) typically limits the low-frequency
response of the amplier. Without coupling capacitors, the amplier in Fig. 2.18(a) can amplify
signals of very low frequency  in fact down to dc. The disadvantage is that any variation in dc
levels due to a variety of reasons in one stage can aect the dc levels in the succeeding stages of
the amplier - instability in the operating point. Fig. 2.18(b) is the dc equivalent circuit of Fig.
2.18(a). For Q1 ,
ET h − VBE
IB1 = (2.52a)
RT h + (1 + β1 )RE1
R1 R2
where RT h = R1 ||R2 = (2.52b)
R1 + R2
R2
ET h = VCC (2.52c)
R1 + R2

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Figure 2.18: (a) Direct-Coupled Amplier Circuit (b) dc equivalent circuit of (a)

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2.4 Problems

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