8085

INTERRUPTS
Classification of 8085 Interrupts & its
priorities
Interrupt: It is a mechanism for suspending the normal execution of the processor in order to service an
I/0 device (hardware interrupts) or an instruction (software interrupts).
An interrupt is a Signal send by an external device to the microprocessor to request the processor to
perform a particular task or work. it is a simple routine program that keeps a check for the occurrence
of the interrupt.
Mainly in the microprocessor-based system the interrupts are used for data transfer between the
peripheral (I/0) and the microprocessor.
If the microprocessor accepts the interrupt and sends the INIA (active Low) signal to the peripheral.
When the interrupt is received, the microprocessor suspends its current activity and upon completion,
it resumes the suspended activity. The processor executes an interrupt service routine (SR) addressed in
the program counter. It returned to the main program by RET instruction. The advantage is that
microprocessors need not waste time in polling the devices.
 Interrupt Process
1. MPUs check all interrupt lines during the execution of each instruction when executing programs.
2. Whenever a processor's Interrupt line is enabled, it completes the current instruction execution.
3. The processor will select the request with the highest priority if more than one lines are enabled
simultaneously.
4. As soon as the current instruction is completed, the processor checks for the respective conditions
for the selected switch interrupt if there is more than one.
5. Upon receiving a request, if the condition is not favorable, the request is discarded or stored; on the
other hand, if the condition is favorable, an internal acknowledges signal or external INTA signal is
generated and an RST (restart) instruction is inserted or the vector location is set.
6. In this case, the processor saves the address of the next instruction (program counter value) on the
stack and switches to the vector or RST location based on that address.
7. The service routine, which uses RET as its last instruction, returns control to the main program by
retrieving the return address from the stack.
Types of Interrupts
There are two types of interrupts in the 8085 microprocessors.

Software Interrupt
◦ [RST-restart]

Hardware Interrupt
◦ TRAP
◦ RST7.5
◦ RST6.5
◦ RSTS.5
◦ INTR
 Software Interrupt
Software-controlled interrupt, is an instruction-based interrupt. This instruction can be used by the

programmer to execute interrupts in the main program.

There are eight software interrupts available in microprocessors that are RSTO to RST7, The vector
address for these interrupts can be calculated as
Interrupt number * 8 = vector address
For RST 5*8 = 40(in decimal) =28h (in Hex)
Vector address for interrupt RST 5 is 0028H. This vector address is stored in the Program Counter (PC).
The instructions allow program control to be transferred from the main program to a predefined service
routine, also known as an ISR (Interrupt Service Routine)
Software Interrupt
For example, output to the screen, execute file etc.
◦ A system call to read or write data to a file
◦ A division by zero exception
◦ A page fault exception
 Hardware Interrupts
Interrupts are activated by peripheral devices by activating their respective pins. A microprocessor
transfers control to an interrupt service routine in response to an interrupting request. ISR routines
complete the task. This task might involve reading data, writing data, uploading statuses, updating
counters, etc. Upon completion of the task, control is returned to the main program. It is called Hardware
Interrupt when microprocessor pins are used to receive interrupt requests.
The 8085 Microprocessor has five hardware interrupts.
◦ TRAP
◦ RST 7.5
◦ RST 6.5
◦ RST 5.5
◦ INTR
 Types of hardware
Maskable interrupts (Can be delayed or rejected):
An interrupt that can be disabled by software,
meaning that we can disable the interrupt by sending appropriate instructions, is called a maskable
interrupt. RST 7.5, RST 6, RST 5.5, INT R are examples of Maskable Interrupts.

Non-Maskable Interrupts (Cannot be delayed or rejected):

An interrupt that cannot be disabled by instruction is called a non-maskable interrupt.

TRAP interrupt is the non-maskable interrupt for 8085,It means that if an interrupt comes via TRAP,
8085 will have to recognize the interrupt and we cannot mask it
 Interrupts can also be classified into
Vectored (the address of the service routine is hard-wired) : In vectored interrupts, the processor
automatically branches to the specific address in response to an interrupt. In vectored interrupts,
the manufacturer fixes the address of the ISR to which the program control is to be transferred.
The TRAP, RST 7.5, RST 6.5, and RST 5.5 are vectored interrupts.

Non-Vectored (the address of the service routine needs to be supplied externally by the device):
In non-vectored interrupts the interrupted device should give the address of the interrupt service
routine (ISR). The INTR is a non-vectored interrupt. Hence when a device interrupts through INTR, it
has to supply the address of ISR after receiving the interrupt acknowledge signal.
 classification of 8085 interrupts is based
on Priority
In the 8085 Microprocessor, there are five interrupts, and the following are the priority.
The table below shows 1 means highest príority whereas 5 mean lowest priority.

In above table we can see that TRAP has highest priority and INTR has lowest priority in all
interrupt.
 8085 Vectored Interrups Trap, RST 7.5,
RST 6.5, RST 5.5 and RST Instruction
Vectored interrupts require the IVA (interrupt vector Address) should supplied by the external device that
gives the interrupt signal. This technique is vectoring. And it can be implemented in a number of ways. The
interrupts (TRAP, RST 7.5, RST 6.5 and RST 5.5) are also called vector interrupts. As each interrupt has fixed
memory location (vector location) for the transfer of control from the normal execution of the routine.
The vector locations of these interrupts shown in table.
 TRAP
This interrupt is a Non-maskable interrupt. It is unaffected by mask or interrupt enable, TRAP has the
highest priority and vectored interrupt (as the vector address is fixed, i.e., location in memory where
control is to be transferred).

TRAP interrupt is edge and level triggered. This means that the TRAP must go high and remain high until
acknowledged. In Sudden power failure, it executes an ISR and sends the data from the main memory to
back up memory. HOLD IS the Signal that overrides TRAP.

(i.e., If the process or receiver receives HOLD and TRAP at the same time then HOLD is recognized first and
then TRAP is recognized).
However, TRAP has lower priority than the HLD signal used for DMA. There are two ways to clear a TRAP
interrupt.
◦ By resetting the microprocessor (External signal)
◦ By giving a high TRAP ACKNOWLEDGE (internal signal).

After recognition of TRAP interrupt 8085 internally generates a high TRAP ACKNOWLEDGE which clears

The flip flop. Once the TRAP is acknowledged, the 8085 completes its current instruction. It then pushes
the Address of the next instruction i.e., return address onto the stack and loads the PC with the fixed
vector address 0024H. Due to this, 8085 starts execution of instructions from address 0024H which is the
starting address of an interrupt service routine for TRAP.
Application : It is used for emergency purposes like power failure, parity error checker, smoke detector,
etc.
 RST 7.5
RST 7.5

It is maskable and vectored interrupt with second priority can be executed by satisfying the following
conditions: execution El (Enable Interrupt) instruction in program does not mask this interrupt, don't
execution DI (Disable Interrupt) before execution this interrupt, and microprocessor don't perform any
other interrupt, before supplying positive edge triggered on pin 7 of microprocessor. After completing
execution of the current instruction, the microprocessor loads PC with vectored address 003C and stores
the PC contents in stack memory.
RST 6.5
It is maskable and vectored interrupt with third priority can execute by satisfying the following
conditions: execution El (Enable nterrupt) instruction in program, not mask this interrupt, don't
execution DI (Disable Interrupt). Before execution this interrupt and microprocessor is don't run
any other interrupt, before supplying level triggered signal on pin 8 of microprocessor. In
response to this interrupt, the microprocessor loads PC with vectored address 0034 after
completing the current instruction and stores the contents of PC in stack mermory after it has
completed executing the current instruction.
RST 5.5 interrupt
It is maskable and vectored interrupt with fourth priority can execute by satisfying the following
conditions:

execution El (Enable Interrupt) instruction in program is not mask this interrupt, don't execution
DI (Disable Interrupt) before execution this interrupt, and microprocessor is don't run any other
interrupt.

before supplying level triggered signal on pin 9 of microprocessor. When this interrupt is
activated, the micronrocessor loads PC with vectored address 002C after complete execution of
current instruction and stores the PC contents in stack memory.
RST instruction
The RSTn acronym stands for "Restart n". In this case, n can only have a value between 0 and 7.
As a result, there are eight possible RST instructions: RST 0. RST 1... RST 7. it is a 1-byte call
instruction. The RST n n instruction functions similarly to:

RST n = CALL n*8

Let us consider RST 4 is functionally equivalent to
CALL 4*8, i.e. CALL 32 = CALL 0020H.
RST 2 has the advantage of being only 1 byte long,
whereas CALL 0010H is 3 bytes long.
As a result, RST instructions are useful for branching to frequently used subroutines.
RST 4
An example of this type of instruction is RST 4. This is a 1-byte instruction.

CALL O020H = PUSH PC + JMP 0010H has the same functionality.

A subroutine is branched from memory address 0020H.

Similarly, RST 5 triggers a subroutine at 5*8 = 0028H. Hence, the subroutine starting at 0020H
should not go beyond 0027H in memory. Only eight locations are available for the subroutine,
which is too small for the subroutine bodies in general. By branching to a subroutine at another
memory location, such as 4050H, this limitation can be overcome. By combining RST 4 and JMP
4050H instructions at memory location 0020H, it is possible to accomplish this.
 8085 Non-Vectored Interrupts : INTR
Non-Vectored Interrupts: In this type of 8085 interrupt, the interrupt address is not known to the
processor so; the interrupt address needs to be sent externally by the device to perform interrupts For
example, INTR.

INTR

INTR is a maskable interrupt. It is a non- vectored interrupt. After receiving INTR, the peripheral has to
supply the address of. It has the lowest priority. It is a level triggered. i.e., Input goes to high and it is
necessary to maintain high state until it is recognized and acknowledged.
 Process of INTR interrupt
1. With the use of the El instruction, the interrupt process should be enabled.
2. Whenever an instruction is executed, the 8085 checks for an interrupt signal.
3. If INTR is high, the microprocessor completes the current instruction, disables the interrupt, and sends
INTR' signal to the peripheral device.
4. INTR' allows the peripheral device to send an RST instruction through data bus.
5. Upon receiving the INTR' signal, the microprocessor saves the memory location of the next instruction on
the stack, and the program is transferred to the 'call' location (ISR Call) specified by the RST instruction.
6. The microprocessor executes the ISR.
7. Within the program, in order to enable further interrupt, ISR must include the ‘El’ instruction.
8. The RET instruction at the end of the ISR retrieves the return address from the stack and the program is
transferred back to the main program which was interrupted.
Thank you