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Hds WKB 2015.1 073384

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fengke930311

We take content rights seriously. If you suspect this is your content, claim it here.

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HDL Designer Series™

Student Workbook

© 1991-2015 Mentor Graphics Corporation

This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors
and is subject to license terms. No part of this document may be photocopied, reproduced, translated, distributed,
disclosed or provided to third parties without the prior written consent of Mentor Graphics..
This document is for information and instruction purposes. Mentor Graphics reserves the right to make
changes in specifications and other information contained in this publication without prior notice, and the
reader should, in all cases, consult Mentor Graphics to determine whether any changes have been
made.

The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in
written agreements between Mentor Graphics and its customers. No representation or other affirmation
of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor
Graphics whatsoever.

MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.

MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR
CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS)
ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT,
EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES.

RESTRICTED RIGHTS LEGEND 03/97

U.S. Government Restricted Rights. The SOFTWARE and documentation have been developed entirely
at private expense and are commercial computer software provided with restricted rights. Use,
duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to the
restrictions set forth in the license agreement provided with the software pursuant to DFARS 227.7202-
3(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - Restricted
Rights clause at FAR 52.227-19, as applicable.

Contractor/manufacturer is:
Mentor Graphics Corporation
8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
Telephone: 503.685.7000
Toll-Free Telephone: 800.592.2210
Website: www.mentor.com
SupportNet: supportnet.mentor.com/
Send Feedback on Documentation: supportnet.mentor.com/doc_feedback_form

TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of
Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the
prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a third-
party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to
indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics’
trademarks may be viewed at: www.mentor.com/trademarks.

End-User License Agreement: You can print a copy of the End-User License Agreement from:
www.mentor.com/eula.

Part Number: 073384

Table of Contents

Module 1
The Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Overview of Mentor Graphics FPGA Design Product Names . . . . . . . . . . . . . . . . . . . . . . . 14
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
What Is HDL Designer? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Supported Platforms and OS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Complete HDL Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
“Standard” Windows Look and Feel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Getting Help: HDS InfoHub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Getting Help: Launch Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
What Is HDL Designer Suitable for?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Where Does HDL Designer Fit in the Design Flow? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Preparing to Use HDL Designer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
The Design Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
The Design Manager – Setup Assistant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
The Design Manager – Basic Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
The Design Manager – Project Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Project Manager – My Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Project Manager – Shared Project Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Project Manager – Open Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Concept of Library/Unit/View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Design Manager – Design Explorer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Design Explorer – Design Unit Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Design Explorer – Source File Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Design Explorer – Logical Object Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Design Explorer – Hierarchy Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Main Icons in the Design Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Manipulations in the Design Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
HDL Designer Design Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
How Does HDL Designer Find These Directories? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Example Project File – Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Create and Modify Library Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Side Data Sub Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Downstream Sub Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Tasks and Templates Sub Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
What Is the Flow Through HDL Designer?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Create a Design Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Create a Design Unit – Bottom-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Create a Design Unit – Top-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Lab 1: Testing and Synthesizing a BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

HDL Designer Series 3

Table of Contents

Module 2
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
What Is a Block Diagram?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
How to Create a Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Block Diagram Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Design Objects: Blocks and Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Add Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Add Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Add ModuleWare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Add Signal Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Make Connections: Bus Ripper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Make Connections: Bundle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Add Port Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Block Diagram Objects Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Interactive Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Make Connections Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Block Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Component Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
User Declarations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Object Visibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Add Comment Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Add Comment: Include Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Add Comment: Using Text Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Page Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Add Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Visualize/Edit IBD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Block Diagram Master Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Block Diagram Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Package References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Navigate Through Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Navigate: Going Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Navigate: Going Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Navigate: Back/Forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Navigate: Using Strokes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Reconcile Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Hierarchical Net Highlight. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Hierarchical Net Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Hierarchical Net Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Re-Level – Add Hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Re-Level – Remove Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Saving the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Lab 2: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Module 3
State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

4 HDL Designer Series

Table of Contents

How to Create a State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

State Machine Styles: Moore versus Mealy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
State Machine Styles: Moore/Mealy/Mixed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
State Diagram Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
State Diagram Objects: Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
FSM Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Re-Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
State Properties: IF/CASE, Actions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Transition Properties: Condition, Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Junction/Link Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
State Machine: Clocks, Resets, and Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
State Machine Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
State Machine Properties: Generation – VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Declarations and Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
State Machine Properties: Statement Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
State Machine Properties: Architecture Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
State Machine Properties: Process Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
State Machine Properties: Encoding – VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Creating “Hard” Encoded “Safe” State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
State Machine Properties: Generation – Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
State Machine Properties: Encoding – Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Signal Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Logic Location in Generated HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Registered versus Clocked Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Register State Actions on Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
How to Choose Which Output Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Output Assignment Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Concurrent State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Concurrent State Machines: Renaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Expression Builder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
State Machine Preferences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Module 4
Design Creation Editors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Design Creation Editors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DesignPad: Design-Aware Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
DesignPad: Fully Integrated, Design-Aware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
DesignPad: Rapidly Navigate HDL Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
DesignPad: Comparing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
DesignPad: Column Editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
DesignPad: Powerful Editing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
DesignPad: Fully Customizable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
What Is a Flow Chart? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
How to Create a Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Flow Chart Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Flow Chart Objects: Start and End Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Flow Chart Objects: Action and Decision Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

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Flow Chart Objects: Case Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Flow Chart Objects: Wait Boxes and Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Adding Objects on a Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Flow Chart Preferences: Invocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Flow Chart Preferences: Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Flow Chart: Object Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Object Properties — VHDL: Action, Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Object Properties — VHDL: Wait, Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Object Properties — VHDL: If . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Object Properties — Verilog: Action, Case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Object Properties — Verilog: Wait, Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Object Properties — Verilog: If. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Flow Chart Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Flow Chart Properties: VHDL Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Flow Chart Properties: Architecture Declarations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Flow Chart Properties: Concurrent Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Flow Chart Properties: Process Declarations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Flow Chart Properties: Verilog Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Flow Chart Properties: Module Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Flow Chart Properties: Concurrent Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Flow Chart Properties: Local Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Hierarchical Flow Charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Concurrent Flow Charts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
How to Create a Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Truth Table Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Editing and Formatting Table Cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Truth Table Properties: Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Truth Table Properties: Global Actions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Truth Table Preferences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Module 5
Editing Symbols/Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
How to Create a New Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
How to Edit a Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Symbol Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Symbol Editor Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Symbol Autoshapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Symbol Editor: Equidistant Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Symbol Editor: Custom Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Symbol Editor: Custom Symbol Graphics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Symbol Editor: Custom Symbol Appearance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Symbol Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Interface Editor: Invocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Interface Editor: Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Editing Generic Declarations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Editing Local Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

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Lab 3: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Module 6
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Test Bench: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Test Bench: Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Test Bench: Stimuli and Checkers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Test Bench: Wait Statement in Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Simulators Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Debug in HDL Designer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Debug: Simulator Set Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Debug: Simulator Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Debug: Log Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Debug: Simulation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Debug: Block Diagram/IBD/SM Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Probe: Block Diagram/IBD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Breakpoint: Block Diagram/IBD/FC-SM Editors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Enable Animation: Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Enable Animation: State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Animation Tools: Flow Chart/State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Activity Trail: State Machine / Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Goto: Flow Chart/State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Optimization and HDL Designer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Code Coverage Simulation Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Code Coverage with HDL Designer - Method 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Code Coverage with HDL Designer - Method 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Code Coverage with HDL Designer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Coverage Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Coverage +cover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Lab 4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Module 7
Version Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Version Management Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
HDL Designer Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Check In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Check Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Get . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Change Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Synchronize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Version Management Tasks Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
When to Use Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

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Interface with Subversion (SVN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

SVN Repository . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Setup SVN in HDL Designer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Organizing HDL Libraries within Repository . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Commit in SVN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Editing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Editing the Design - Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Editing the Design - Commit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Getting Specific Version of the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Reverting Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
What Type of Objects do we Need to Lock?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Handling Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
SVN Workspace Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Checking Out the Workspace Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Adding the Workspace Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Committing the Workspace Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Reverting Changes in the Workspace Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Updating the Workspace Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Reporting the Status of the Workspace Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Module 8
Add HDL Files/Visualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Add Existing HDL Files – Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Add Existing HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Add Existing HDL Files: Step 2 – File Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Add Existing HDL Files: Step 3 – Target Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Add Existing HDL Files: Step 4 – Target Directories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Design Explorer with Imported Design Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Understanding Visualization versus Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Visualize Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Visualize Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Visualization Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Alternate Step – Convert to Graphics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Interactive Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Lab 5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Module 9
IP and Vendor Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Top-Down Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Using HDL Designer for Top-Down Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Mixing Top-Down With Bottom-Up Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
What Is ModuleWare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
ModuleWare – Dynamic # of Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
ModuleWare – Settings Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
ModuleWare – Automatic Port Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
ModuleWare – In-Place Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

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Table of Contents

ModuleWare – Language Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

FPGA Vendor IP Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
FPGA Tool Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
FPGA Tool Integration – Xilinx CoreGen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
FPGA Tool Integration - Xilinx Vivado . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Xilinx Vivado Wizard – Flow Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Xilinx Vivado Wizard – Setup Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Xilinx Vivado Wizard – Create/Update Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Xilinx Vivado Wizard – Compile Simlib Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Xilinx Vivado Wizard – Import IP Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Import Vivado IP Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
FPGA Tool Integration - Altera. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Add Gate Level Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Simulation Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Lab 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

Module 10
Setup and Team Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Resource Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Team Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Resource Settings: User / Team. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Setting Up for Teams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
User and Team Resource Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Resource Settings: Location (Ref. Page) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Team and User Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Main Settings: General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Main Settings: Text Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Main Settings: Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Main Settings: Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Main Settings: Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Main Settings: User Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Code Generation Preferences – VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Code Generation Preferences – Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
User Template Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
User / Team Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
User/Team Templates and Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Version Management Team Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

Module 11
DesignChecker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Introducing Static Design Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
What Types of Checks Can Be Performed? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Understanding the Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
DesignChecker Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Understanding Base Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

HDL Designer Series 9

Table of Contents

Built-In Rulesets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

Quickly Build Own Rulesets (Designer/Manager) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
DesignChecker Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Getting Help on Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Editing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Creating a Policy (Designer/Manager) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Launching DesignChecker (Designer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Examine the Results (Designer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Results Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Interact With the Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Fix Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Trace to Graphics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Trace to HDL Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Using the Code Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
DesignChecker Viewpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Export Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

Module 12
Interface Based Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Interface Based Design: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Interface Based Design: Overview (cont.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Interface Based Design: Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
IBD Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
IBD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Hide/Show Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Filter Columns/Rows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Filter Rows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Create Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Visualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Net-Centric Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Port-Centric Connectivity – Unconnected Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Quick Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Signal Busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Bundles in IBD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Port Map Expression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Generate Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Adding a Level of Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Adding Requirement References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

Module 13
Documentation and Viewpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Documentation Using OLE: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Documentation Using OLE: Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Documentation Using OLE: Drag Bar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Documentation Using OLE: Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

10 HDL Designer Series

Table of Contents

Documentation Using OLE: Link or Copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

Documentation Using OLE: File Registration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
Documentation Without OLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Documentation Using HTML: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
Documentation Using HTML: Invocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Documentation Using HTML: Hierarchy Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Documentation Using HTML: HTML Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Documentation Using HTML: Graphics Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Documentation Using HTML: Browser View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Viewpoints – Visualize Design Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Viewpoint Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Viewpoint – Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Viewpoint – Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Viewpoint – Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Find – Advanced Find . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Report Where Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Report Unbound Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Lab 7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

Appendix A
Tracing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
What Is ReqTracerTM? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
ReqTracer Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Sample Requirement Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
ReqTracer: Management View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
ReqTracer: Coverage Analysis View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
ReqTracer: Impact Analysis View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
ReqTracer: Graphical View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
ReqTracer Integration with HDL Designer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Enabling Requirements Referencing – ReqTracer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Enabling Requirements Referencing – HDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Defining Requirement References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
Adding Requirement Reference – Graphical Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Pasting Requirement Reference – Graphical Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
Setting Display Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Generating HDL from Graphical Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
Refreshing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Examining and Locating Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
ReqTracer Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

HDL Designer Series 11

Table of Contents

12 HDL Designer Series

Module 1
The Basics

Objectives
Upon completion of this module, you will be able to:

• Explain a general introduction to HDL Designer

• Understand the Design Manager
• Understand the Project Manager
• Understand the Launch Pad
• Know how to access the Side Data/Downstream windows
• Explain the concept of Library/Unit/View
• Understand the concepts of Design Unit Creation within HDL Designer

HDL Designer Series 13

The Basics
Overview of Mentor Graphics FPGA Design Product Names

Overview of Mentor Graphics FPGA Design Product Names

• HDL Designer • Precision RTL

• Visual Elite HDL • Precision RTL Plus
• HDL Author • Precision Physics
ReqTracer®

Precision RTL Plus

HDL Designer

• ModelSim®
• Questa® Advanced
• HDL Designer
Simulator
• Precision RTL Plus • Mentor® Verification IP
1-2 • HDL Designer Series: The Basics Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

14 HDL Designer Series

The Basics
Notes

Notes

Notes
♦ HDS stands for HDL Designer Series. This is the suite of
products which includes HDL Designer. However this
acronym will be often used throughout the document in place
of HDL Designer to make it shorter

♦ RMB stands for Right Mouse Button

♦ LMB stands for Left Mouse Button

♦ DU stands for Design Unit

Notes:

HDL Designer Series 15

The Basics
What Is HDL Designer?

What Is HDL Designer?

♦ A mixed text and graphics design environment for:
 Design creation — rapid entry method: text, tabular, graphical.
 Design reuse — establish design integrity, discover design.
 Design checker — track down syntax, semantic, runtime errors.
 Documentation — create documents for internal and external
customers.
 Downstream tool integration — built-in Mentor Graphics, 3rd-
party, FPGA vendor tool integration.
♦ Suitable for both FPGAs and ASICs.
♦ Available on Windows and Linux platforms.
♦ Capable of writing VHDL, Verilog, or mixed language.
♦ Capable of reading and tracing dependencies for VHDL,
Verilog, and SystemVerilog.
♦ A “Plug-and-Play” solution.

Notes:

16 HDL Designer Series

The Basics
Supported Platforms and OS

Supported Platforms and OS

♦ Single source application — Windows and Linux
♦ Identical functionality
♦ Guaranteed inter-operability
♦ Simultaneous release

Windows Red Hat

Enterprise
Linux 5/6

Notes:

HDL Designer Series 17

The Basics
Complete HDL Design Environment

Complete HDL Design Environment

♦ System Verilog Assistant is an

EDA tool that provides an
RTL-
based SystemVerilog excellent environment for
Structured Assistant testing, creating and modifying
Flow
Verilog and SystemVerilog
designs.

Design Register
Checking Assistant

♦ Register Assistant is a register

♦ Are only included in HDL management tool that allows
Designer. making changes to register
specifications and automatically
generate a number of derived
♦ The operation of both tools is outputs.
outside the scope of this class.

Notes:

18 HDL Designer Series

The Basics
“Standard” Windows Look and Feel

“Standard” Windows Look and Feel

♦ On all platforms
the same
behavior

Notes:

HDL Designer Series 19

The Basics
Getting Help: HDS InfoHub

Getting Help: HDS InfoHub

Help > Help and Manuals [F1]
♦ Access to multiple Manuals and Application Notes available in HTML and PDF format
♦ Provides searching of all HTML content
♦ Direct access to the HDL Designer SupportNet site to check for software updates,
technical notes, and application notes

Notes:

20 HDL Designer Series

The Basics
Getting Help: Launch Pad

Getting Help: Launch Pad

View > Sub Windows > Launch Pad

♦ A guide to help with HDL

Designer flow
 Design Creation/Import
 Design Visualization,
Navigation, and
Checking
 Running Tasks
 Projects
 What’s new in HDL
Designer
♦ Launch Task
♦ Watch Demo

Notes:

HDL Designer Series 21

The Basics
What Is HDL Designer Suitable for?

What Is HDL Designer Suitable for?

Graphical Block Based Text Based

Design Design Design
♦ Designs can be represented Graphically as:
 Block Diagrams
 State Transition Diagrams
 Flow Charts
 Interface Based Design Tables
 Truth Tables … or Text Based as HDL files

Notes:

22 HDL Designer Series

The Basics
Where Does HDL Designer Fit in the Design Flow?

Where Does HDL Designer Fit in the Design Flow?

Consider a typical design flow (i.e. FPGA):
HDL Designer HDL Designer

1
Design
 VHDL
Verilog
Test
Bench
2 
VHDL
Verilog

3
ModelSim

Precision RTL ModelSim Design Sequences

1. Capture RTL Design


2. Capture Test Bench
EDIF
3. Simulate RTL Design
4 7 4. Synthesize and Optimize Design


5. Place and Route Design
FPGA Vendor 6
HDL 6. Generate Back-annotated HDL
Place and Route Vital + SDF
7. Simulate Design with timing

5
EDIF

 Precision RTL HDL Designer Used Here

Notes:

HDL Designer Series 23

The Basics
Preparing to Use HDL Designer

Preparing to Use HDL Designer

Each of these topics will be discussed in the following slides:

♦ Design Manager - Setup Assistant

♦ Design Manager - Basic Layout
♦ Design Manager - Project Manager
♦ Project Manager - Project Files
♦ Concept of Library/Unit/View
♦ Design Manager - Design Explorer
♦ HDL Designer Design Data Structure

Notes:

24 HDL Designer Series

The Basics
The Design Manager

The Design Manager

♦ Main “cockpit” for controlling HDS design flows
♦ Full control over window, menu, and toolbar visibility
♦ Represent, access, and organize all aspects of the design
♦ Easy navigation of design
 Helps organization
 Aids understanding
♦ Management of design (tasks, filters, etc.)
♦ Tools and Flows
♦ Templates
♦ Version Control (individual repositories)

Notes:

HDL Designer Series 25

The Basics
The Design Manager – Setup Assistant

The Design Manager – Setup Assistant

♦ The HDS Setup Assistant Wizard guides you through
the configuration of HDL Designer Series tool.
♦ Automatically invoked
upon first HDL Designer
invocation.
♦ Walk down the tree
answering questions and
specifying information.
♦ Sets up the project.
♦ Create a new project
using the Assistant.
♦ Change setup at any
time:
Help > HDS Setup Assistant

Notes:

26 HDL Designer Series

The Basics
The Design Manager – Basic Layout

The Design Manager – Basic Layout

Menu Bar The Design Manager – Basic Layout

♦ Access commands
via:
 Menu Bar
 Tool Bar
 Shortcut Bar
Tool Bar  Popup Menu
 Sub browser
window tabs
Sub browser tabs
♦ Status bar provides
Popup Menu [RMB] information about the
current status of the
associated window /
command / warning.

Shortcut Bar Status Bar

Notes:

HDL Designer Series 27

The Basics
The Design Manager – Project Manager

The Design Manager – Project Manager

♦ Edit/show library mappings within a

given project (.hdp) and open
alternative project files.
♦ Create new projects and specify the
libraries contained in your project
using a wizard.
♦ Libraries are grouped by type, by
default Regular work libraries are
expanded.
Library Types
• Regular: where you do all your work
• Protected: reusable, referenced, but cannot modify
• Downstream: compiled libraries, no sources in HDS

♦ Open Design Explorer windows on

any number of libraries simply by
double-click or “Explore”.
♦ Perform data/design management
operations on mappings and libraries.

Notes:

28 HDL Designer Series

The Basics
Project Manager – My Project File

Project Manager – My Project File

♦ “My Project” contains information about the libraries
used in a project.
♦ It also contains a reference to a Shared project file
(see next page).
♦ Can display My Project and/or Shared Project
mappings.
♦ My mappings override Shared if there is a conflict.
♦ New projects can be created using “New Project”
wizard.

♦ Open other projects using “Open Project”.

♦ Can also “Close Project”.

Notes:

HDL Designer Series 29

The Basics
Project Manager – Shared Project Files

Project Manager – Shared Project Files

♦ Shared project files typically contain:
 Mappings for project-wide libraries (vendor libraries, ieee, IP, etc.)
 Mappings for project-wide VM repositories.
♦ Shared Mappings shown by icon.
♦ The location is stored in My Project.
♦ Default location is in the Team Preferences
tree: $HDS_TEAM_HOME/shared.hdp.
♦ To edit shared mappings, must switch
into “Edit Shared Project” (RMB over
Shared Project) mode:
 File maybe made read-only by
Project Manager.

 Only Shared mappings are visible.

Notes:

30 HDL Designer Series

The Basics
Project Manager – Open Project

Project Manager – Open Project

♦ Lists last 10 projects opened.
♦ Shows Name, Description and Location (directory).
♦ Choose from list or Browse to find another Project file.

Notes:

HDL Designer Series 31

The Basics
Concept of Library/Unit/View

Concept of Library/Unit/View

Concept of Library/Unit/View
♦ HDL Designer is built on a concept of Library/Unit/View.
 This is analogous to the structure of Library/Entity/Architecture
in VHDL.
 There can only be one interface per Design Unit. Therefore, there
can only be one Design Unit of a given name per Library.
 There may be multiple views per Unit. The same View name may
be used in different Units.
 To use the same Unit name with a different interface, the new Unit
must be stored in a different Library.

library  x 
y

unit a b a a

view rtl zzz rtl rtl zzz

x
1-20 • HDL Designer Series: The Basics Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

32 HDL Designer Series

The Basics
Design Manager – Design Explorer

Design Manager – Design Explorer

♦ The Design Explorer allow you to explore the content of the
libraries within a project.

New Tabs for Libraries

Double-click or use RMB >
Explore Library

Notes:

HDL Designer Series 33

The Basics
Design Explorer – Design Unit Browser

Design Explorer – Design Unit Browser

Library ♦ Represents graphical

and text components
as Design Units
 Shows logical
content down to
leaf-level
Views  Hierarchy shown in
separate pane

Design Units ♦ Shortcuts:

 Drag and drop
 Expand/Collapse:
Spacebar

Notes:

34 HDL Designer Series

The Basics
Design Explorer – Source File Browser

Design Explorer – Source File Browser

♦ Shows actual file structure on

disk under HDL mapping.
♦ Also shows logical content of
files.
♦ Source files indicated with
(“S”) organized in this example
into RTL/Verilog, RTL/VHDL
and Testbench.
♦ Manage files and folders within
the HDL structure.

Notes:

HDL Designer Series 35

The Basics
Design Explorer – Logical Object Browser

Design Explorer – Logical Object Browser

♦ Multi-column list format.
♦ Graphical and textual design units.
♦ Sort, group, filter, and search by name or attributes.
♦ Save sorting, grouping, and filtering rules in viewpoints.

Notes:

36 HDL Designer Series

The Basics
Design Explorer – Hierarchy Pane

Design Explorer – Hierarchy Pane

♦ Shows the logical design hierarchy
from one or more specified root
points
♦ Default view used unless otherwise
specified for a given instance
♦ Hierarchy pane auto-hides if no
hierarchy displayed
♦ Shortcuts:
 Expand/Collapse: Spacebar
 Drag and drop or use Shortcut
♦ Configurations:
 Can show hierarchy from a
configuration
Unbound components  Color shows
show up red
use of
configuration

Notes:

HDL Designer Series 37

The Basics
Main Icons in the Design Explorer

Main Icons in the Design Explorer

♦ Library ♦ State Diagram view
 Expanded  Normal
 Collapsed  Concurrent
♦ Block design unit ♦ ModuleWare
♦ Component design unit  Design Unit
 Symbol
♦ Symbol for component interface
♦ HDL Model
♦ Block Diagram view  VHDL entity
♦ IBD view  VHDL architecture
♦ Flow Chart view  Configuration declaration
 Normal  VHDL package header
 Concurrent  VHDL package body
♦ Truth Table view  Verilog file
 Verilog module
♦ Configuration design unit
 Verilog Include
♦ Package design unit  Generate frame

Notes:

38 HDL Designer Series

The Basics
Main Icons in the Design Explorer

Main Icons in the Design Explorer (Cont.)

♦ Icon overlay
 Don’t touch
 Default view
 Foreign view
 Gate level
 Top marker
 Read-only
 Reference
 Design Root
 HDL parser
errors
 HDL source

♦ Plain Text file

♦ Unknown DU
♦ Unknown view

Notes:

HDL Designer Series 39

The Basics
Manipulations in the Design Explorer

Manipulations in the Design Explorer

♦ On a design unit or design unit view basis
you can:
Paste Special for Copy.
 Cut (Move) [Ctrl+X] or Copy [Ctrl+C]
– Invalid locations indicated by
 Delete [Del]
 Rename [F2]
 Paste [Ctrl+V]
 Paste Special

♦ The Cut and

Copy can be
hierarchical
The Copy Special Options
and through and Move Special Options
components Paste Special for Cut (Move). dialog boxes appear when
pasting with “Paste Special”.

Notes:

40 HDL Designer Series

The Basics
HDL Designer Design Data Structure

HDL Designer Design Data Structure

HDL Directory (Source / Generated)

arbitrary directory structure and filenames

1. Save
HDL Designer
Design Data Directory
contains graphical data,
2. Generate side data, and meta data
(for graphical views) directory structure

3. Compile
Downstream Data Directories
any number of downstream
directories for tasks which
require working directories

Notes:

HDL Designer Series 41

The Basics
How Does HDL Designer Find These Directories?

How Does HDL Designer Find These Directories?

Through the Library Mappings in a Project file. examples.hdp

The logical library name is mapped to a physical

directory on the disk for each of the directories:

[hdl] - HDL Directory Library

Mappings
Keywords in Project file

[hds] – HDL Designer Design Data Directory

[ModelSim]
Optional
Mappings
[Precision] - Downstream Data Directories
[Leonardo]

Notes:

42 HDL Designer Series

The Basics
Example Project File – Format

Example Project File – Format

HDL Mapping

HDL Designer
Design Data
Mapping

Downstream
Mapping
(tool dependent)

logical library name

Shared Mapping

Notes:

HDL Designer Series 43

The Basics
Create and Modify Library Mappings

Create and Modify Library Mappings

♦ Create new Library using New Library Wizard.
♦ Edit mappings using Edit Mappings Wizard or directly.
♦ Two libraries must not have the same HDL/HDS mappings!
♦ Default assumes “Regular” library.
♦ Default is to automatically create mappings based on Library name,
Root directory, and default structure.
♦ Downstream mappings created automatically when needed.
♦ Changes saved to project file immediately.

Notes:

44 HDL Designer Series

The Basics
Side Data Sub Window

Side Data Sub Window

View > Sub Windows > Side Data/Downstream

♦ Design Data
 This part is used by HDS to store
some data that may be needed
later.
– ngc file generated by CoreGen.
– edif file generated by synthesis tool.
– Simulation result files.
– sdf back-annotation file for gate
level simulation.
– Tcl generated scripts.
– PSL files
♦ User Data
 Reserved for the designer to store
any kind of design relative data.
 Folders and sub-folders can be
created by the user.
 File can be copied or referenced.
♦ The Side Data contents can be
optionally versioned with the
source data.
1-33 • HDL Designer Series: The Basics Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 45

The Basics
Downstream Sub Window

Downstream Sub Window

View > Sub Windows > Side Data/Downstream

♦ Shows the objects (compiled

views, script, ini files, etc.)
created for and by the tools
invoked from HDS through
various tasks.

♦ It is tool dependent.
Use tabs to switch
between downstream
tool data.

Notes:

46 HDL Designer Series

The Basics
Tasks and Templates Sub Window

Tasks and Templates Sub Window

View > Sub Windows > Tasks and Templates ♦ Automate repetitive flow
details
 Use built-in tool flows
– ModelSim / QuestaSim
– Precision RTL Synthesis
 Use built-in 3rd-party tool
integration
– Cadence®, Synopsys®,
and others
♦ Integrate custom tools
♦ Build custom design flows
♦ Flow data stored in
Downstream directory
♦ Separate “My Tasks” /
“Team Tasks” possible
♦ “My Templates” / “Team
Templates” available for
new text files
1-35 • HDL Designer Series: The Basics Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 47

The Basics
What Is the Flow Through HDL Designer?

What Is the Flow Through HDL Designer?

There are four basic steps in using HDL Designer:

1. Create / Open a project file.

2. Edit and Save Diagram or HDL Text.

 Diagrams are edited interactively, then saved as an ASCII file.
 Each object type has a defined naming convention.

3. Generate — Generate HDL for Diagram.

 HDL code is automatically generated for the diagram in ASCII
files.

4. Compile — Prepare HDL for downstream tools.

 The HDL code is compiled for simulation, or scripts are
generated to process the HDL code for use by downstream
tools such as synthesis.

Notes:

48 HDL Designer Series

The Basics
Create a Design Unit

Create a Design Unit

♦ The creation of a design unit is an operation that is

common to the different editors.

♦ Two approaches are possible:

1) You create the Design Unit View first (Bottom-up
approach).
2) You create the interface first (Top-down approach).

Notes:

HDL Designer Series 49

The Basics
Create a Design Unit – Bottom-Up

Create a Design Unit – Bottom-Up

♦ Method #1

♦ Select in the Design Explorer

Main Shortcut Bar to open the File
Creation Wizard.
♦ Choose Block Diagram, IBD, State
Diagram, Flow Chart or Truth Table.
♦ Save it into the library of your choice.

NOTE:
It is possible to name the unit and
place it in a library as you open it.

Notes:

50 HDL Designer Series

The Basics
Create a Design Unit – Bottom-Up

Create a Design Unit – Bottom-Up (Cont.)

♦ Edit the interface.
 In the IBD and Truth Table editor use:
File > Open >
Open Up/Interface

Notes:

HDL Designer Series 51

The Basics
Create a Design Unit – Bottom-Up

Create a Design Unit – Bottom-Up (Cont.)

♦ Edit the interface.
 Use the Open Up stroke (Middle Mouse Button) in the Block Diagram,
State Machine or Flow Chart editors.

Notes:

52 HDL Designer Series

The Basics
Create a Design Unit – Top-Down

Create a Design Unit – Top-Down

♦ Method #2

♦ Start by creating the

Design Unit interface
or symbol.

♦ Save it into the library

of your choice.

Notes:

HDL Designer Series 53

The Basics
Create a Design Unit – Top-Down

Create a Design Unit View – Top-Down (Cont.)

♦ Method #2 Open > New View

♦ Open a new view of your choice.

♦ The interface defined previously is

available.
1-42 • HDL Designer Series: The Basics Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

54 HDL Designer Series

The Basics
Lab 1: Testing and Synthesizing a BCD Counter

Lab 1: Testing and Synthesizing a BCD Counter

♦ Lab Goal: Test and synthesize a BCD counter
 Part 1: Set up HDL Designer using the Setup Assistant
 Part 2: Create a project file and library mapping and browse
design
– Create a new project file
– Map local component library
– Testing environment is pre-configured
– Look at test routine
– Generate HDL code to ensure no syntax errors
 Part 3: Simulate the BCDCounter test bench
– Invoke ModelSim from Design Browser
– Run the test bench on BCDCounter
 Part 4: Synthesize the BCDCounter design
– Invoke Precision RTL from Design Browser
– Synthesize using QuickSetup Tab
– Confirm and view resulting schematics, area and timing report

Notes:

HDL Designer Series 55

The Basics
Lab 1: Testing and Synthesizing a BCD Counter

56 HDL Designer Series

Module 2
Block Diagrams

Objectives
Upon completion of this module, you will be able to:

• Introduction to Block Diagrams

• When to use Block Diagrams
• Block Diagram Design Objects
• Working in the Block Diagram Editor
• Creating and opening a Block Diagram
• Adding Blocks/Components to a Block Diagram
• Routing signals in a Block Diagram
• Adding comments
• Saving the Block Diagram

HDL Designer Series 57

Block Diagrams
What Is a Block Diagram?

What Is a Block Diagram?

♦ Similar to a Schematic
 Blocks represent collections of functionality/hierarchy.
 Blocks connected by signals.
 Provides a data flow view of the design.
– Fast generation
– Easy to understand
 Models structural HDL code.
♦ Advantages
 Can generate new blocks quickly.
 Can use pre-defined blocks.
 Underlying hierarchy/functionality can be defined later.
 Each block can contain multiple and/or concurrent views.
 Block interface defined “on the fly”.
 Signal width defined in context.

Notes:

58 HDL Designer Series

Block Diagrams
How to Create a Block Diagram

How to Create a Block Diagram

File > New > Design Content >

Graphical View > Block Diagram

♦ Also refer to Module 1 for creating a new Design Unit.

Notes:

HDL Designer Series 59

Block Diagrams
Block Diagram Design Objects

Block Diagram Design Objects

♦ Four types of design objects:
 Text Objects
– Comment Blocks
 Block Objects
– Blocks
– Embedded Blocks
– Components
 Signal Objects
– Signals (one bit)
– Busses (multi-bit)
– Bundles (grouped signals)
 Port Objects
– Ports (In/Out/InOut/Buffer)
– Global Connectors

Notes:

60 HDL Designer Series

Block Diagrams
Design Objects: Blocks and Components

Design Objects: Blocks and Components

♦ Default color: Blue. ♦ Default color: Green.

♦ Represents a “design unit”. ♦ Represents a “design unit”.
♦ Clock/Inversion Symbolism. ♦ Clock/Inversion Symbolism.
♦ Interface changes as ♦ Fixed interface.
connections change. ♦ Multiple Instances.
♦ Unique instance or “proto- ♦ Blocks may be “promoted” to
component”. Components.
♦ Underlying “view” can be ♦ Edit appearance in Symbol
added later. Editor.
♦ Multiple views supported. ♦ Displayed information:
♦ Edit appearance in place.  Source Library
♦ Displayed information:  Block Name
 Source Library  Instance Reference
 Block Name  I/O interface
 Instance Reference

Notes:

HDL Designer Series 61

Block Diagrams
Add Block

Add Block

Add Block
or Add > Block

1. Add the new Block.

Note: You can resize the Block when you add it.

Notes:

62 HDL Designer Series

Block Diagrams
Add Block

Add Block (Cont.)

3. Choose a new view.

2. Open Down on the Block.

Either double-click on the block or

RMB > Open As > New View.
4. Change the name.

Notes:

HDL Designer Series 63

Block Diagrams
Add Component

Add Component

Add > Component [F3]

♦ Drag or copy a component out of the ♦ The symbol is
Component Browser among the extracted in both
existing ModuleWare or HDS libraries. cases for
♦ You can select a particular view if instantiation.
several are available.

Notes:

64 HDL Designer Series

Block Diagrams
Add Component

Add Component (Cont.)

Add > IP ♦ When relevant a list of the entities found in

the source file is proposed to the user.
♦ The compiled library where the external IP
have been pre-compiled is necessary.

Notes:

HDL Designer Series 65

Block Diagrams
Add ModuleWare

Add ModuleWare

Add > ModuleWare

The parameter setting
dialog box can
optionally pop up.

Drag and Drop

Notes:

66 HDL Designer Series

Block Diagrams
Add Signal Objects

Add Signal Objects

Add >

Add Signal
Add Signal with a Port

Add Bus
Add Bus with a Port
Add Bus with a Ripper

Signal stub Add Bundle

Add Bundle with a Ripper
Signal: Scalar
Bus: Vector
Bundle: Arbitrary grouping of signals
2-11 • HDL Designer Series: Block Diagrams Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 67

Block Diagrams
Make Connections: Bus Ripper

Make Connections: Bus Ripper

The slices are remembered.

Notes:

68 HDL Designer Series

Block Diagrams
Make Connections: Bundle

Make Connections: Bundle

Add > Bundle

1. Add a bundle.

2. Edit the Properties to add

the signals.

Notes:

HDL Designer Series 69

Block Diagrams
Make Connections: Bundle

Make Connections: Bundle (Cont.)

Even simpler...

1. Select a bunch of signals.

2. Create a bundle.

3. The tool will pick the selected signals

and create the bundle.

Notes:

70 HDL Designer Series

Block Diagrams
Add Port Objects

Add Port Objects

Add >

♦ A port has no name until it is

connected to a signal.
♦ Add a global connector first; then add
the blocks.
Add Port In
Add Port Out
Add Port Inout
To = In Add Port Buffer

♦ The port direction of the command

From = Out depends if you go to or from a block.
Add Global Connector

Global connector: Common to blocks (including Embedded)

Notes:

HDL Designer Series 71

Block Diagrams
Block Diagram Objects Summary

Block Diagram Objects Summary

Add >
Block:
- Fluid Interface
- Library/Block/Instance names
Component:
- Fixed Interface
Add Block
- Library/Comp./Instance names
<External IP>
- External HDL
Add Component - Compiled outside
<ModuleWare>
- Pre-defined
Add Embedded Block
- Parameterized
- Technology independent
- Language independent
Embedded Block:
Add Frame
- No hierarchy created
(For, If, Block)
- Any view including HDL
Enter HDL or - Can be entered as Text, Flow
Send to Editor. Chart, State Machine, Truth Table
Frame:
For, If, Block
Context added automatically when necessary. - Repeating/Conditional Instances
2-16 • HDL Designer Series: Block Diagrams Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

72 HDL Designer Series

Block Diagrams
Interactive Routing

Interactive Routing

Interactive Routing
♦ Choose routing
style while
dragging blocks or
components.
♦ Press Z to choose
routing style:
 River
 Diagonal
 Diagonal Ends
 Dog Leg
♦ Press Ctrl-r to
clean up routing
after releasing
ghosted object.

Notes:

HDL Designer Series 73

Block Diagrams
Make Connections Summary

Make Connections Summary

1. By Name (signal stubs)

2. Explicit Connection

3. Through Embedded
Block (to connect signals
with different names)

4. With Port Map Frame

Diagram > Port Map Frame > Enable

or
RMB > Port Map Frame > Enable

Notes:

74 HDL Designer Series

Block Diagrams
Block Properties

Block Properties

Block Properties
-1- The object must be selected
first in both cases.

-2-

RMB > Object Properties

Notes:

HDL Designer Series 75

Block Diagrams
Block Properties

Block Properties (Cont.)

Different Generics/Parameters
pre-defined declarations dialog box
shapes
See Component
Properties slide.

VHDL attributes/
Synthesis constraints

Notes:

76 HDL Designer Series

Block Diagrams
Block Properties

Block Properties (Cont.)

A block can be turned

into a component.
This operation can not
be undone!

Notes:

HDL Designer Series 77

Block Diagrams
Component Properties

Component Properties

Useful to take Vital component

to synthesis

Generics/Parameters
are entered in the symbol
unlike the block

VHDL attributes/
Synthesis constraints

Notes:

78 HDL Designer Series

Block Diagrams
Signal Properties

Signal Properties

Thickness of the wire

Enables array definition

Determines the scope of any

action performed on the signal
(e.g. rename)

Notes:

HDL Designer Series 79

Block Diagrams
Signal Properties

Signal Properties (Cont.)

Signal Attributes and Comments

Example usage for attributes:

VHDL:
attribute PRESERVE_SIGNAL : boolean;
attribute PRESERVE_SIGNAL of rst_int : signal is true;
Verilog:
//pragma attribute rst_int preserve_signal true

Specifies that the signal must survive synthesis.

Notes:

80 HDL Designer Series

Block Diagrams
User Declarations

User Declarations

♦ Generated VHDL Code:

Notes:

HDL Designer Series 81

Block Diagrams
Object Visibility

Object Visibility

RMB > Object Visibility

Notes:

82 HDL Designer Series

Block Diagrams
Add Comment Text

Add Comment Text

Click the LMB and type text here.

Add > Comment Text

Notes:

HDL Designer Series 83

Block Diagrams
Add Comment Text

Add Comment Text (Cont.)

Control text position

within text box

Notes:

84 HDL Designer Series

Block Diagrams
Add Comment: Include Position

Add Comment: Include Position

RMB > Include in HDL

User-defined comment location
in the generated code

Comments can then be attached to an object.

Notes:

HDL Designer Series 85

Block Diagrams
Add Comment: Using Text Editor

Add Comment: Using Text Editor

RMB > Send to Editor

RMB > Finish Edit
External Text Editor can be used.

The text is grayed until...

…you finish the Edit(s).

Notes:

86 HDL Designer Series

Block Diagrams
Page Setup

Page Setup

Page Setup
File > Page Setup

♦ You choose up-front the page options.

♦ You can display (or not) the boundaries and page number in the editor.
♦ You see what you print out.
♦ It applies to all the editors. (You do not see the boundaries for the tables.)
2-31 • HDL Designer Series: Block Diagrams Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 87

Block Diagrams
Page Setup

Page Setup (Cont.)

Page boundaries

Page number

Notes:

88 HDL Designer Series

Block Diagrams
Add Panel

Add Panel

Add Panel
Add > Panel

Panel allows to: Exclude an area for auto-route

- Print
- Zoom into a part of the design.

A Panel can be dragged into

Microsoft Word using OLE. RMB > Appearance

Notes:

HDL Designer Series 89

Block Diagrams
Visualize/Edit IBD

Visualize/Edit IBD

Diagram > Edit IBD

Diagram > Visualize IBD

More on IBDs in Module 13

Notes:

90 HDL Designer Series

Block Diagrams
Block Diagram Master Preferences

Block Diagram Master Preferences

Options > Master Preferences > Structural Diagram

♦ The Master Preferences

are applied when
creating a new block
diagram.
♦ They can be overridden
on a block diagram
basis.

Notes:

HDL Designer Series 91

Block Diagrams
Block Diagram Master Preferences

Block Diagram Master Preferences (Cont.)

General Preferences

Default Settings

Notes:

92 HDL Designer Series

Block Diagrams
Block Diagram Preferences

Block Diagram Preferences

Options > Diagram Preferences

Big flexibility in the

Preferences
management

Notes:

HDL Designer Series 93

Block Diagrams
Block Diagram Preferences

Block Diagram Preferences (Cont.)

Notes:

94 HDL Designer Series

Block Diagrams
Package References

Package References

Package References
Diagram > Package References
or
Just double-click on
Package List.

Context updated by the tool when

necessary (i.e. adding new components).

Syntax is automatically checked when

you confirm the dialog box (unless syntax
checking has been disabled in the master
diagram preferences).

Notes:

HDL Designer Series 95

Block Diagrams
Navigate Through Hierarchy

Navigate Through Hierarchy

Window > Use Same Window

Two modes available while navigating:

1. One window (Use Same Window)
2. Multiple windows

Notes:

96 HDL Designer Series

Block Diagrams
Navigate: Going Down

Navigate: Going Down

RMB > Open As

OR…
Just double-click
on the block.

Notes:

HDL Designer Series 97

Block Diagrams
Navigate: Going Up

Navigate: Going Up

File > Open > Open Up

OR simpler...

Open Up on a component
takes you to the symbol.

Notes:

98 HDL Designer Series

Block Diagrams
Navigate: Back/Forward

Navigate: Back/Forward

Back

Forward

When the Window > Use Same Window mode is

enabled, you can use the Back and Forward
buttons to go to the Previous or the Next displayed
window (if relevant).

Notes:

HDL Designer Series 99

Block Diagrams
Navigate: Using Strokes

Navigate: Using Strokes

Execute a command using a stroke by simply holding the middle mouse
button (MMB) down and dragging across the graphic editor window.

Ctrl + MMB
enables
panning.

A second level of strokes is enabled with the Shift key.

Notes:

100 HDL Designer Series

Block Diagrams
Reconcile Interface

Reconcile Interface

Reconcile Interface
Interface Discrepancy between the symbol and the block diagram

Scenario #1 2. The View interface is no longer up-to-date.

3. Diagram > Update > Interface

1. You modify the symbol interface
(i.e. add Out1).

Notes:

HDL Designer Series 101

Block Diagrams
Reconcile Interface

Reconcile Interface (Cont.)

While reconciling you can:

- Update the active view
- Update the component interface/symbol

You can optionally enforce consistent

case and port ordering when reconciling.

Notes:

102 HDL Designer Series

Block Diagrams
Reconcile Interface

Reconcile Interface (Cont.)

Interface Discrepancy between the symbol and the block diagram
Scenario #2

1. You modify the Block Diagram interface

(i.e. delete In1). 2. The Symbol interface
is no longer up-to-date.

3. When you save, the inconsistency

in the interface is detected.

Notes:

HDL Designer Series 103

Block Diagrams
Hierarchical Net Highlight

Hierarchical Net Highlight

Clear Net Highlight

Highlight Net: - in Diagram
- in Hierarchy
1. Select the net.

3. Select the options.

4. Status of what was highlighted.

5. Double-click opens the selected view.
2. RMB > Highlight Net > Hierarchical
2-48 • HDL Designer Series: Block Diagrams Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

104 HDL Designer Series

Block Diagrams
Hierarchical Net Change

Hierarchical Net Change

For example, I want to rename a signal through the hierarchy.
1. Edit the signal properties.

4. Choose the options.

2. Rename the signal.

3. Check the scope of the change.

5. Check the status carefully.

6. Double-click opens the selected view.

If you rename a signal that enters a language block, the interface of the block is modified,
but not the HDL. You get a warning that the HDL must be modified accordingly!

Notes:

HDL Designer Series 105

Block Diagrams
Hierarchical Net Insertion

Hierarchical Net Insertion

♦ Net Insert/Delete
up/down.
♦ The net inserted can be
highlighted.
♦ You can verify before
applying the change.
RMB > Insert Net > Hierarchical

Notes:

106 HDL Designer Series

Block Diagrams
Re-Level – Add Hierarchy

Re-Level – Add Hierarchy

♦ Re-level block hierarchy
 Select blocks
 Specify name of new
block/component
 AutoLayout to route
signal connections

Notes:

HDL Designer Series 107

Block Diagrams
Re-Level – Add Hierarchy

Re-Level – Add Hierarchy (Cont.)

♦ Blocks replaced
♦ Hierarchy created

Notes:

108 HDL Designer Series

Block Diagrams
Re-Level – Remove Hierarchy

Re-Level – Remove Hierarchy

♦ Remove Hierarchy
1. Select Block
RMB > Re-level > Remove Hierarchy

Notes:

HDL Designer Series 109

Block Diagrams
Re-Level – Remove Hierarchy

Re-Level – Remove Hierarchy (Cont.)

♦ Remove Hierarchy
2. Confirm Deletion

Notes:

110 HDL Designer Series

Block Diagrams
Saving the Design

Saving the Design

File > Save (Ctrl-S)

♦ Save design as
 Library
 Design Unit (entity/module
name)
 View (architecture)

Notes:

HDL Designer Series 111

Block Diagrams
Lab 2: Overview

Lab 2: Overview

Lab 2: Overview
♦ The purpose if this lab is to familiarize you with the Block
Diagram editor.

♦ First, you will invoke HDL Designer and create a new project.

♦ Then you will draw a block diagram for the top level of a
design that generates an approximation of a wave generator.

Notes:

112 HDL Designer Series

Module 3
State Machines

Objectives
Upon completion of this module, you will be able to:

• Explain a general overview of Finite State Machines

• Explain the different State Machine styles
• Know how to access State Machine preferences
• Create Finite State Machine Design Objects
• Know how to access the Design Object properties
• Know how to access the HDL Code Generation preferences
• Set the signal status
• Create Concurrent State Machines
• Understand re-leveling

HDL Designer Series 113

State Machines
How to Create a State Machine

How to Create a State Machine

File > New > Design Content >

Graphical View > State Diagram

♦ Also refer to Module 1 for creating a new Design Unit.

Notes:

114 HDL Designer Series

State Machines
State Machine Styles: Moore versus Mealy

State Machine Styles: Moore versus Mealy

Moore
Combinational
Φ Clock
Combinational
Next Current
Inputs Output
state state
Input Output
Forming Forming
Outputs are dependant
Logic Logic
On State Only.

Storage

Mealy
Combinational
Φ Clock
Inputs

Next Current
Output
state state
Input Output
Inputs Forming Forming
Logic Logic Outputs are dependant
On State and Inputs.

Storage Combinational
3-3 • HDL Designer Series: State Machines Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 115

State Machines
State Machine Styles: Moore versus Mealy

State Machine Styles: Moore versus Mealy (Cont.)

♦ Moore state machine are a function of its state only.
 Outputs only change if the state changes.
♦ The outputs of a Mealy state machine are a function of its
current state and inputs.
 Changing the input has a corresponding affect on the outputs.
 Outputs change in the transition between states.
♦ If a Moore state contains an assignment to an input signal, the
state machine has an input dependency and its outputs are a
function of both the state and the inputs — such as Mealy.

Notes:

116 HDL Designer Series

State Machines
State Machine Styles: Moore/Mealy/Mixed

State Machine Styles: Moore/Mealy/Mixed

Output assignment
in the states

Moore Mealy
Mixed
Output assignment
in the transitions
Output assignment
in both states and
transitions

Notes:

HDL Designer Series 117

State Machines
State Diagram Objects

State Diagram Objects

Add >

condition
Simple state
Initial Startup
of Machine State

Transition
Interrupt point
Link
Junction
priority
Transition: Change of States – may include action.
Link: To a state (including hierarchical) or a
action junction.
Junction: Connection to transitions common
to more than one state.
Wait state Hierarchical state Interrupt: Applies to all states.
State: Simple, Hierarchical or Wait.
3-6 • HDL Designer Series: State Machines Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

118 HDL Designer Series

State Machines
State Diagram Objects: Hierarchy

State Diagram Objects: Hierarchy

Add >

- Multiple entry points allowed.

Hierarchical State
- Can exit with a link.
- Multiple levels of hierarchy
allowed.

Entry point

Exit point

Notes:

HDL Designer Series 119

State Machines
FSM Wait States

FSM Wait States

♦ FSM remains in a given state for a specified number of clock cycles.
♦ Applies to Synchronous FSMs only.
♦ Supports parameterized wait values.
♦ Transitions from Wait State can be expressions or simple/complex TIMEOUT
conditions.

Notes:

120 HDL Designer Series

State Machines
FSM Wait States

FSM Wait States (Cont.)

♦ Wait States support IF-style transition decoding only.
♦ On-entry to a Wait State, counter is set and counts down on
each clock edge. TIMEOUT asserted when counter reaches
zero.
♦ Counter is NOT reset by Implicit or Explicit loop-backs.
♦ Any number of Wait states allowed.
♦ The same timeout and counter signals are used for each Wait
state in the same concurrent machine.

Notes:

HDL Designer Series 121

State Machines
FSM Wait States

FSM Wait States (Cont.)

♦ Can specify the VHDL type for the Timeout and other counter
signals in Master Preferences and for each concurrent SM.

♦ Can also specify the bounds for the

counter signal if parameterized
(non-integer) wait values are used.

Options > Master Preferences > State Diagram > Diagram > State Machine Properties >
Default Settings > VHDL/Verilog Wait States State Machine > Generation > Advanced >
Wait State Settings
3-10 • HDL Designer Series: State Machines Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

122 HDL Designer Series

State Machines
Re-Leveling

Re-Leveling

Diagram > Re-Level > Add hierarchy Add or remove hierarchy.

Diagram > Re-Level > Remove hierarchy

Notes:

HDL Designer Series 123

State Machines
State Properties: IF/CASE, Actions

State Properties: IF/CASE, Actions

- Simple State
- Hierarchical State
- Wait State
- As Is

Output assignments CASE Style

♦Typically
creates faster,
else / when others parallel,
multiplex-based
circuit
IF Style
♦Typically creates
serial, priority,
decoder-based
circuit

Notes:

124 HDL Designer Series

State Machines
State Properties: IF/CASE, Actions

State Properties: IF/CASE, Actions (Cont.)

WHEN check_lock => WHEN check_lock =>

IF (sin='1') THEN CASE sin IS
Rcv_next_state <= waiting; WHEN '1' =>
ELSIF (sin='0') THEN Rcv_next_state <= waiting;
Rcv_next_state <= rcv_locked; WHEN '0' =>
ELSE Rcv_next_state <= rcv_locked;
Rcv_next_state <= check_lock; WHEN OTHERS =>
END IF; Rcv_next_state <= check_lock;
END CASE;

Notes:

HDL Designer Series 125

State Machines
Transition Properties: Condition, Actions

Transition Properties: Condition, Actions

Several transitions can be selected at a time

and conditions/actions applied to all of them!

Notes:

126 HDL Designer Series

State Machines
Junction/Link Properties

Junction/Link Properties

Junction/Link Properties
You can specify a name
- It does not appear in the
generated HDL
- Can be a link target

The target can be:

- A valid state
- A junction

Notes:

HDL Designer Series 127

State Machines
State Machine: Clocks, Resets, and Enables

State Machine: Clocks, Resets, and Enables

Name: Can be any input signal
defined at the design units interface
Edge:
– Rising
– Falling
– Specified (e.g. rising_edge(clk)) RMB > Object Properties

Name: Can be any input signal

defined at the design units interface
Mode:
– synchronous
– asynchronous
Level:
– Low
– High
– Specified

Name: Can be any input signal

defined in the dropdown list
Level:
- Low
- High
- Specified

Notes:

128 HDL Designer Series

State Machines
State Machine Properties

State Machine Properties

Diagram > State Machine Properties

RMB > State Machine Properties

Notes:

HDL Designer Series 129

State Machines
State Machine Properties: Generation – VHDL

State Machine Properties: Generation – VHDL

An asynchronous machine
requires a propagation delay.

The hard encoding scheme

must be selected to access
the One-Hot option.

3 Processes
- Clocked
- Nextstate
- Output Merged with
2 Processes

Only with Case

HDL Style

Instead of current state

Applies to extra clocked or registered outputs

Notes:

130 HDL Designer Series

State Machines
State Machine Properties: Generation – VHDL

State Machine Properties: Generation – VHDL (Cont.)

Default:
- current_state
- next_state

Add Pragma (*):

- sync_set_reset_local
- async_set_reset_local Additional code necessary
for animation

Interrupt handling
Default: HDL Designer generates a enumerated type Choose Override versus exclusive if-then-else
with a type enumeration for each state. statement

Specify Type:
- A custom type can be used.
- Hard encoding is necessary (see later).
Assign value to output port: The specified port (*): Using keyword (pragma/synopsys/
type is used. The current_state is assigned to exemplar/synthesis) Options > VHDL >
that port. Style > Pragma Setup

Notes:

HDL Designer Series 131

State Machines
Declarations and Statements

Declarations and Statements

Information can be entered:

- In the forms
- Directly on the schematic

Notes:

132 HDL Designer Series

State Machines
State Machine Properties: Statement Blocks

State Machine Properties: Statement Blocks

Default state assignments.

Placed before the state decode
statements.

Global Actions placed at the

beginning of the output process.

Concurrent Statements placed

at the end of the SM architecture
3-21 • HDL Designer Series: State Machines Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 133

State Machines
State Machine Properties: Architecture Declarations

State Machine Properties: Architecture Declarations

User-defined architecture
declarative section.

Notes:

134 HDL Designer Series

State Machines
State Machine Properties: Process Declaration

State Machine Properties: Process Declaration

clocked and output

process declarations

Notes:

HDL Designer Series 135

State Machines
State Machine Properties: Encoding – VHDL

State Machine Properties: Encoding – VHDL

Attribute Scheme
- syn_encoding (Synplify): supports
Sequential,
1-Hot, Gray, or any other specified style.
Optionally allows “Safe” style.
- type_encoding_style (Leonardo Spectrum
and
Precision Synthesis): supports Binary
1-Hot, 2-Hot, Gray, Random, or any other
style.
- enum_encoding (Synopsys): supports
Sequential, 1-Hot, 2-Hot, Gray,
Johnson, or manual style.
- type_encoding (Leonardo Spectrum and
Precision Synthesis): supports Sequential,
1-Hot, 2-Hot, Gray, Johnson, or manual
style.

Notes:

136 HDL Designer Series

State Machines
State Machine Properties: Encoding – VHDL

State Machine Properties: Encoding – VHDL (Cont.)

- Encoding: Shows state encoding

when enum_encoding,
type_encoding, or Specified
Scheme is selected.
- Manual style allows you to modify
encoding values table.

Scheme
- Specified: Specify Sequential, 1-Hot,
2-Hot, Gray, Johnson, or Manual styles.

Notes:

HDL Designer Series 137

State Machines
Creating “Hard” Encoded “Safe” State Machines

Creating “Hard” Encoded “Safe” State Machines

♦ A safe state machine needs a hard-coded state vector.
 Every state is declared as a constant, the value of the state
register is explicitly defined.
 This prevents the synthesis tool from optimizing redundant
states.
♦ HDL Designer does this automatically, when syn_encoding
Scheme and “Safe” Style are selected.

Notes:

138 HDL Designer Series

State Machines
State Machine Properties: Generation – Verilog

State Machine Properties: Generation – Verilog

3 Always Blocks
- Clocked
- Nextstate Merged with
- Output 2 Blocks

If / One-Hot / Case Generation

For Case, can use
- case
- casex casex and casez
- casez require “Manual”
encoding

Assignment Type
- Blocking
- Non Blocking
- Mixed

Notes:

HDL Designer Series 139

State Machines
State Machine Properties: Generation – Verilog

State Machine Properties: Generation – Verilog (Cont.)

Default: HDL Designer generates a

enumerated type with a type enumeration
for each state.
Assign value to output port:
The current_state is assigned to the
specified port.

Use delay for current state assign:

Delay between the assignment of the
next state (or reset state) to the current
state (assumes synchronous fsm).

Notes:

140 HDL Designer Series

State Machines
State Machine Properties: Encoding – Verilog

State Machine Properties: Encoding – Verilog

Pragma Scheme
- enum (Precision Synthesis): supports Binary,
1-Hot, 2-Hot, Gray, Random, or other specified
style.
- syn_encoding (Synplify): supports Sequential,
1-Hot, Gray, or other specified style.
Optionally allows “Safe” style.

Notes:

HDL Designer Series 141

State Machines
Signal Status

Signal Status

Signal Status
Signal Declarations Signal Status

Select Signals Table from

Structure Navigator

RMB > Signals Table

Notes:

142 HDL Designer Series

State Machines
Signal Status

Signal Status (Cont.)

Port or Local Signal Name

Mode: IN, OUT, INOUT, LOCAL, BUFFER (VHDL only)

VHDL type def or Verilog net type

Range (May use short or long VHDL format)

Initial Value for VHDL Signal

Or
Delay Value for Verilog Signal

Notes:

HDL Designer Series 143

State Machines
Signal Status

Signal Status (Cont.)

IN and LOCAL signals can specify

clock, enable, and resets. OUT,
INOUT, and BUFFER are always
set to “Data”.
Defaults for Outputs
Name of concurrent SM in which and Locals.
Output is assigned Combinatorial
scheme must have
Clock, Reset, Enable, or State
default value.
Variable Expression

Outputs Signals:
Reset Value:
Registered, Combinatorial, or
Required for all
Clocked
Clocked and
Local Signals:
Registered signals
Combinatorial or Clocked

Notes:

144 HDL Designer Series

State Machines
Logic Location in Generated HDL

Logic Location in Generated HDL

1) COMBINATORIAL Next state
Current state

Input Output Outputs

Forming State Forming
Logic Variable Logic

Inputs nextstate clocked output

Outputs assigned in the output process

2) STATE VARIABLE = OUTPUTS (Medvedev)

Next state
Current state Alternate method:
Moore machine with
Input Outputs explicitly-encoded
Forming State
Logic Variable outputs.

Inputs nextstate clocked

Outputs assigned in concurrent statements directly from the state variable

Notes:

HDL Designer Series 145

State Machines
Logic Location in Generated HDL

Logic Location in Generated HDL (Cont.)

3) CLOCKED Next state
Current state

Input Output Outputs

Forming State Forming Output
Logic Variable Logic Register

Inputs nextstate clocked

Outputs_cld

Outputs <= Outputs_cld; Continuous assignment (outside process)

4) REGISTERED Next state

Current state Outputs_int

Input Output Outputs

Forming State Forming Output
Logic Variable Logic Register

output
Inputs nextstate clocked

Outputs <= Outputs_int; in the clocked process

Notes:

146 HDL Designer Series

State Machines
Registered versus Clocked Outputs

Registered versus Clocked Outputs

Unchecked
by default.

Different behavior at
clk
current_state S2:
reset
Combinatorial and
Registered Outputs change z_comb
to their default value. z_reg
Clocked Outputs hold their z_clocked
value until a new value is
current_state s0 s1 s2 s3 s0
assigned.
next_state s1 s2 s3 s0 s1

One clock period delay is added to the Registered and Clocked Outputs
versus Combinatorial Output.

Notes:

HDL Designer Series 147

State Machines
Register State Actions on Next State

Register State Actions on Next State

Diagram > State Machine Properties >
Generation

Applies to Clocked and

Registered Outputs.
clk
reset
z_comb
z_reg

z_clocked
current_state s0 s1 s2 s3 s0

next_state s1 s2 s3 s0 s1

Combinatorial, Registered and Clocked Outputs all change to their new

value at the same time, based on the value of the next_state variable.

Notes:

148 HDL Designer Series

State Machines
How to Choose Which Output Type

How to Choose Which Output Type

♦ Clocked is a good choice if you need to work with the
registered signal inside the FSM. For example, as a counter
or flag, as mentioned earlier.
 Clocked is the best fail-safe choice because, since it is clocked
(<out>_cld is actually a clocked signal) it always holds its value.
 With 1 process state machines, this is the only available Output
type, and signal status give no option for any other type
♦ Registered is appropriate if you need to work with the
combinatorial version of the signal inside the FSM and just
want to retime the outputs. This can be useful for pipelining.
♦ Combinatorial is appropriate if the signal does not need
retiming or to be registered.
HDS InfoHub:
1. Manuals > State Machine Editors User Manual
2. Application Notes > How to predict the output of finite state machines in
HDL Designer Series
3-37 • HDL Designer Series: State Machines Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 149

State Machines
Output Assignment Priority

Output Assignment Priority

A few actions impact the

value of the outputs.

The actions are prioritized

as shown below.

Execution Priority
(Highest at the Top)
Reset actions (jumps to Start State)

Interrupt transition actions

Normal transition actions

State actions

Global actions

Notes:

150 HDL Designer Series

State Machines
Concurrent State Machines

Concurrent State Machines

Double-click to Open Machine

Add Machine
Shared:
♦ Interface Delete Machine
♦ Package list
♦ Concurrent statements
♦ Architecture/Module declarations

Separate:
♦ Global actions
♦ HDL generation options
♦ State encoding Add > Concurrent State Machine [Ctrl-F2]
♦ Process declarations

Notes:
♦ Treated as a single design object (one HDL file generated, all concurrent state
machines are saved when any state diagram is saved).
♦ State names must be unique.
♦ Cannot create links between concurrent state machines.
3-39 • HDL Designer Series: State Machines Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 151

State Machines
Concurrent State Machines: Renaming

Concurrent State Machines: Renaming

Diagram > Rename Concurrent Machine

Default name is csm as

defined in the State Diagram
Master Preferences.

Notes:

152 HDL Designer Series

State Machines
Expression Builder

Expression Builder

2. Expression Builder appears.

1. Double-click transition
expression to edit.

3. Can edit directly.

4. Can turn off expression builder.

Notes:

HDL Designer Series 153

State Machines
State Machine Preferences

State Machine Preferences

Options > Master Preferences > State Diagram

Polyline
style

Correct HDL syntax entry.

Spline
style

Notes:

154 HDL Designer Series

State Machines
State Machine Preferences

State Machine Preferences (Cont.)

Options > Master Preferences > State Diagram

Signal status: see slides 31-38

Object Visibility Inside Diagrams

Notes:

HDL Designer Series 155

State Machines
State Machine Preferences

156 HDL Designer Series

Module 4
Design Creation Editors

Objectives
Upon completion of this module, you will be able to:

• Understand HDS Design Creation Editors

• Understand the DesignPad Text Editor
• Create and open a Flow Chart
• Know the Flow Chart design objects
• Know how to access the Flow Chart preferences/properties
• Know how to create Hierarchical/Concurrent Flow Charts
• Describe a general overview to the Truth Table
• Understand Truth Table notation
• Know how to edit and format a Truth Table
• Know how to access Truth Table preferences/properties

HDL Designer Series 157

Design Creation Editors
Design Creation Editors

Design Creation Editors

♦ The HDL Designer includes:

 Integrated language-sensitive HDL text editor (Design Pad)

 Graphical Editors:
– Block Diagram and IBD View Editors
– Flow Chart Editor
– Truth Table Editor
– State Diagram Editor

Notes:

158 HDL Designer Series

Design Creation Editors
DesignPad: Design-Aware Text Editor

DesignPad: Design-Aware Text Editor

♦ Fully integrated with HDL Designer
 Automatic update of Design Manager/Embedded Blocks when
editing
 Drag and Drop any component and ModuleWare
♦ Similar functionality to other HDL Designer editors
 Design navigation (open up/down)
 Cross-reference
– Error/warning messages
– Text and graphic views
– Simulation and synthesis tool views
 HTML export

Notes:

HDL Designer Series 159

Design Creation Editors
DesignPad: Fully Integrated, Design-Aware

DesignPad: Fully Integrated, Design-Aware

Customizable menu

View > Toolbars

Multiple tabs

Code Browser

View > Code Browser Split windows

Window > Split

Window > Remove Split

Language Templates

View > Language Templates

Notes:

160 HDL Designer Series

Design Creation Editors
DesignPad: Rapidly Navigate HDL Code

DesignPad: Rapidly Navigate HDL Code

♦ Outline of code structure plus immediate access
to any code block.
 Outline mode allows you to collapse (fold) the text
in the edit window/pane into nested code blocks.
♦ Cross-highlight between code browser and text.
♦ Find in code browser with travelog.
Document > Outline Mode

Outline
Mode

Notes:

HDL Designer Series 161

Design Creation Editors
DesignPad: Comparing Files

DesignPad: Comparing Files

♦ Powerful file comparison

Document > Compare Two Files

 Highlights differences
 Selectively apply
changes to either file

Notes:

162 HDL Designer Series

Design Creation Editors
DesignPad: Column Editing

DesignPad: Column Editing

♦ Rectangular (columnar) region cut/paste

 Select Column mode

Document > Column Select Mode

 Select column to copy

 Click copy (Ctrl+C)
 Select column to replace
 Paste the column in (Ctrl+Shift+V)

Edit > Paste Column

Notes:

HDL Designer Series 163

Design Creation Editors
DesignPad: Powerful Editing

DesignPad: Powerful Editing

♦ Cut, copy, paste, append

♦ Drag and drop from other tools
♦ Drag and drop editing:
 Move/copy
 Optional valid target highlighting
♦ Adding comment characters around block
of code. RMB > Comments

♦ Completion of words
 Ctrl+Spacebar
 Select to complete

Notes:

164 HDL Designer Series

Design Creation Editors
DesignPad: Fully Customizable

DesignPad: Fully Customizable

♦ Configurable menus, toolbars, and shortcut keys.
♦ Create your own custom functions in Tcl.
♦ Configure the tool to your exact requirements with extensive
preference settings.
♦ Repeat common operations using macro record/playback.
Options > Preferences Options > Customize

Notes:

HDL Designer Series 165

Design Creation Editors
What Is a Flow Chart?

What Is a Flow Chart?

♦ A Flow Chart is:
 One Process in VHDL
 One Procedural Block in Verilog
(always or initial)
♦ A Flow Chart consists of:
 A set of HDL instructions
 Flow Control
– Loops
– Case Statements
– Decision Boxes (IF-THEN-ELSE)
♦ Features
 Sequential execution
 Concurrent Flow Charts
 Styles
– Wait Statements for Test benches
– Sensitivity List for Synthesis
 Styles cannot be mixed in a single Flow Chart

Notes:

166 HDL Designer Series

Design Creation Editors
How to Create a Flow Chart

How to Create a Flow Chart

File > New > Design Content >

Graphical View > Flow Chart

Notes:

HDL Designer Series 167

Design Creation Editors
Flow Chart Objects

Flow Chart Objects

Add >
Start-End Points

Action Box
Hierarchical Action Box
Decision Box

Wait Box

[Start-End] Loop Box

[Start-Add] Case Box, Case Port
Flow

- Only one Start Point

- At least one End Point

Notes:

168 HDL Designer Series

Design Creation Editors
Flow Chart Objects: Start and End Points

Flow Chart Objects: Start and End Points

♦ Start Point
 Designates entry into design view
or level of hierarchy
 Only one start point per concurrent
flow chart and level of hierarchy
allowed

♦ End Point
 Ends a flow chart
 May have multiple end points

Notes:

HDL Designer Series 169

Design Creation Editors
Flow Chart Objects: Action and Decision Boxes

Flow Chart Objects: Action and Decision Boxes

♦ Action Box
 Sequential statements
 Assignments
 Object ID (default => “ax”)

♦ Hierarchical Action Box

 Creates hierarchical flow chart
 Flow Chart within Flow Chart

♦ Condition Box
 Branches on value of condition
 Must branch forward in Flow Chart
 Object ID (default => “dx”)
 Swappable True/False assignment

Notes:

170 HDL Designer Series

Design Creation Editors
Flow Chart Objects: Case Boxes

Flow Chart Objects: Case Boxes

♦ Case
 Automatically adds End Case box
 Object ID (default => “cx”)
 Case expression
 Add “ports” for values
 Initial default ports are:
– value0
– value1
– OTHERS

♦ Multiple Case Boxes can be

nested, but all branches of a
specific Case Box have to meet in
the same End Case Box.

Notes:

HDL Designer Series 171

Design Creation Editors
Flow Chart Objects: Wait Boxes and Loops

Flow Chart Objects: Wait Boxes and Loops

♦ Wait Box
 Inserts wait conditions
 Wait for
– Time, forever, until
– Clock edge
– Signal
 Object ID (default => “wx”)
♦ Start Loop Box
 Beginning of loop statement
 Contains loop expression
 Object ID (default => “Ix”)
♦ End Loop Box
 Delineates end of loop
 Only method of returning
flow “upstream”

Notes:

172 HDL Designer Series

Design Creation Editors
Adding Objects on a Flow Chart

Adding Objects on a Flow Chart

♦ Use the Add menu or one of the

Flow Chart toolbar buttons.
♦ A flow is automatically
connected to the nearest
unconnected port on an
existing object.
♦ If several available ports, the
ghost flow snaps between them
as you move the cursor.

Automatic connection mode.

Notes:

HDL Designer Series 173

Design Creation Editors
Adding Objects on a Flow Chart

Adding Objects on a Flow Chart (Cont.)

Move cursor over an or

existing flow while
adding an object.

Only works for vertical flows.

Automatic insertion mode.

Notes:

174 HDL Designer Series

Design Creation Editors
Flow Chart Preferences: Invocation

Flow Chart Preferences: Invocation

Options > Master Preferences > Flow Chart

Notes:

HDL Designer Series 175

Design Creation Editors
Flow Chart Preferences: Default Values

Flow Chart Preferences: Default Values

Options > Master Preferences > Flow Chart

Name of the flow

chart process.

Notes:

176 HDL Designer Series

Design Creation Editors
Flow Chart: Object Properties

Flow Chart: Object Properties

Edit > Object Properties [Alt-Enter] or RMB > Object Properties

First, select the object…

…or simply double-click

on the object (except the
Hierarchical Action Box).

Notes:

HDL Designer Series 177

Design Creation Editors
Object Properties — VHDL: Action, Case

Object Properties — VHDL: Action, Case

Action Box
a6
a6

Case

Notes:

178 HDL Designer Series

Design Creation Editors
Object Properties — VHDL: Wait, Loop

Object Properties — VHDL: Wait, Loop

Wait Box

wait [on Sensitivity List] [until Condition] [for Time Expression];

Loop

Forever (use EXIT or NEXT statement), Specify (FOR or WHILE)

Notes:

HDL Designer Series 179

Design Creation Editors
Object Properties — VHDL: If

Object Properties — VHDL: If

Decision Box

off on

Notes:

180 HDL Designer Series

Design Creation Editors
Object Properties — Verilog: Action, Case

Object Properties — Verilog: Action, Case

Action Box

case
casex
casez
As is

Case

// pragma full_case
// pragma parallel_case
// pragma parallel_case full_case
As is
4-25 • HDL Designer Series: Design Creation Editors Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 181

Design Creation Editors
Object Properties — Verilog: Wait, Loop

Object Properties — Verilog: Wait, Loop

Wait Box

Loop

Notes:

182 HDL Designer Series

Design Creation Editors
Object Properties — Verilog: If

Object Properties — Verilog: If

Decision Box

off
on

Notes:

HDL Designer Series 183

Design Creation Editors
Flow Chart Properties

Flow Chart Properties

RMB > Flow Chart Properties

Notes:

184 HDL Designer Series

Design Creation Editors
Flow Chart Properties: VHDL Generation

Flow Chart Properties: VHDL Generation

Sequential option brings the
Clock and Reset dialog boxes.

Name: Can be any input signal

defined in the dropdown list.
Edge:
- Rising
- Falling
- Specify (eg: rising_edge(clk))

Name: Can be any input signal

defined in the dropdown list.
Mode:
- synchronous
- asynchronous
Level:
- Low
- High
- Specify
Add Pragma (*): (*): pragma / synopsys / exemplar / synthesis
- sync_set_reset_local Options > VHDL > Style > Pragma Setup
- async_set_reset_local

Notes:

HDL Designer Series 185

Design Creation Editors
Flow Chart Properties: VHDL Generation

Flow Chart Properties: VHDL Generation (Cont.)

The sensitivity list

is extracted.

To instrument the code

for animation.

Notes:

186 HDL Designer Series

Design Creation Editors
Flow Chart Properties: Architecture Declarations

Flow Chart Properties: Architecture Declarations

Notes:

HDL Designer Series 187

Design Creation Editors
Flow Chart Properties: Concurrent Statements

Flow Chart Properties: Concurrent Statements

Placed at the end

of the code.

Notes:

188 HDL Designer Series

Design Creation Editors
Flow Chart Properties: Process Declarations

Flow Chart Properties: Process Declarations

- Placed in the declarative

region of the Flow Chart
process.
- Not shared with concurrent
Flow Charts nor any other
concurrent statement.

Notes:

HDL Designer Series 189

Design Creation Editors
Flow Chart Properties: Verilog Generation

Flow Chart Properties: Verilog Generation

Sequential option brings the
Clock and Reset dialog boxes.

Name: Can be any input signal

defined in the dropdown list.
Edge:
- Rising
- Falling
- Specify

Name: Can be any input signal

defined in the dropdown list.
Mode:
- synchronous
- asynchronous
Level:
- Low
- High
- Specify
Add Pragma (*): (*) : pragma / synopsys / exemplar / synthesis
- sync_set_reset_local Options > Verilog > Style > Pragma Setup
- async_set_reset_local

Notes:

190 HDL Designer Series

Design Creation Editors
Flow Chart Properties: Verilog Generation

Flow Chart Properties: Verilog Generation (Cont.)

The sensitivity list

is extracted.

To instrument the code

for animation.

Two Verilog Procedural Blocks:

- always → executed continuously
- initial → executed once
Two types of block:
- Sequential → begin - end
- Parallel → fork - join
4-35 • HDL Designer Series: Design Creation Editors Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 191

Design Creation Editors
Flow Chart Properties: Module Declarations

Flow Chart Properties: Module Declarations

Notes:

192 HDL Designer Series

Design Creation Editors
Flow Chart Properties: Concurrent Statements

Flow Chart Properties: Concurrent Statements

Placed at the end

of the code.

Notes:

HDL Designer Series 193

Design Creation Editors
Flow Chart Properties: Local Declarations

Flow Chart Properties: Local Declarations

Not shared with concurrent

Flow Charts nor any other
concurrent statement.

Notes:

194 HDL Designer Series

Design Creation Editors
Hierarchical Flow Charts

Hierarchical Flow Charts

Parent diagram Child diagram

Only one
process
Created.

Notes:

HDL Designer Series 195

Design Creation Editors
Concurrent Flow Charts

Concurrent Flow Charts

Double-click to open Chart

Shared: Add Concurrent Chart

♦ Interface
♦ Package list Delete Chart
♦ Concurrent statements
♦ Architecture/Module declarations

Separate:
♦ Sensitivity List
♦ Process Declarations Add > Concurrent Flow Chart [Ctrl-F2]
Notes:
♦ Treated as a single design object (one HDL file generated, all concurrent flow
charts are saved when any flow chart is saved).
♦ Object names must be unique.
♦ Separate VHDL process or Verilog always/initial block for each flow chart.

Notes:

196 HDL Designer Series

Design Creation Editors
How to Create a Truth Table

How to Create a Truth Table

File > New > Design Content >

Graphical View > Truth Table

♦ Also refer to Module 1 for creating a new Design Unit.

Notes:

HDL Designer Series 197

Design Creation Editors
Truth Table

Truth Table

♦ Describe a decoder or multiplexor ♦ HDL statement blocks

♦ Combinatorial/Sequential ♦ Full syntax checking
♦ Any legal HDL expressions
4-42 • HDL Designer Series: Design Creation Editors Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

198 HDL Designer Series

Design Creation Editors
Truth Table Notation

Truth Table Notation

Output
Columns

Input
Column

Input Output
Expression Expressions

Blank Row (ELSE / WHEN OTHERS)

Notes:

HDL Designer Series 199

Design Creation Editors
Editing and Formatting Table Cells

Editing and Formatting Table Cells

Drag the
Cell formatting buttons
dividers
to resize
rows and
columns.

Click in a cell to enter new text or Popup menu for manipulating

overwrite existing text; double-click to rows and columns
edit existing text.
4-44 • HDL Designer Series: Design Creation Editors Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

200 HDL Designer Series

Design Creation Editors
Truth Table Properties: Generation

Truth Table Properties: Generation

Table > Truth Table Properties

Specify Sequential or
Combinatorial behavior.

List of signals separated

by commas.

Notes:

HDL Designer Series 201

Design Creation Editors
Truth Table Properties: Global Actions

Truth Table Properties: Global Actions

Global Actions:
♦ Always performed.
♦ Important for
synthesis.
♦ Used to avoid implied
latches.

Notes:

202 HDL Designer Series

Design Creation Editors
Truth Table Preferences

Truth Table Preferences

All Truth Tables – Design Manager
Options > Master Preferences > Truth Table

Change text font.

Notes:

HDL Designer Series 203

Design Creation Editors
Truth Table Preferences

Truth Table Preferences (Cont.)

Individual Truth Table
Options > Diagram Preferences

Notes:

204 HDL Designer Series

Module 5
Editing Symbols/Interfaces

Objectives
Upon completion of this module, you will be able to:

• Create/edit a Symbol
• Understand Symbol notation
• Know how to use the Symbol Editor
• Know how to create a custom Symbol
• Know how to access Symbol properties
• Know how to access the Interface Editor

HDL Designer Series 207

Editing Symbols/Interfaces
How to Create a New Symbol

How to Create a New Symbol

or
File > New > Design Content >
Graphical View > Interface

Then choose “Symbol”

In the Structure Navigator.

♦ Also refer to Module 1 for creating a new Design Unit.

Notes:

208 HDL Designer Series

Editing Symbols/Interfaces
How to Edit a Symbol

How to Edit a Symbol

Make sure symbols are displayed
in the Design Unit view.

Double-click on symbol.

Notes:

HDL Designer Series 209

Editing Symbols/Interfaces
Symbol Notation

Symbol Notation

♦ Input ports are shown by entering the

symbol and output ports by exiting
from the symbol.

♦ A bidirectional (InOut) port is indicated

by and a buffer port by .

♦ Any input port can be shown as an edge

triggered clock signal.

♦ Any input, output, bidirectional, or

buffer port can be shown as an active
low (not) signal.

Notes:

210 HDL Designer Series

Editing Symbols/Interfaces
Symbol Editor Objects

Symbol Editor Objects

Add >

Comment Text

Input Port

Output Port

Inout Port

Buffer Port

Notes:

HDL Designer Series 211

Editing Symbols/Interfaces
Symbol Autoshapes

Symbol Autoshapes

A few common pre-defined

Diagram > Autoshapes shapes can be used.

Notes:

212 HDL Designer Series

Editing Symbols/Interfaces
Symbol Editor: Equidistant Ports

Symbol Editor: Equidistant Ports

RMB > Equidistant Ports

Will correct the port spacing automatically.

Notes:

HDL Designer Series 213

Editing Symbols/Interfaces
Symbol Editor: Custom Symbol

Symbol Editor: Custom Symbol

Diagram > Custom Symbol

RMB > Custom Symbol

You can customize the shape

inside the Symbol boundary.

Notes:

214 HDL Designer Series

Editing Symbols/Interfaces
Symbol Editor: Custom Symbol Graphics

Symbol Editor: Custom Symbol Graphics

Line Rectangle
Polyline Ellipse
Arc Circle
Polygon

Bitmaps Add > Comment Graphics

Grouping
Order
Rotate
Flip
5-9 • HDL Designer Series: Editing Symbols/Interfaces Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 215

Editing Symbols/Interfaces
Symbol Editor: Custom Symbol Appearance

Symbol Editor: Custom Symbol Appearance

RMB > Appearance

Notes:

216 HDL Designer Series

Editing Symbols/Interfaces
Symbol Properties

Symbol Properties

Symbol Properties
RMB > Object Properties

Notes:

HDL Designer Series 217

Editing Symbols/Interfaces
Interface Editor: Invocation

Interface Editor: Invocation

File > New > Design Content > Graphical View > Interface

Tabular IO view.

Symbol Editor.
Alternative view for the
symbol in tabular IO
format.

Notes:

218 HDL Designer Series

Editing Symbols/Interfaces
Interface Editor: Example

Interface Editor: Example

Table > Filter

The full tabular IO view

displays the interface as
a matrix of seven
columns with a separate
row for each signal.

With Filters turned on, separate dropdown selections on each

column allow displaying of input, output, bidirectional (inout),
buffer (VHDL), generics (VHDL), or parameters (Verilog).
Default is <ALL>.

Notes:

HDL Designer Series 219

Editing Symbols/Interfaces
Editing Generic Declarations

Editing Generic Declarations

RMB > Object Visibility

Generics Table

Notes:

220 HDL Designer Series

Editing Symbols/Interfaces
Editing Local Declarations

Editing Local Declarations

uart_top Package List Edit > Object Properties

addr : std_logic_vector(2:0) LIBRARY ieee;
USE ieee.std_logic_1164.all; Generic Declarations
clk : std_logic

cs : std_logic
datout : std_logic_vector(7:0) USE ieee.std_logic_arith.all; delay integertime 10 ns
width positive 16
or
datin : std_logic_vector(7:0) Declarations
int : std_logic
nrw : std_logic Ports:
-- 3-bit address bus
rst : std_logic addr : IN std_logic_vector (2 DOWNTO 0) ;
sout : std_logic clk : IN std_logic ; -- 10 MHz clock
sin : std_logic
cs : IN std_logic ; -- chip select
-- 8-bit data in bus from cpu
datin : IN std_logic_vector (7 DOWNTO 0) ;
nrw : IN std_logic ; -- read(0), write(1)
rst : IN std_logic ; -- reset(0)
sin : IN std_logic ; -- serial input
-- 8-bit data out bus to cpu
datout : OUT std_logic_vector (7 DOWNTO 0) ;
int : OUT std_logic ; -- interrupt (1)
sout : OUT std_logic -- serial output
Double-click User:
attribute array_pin_number of count: signal is ("P1", "P2", "P3", "P4");
attribute required_time of count: signal is 3 ns;

Notes:

HDL Designer Series 221

Editing Symbols/Interfaces
Lab 3: Overview

Lab 3: Overview

Lab 3: Overview
♦ In lab 2 you created a top-level block diagram for the
wave_gen design. Make sure you finished lab 2 successfully!

♦ The purpose of this lab is to familiarize you with the state

diagram editor and the truth table editor.

Notes:

222 HDL Designer Series

Module 6
Simulation

Objectives
Upon completion of this module, you will be able to:

• Describe Test Bench within HDL Designer

• Know how to generate a Test Bench within HDS
• Debug in HDL Designer
• Animate in HDL Designer
• Understand Optimization in HDL Designer
• Know how to Enable Code Coverage within HDS

HDL Designer Series 223

Simulation
Test Bench: Introduction

Test Bench: Introduction

A test bench is made for:
♦ Applying stimuli to the design
♦ Ensuring the design responds as expected

A test bench can be created in graphics, as a block diagram

containing the instantiated device under test (DUT) and the test
bench component(s).
DUT

Style 1 Style 2

Notes:

224 HDL Designer Series

Simulation
Test Bench: Generation

Test Bench: Generation

1. Select component (DUT).

The Style 2 test bench can be created
by HDL Designer automatically from
an existing component.

DUT
2.

or 3. UART

File > New > Test Bench

Notes:

HDL Designer Series 225

Simulation
Test Bench: Stimuli and Checkers

Test Bench: Stimuli and Checkers

♦ The test bench components (stimuli and checkers) are
predominantly sequential in nature.
♦ They can conveniently be represented in graphics using HDL
Designer graphical paradigms like Flow Chart or State
Machine.

Notes:

226 HDL Designer Series

Simulation
Test Bench: Wait Statement in Flow Chart

Test Bench: Wait Statement in Flow Chart

♦ “Wait for time” statements
are not synthesizable.

♦ “Wait for signal” statements

can replace sensitivity list.
Implied
Loop for all
♦ When End Point reached, processes
execution loops back to (unless wait
Start point. forever)
 Example: Clock signal
generator.

♦ Wait with no time will wait

forever.
 Recommendation: Place at
end of test bench.

Notes:

HDL Designer Series 227

Simulation
Simulators Interface

Simulators Interface

Simulators Interface
♦ HDL Designer supports integration with downstream tools for
HDL simulation.
♦ You can choose your simulation tool from within “HDS Setup
Assistant Wizard”

Notes:

228 HDL Designer Series

Simulation
Debug in HDL Designer

Debug in HDL Designer

♦ In addition to the automatic Test Bench generation feature,
HDL Designer provides the user with an extended interactive
simulation debugging environment.
♦ The integration between the best-in-class
ModelSim/QuestaSim simulator and HDL Designer provides a
very effective and productive debugging environment:
 Complete interaction between both products
– ModelSim/QuestaSim Windows HDL Designer graphical
views
 Interactive graphical debugging session
– State Machine animation
– Flow Chart animation
– Block Diagram probing
– Simulation replay

Notes:

HDL Designer Series 229

Simulation
Debug: Simulator Set Up

Debug: Simulator Set Up

Tasks > Tasks and Templates

♦ The task manager contains user tasks for HDL generation, compiling
for, or invoking the ModelSim simulator, preparing data, invoking, or
running flows with Precision Synthesis, and several other tasks.
Drag and drop Team Specific
tasks from “My Tasks also
Tasks” to the available.
Shortcut Bar.

You can also

build your
own tasks.

Notes:

230 HDL Designer Series

Simulation
Debug: Simulator Set Up

Debug: Simulator Set Up (Cont.)

1. select

2. Click RMB > Settings

♦ Compile and Invoke Settings display defaults from Help > HDS Setup Assistant.

Notes:

HDL Designer Series 231

Simulation
Debug: Simulator Set Up

Debug: Simulator Set Up (Cont.)

1.Select

2. Click RMB > Settings

Allow cross probing(default)

Notes:

232 HDL Designer Series

Simulation
Debug: Simulator Start

Debug: Simulator Start

1. Select Test Bench.

2. To allow the cross-probing between

HDL Designer and the simulator.

3. Verify Library, Design unit,

and Simulator Resolution.

Notes:

HDL Designer Series 233

Simulation
Debug: Log Window

Debug: Log Window

Save Cut, Copy, Paste

Clear
Close Page
Next Warning

Previous Warning
Previous Error Next Error

Notes:

234 HDL Designer Series

Simulation
Debug: Log Window

Debug: Log Window (Cont.)

Cross Reference to Source

(Graphics)

Stay Minimized/Closed

Cross Reference to Generated HDL

Notes:

HDL Designer Series 235

Simulation
Debug: Simulation Control

Debug: Simulation Control

Step Restart Simulator

Step Over

Run to Next Event

Continue

Run Forever

Run For Time

run 100
run 200
run 300 All these simulator commands
run 400
Choose are available from HDL Designer.
Default

Notes:

236 HDL Designer Series

Simulation
Debug: Block Diagram/IBD/SM Editor

Debug: Block Diagram/IBD/SM Editor

2. Add Wave
1. Select the signals Delete Wave
in the block diagram.

Notes:

HDL Designer Series 237

Simulation
Debug: Block Diagram/IBD/SM Editor

Debug: Block Diagram/IBD/SM Editor (Cont.)

Add List Add Probe

Delete Probe
Delete List
Delete All Probes

Highlight Object Show the value while

simulation proceeds.

Signal Info

Notes:

238 HDL Designer Series

Simulation
Probe: Block Diagram/IBD

Probe: Block Diagram/IBD

Enable/Disable
Cursor Tracking
Probe changes from yellow to
red if signal value changes. Probe
Properties

The probe value is updated when you

move the cursor in the wave window.

Notes:

HDL Designer Series 239

Simulation
Breakpoint: Block Diagram/IBD/FC-SM Editors

Breakpoint: Block Diagram/IBD/FC-SM Editors

Add Breakpoint Disable (All) Breakpoint(s)

Delete (All) Breakpoint(s) Enable (All) Breakpoint(s)

Notes:

240 HDL Designer Series

Simulation
Enable Animation: Flow Chart

Enable Animation: Flow Chart

RMB > Flow Chart Properties

Notes:

HDL Designer Series 241

Simulation
Enable Animation: State Machine

Enable Animation: State Machine

RMB > State Machine Properties

Notes:

242 HDL Designer Series

Simulation
Animation Tools: Flow Chart/State Machine

Animation Tools: Flow Chart/State Machine

Global Data Capture

applies to all state
diagrams and flow charts
in the current simulation
hierarchy.

Notes:

HDL Designer Series 243

Simulation
Animation Tools: Flow Chart/State Machine

Capture Mode: Flow Chart/State Machine (Cont.)

In Capture mode the
State Diagram and
Flow Chart objects
become white to display
the simulation progress.
Data Capture

Clear Captured Events

Activity Trails
Show Animation

Applies to all windows in

the current simulation.

Control the animation activity.

Notes:

244 HDL Designer Series

Simulation
Activity Trail: State Machine / Flow Chart

Activity Trail: State Machine / Flow Chart

Current

Previous
Previous

Activity Trails color code Current

Red: Current state / box or last transition taken
Yellow: Previous state / box or transitions
Blue: Previously visited states / boxes and transitions
Green: Transitions evaluated but not followed
White: Unvisited objects
6-23 • HDL Designer Series: Simulation Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 245

Simulation
Goto: Flow Chart/State Machine

Goto: Flow Chart/State Machine

Only for State Machine

Goto Latest

Goto Start

Goto Time

Movement
Move By States
Move by Events
Move By Clocks
Goto Next

Goto Previous Must be selected to

enable Move By Clocks.

Notes:

246 HDL Designer Series

Simulation
Optimization and HDL Designer

Optimization and HDL Designer

♦ By default vopt will run with all
optimizations on.

♦ Enabling the HDS

communications will disable most
optimizations
( This is on by default)

♦ Running in GUI mode will be

slower

♦ Turning on coverage will Disable

many optimizations

♦ In HDL Designer, use

“-voptargs” to pass arguments to
vopt.

Notes:

HDL Designer Series 247

Simulation
Code Coverage Simulation Metrics

Code Coverage Simulation Metrics

♦ To collect coverage data for a design, you must actively select the
type of code coverage you want to collect, and then enable the
coverage collection mechanism for the simulation run.
♦ There are various types of coverage:
 Statement coverage — counts the execution of each statement
 Branch coverage — counts the execution of each conditional
“if/then/else” and “case” statement
 Condition coverage — analyzes the decision made in “if” and ternary
statements Expression coverage — analyzes the expressions on the right
hand side of assignment statements
 Toggle coverage — counts each time a logic node transitions from one
state to another
 FSM coverage — counts the states, transitions, and paths within a finite
state machine
 SystemVerilog class coverage — collects data for each elaborated class
type and each specialization of a parameterized class
♦ All types of coverage can be set from within HDS

Notes:

248 HDL Designer Series

Simulation
Code Coverage Simulation Metrics

Code Coverage Simulation Metrics (Cont.)

♦ There are two points at which ModelSim Code Coverage can
be defined:
 During Compile (vlog/vcom)
 During optimization (vopt)

♦ The vopt stage is run automatically as part of simulation

(vsim)
 Coverage options are passed to vopt via the vsim switch
‘-voptargs’

♦ HDS can define coverage in either manner.

Notes:

HDL Designer Series 249

Simulation
Code Coverage with HDL Designer - Method 1

Code Coverage with HDL Designer - Method 1

♦ Defining coverage during compile

Compile Elab/load
vcom/vlog vsim 2
1
Enable
Coverage Coverage
Options

Notes:

250 HDL Designer Series

Simulation
Code Coverage with HDL Designer - Method 2

Code Coverage with HDL Designer - Method 2

♦ Defining coverage during at optimize.

Compile Optimize Elab/load

vcom/vlog vopt vsim

Enable
1 2 Coverage
Coverage
Options

♦ Options passed
to vopt via vsim
-voptargs

Notes:

HDL Designer Series 251

Simulation
Code Coverage with HDL Designer

Code Coverage with HDL Designer

During Compile During vopt

♦ In this case we are instrumenting ♦ In this case we are instrumenting
the code during compilation. the code during vopt
♦ Problems: It’s “sticky” -> slow ♦ No need to recompile to remove
performance if you are not careful instrumentation
♦ You need to recompile to remove ♦ Easy to specify where you want
instrumentation coverage (switches)
♦ You don’t want code coverage on ♦ This is the preferred way to add
your TB, so you need different coverage
options for DUT and TB ♦ HDS will remember your last
settings so it’s easy to toggle
coverage on off

Not Recommended! Recommended

Notes:

252 HDL Designer Series

Simulation
Coverage Options

Coverage Options

♦ -voptargs= this specifies the arguments you want to supply to vopt,

the args should be in “”

 +cover= Specify the coverage metrics you want to collect (next slide)
 +<dut name>. Specify the design units, you want to collect metrics on
 Note the dot “.” this tells the simulator to apply coverage hierarchally
 -coverexcludedefault Do not collect coverage on default statements
 -coverage turns on the coverage, you can also use the tick box on the GUI.
 -noincr disables vopt reusing previously optimized blocks

Notes:

HDL Designer Series 253

Simulation
Coverage +cover

Coverage +cover

Coverage +cover
♦ Define Code Coverage metrics to collect using +cover
 +cover[=<spec>][+<module>[.]]

<spec> — one or more of the following characters:

b — Collect branch statistics.
c — Collect condition statistics. Collects only FEC statistics, unless -
coverudp is specified.
e — Collect expression statistics, Collects only FEC statistics, unless -
coverudp is specified.
s — Collect statement statistics.
t — Collect toggle statistics. Overridden if ‘x’ is specified elsewhere.
x — Collect extended toggle statistics. This takes precedence, if ‘t’ is
specified elsewhere.
f — Collect Finite State Machine statistics.
♦ Enable runtime override of parameters/generics
 Verilog/SV parameters: +floatparameters[+selection[.]]
 VHDL generics: +floatgenerics[+selection[.]]
 Limits optimization freedom so avoid unnecessary application
6-32 • HDL Designer Series: Simulation Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

254 HDL Designer Series

Simulation
Lab 4 Overview

Lab 4 Overview

Lab 4 Overview
♦ Having completed the first three labs, you now have a block
diagram called wave_gen that describes the top level of the
system.

♦ You also have completed the three sub-blocks (controller,

counter, and count_feedback) that describe what the system
does.

♦ The purpose of this lab is to familiarize you with the flow chart
editor, plus creating and using a test bench.

♦ In addition you will simulate the complete design using HDL

Designer and ModelSim with its various animation and
debugging features, you will also enable code coverage and
save the results.
6-33 • HDL Designer Series: Simulation Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 255

Simulation
Lab 4 Overview

256 HDL Designer Series

Module 7
Version Management

Objectives
Upon completion of this module, you will be able to:

• Understand Version Management concepts

• Know how to access HDL Designer Version Management Setup
• Understand the various Version Management tasks
• List what Version Management tasks are supported by which Version Management
tools
• Know how to use SVN with HDL Designer Version Management Interface
• Understanding SVN Workspace Operations

HDL Designer Series 257

Version Management
Version Management Concepts

Version Management Concepts

♦ To track and audit changes made to files.

♦ To retrieve previous versions of files.

♦ To control changes made by multiple people.

 Avoid concurrent edits.
 To record why a person made particular changes.

♦ To create and use labels/tags.

 A label/tag is a set of files from a particular point in time.
 The set of files may have different versions.

Notes:

258 HDL Designer Series

Version Management
HDL Designer Environment

HDL Designer Environment

♦ Easy to use and customize Options > Version Management
♦ Supports ClearCase (Rational), DesignSync (Synchronicity),
VSS (Mainsoft or Microsoft Visual SourceSafe), SoS (ClioSoft), SVN (Subversion)
♦ Supports repository locations on remote servers
using a CVS pserver, RSH (remote shell), or SSH (secure shell) mechanism
♦ RCS and CVS are included in HDL Designer installation
♦ Compatible with older repositories
 Support for HDL and downstream data and “Side Objects”
 Available in Design Unit window and all Graphical Editors
 Version Management commands accessible via tool bar buttons

Label
Change Lock Synchronize
Status
Get History
Check Out
Compare against
Check In repository

Notes:

HDL Designer Series 259

Version Management
Setup

Setup

Setup
Options > Version Management

Choose RCS, CVS, DesignSync, VSS,

SoS, SVN, or ClearCase.

Specify repository directories for both

HDS (Graphical) and HDL objects.

Choose objects for version

management operations.

Specify other options.

Notes:

260 HDL Designer Series

Version Management
Check In

Check In

Called Commit in Subversion

Check In
♦ Check In the selected objects (libraries, design units, and
design unit views) to the repository using latest or specified
version.
Single Level or hierarchy
and associated packages.

Allows Side Data to be checked

in with Design Unit view.
(Careful… could contain large To transfer an
binary files) existing label.

Latest or specified version

Label (optional)

Description (optional)
To re-use the last
description.
7-5 • HDL Designer Series: Version Management Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 261

Version Management
Check In

Check In (Cont.)

Before Check-In After Check-In

Read-only (checked in)

Notes:

262 HDL Designer Series

Version Management
Check Out

Check Out

Check Out
♦ Check Out selected objects from repository using
latest/specified version
 Will replace any “read-only” copies which exist in workspace
 Cannot check out a file if it is already “editable”

Single level or
hierarchy and
packages.

Latest or specified
version.

A “Lock” allows only

this user to make edits
to the checked-out
objects. Repository Browser dialog box
appears if nothing selected.

Notes:

HDL Designer Series 263

Version Management
Get

Get

Get
♦ Get performs check-out without a “lock”, creating “read-only”
copies.
 Check-out the selected objects from the repository using latest or
specified version as read only
 Not available for ClearCase
and Subversion.

Single level or hierarchy

and packages.

Latest or specified version.

Replace “editable” files with

“read only” version.

Notes:

264 HDL Designer Series

Version Management
Change Lock

Change Lock

Change Lock
♦ Lock makes selected objects in workspace “editable”.
♦ Unlock makes selected objects in workspace “read-only”.

Lock or Unlock

Notes:

HDL Designer Series 265

Version Management
Label

Label

Label
♦ Add/Remove/Overwrite a
symbolic name for selected
objects.
 The label is used to identify a
set of version controlled
design objects which may have
different individual version
numbers, but share a common
label.
 Not available Subversion.

Add/Remove/Overwrite a label
with a user provided “Label”.

Notes:

266 HDL Designer Series

Version Management
Synchronize

Synchronize

Synchronize
♦ Performs a check-out without a lock.
 Existing “read-only” objects are overwritten.
 Existing “editable” objects ignored.
 Option to update
workspace with
missing files.

Add missing files

Notes:

HDL Designer Series 267

Version Management
Status

Status

Status
♦ Show status of the selected object.

1. Choose options

2. Status displayed

Editable or read-only Labels/Tags

Locker’s Name and Version

Notes:

268 HDL Designer Series

Version Management
History

History

History
♦ Show the version history of selected object.

1. Choose options 2. Choose From the List

Summary

Details

Notes:

HDL Designer Series 269

Version Management
Version Management Tasks Supported

Version Management Tasks Supported

RCS CVS ClearCase DesignSync VSS SoS Subversion

Check In       
Check Out       
Get    
Undo Check
Out (Revert)
     
Change
Lock
   
Adding
Label
     
Synchronize      
Report
Status
      
Reporting
History
      
Compare     
Create a
Branch

Delete 
7-14 • HDL Designer Series: Version Management Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

270 HDL Designer Series

Version Management
When to Use Reference

When to Use Reference

♦ Save the changes in the repository => Check In
 Will save the differences comparing with last version
♦ Retrieve latest/specified version for editing => Check Out
♦ Retrieve latest/specified version in read-only mode for
information => Get
 Give an error message if you get a file which is editable in the
workspace
– Optional “replace writable files”
 Get a library always gets the whole of those currently in the
repository

Notes:

HDL Designer Series 271

Version Management
When to Use Reference

When to Use Reference (Cont.)

♦ Update workspace using latest/specified version in the
repository => Synchronize
 Ignore writable files
 Synchronize a library with objects currently in the workspace
– Optional “add files not currently in my workspace”
 Keep the read-only ones up-to-date with what in the repository
♦ Find the usage information of specified object => Status
♦ Find the version history of selected object => History
♦ Change editing mode of selected object => Change Lock
♦ Define a tag for a group of selected objects for specific
actions like simulation or synthesis => Label

Notes:

272 HDL Designer Series

Version Management
Interface with Subversion (SVN)

Interface with Subversion (SVN)

♦ Prerequisites:
 SVN is not included in HDL Designer and should be installed
separately.
 SVN executable file should be added to the PATH environment
variable.
 SVN Repository should be created manually using SVN
command:
svnadmin create <path to file>
– For Windows : using the DOS shell
– For Linux : using the command line prompt

 SVN Workspace can be simply created as a folder in Windows or

a directory in Linux

Notes:

HDL Designer Series 273

Version Management
SVN Repository

SVN Repository

The command will create a

folder/directory and initialize it
with shown file and folder structure

Notes:

274 HDL Designer Series

Version Management
Setup SVN in HDL Designer

Setup SVN in HDL Designer

♦ SVN is enabled by checking
the “Enable Version
Management” checkbox and
choosing the “SVN VM
interface”.
♦ If the repository location is on:
 A Local Directory, you have to write
“file:///” before the repository
location or browse to the location.

 A Web Server, it should be written

in an URL form
“http://host.example.com”.

 If you are using a server location,

the location should be written as
svn://server_name.

Notes:

HDL Designer Series 275

Version Management
Organizing HDL Libraries within Repository

Organizing HDL Libraries within Repository

♦ All created libraries are
mapped to the same
repository within the same
project.

♦ It is the designer’s choice

either to create one
repository for all his projects
or create a single repository
for each.

♦ The VM mapping is only

used by HDS when initially
adding the library to
repository.

Notes:

276 HDL Designer Series

Version Management
Commit in SVN

Commit in SVN

Commit in SVN
♦ “Commit” in SVN is the same as “check in” in other systems.

Before

Notice the VM version

and the Access Right
before commit

Notes:

HDL Designer Series 277

Version Management
Commit in SVN

Commit in SVN (Cont.)

After

After the Commit, notice that the VM version has incremented

and the Access Right changed to read only.

Notes:

278 HDL Designer Series

Version Management
Editing the Design

Editing the Design

♦ To be able to edit in your design after doing a commit you have to
“lock” the design to prevent simultaneous editing in the design.

DUT >RMB >Version Management >Lock

Notes:

HDL Designer Series 279

Version Management
Editing the Design - Lock

Editing the Design - Lock

♦ After the “Lock”:
– The design has become editable (absence of “x”s)
– VM Lockers column has the name of the user (eg.weaama)
– Note: The VM Versions remains at 1 as no changes have been made
to the design

Notes:

280 HDL Designer Series

Version Management
Editing the Design - Commit

Editing the Design - Commit

♦ Modification to the design will change the VM status to
Modified

♦ Design can be then committed

Version incremented and status changed to up-to-date

Notes:

HDL Designer Series 281

Version Management
Getting Specific Version of the Design

Getting Specific Version of the Design

♦ To update a specific version of a design in the current
workspace use “update”

Version 1 will be retrieved

Notes:

282 HDL Designer Series

Version Management
Reverting Modifications

Reverting Modifications

Reverting Modifications
♦ After modifying your design and before committing the
change, you can revert all the changes.

Notes:

HDL Designer Series 283

Version Management
What Type of Objects do we Need to Lock?

What Type of Objects do we Need to Lock?

♦ HDL Designer has two types of Objects

Graphical Textual

Treated as
Saved as
binary
text files
files.

Can’t be Can be
merged merged

Require Do not
require
lock lock
Graphical Objects need lock
Read only Editable
after after
commit commit

Notes:

284 HDL Designer Series

Version Management
Handling Conflicts

Handling Conflicts

Handling Conflicts
♦ When two users try to commit their changes in the same text files
(both versions are editable in the workspace)
♦ TkDiff” can be used to display the differences made by the two
users.
♦ TkDiff is invoked
After comparing your
file with the one in the
Repository.

Notes:

HDL Designer Series 285

Version Management
SVN Workspace Operations

SVN Workspace Operations

♦ Checking Out the Workspace Directory

♦ Adding the Workspace Directory

♦ Committing the Workspace Directory

♦ Reverting Changes in the Workspace Directory

♦ Updating the Workspace Directory

♦ Reporting the Status of the Workspace Directory

Notes:

286 HDL Designer Series

Version Management
Checking Out the Workspace Directory

Checking Out the Workspace Directory

♦ This procedure allows you to get a writable copy of the repository to
the workspace.

Version Management > Workspace > Check Out Workspace

Notes:

HDL Designer Series 287

Version Management
Adding the Workspace Directory

Adding the Workspace Directory

♦ This procedure allows you to add the entire content of the workspace
directory to the repository on the next commit operation.

Version Management > Workspace > Add Workspace

Notes:

288 HDL Designer Series

Version Management
Committing the Workspace Directory

Committing the Workspace Directory

♦ This procedure allows you to send any changes in the entire
workspace directory to the repository. Any items that have the status
“Modified” or “Added” will have a new version number in the
repository.
Version Management > Workspace > Commit Workspace

Notes:

HDL Designer Series 289

Version Management
Reverting Changes in the Workspace Directory

Reverting Changes in the Workspace Directory

♦ This procedure allows you to undo any local edits in the workspace
directory of the library, such as modified files or files added for the
next commit.

Version Management > Workspace > Revert Workspace

Notes:

290 HDL Designer Series

Version Management
Reverting Changes in the Workspace Directory

Reverting Changes in the Workspace Directory (Cont.)

♦ Note: This procedure revert the workspace to what it was at the latest
commit or checkout operation

Notes:

HDL Designer Series 291

Version Management
Updating the Workspace Directory

Updating the Workspace Directory

♦ This procedure allows you bring the changes done in the
repository to the workspace.

Version Management > Workspace > Update Workspace

Notes:

292 HDL Designer Series

Version Management
Reporting the Status of the Workspace Directory

Reporting the Status of the Workspace Directory

♦ This procedure enables you to view a status report on the
contents of the workspace directory.

Version Management > Workspace > Status Workspace

Notes:

HDL Designer Series 293

Version Management
Reporting the Status of the Workspace Directory

294 HDL Designer Series

Module 8
Add HDL Files/Visualization

Objectives
Upon completion of this module, you will be able to:

• Understand the basics of adding HDL files into HDL Designer

• Explain the three steps of adding HDL files
• Know how to Visualize an HDL design
• Know how to convert an HDL design to graphics

HDL Designer Series 295

Add HDL Files/Visualization
Add Existing HDL Files – Overview

Add Existing HDL Files – Overview

♦ Adding any HDL design into HDL Designer environment
 Automatically recovering structural relationships as hierarchy
 Change to graphics or keep as HDL text
 Many options to control the end-results
 Performs HDL checks
– Non-strict checks
– Detection of syntactic and semantic errors
– Multiple declaration detection
– Black-box detection
– Any behavioral code accepted
♦ HDL Designer pragmas — hds translate_on / hds translate_off
 Gives user the control to instruct HDL Designer to ignore chosen
fragments of HDL
– Instruct HDL Import to ignore specific fragments such as system
functions in Verilog

Notes:

296 HDL Designer Series

Add HDL Files/Visualization
Add Existing HDL Files

Add Existing HDL Files

File > New > Design Content

Notes:

HDL Designer Series 297

Add HDL Files/Visualization
Add Existing HDL Files

Add Existing HDL Files (Cont.)

♦ Alternative Method — Select an empty Library in the Design
Explorer
♦ Choose Document & Visualize

Notes:

298 HDL Designer Series

Add HDL Files/Visualization
Add Existing HDL Files: Step 2 – File Selection

Add Existing HDL Files: Step 2 – File Selection

Copy Files or
reference in place

“Using an Existing Filelist” allows you to specify

a file containing a list of HDL files to import.
8-5 • HDL Designer Series: Add HDL Files/Visualization Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 299

Add HDL Files/Visualization
Add Existing HDL Files: Step 2 – File Selection

Add Existing HDL Files: Step 2 – File Selection (Cont.)

♦ Recursive search of the files when they are spread out in
several directories.

♦ The file list can be saved for later use.

♦ Mixed language can be imported.

Notes:

300 HDL Designer Series

Add HDL Files/Visualization
Add Existing HDL Files: Step 3 – Target Libraries

Add Existing HDL Files: Step 3 – Target Libraries

♦ The files are parsed

and analyzed.
♦ Any warnings or
errors are reported
at that stage.

Import only error free code

Notes:

HDL Designer Series 301

Add HDL Files/Visualization
Add Existing HDL Files: Step 4 – Target Directories

Add Existing HDL Files: Step 4 – Target Directories

Specify additional options.

Can create graphical

representation now or later.

Notes:

302 HDL Designer Series

Add HDL Files/Visualization
Design Explorer with Imported Design Units

Design Explorer with Imported Design Units

Imported
design units

Top level

Design hierarchy

Imported
HDL files

Notes:

HDL Designer Series 303

Add HDL Files/Visualization
Understanding Visualization versus Entry

Understanding Visualization versus Entry

Visualization Entry
Done in
previous
steps 1-4
Read Edit Edit
Code Graphics Text

Generate
Visualize Convert
Code

View HDL

4 View Types 10 Editor Types

Notes:

304 HDL Designer Series

Add HDL Files/Visualization
Visualize Design

Visualize Design

1. Select design unit

2. Select
Document
& Visualize

Notes:

HDL Designer Series 305

Add HDL Files/Visualization
Visualize Options

Visualize Options

♦ The “Visualization Options”

tab provides settings for
generating visualization
views from HDL text views.
♦ More options available under
“Graphics Appearance” tab.

Notes:

306 HDL Designer Series

Add HDL Files/Visualization
Visualization Results

Visualization Results

Visualization Results
♦ Results placed in Files window of Design Explorer

Double-click to open Block Diagram

Notes:

HDL Designer Series 307

Add HDL Files/Visualization
Alternate Step – Convert to Graphics

Alternate Step – Convert to Graphics

HDL > Convert To Graphics > Single Level

HDL > Convert To Graphics > Hierarchy Through Components

♦ Select a design unit

(pure HDL) and generate
a graphical description.
♦ Optional, select an
already visualized
design and convert the
visualized design to a
graphical representation.
♦ This adds a new
“permanent” graphical
view in the Design Unit
window.

Notes:

308 HDL Designer Series

Add HDL Files/Visualization
Alternate Step – Convert to Graphics

Alternate Step – Convert to Graphics (Cont.)

♦ Convert to
Graphics requires
more options
specifying which
Hierarchy options
graphical views
will be used to
describe:
 The hierarchy

Leaf level options  The leaf-levels

Notes:

HDL Designer Series 309

Add HDL Files/Visualization
Alternate Step – Convert to Graphics

Alternate Step – Convert to Graphics (Cont.)

Additional options

Structural
Diagram
options

Notes:

310 HDL Designer Series

Add HDL Files/Visualization
Interactive Routing

Interactive Routing

Interactive Routing
Choose routing
style while
dragging blocks or
components.
♦ Press Z to
choose
routing style:
 River
 Diagonal
 Diagonal Ends
 Dog Leg
♦ Press Ctrl-r to
clean up
routing after
releasing
ghosted object.
8-17 • HDL Designer Series: Add HDL Files/Visualization Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 311

Add HDL Files/Visualization
Lab 5 Overview

Lab 5 Overview

Lab 5 Overview
♦ The purpose of this lab is to familiarize you with the
functionality to add and visualize HDL files.

♦ This lab works independently from the first four labs.

Notes:

312 HDL Designer Series

Module 9
IP and Vendor Flows

Objectives
Upon completion of this module, you will be able to:

• Understand Top-Down design

• Describe ModuleWare
• Understand the FPGA Vendor Tool Integration with Xilinx Core Generation/Vivado
• Understand the FPGA Vendor Tool Integration with Altera
• Know how to import Gate Level into ModelSim
• Know how to run a simulation comparison

HDL Designer Series 315

IP and Vendor Flows
Top-Down Design

Top-Down Design

Top-Down Design
♦ Top-Down Design Flow:
 Concept
 Define design interface to external world
 Define high-level tasks
 Define interfaces between high-level tasks ?
 Design high-level tasks in behavioral VHDL
– Early Simulation of Dataflow
 Develop sub-tasks for each task
RAM
– Define sub-tasks I/O
– Define interfaces CPU
– Develop sub-sub-tasks
– Iterate as necessary
♦ Advantages:
 Divides large designs into easily grasped sections
 Tasks may be assigned to different work groups early in design
cycle

Notes:

316 HDL Designer Series

IP and Vendor Flows
Using HDL Designer for Top-Down Design

Using HDL Designer for Top-Down Design

♦ Process
 Use Block Diagram for top level of design
 Create functional blocks to represent tasks
 Create I/O ports, connect to high-level blocks
 Create interconnections between high-level blocks
– Design high-level blocks in behavioral HDL
 Simulate Dataflow
– If OK, replace behavioral with RTL HDL on block by block basis
 Convert blocks with multiple instances to components
 Open Down into blocks to create lower-level views
– May be any Design Unit Type (State Machine, Block Diagram, etc.)
 Repeat process for lower-level views as necessary

Notes:

HDL Designer Series 317

IP and Vendor Flows
Mixing Top-Down With Bottom-Up Design

Mixing Top-Down With Bottom-Up Design

♦ Use library components(1) for common functions
 ModuleWare — glue logic up to Register level
 LPMs
♦ Use technology specific(2) macrofunctions
 Altera MegaWizard — complex logic, vendor
specific
 Xilinx Cores — complex logic, vendor specific
♦ Use complex IP(3) for standard applications (3)
 PCI, Bluetooth, USB, DSP, Microprocessors
♦ Use Generics/Parameters to create n-bit wide (2)
components
 Design Reuse
 Scalability of Design
(1)
♦ Build higher-level components from existing
components
 For example, BCD Register from BCD Counters

Notes:

318 HDL Designer Series

IP and Vendor Flows
What Is ModuleWare

What Is ModuleWare

What Is ModuleWare
♦ Swiftly add common
functionality to your
design
 Over 120 models
 Parameterizable
– Generates optimized
HDL code
 VHDL and Verilog
 High quality
synthesis
results
 Vendor & technology
independent
 Reference Guide
♦ Drag and drop into:
 IBD
 Block Diagram
 DesignPad
9-5 • HDL Designer Series: IP and Vendor Flows Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 319

IP and Vendor Flows
ModuleWare – Dynamic # of Ports

ModuleWare – Dynamic # of Ports

♦ Available for:
 N-input and variable width logic
gates
 Split and Merge
♦ Simply drag top or bottom of
part to increase/decrease number
of ports
♦ Alternatively change the
setting in the dialog box

Double-click

Notes:

320 HDL Designer Series

IP and Vendor Flows
ModuleWare – Settings Display

ModuleWare – Settings Display

♦ Summary of settings displayed in tooltip
♦ User control over level of detail
 Master & Diagram preferences
 Per-object in parameters dialog box

Options > Master Preferences >

Options > Diagram
Structural Diagram > ModuleWare
Preferences

Notes:

HDL Designer Series 321

IP and Vendor Flows
ModuleWare – Settings Display

ModuleWare – Settings Display (Cont.)

♦ Symbols also show main values
as appropriate

Notes:

322 HDL Designer Series

IP and Vendor Flows
ModuleWare – Automatic Port Widths

ModuleWare – Automatic Port Widths

♦ Port widths derived from nets connected to ports (integer
bounds)
♦ Slice/element support:
 Connect slices/elements directly to ports
 Invalid widths shown by “!” and flagged during generation

Notes:

HDL Designer Series 323

IP and Vendor Flows
ModuleWare – In-Place Changes

ModuleWare – In-Place Changes

♦ Replace with similar parts.

Notes:

324 HDL Designer Series

IP and Vendor Flows
ModuleWare – In-Place Changes

ModuleWare – In-Place Changes (Cont.)

♦ Invert and change mode of ports.

Notes:

HDL Designer Series 325

IP and Vendor Flows
ModuleWare – Language Support

ModuleWare – Language Support

♦ VHDL
 Supports std_ulogic and signed/unsigned in addition to std_logic
 Supported package combinations:
– ieee.std_logic_1164 plus...
– ieee.std_logic_arith or ieee.numeric_std
 “sign_type” parameter retained for arithmetic functions
 Type conversion automatically applied where necessary
♦ Verilog
 Arithmetic parts support signed/unsigned types
 Options based on main style settings:
– Port declarations ANSI-C or List
– @* or comma-separated sensitivity list supported
– New-style attributes or old-style pragmas

Notes:

326 HDL Designer Series

IP and Vendor Flows
FPGA Vendor IP Integration

FPGA Vendor IP Integration

♦ For:
 Altera MegaWizard & SOPC Builder
 Xilinx CORE Generator & Platform Studio
 Xilinx Vivado Flow
♦ Direct access to FPGA vendor IP cores
 Accessible through Tasks window
 Ready for instantiation in Block Diagram, IBD or DesignPad
 Simulation model for verification
 Optimized netlist for vendor Place and Route tool
♦ Prerequisite for Simulation:
 Vendor library must be compiled and mapped for ModelSim (only
once)
 CORE Generator / Vivado/ MegaWizard covered in detail in Lab
Exercise 6

Notes:

HDL Designer Series 327

IP and Vendor Flows
FPGA Vendor IP Integration

FPGA Vendor IP Integration (Cont.)

HDS InfoHub: Application Notes > “HDL Designer Vivado interface common flows”
HDS InfoHub: Application Notes > “Designing with Xilinx's Coregen Components within HDL Designer”
HDS InfoHub: Application Notes > “Designing with Altera’s NIOS II embedded processor in HDL
Designer”

Notes:

328 HDL Designer Series

IP and Vendor Flows
FPGA Tool Integration

FPGA Tool Integration

♦ Choose your technology preference from HDS Setup Assistant Wizard

Notes:

HDL Designer Series 329

IP and Vendor Flows
FPGA Tool Integration – Xilinx CoreGen

FPGA Tool Integration – Xilinx CoreGen

1
Invoke the tool
2
• Select the family,
from My Tasks
language, synthesis
or the Shortcut
tool, library etc.
Bar
• Invoke the Xilinx
Coregen Tool

Notes:

330 HDL Designer Series

IP and Vendor Flows
FPGA Tool Integration – Xilinx CoreGen

FPGA Tool Integration – Xilinx CoreGen (Cont.)

Notes:

HDL Designer Series 331

IP and Vendor Flows
FPGA Tool Integration – Xilinx CoreGen

FPGA Tool Integration – Xilinx CoreGen (Cont.)

♦ The HDL is created and
imported into HDL
Designer.

♦ A symbol is automatically
created.
 Ready for instantiation.
 The Library reference to
Xilinx Core Lib is
automatically added.

♦ Note that the leaf cell is

Notes:

332 HDL Designer Series

IP and Vendor Flows
FPGA Tool Integration – Xilinx CoreGen

FPGA Tool Integration – Xilinx CoreGen (Cont.)

♦ .xco: The CORE Generator
input file containing the
parameters used to
regenerate the core.

♦ .ngc: The binary Xilinx

implementation netlist file
containing the information
required to synthesize the
module in a Xilinx FPGA.

Notes:

HDL Designer Series 333

IP and Vendor Flows
FPGA Tool Integration - Xilinx Vivado

FPGA Tool Integration - Xilinx Vivado

♦ HDL Designer Series

integrates with Xilinx
Vivado.
♦ The goal is to:
 Provide the ability to
simulate a Vivado
project which includes
IP catalog cores
 Allow HDS users to
perform flows in
Vivado through calling
a Vivado Tcl script.

Notes:

334 HDL Designer Series

IP and Vendor Flows
Xilinx Vivado Wizard – Flow Page

Xilinx Vivado Wizard – Flow Page

Project: Vivado Project is created

Allows you to create a new Vivado Non-Project: Vivado will directly process
project or update an existing one the files passed to it

If using vendor primitives or IP, you need

Optionally import Vivado IP from the to compile and map the libraries within
Vivado Project into HDL Designer HDL Designer.

Run your own scripts within the flow

Generates batch scripts which you
can optionally modify or use
Controls whether Vivado is invoked
in the background (batch) or
interactively (GUI)

Notes:

HDL Designer Series 335

IP and Vendor Flows
Xilinx Vivado Wizard – Setup Page

Xilinx Vivado Wizard – Setup Page

Specify the path to Vivado executable

Specify the Compiler version to be

used

Required when creating new project,

otherwise can be left empty

Notes:

336 HDL Designer Series

IP and Vendor Flows
Xilinx Vivado Wizard – Create/Update Page

Xilinx Vivado Wizard – Create/Update Page

Removes files from Vivado project

not from disk

Control how Design files

are added to the Vivado
Project

Any existing IP in the Vivado

project will be retained

This reports the list of

design and IP files
which will be passed
to Vivado

Notes:

HDL Designer Series 337

IP and Vendor Flows
Xilinx Vivado Wizard – Compile Simlib Page

Xilinx Vivado Wizard – Compile Simlib Page

♦ This step compiles

the Xilinx
simulation libraries
for use in the
current project or in
If working in a team all projects.
♦ This flow is
supported in both
project and non-
project modes.
You can control
whether existing
mappings are
retained or
overwritten.

Notes:

338 HDL Designer Series

IP and Vendor Flows
Xilinx Vivado Wizard – Import IP Page

Xilinx Vivado Wizard – Import IP Page

♦ This page is used to
import Vivado IP
into HDL Designer
and compile it.
♦ Once imported, you
can instantiate and
simulate Vivado IP
within your HDL
Designer project

Notes:

HDL Designer Series 339

IP and Vendor Flows
Import Vivado IP Example

Import Vivado IP Example

This flow will show how to import a Vivado IP from Vivado project to your HDL
Designer project.
2
In the Flow
Page

1
Select the top
design unit
and press
Xilinx Vivado
Flow

Notes:

340 HDL Designer Series

IP and Vendor Flows
Import Vivado IP Example

Import Vivado IP Example (Cont.)

♦ In the Vivado GUI (Create IP using the IP Catalog)
3
• Open the
IP Catalog
• Select the
IP

Notes:

HDL Designer Series 341

IP and Vendor Flows
Import Vivado IP Example

Import Vivado IP Example (Cont.)

5 6
• In the Flow • In the Import
Page, select Page, select
import IP and copy files and
launch the tool in compile the
Batch mode instantiated IP

Notes:

342 HDL Designer Series

IP and Vendor Flows
Import Vivado IP Example

Import Vivado IP Example (Cont.)

7
• In the IP Import
Dialog, select all
available IPs

♦ In HDL Designer

♦ Within HDL Designer instantiate

the IP in a Block Diagram or HDL
code
♦ Run simulation
♦ Ensure simulation elaborates

Notes:

HDL Designer Series 343

IP and Vendor Flows
FPGA Tool Integration - Altera

FPGA Tool Integration - Altera

2
1 Create a new
Invoke the tool megafunction
from My Tasks or import an
or the Shortcut existing one.
Bar 2

3
• Select Application
(Quartus/Quartus
II or Max+PLUS
II).
• Specify the
destination library.

Notes:

344 HDL Designer Series

IP and Vendor Flows
FPGA Tool Integration - Altera

FPGA Tool Integration – Altera (Cont.)

♦ Megafunction creation can be done through MegaWizard or IP

Catalog depending on the Altera Quatrus II used version

Starting from
In Quatrus II Quatrus II
version 13.0 an earlier version 14.0

Notes:

HDL Designer Series 345

IP and Vendor Flows
FPGA Tool Integration - Altera

FPGA Tool Integration – Altera (Cont.)

1 2
Invoke Select the
Quatrus II, device family
open the IP
Catalog

3
Select the
Megafunction

Notes:

346 HDL Designer Series

IP and Vendor Flows
FPGA Tool Integration - Altera

FPGA Tool Integration – Altera (Cont.)

4
Choose the
parameters

Can generate netlist for timing

and resource estimation.

Notes:

HDL Designer Series 347

IP and Vendor Flows
FPGA Tool Integration - Altera

FPGA Tool Integration – Altera (Cont.)

♦ The IP is created outside the HDL Designer environment.
♦ Needs to be imported to the project.

Browse to where
you saved your
variation

1
Select the top
design unit
and invoke
Altera
MegaWizard

Notes:

348 HDL Designer Series

IP and Vendor Flows
FPGA Tool Integration - Altera

FPGA Tool Integration – Altera (Cont.)

♦ The new HDL component is imported into HDL Designer

♦ .cmp: VHDL component declaration file

♦ .qip: Quartus II IP File – lists the files necessary
for Quartus II compilation
♦ .jpg / .html: Sample waveforms
♦ .v: Synthesis area and timing estimation netlist

Notes:

HDL Designer Series 349

IP and Vendor Flows
Add Gate Level Netlist

Add Gate Level Netlist

♦ Back annotate the design by

adding a VHDL or Verilog gate
level netlist created by the
Place & Route tool.

RMB > Add > Gate Level

Notes:

350 HDL Designer Series

IP and Vendor Flows
Add Gate Level Netlist

Add Gate Level Netlist (Cont.)

♦ Add the netlist model into the hdl library as an alternative design
unit view, or create a reference to the model in the downstream
library (or other external location).
♦ The added netlist automatically becomes the default view for the
Design Unit (if enabled).

1. Browse to HDL Netlist

2. Browse to SDF File

3. Copy or Reference
the Files
New Gate Level Netlist

Notes:

HDL Designer Series 351

IP and Vendor Flows
Simulation Comparison

Simulation Comparison

Simulation Comparison
♦ There is an easy way to validate the post-synthesis (eventually,
back-annotated simulation) results using the waveform
comparison feature of ModelSim / QuestaSim.

♦ Create a folder (e.g.

Golden_Results) in 2. Create a folder
the Side Data
window to store the
1. Select the test bench 3. Copy
RTL HDL simulation
results called by
default vsim.wlf
(copy from the
Downstream
window).

Notes:

352 HDL Designer Series

IP and Vendor Flows
Simulation Comparison

Simulation Comparison (Cont.)

Tools > Waveform Compare > Comparison Wizard

♦ Simulate the test bench in ModelSim with
the imported gate level netlist from the
Place & Route tool.
♦ Follow the wizard indications.

Notes:

HDL Designer Series 353

IP and Vendor Flows
Simulation Comparison

Simulation Comparison (Cont.)

♦ Follow the wizard indications:

Notes:

354 HDL Designer Series

IP and Vendor Flows
Simulation Comparison

Simulation Comparison (Cont.)

♦ To finally see the differences in red

♦ With some neat options for smart comparison

Notes:

HDL Designer Series 355

IP and Vendor Flows
Lab 6 Overview

Lab 6 Overview

Lab 6 Overview
♦ The purpose of this lab is to familiarize you with the Xilinx
CORE Generator or Altera MegaWizard integration of HDL
Designer.

♦ You will modify the Wave Generator you created in labs 2-4 to
add a component from either the Xilinx CORE Generator/
Vivado or the Altera MegaWizard, as appropriate.

♦ The design will then be synthesised in Precision, and place

and routed in Xilinx or Altera.

♦ Finally, you will add the gate level netlist and timing to the
design and compare RTL simulation results against post-
layout simulation results in ModelSim.

Notes:

356 HDL Designer Series

Module 10
Setup and Team Design

Objectives
Upon completion of this module, you will be able to:

• Know how to set and use Resource Settings

• Understand User/Team Preferences
• Know how to set Main settings
• Know how to set Code Generation preferences
• Know how to use User/Team templates
• Know how to set Version Management Setup options for Teams

HDL Designer Series 357

Setup and Team Design
Resource Settings

Resource Settings

Resource Settings
Resource settings allow:
1. Setting the design environment (text editor, third party tools)
2. Defining the graphical environment
3. Controlling code generation format

♦ Tool Settings
 Compiler, Simulator, Synthesizer, Custom tools
♦ General Preferences
 Text Editor, Check, Save
♦ Editors
 Structural Diagram, Interface, State Diagram, Flow Chart, Truth Table
♦ Code generation
 VHDL, Verilog
♦ Two levels of Resources:
Resource settings can be set by
 User Resources individual users or by teams.
 Team Resources
10-2 • HDL Designer Series: Setup and Team Design Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

358 HDL Designer Series

Setup and Team Design
Team Requirements

Team Requirements

Team Requirements
Internal IP Web Review Documentation

Notes:

HDL Designer Series 359

Setup and Team Design
Resource Settings: User / Team

Resource Settings: User / Team

Team Administrator

User A
User can
reference
the team
User B resources
directory
location.

User C
e.g. Windows 7:
C:\Users\<username>\AppData\Roaming\
HDL Designer Series\hds_user

Notes:

360 HDL Designer Series

Setup and Team Design
Setting Up for Teams

Setting Up for Teams

Options > Main
♦ Once the tool is set up, “publish”
♦ Copy team preferences to a central
location
♦ Team points to central team
preferences (set files read-only for
designers)

Notes:

HDL Designer Series 361

Setup and Team Design
User and Team Resource Settings

User and Team Resource Settings

User Mode Team Mode

♦ Default mode when HDS ♦ Can be set: Options> main>
invoked for the first time. Switch To Team Mode.

♦ Preferences are saved in user ♦ Preferences are saved in team

directory: directory:
 -user_home switch  -team_home switch
 $HDS_USER_HOME  $HDS_TEAM_HOME

♦ Preferences can be set by user ♦ Preferences can only be set by

administrator

Notes:

362 HDL Designer Series

Setup and Team Design
Resource Settings: Location (Ref. Page)

Resource Settings: Location (Ref. Page)

♦ User Resource Settings
 Location specified by the -user_home command line switch if set.
 Location specified by the HDS_USER_HOME environment variable if set.
 The current working directory when the tool is invoked if found.
 The user directory ($HOME on Linux or user profile on Windows) if found.
 If no resource files exist at any of these locations, a set of hard-coded
defaults are used.

♦ Team Resource Settings

 Include Generation Properties, HDL Filename Templates, Version
Management, Team Tasks and Team Templates setup options.
 Team preferences should be read-only.
 Location specified by the -team_home command line switch if set.
 Location specified by the HDS_TEAM_HOME environment variable if set.
 Location specified in the General tab of the Main Settings dialog box.
 The current working directory when the tool is invoked if found.
 The user directory ($HOME on Linux or user profile on Windows) if found.
 If no resource files exist at any of these locations, the installation defaults
are used.

Notes:

HDL Designer Series 363

Setup and Team Design
Team and User Preferences

Team and User Preferences

♦ The HDL Designer Series supports:
 Team preferences which are intended to be shared by all
members of a team working on the same design

 User preferences which can be set by each individual user

♦ Team preferences can only be set by an administrator who

has write access to the team preferences directory location.

♦ The team preferences include

 HDL filename rules
 Generation properties
 File registration
 Version management setup options

Notes:

364 HDL Designer Series

Setup and Team Design
Team and User Preferences

Team and User Preferences (Cont.)

♦ The user preferences include:
 Options for general setup
 Options for text and diagram creation
 HDL generation checks
 Options for saving diagrams
 You can also set preferences for VHDL, Verilog, design
management, HDL2Graphics and each type of graphic diagram.

♦ Most of the preferences can be set using dialog boxes which

are accessed from the Options menu

Notes:

HDL Designer Series 365

Setup and Team Design
Main Settings: General

Main Settings: General

Options > Main
♦ The General tab provides
general setup and
configuration preferences.
 File Naming:
– Automatically downcase
design unit names as they are
entered
– Display Actual filenames or
logical names

 Toolbar buttons remain active

after using a toolbar or menu
command.

 Switch between Team Mode

and Single User Mode

Notes:

366 HDL Designer Series

Setup and Team Design
Main Settings: General

Main Settings: General (Cont.)

 Specify an alternative
directory for the temporary
files created during HDL
compilation

 Specify the default

measurement units used for
printing

 Set the default HDL language

for new VHDL and Verilog
views

Notes:

HDL Designer Series 367

Setup and Team Design
Main Settings: Text Editor

Main Settings: Text Editor

Options > Main > Text
♦ The editor and the viewer can
be different.
♦ A default text editor
“DesignPad” is provided.
♦ Other editors can be added.

Notes:

368 HDL Designer Series

Setup and Team Design
Main Settings: Diagrams

Main Settings: Diagrams

Options > Main > Diagrams ♦ Specify the default font
♦ Reference the title block
 Specify location of
template title block
used in new diagrams
 Defaults to
$HDS_TEAM_VER/title_
block.tmpl
♦ Enable Strokes

Notes:

HDL Designer Series 369

Setup and Team Design
Main Settings: Checks

Main Settings: Checks

Options > Main > Checks
♦ Sets up checks when HDL
code is parsed or generated
♦ Reported in Log Window
♦ Can analyze if code is
synthesizable
♦ Strict checking creates
failures versus warnings

Notes:

370 HDL Designer Series

Setup and Team Design
Main Settings: Save

Main Settings: Save

Options > Main > Save

♦ Auto-save
♦ Create backup file
♦ Update symbol/Interface
♦ Update view

Notes:

HDL Designer Series 371

Setup and Team Design
Main Settings: User Variables

Main Settings: User Variables

Options > Main > User Variables ♦ Allows you to enter variables
as name and value pairs.
♦ To use a variable, enter the
variable name preceded by the
% character.

Notes:

372 HDL Designer Series

Setup and Team Design
Code Generation

Code Generation

Code Generation
♦ HDL File naming convention.
 Based on the file type (entity, architecture, package)
 Split or combined
 Case control
♦ Coding style setting.
 Keyword case control
 indentation
♦ HDL Generation options.
 Language dependent, Script creation process
♦ The coding style can also be controlled from the editors (e.g.
SM coding style) to abide by the Corporate standards as much
as possible.
♦ The HDL code generation can be interrupted by holding down
the Esc key (only on Windows, not on Linux).

Notes:

HDL Designer Series 373

Setup and Team Design
Code Generation Preferences – VHDL

Code Generation Preferences – VHDL

Options > VHDL > File

To be compliant with the

user’s company:

- Naming convention
- Syntax and coding style
- Flow requirements

Notes:

374 HDL Designer Series

Setup and Team Design
Code Generation Preferences – VHDL

Code Generation Preferences – VHDL (Cont.)

Options > VHDL > Style

Notes:

HDL Designer Series 375

Setup and Team Design
Code Generation Preferences – VHDL

Code Generation Preferences – VHDL (Cont.)

Options > VHDL > Headers

Notes:

376 HDL Designer Series

Setup and Team Design
Code Generation Preferences – VHDL

Code Generation Preferences – VHDL (Cont.)

Options > VHDL > Default Packages

Notes:

HDL Designer Series 377

Setup and Team Design
Code Generation Preferences – Verilog

Code Generation Preferences – Verilog

Options > Verilog > File

Notes:

378 HDL Designer Series

Setup and Team Design
Code Generation Preferences – Verilog

Code Generation Preferences – Verilog (Cont.)

Options > Verilog > Style

Notes:

HDL Designer Series 379

Setup and Team Design
Code Generation Preferences – Verilog

Code Generation Preferences – Verilog (Cont.)

Options > Verilog

Notes:

380 HDL Designer Series

Setup and Team Design
User Template Creation

User Template Creation

♦ Specify default template for each category.

♦ Optional file naming rules contained in template.

 Fixed name (e.g. untitled)
 File name template using internal/user defined variables
– E.g. %(entity_name)_ent

♦ Templates can contain variables which can be automatically

elaborated or manually edited in the wizard when used.

Notes:

HDL Designer Series 381

Setup and Team Design
User Template Creation

User Template Creation (Cont.)

File > New > Design Content

Notes:

382 HDL Designer Series

Setup and Team Design
User Template Creation

User Template Creation (Cont.)

Notes:

HDL Designer Series 383

Setup and Team Design
User / Team Templates

User / Team Templates

♦ Templates provided for all standard
Verilog and VHDL constructs.
♦ Customized templates can be created
to meet company, team, and
individual needs.
♦ Templates are saved in a Template
directory.
 User and/or Team preferences
– Move/Copy between User/Team
– Must be Team Admin to edit Team
Templates
– Default User set placed in
hds_user/<ver>/templates
– Team Templates reside in
hds_team/<ver>/templates (initially
empty)
 View type implied from directory (e.g.
VHDL Architecture).
 Can be exchanged easily — not buried
in preferences file.

Notes:

384 HDL Designer Series

Setup and Team Design
User/Team Templates and Tasks

User/Team Templates and Tasks

In In
User Mode Team Mode

Notes:

HDL Designer Series 385

Setup and Team Design
Version Management Team Preferences

Version Management Team Preferences

♦ Version Management is an important part of team design

♦ Synchronization between team members is important to

maintain one up-to-date design repository

♦ HDL Designer supports SVN specific version management

team preferences

 Team Preference setting to force Commit to perform multiple SVN

Operations
 Team Preference setting to force locking on all design units in order to
modify

Notes:

386 HDL Designer Series

Module 11
DesignChecker

Objectives
Upon completion of this module, you will be able to:

• Understand Design Checking

• Know what types of checks can be performed with DesignChecker
• Understanding the DesignChecker process
• Understanding Base Rules
• Create a policy
• Launch DesignChecker
• Examine the results
• Fix violations
• Export results

HDL Designer Series 395

DesignChecker
Introducing Static Design Checking

Introducing Static Design Checking

♦ What is Design Checking?
 Evaluating RTL code to determine if there exists any violations
based on a set of coding rules.

♦ What is Static Design Checking?

 Checks that:
– Can be validated based on the code alone: at face value or by
inference.
– Do not require a translation to a gate-level netlist.
– Do not require synthesis, simulation, DFT, or formal engines.

♦ What is Deep Checking?

 To improve checking a simple synthesis is initiated.
 Only used where a rule that requires it is included in Policy.

Notes:

396 HDL Designer Series

DesignChecker
What Types of Checks Can Be Performed?

What Types of Checks Can Be Performed?

♦ Good coding practices: Ensure expected and good results
 No extra or unused signals
 Avoid internally-generated resets
 No multiply-driven signals
 Check for clock boundary crossing and synchronization
♦ Format and readability: Make code easy to understand
 Establish complexity rules (number of objects allowed or nesting levels)
 Use separate lines for each statement
 Establish a common order of statements
 Establish the maximum characters per line
 Choose a common FSM coding style
♦ Downstream tool checks: Catch issues before running other tools
 Avoid latches and inferred registers
 Ensure naming compatibility with downstream tools
 Avoid default initialization
 Establish a subset of allowed constructs
 Use complete sensitivity lists

Notes:

HDL Designer Series 397

DesignChecker
What Types of Checks Can Be Performed?

What Types of Checks Can Be Performed? (Cont.)

♦ Portability/reuse checks: Ensure easy reuse of source code
 Do not use hard-coded numeric values
 Adhere to a naming convention
 Use standard types
 Adhere to a common vector/bus order
 Establish common methodology for what items should exist in
separate files (constants, parameters, etc.)
♦ Cross-language compatibility: Enable language translation
 Use a common subset of language constructs
 Avoid use of keywords as identifiers
 Avoid language-specific instances of gates
 Use named associations
 Avoid mixed-case names
 Do not use the same name for different identifiers

Notes:

398 HDL Designer Series

DesignChecker
Understanding the Process

Understanding the Process

Configure Ruleset(s)
Setup:
Designer/Manager
Define Policies

Run Checks
Results:
Designer
Analyze Results

Notes:

HDL Designer Series 399

DesignChecker
DesignChecker Node

DesignChecker Node

DesignChecker Node
♦ Includes Policies, Rulesets, Master Clocks
and Resets, and Exclusion Pragmas
♦ HDL Designer Explorer Mode
 Change the path to policies
 Set a default policy
 Change the path to rulesets
 Set master clocks and resets
 Enable/disable the DesignChecker
checking_off/on exclusion pragma
♦ Invoke DesignChecker to manage policies
and Rulesets

Notes:

400 HDL Designer Series

DesignChecker
Understanding Base Rules

Understanding Base Rules

♦ Viewed in DesignChecker GUI

♦ Stored in Rulesets (folders)
♦ Organized by topic
 Refined over time
 No overlaps
♦ Read-only — but you can view
the parameters
♦ Internal to the tool
♦ Cannot be added by you

Notes:

HDL Designer Series 401

DesignChecker
Built-In Rulesets

Built-In Rulesets

Built-In Rulesets
♦ Supports out-of-the-box use
 Reuse Methodology Manual- 3rd Edition
 Altera
 Xilinx
 Safety-Critical
 DO254 – extends Safety Critical
 Checklist – 0-in checks
 Essentials – default, core checks
writeable

Run Examine Results Add to your Ruleset Modify Parameters

Notes:

402 HDL Designer Series

DesignChecker
Quickly Build Own Rulesets (Designer/Manager)

Quickly Build Own Rulesets (Designer/Manager)

♦ Create ruleset(s)
 A ruleset is simply a folder
 Use good organization
– Descriptive naming
– Use hierarchy
– Allows convenient on/off ability
– The hierarchical groupings can also
be called rulesets
♦ All ruleset names within a hierarchy
must be unique
♦ Drag and drop base rulesets and
rules into your own rulesets
♦ Change rule parameters

Notes:

HDL Designer Series 403

DesignChecker
DesignChecker Options

DesignChecker Options

Options > Design Quality Options

♦ Include Disabled Rules

 Add disabled rules to Quality Score

Notes:

404 HDL Designer Series

DesignChecker
Getting Help on Rules

Getting Help on Rules

♦ Select the rule then ask for help

♦ Other rule help available:
 Base Rule Reference Guide
 Common Base Rule Parameters
 Regular Expressions
♦ Presented in HTML format

Notes:

HDL Designer Series 405

DesignChecker
Editing Parameters

Editing Parameters

Editing Parameters
♦ Within the Parameter window
 Enter strings
 Select from dropdown lists
 Choose from dialog boxes

Example 1:

Notes:

406 HDL Designer Series

DesignChecker
Editing Parameters

Editing Parameters (Cont.)

♦ Strings that you enter are checked
for errors
Example 2:

Double-click to open

Notes:

HDL Designer Series 407

DesignChecker
Creating a Policy (Designer/Manager)

Creating a Policy (Designer/Manager)

♦ A policy is a named link to rulesets.

 Allows you to de-activate
rulesets/rules.
 Always reflects referenced rulesets.
 Multiple policies allowed — only one
“in play”.

♦ Policy names must be unique.

♦ Drag and drop rulesets into policy.

Notes:

408 HDL Designer Series

DesignChecker
Launching DesignChecker (Designer)

Launching DesignChecker (Designer)

♦ Select a design unit or file in
one of the browsers.
♦ Select a Policy to run (or create
a new one).
♦ DesignChecker automatically
detects clocks and resets, but
you can explicitly identify them
as well (use RMB).
♦ Simple click on the Check
button, or RMB on the Check
button, and decide to run
analysis on:
 Run Single
 Run Through Blocks
 Run Through Components
 Run Through Design Root
♦ DesignChecker analysis
results appear in their own
window.
11-15 • HDL Designer Series: DesignChecker Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 409

DesignChecker
Examine the Results (Designer)

Examine the Results (Designer)

New Tab
with Results

Notes:

410 HDL Designer Series

DesignChecker
Results Summary

Results Summary

Design Information

Design Quality

Notes:

HDL Designer Series 411

DesignChecker
Results Summary

Results Summary (Cont.)

Violations by Rules
Violations by
Design Units

Notes:

412 HDL Designer Series

DesignChecker
Interact With the Summary

Interact With the Summary

♦ Click on any row.
♦ The “Results” view changes accordingly.
♦ Get the original view back easily.

Notes:

HDL Designer Series 413

DesignChecker
Fix Violations

Fix Violations

Hierarchical Columns

Explicit Violation Message

Code Snippet

Hint

Notes:

414 HDL Designer Series

DesignChecker
Trace to Graphics

Trace to Graphics

Trace to Graphics
♦ Correct graphically
♦ Re-run DesignChecker (code automatically regenerated)

Click Open Source

or double-click line number.

Notes:

HDL Designer Series 415

DesignChecker
Trace to HDL Code

Trace to HDL Code

♦ Trace from violation ♦ Use to analyze and debug violations
♦ Or, start in DesignPad ♦ Re-run the analysis

Click Open HDL

or use the RMB.

Notes:

416 HDL Designer Series

DesignChecker
Using the Code Browser

Using the Code Browser

♦ Shows errors, warnings, and
notes for each design object

♦ Provides a method to quickly

find trouble spots and to
navigate right to them

♦ Totals roll up to the design

unit/folder level

Notes:

HDL Designer Series 417

DesignChecker
DesignChecker Viewpoints

DesignChecker Viewpoints

DesignChecker Viewpoints
♦ Viewpoints allow you to sort and filter check reports in
differing ways:
♦ Severity and Ruleset ♦ Severity and File

Notes:

418 HDL Designer Series

DesignChecker
DesignChecker Viewpoints

DesignChecker Viewpoints (Cont.)

♦ Use viewpoint manager
to:
 Change the sort order of
the results (using
groups).
 Change visible columns.
 Filter what parts of
results are visible.
 Make own viewpoints,
containing any of the
above.

Notes:

HDL Designer Series 419

DesignChecker
Export Results

Export Results

♦ Export result table, summary report, exclusions, rule details,

and/or checked files/design units as CSV, TSV, or HTML.
♦ Export the violation report from DesignPad.

Notes:

420 HDL Designer Series

Module 12
Interface Based Design

Objectives
Upon completion of this module, you will be able to:

• Understand Interface Based Design

• Understand IBD Elements
• Understand IBD Features
• Understand Grouping
• Know how to create IBD Viewpoint
• Understand IBD Visualization

HDL Designer Series 421

Interface Based Design
Interface Based Design: Overview

Interface Based Design: Overview

♦ IBD represents the structure of a design by a tabular description of
the interfaces between blocks.
♦ IBD and the corresponding block diagram are two ways to display
the same information. You can switch from one to the other.
♦ HDS preserves the full synchronization between both views after
editing.
♦ Whatever you edit and save in one view is updated in the other.

Table > Edit as Block Diagram Diagram > Edit as IBD

Table > Visualize as Block Diagram Diagram > Visualize as IBD

Edit/Visualize as Block Diagram

Notes:

422 HDL Designer Series

Interface Based Design
Interface Based Design: Overview (cont.)

Interface Based Design: Overview (cont.)

♦ Manage the fine details of the design while still visualizing the
big picture
 Can see both the “forest and the trees”.
♦ Rapid design capture for complex designs.
♦ Editing and filtering mechanisms of tabular represented data.
♦ Clear, concise design documentation .
 Visualize full/partial block diagrams from IBD and vice-versa.
♦ Synchronized 2-way editing between IBD and block diagram.

Notes:

HDL Designer Series 423

Interface Based Design
Interface Based Design: Utilization

Interface Based Design: Utilization

♦ IBD can be used in three different but complementary areas:
 Productive Design Entry tool
– Easy and rapid entry of complex designs — spreadsheet approach
– Easy to describe complex interconnection and hierarchy
– Design can be created piece by piece
 Documentation tool
– Direct copy/paste into other documents (OLE supported)
– Better readability than huge block diagrams
– Ability to split a big design in sub-tables
– Filter to investigate items of interest
 Design Re-Use tool
– Creation of the IBD table at import
– Easy to read/navigate for design reviews (sub-tables)
– Easy to find the interconnection between functional blocks in
existing HDL

Notes:

424 HDL Designer Series

Interface Based Design
IBD Elements

IBD Elements

Unconnected
IBD Elements Blocks, IP, Initial
ports components Value
Port maps

Port/Signal name, Top level ports Comments

Interconnect
type, and bounds

Notes:

HDL Designer Series 425

Interface Based Design
IBD Features

IBD Features

IBD Features
♦ Multi-Level Grouping
 Columns/nets
 Any number of levels
 Group Name plus optional group comments
♦ Multi-level Filtering
♦ Automatic and manual “drag and drop” row ordering
♦ Move columns/rows
♦ Show/Hide columns
♦ Sort columns/rows
♦ Auto-Size
♦ Split Window
♦ Control cell appearance
♦ Rapid entry:
 Single-click edit
 Context-sensitive dropdown menus
 Spreadsheet-like (series fill, drag fill, drag select, etc.)
 Copy/Move Here

Notes:

426 HDL Designer Series

Interface Based Design
Grouping

Grouping

♦ Row grouping
 Grouping rows of signals.
 Useful for analysis and
organization of a large
design.
 Group I/O, bus signals,
etc.
 Groups can be labeled
with multi-line comments.

Notes:

HDL Designer Series 427

Interface Based Design
Grouping

Grouping (Cont.)

Grouping (Cont.)
♦ Column grouping
 Group columns of instances, user columns, etc.
 Helps with organization.
 Groups can be nested.

Notes:

428 HDL Designer Series

Interface Based Design
Hide/Show Columns

Hide/Show Columns

Hide/Show Columns
1. Select columns.

Notes:

HDL Designer Series 429

Interface Based Design
Filter Columns/Rows

Filter Columns/Rows

Filter Columns/Rows
♦ Display and work on a subset of the design.
♦ Save as IBD viewpoint to provide persistent views of filtered data.
♦ AND/OR logic filtering.
♦ Perform any combination of row/column filtering and show/hide
contents.

or
Data > Filters > Filter Settings
Data > Filters > Filter Rows and Columns

Notes:

430 HDL Designer Series

Interface Based Design
Filter Rows

Filter Rows

1. Enter a simple
match string.

3. Add additional strings or dropdown

list choices to refine filter.

4. Select <Create Viewpoint> to save.

Notes:

HDL Designer Series 431

Interface Based Design
Create Viewpoint

Create Viewpoint

1. Select desired rows and/or columns.

RMB > Create Viewpoint

3. Select and rename as desired.

Notes:

432 HDL Designer Series

Interface Based Design
Visualization

Visualization

Visualization
♦ A filtered IBD view can be visualized as a block diagram.

Notes:

HDL Designer Series 433

Interface Based Design
Net-Centric Connectivity

Net-Centric Connectivity

Expanded to see
Port and/or Actual.

Port and Actual

collapsed.

Enter Port name if

Select I, O, or B.
different than net.

Signal/port IO stubs automatically added to design unit.

Notes:

434 HDL Designer Series

Interface Based Design
Port-Centric Connectivity – Unconnected Ports

Port-Centric Connectivity – Unconnected Ports

Number of
unconnected.

Expanded to
show details. Filter on
direction.

Connect to new/existing
nets or expressions.

Notes:

HDL Designer Series 435

Interface Based Design
Quick Connect

Quick Connect

Quick Connect
♦ Rapidly connect
multiple ports
across the table.
♦ Select 2 or more
unconnected
ports or
1 net and 1 or
more
unconnected
ports.
 LMB to select
first item,
Ctrl+LMB to
select
additional
items.
♦ RMB > Connect

Notes:

436 HDL Designer Series

Interface Based Design
Quick Connect

Quick Connect (Cont.)

Notes:

HDL Designer Series 437

Interface Based Design
Signal Busses

Signal Busses

Signal Busses
♦ Individual bits or slices can be ripped from a bus.
♦ Busses or slices can be parameterized.
2. or Add > Slice

1. Select net row.

4. Connect
as desired.
3. Specify index
or slice range.

Notes:

438 HDL Designer Series

Interface Based Design
Bundles in IBD

Bundles in IBD

2.
♦ Visually represent
several signals between
blocks.
♦ Similar to block diagram
implementation.
♦ Net declarations
separate from bundle.

4. Select and rename as desired.

1. Select signal
rows for bundle.

Notes:

HDL Designer Series 439

Interface Based Design
Port Map Expression

Port Map Expression

1. or Add > Expression Row

3. Enter or
2. Enter select signal
expression. or expression.

4. (optional) Select
expression row, Add >
Slice, make selection
in new expression row.

5. Resulting code.

Notes:

440 HDL Designer Series

Interface Based Design
Generate Frames

Generate Frames

Generate Frames 2.

♦ Several kinds of frames

supported: 1. Select instance.
 FOR – replicate an instance.
 IF – conditional structures.
 ELSE – can be used with an IF 3. Select and edit as needed.
frame.
 BLOCK – objects to be
generated as concurrent HDL
statements (VHDL only).
♦ Flexible Port Mapping for
complex connections. g0: FOR k IN 0 TO 2 GENERATE
♦ Add objects into a Frame I0 : alu
port map (
or operator => ctrl(2+k*3 downto k*3),
♦ Add a frame to a selected set operand1 => A(7-k*8 downto k*3),
operand2 => B(7-k*8 downto k*3),
of columns. result => Y(7-k*8 downto k*3)
);
end generate g0;
4. Resulting code.

Notes:

HDL Designer Series 441

Interface Based Design
Adding a Level of Hierarchy

Adding a Level of Hierarchy

♦ Create a level of hierarchy by adding a block, and push down
by double-clicking.

♦ Then enter a DU name and a view name. It can be

another IBD Table.

Notes:

442 HDL Designer Series

Interface Based Design
Adding Requirement References

Adding Requirement References

2. Add/paste requirement references.

1. Toggle
row on/off
with toolbar
button.

3. Space separated if multiple.

Notes:

HDL Designer Series 443

Interface Based Design
Adding Requirement References

444 HDL Designer Series

Module 13
Documentation and Viewpoints

Objectives
Upon completion of this module, you will be able to:

• Know how to document with OLE

• Understand documentation with HTML export
• Understand Viewpoints – Visualize design data
• Know how to use Report Where Used
• Report unbound components

HDL Designer Series 445

Documentation and Viewpoints
Documentation Using OLE: Overview

Documentation Using OLE: Overview

♦ HDL Designer Series diagram editor views (block diagram,
state diagram, and flow chart) support the Windows OLE
(Object Linking and Embedding) standards.
♦ These views can be imported into any OLE compatible PC
documentation tool:
 Microsoft Office applications
 Adobe FrameMaker

♦ Table editor views (truth table, tabular IO and IBD) support

OLE for tools which recognize enhanced metafiles.
♦ Microsoft Office XP or newer, but not FrameMaker.
♦ Enhanced metafiles required to display vertical text in diagram.
♦ Rotate vertical text in diagram if documentation tool does not
support enhanced metafiles.

Notes:

446 HDL Designer Series

Documentation and Viewpoints
Documentation Using OLE: Overview

Documentation Using OLE: Overview (Cont.)

♦ The interface used for importing OLE objects varies between
tools:
 Direct import by drag and drop.
 Insert Object or Import Object command.
♦ What does OLE mean in practice?
 Your documentation is truly automatically updated when you
modify the view in HDL Designer.
 You can also modify your view directly from the document.
 It is a real dynamic document!

Notes:

HDL Designer Series 447

Documentation and Viewpoints
Documentation Using OLE: Requirements

Documentation Using OLE: Requirements

♦ A few requirements before you can use OLE:
 The .hdp project file that contains the library mapping
information must be saved in a standard location which can be
accessed from the documentation tool.
 Initialization and preferences files saved in a working directory or
at locations specified by the HDS_LIBS and HDS_USER_HOME
environment variables cannot be used when using OLE.
♦ OLE is not supported on Linux.

Notes:

448 HDL Designer Series

Documentation and Viewpoints
Documentation Using OLE: Drag Bar

Documentation Using OLE: Drag Bar

♦ Enabling OLE for the current view from the editor:

Window > OLE

Notes:

HDL Designer Series 449

Documentation and Viewpoints
Documentation Using OLE: Panels

Documentation Using OLE: Panels

♦ Panels and multiple views (concurrent state machines or flow
charts) are supported.

Notes:

450 HDL Designer Series

Documentation and Viewpoints
Documentation Using OLE: Link or Copy

Documentation Using OLE: Link or Copy

♦ OLE works directly from the documentation tool to insert an
object:
Insert > Object

Link to file

Notes:

HDL Designer Series 451

Documentation and Viewpoints
Documentation Using OLE: File Registration

Documentation Using OLE: File Registration

♦ The fast way…take advantage of the Task and File
Registration mechanism.
1. Register Microsoft Word 2. In the User Side Data you can
executable and extension. create a new Word document.

3. Drag and Drop the OLE bar

Notes:

452 HDL Designer Series

Documentation and Viewpoints
Documentation Without OLE

Documentation Without OLE

♦ On PC, you can also use the Copy Picture command to copy
the entire diagram to the system clipboard.
Diagram > Copy Picture

Notes:

HDL Designer Series 453

Documentation and Viewpoints
Documentation Using HTML: Overview

Documentation Using HTML: Overview

♦ It is very convenient to be able to “publish” the design and
associated information in the form of HTML pages which can
be traversed using common web browsers.
♦ It is very useful for design reviews.
♦ It is especially helpful for documentation on PC and UNIX.
♦ It is a document you can ship to anybody because you can
control its content.

Notes:

454 HDL Designer Series

Documentation and Viewpoints
Documentation Using HTML: Invocation

Documentation Using HTML: Invocation

♦ One button HTML website creation.
♦ Stores the results (or links to the results) in the
Files browser.

Notes:

HDL Designer Series 455

Documentation and Viewpoints
Documentation Using HTML: Hierarchy Options

Documentation Using HTML: Hierarchy Options

♦ User-defined granularity of
the document:
 Hierarchy depth
 Included items
 Settings

Notes:

456 HDL Designer Series

Documentation and Viewpoints
Documentation Using HTML: HTML Settings

Documentation Using HTML: HTML Settings

♦ The generated HDL and the Side Data directories content can be
included in the document.
♦ Customized or default title page available.

Notes:

HDL Designer Series 457

Documentation and Viewpoints
Documentation Using HTML: Graphics Settings

Documentation Using HTML: Graphics Settings

♦ Three different graphic
formats available:
 JPEG (Joint Photographic
Experts Group)
– Possible to set the
compression percentage
as required
 PNG (Portable Network
Graphics)
 SVG (Scalable Vector
Graphics) default.
– Best quality
– Best zooming and
navigation
– Requires download from
Adobe
– www.adobe.com/svg/main.
html

Notes:

458 HDL Designer Series

Documentation and Viewpoints
Documentation Using HTML: Browser View

Documentation Using HTML: Browser View

♦ The document is divided in two parts:

Navigation Frame Design Frame

• Diagram
• Information
• Side Data
• HDL

Notes:

HDL Designer Series 459

Documentation and Viewpoints
Viewpoints – Visualize Design Data

Viewpoints – Visualize Design Data

♦ Design Explorer supports multiple, user-defined, design-
centric viewpoints on the data.
♦ Organize design data without actually changing it.
♦ Specify custom Sort, Group and Filter operations to see only
the data you want to see, in the way you want to see it.
♦ Describe how design data is displayed and persists between
work sessions.
 All Design Explorer data is presented the way it was when you
exited HDS.
♦ Attribute Columns.
 A number of attributes supplied — status attributes and user-
defined in the future.
 See important information about an object.
 Sort, group, filter, and search by attributes.

Notes:

460 HDL Designer Series

Documentation and Viewpoints
Viewpoint Management

Viewpoint Management

or Tools > Viewpoint Manager

Create, activate,
rename, delete
viewpoints.

Drag viewpoints
into shortcuts bar.

Notes:

HDL Designer Series 461

Documentation and Viewpoints
Viewpoint – Columns

Viewpoint – Columns

Viewpoint – Columns
♦ Specify desired
columns.
♦ Click on column
heading to toggle
sort ascending /
descending.
♦ Drag and drop
column headings
to change order.

Notes:

462 HDL Designer Series

Documentation and Viewpoints
Viewpoint – Groups

Viewpoint – Groups

Viewpoint – Groups
♦ Summary information.
♦ Group order determined
by order of clicking check
boxes .
♦ Can change group order
with up / down arrow
buttons.

Notes:

HDL Designer Series 463

Documentation and Viewpoints
Viewpoint – Filters

Viewpoint – Filters

Enable Filters

♦ Show/hide objects in order to

focus on what is important at a
given time.
♦ Select which objects to show.
♦ Optionally specify filter string.
♦ Supports case match, whole
word match, plus simple and
full GNU regular expressions.

Notes:

464 HDL Designer Series

Documentation and Viewpoints
Find – Advanced Find

Find – Advanced Find

Tools > Find

Find by name or attributes.

Tools > Advanced Find

Results displayed in
a Design Explorer
“Search” tab.

Notes:

HDL Designer Series 465

Documentation and Viewpoints
Report Where Used

Report Where Used

Tools > Reports > Where Used
♦ Reports where the selected object is used in the hierarchy.
 (e.g. where a component is instanced)
♦ Can restrict the analysis to specific libraries.
♦ Results displayed in a Design Explorer “Where Used” tab.
 Also displayed by Data Management operations when moving or
renaming objects.

Notes:

466 HDL Designer Series

Documentation and Viewpoints
Report Unbound Components

Report Unbound Components

Tools > Reports > Unbound Components > Sort by Parent
Tools > Reports > Unbound Components > Sort by Target

♦ Find unbound components for

the selected object downwards in
the hierarchy.
♦ Results displayed in the log
window.
♦ Sort by Parent
 Lists all unbound instances
referenced by the selected
object.
♦ Sort by Target
 Lists the unbound components
with no views defined for the
selected object.
 Useful in identifying ‘black box’
components.

Notes:

HDL Designer Series 467

Documentation and Viewpoints
Lab 7 Overview

Lab 7 Overview

Lab 7 Overview
♦ Create documentation for the Wave Generator you created in
labs 2 – 4 and lab 6.

Notes:

468 HDL Designer Series

Appendix A
Tracing Requirements

Objectives
Upon completion of this module, you will be able to:

• Explain the Purpose of RecTracerTM

• Provide a simple introduction to the different views in ReqTracerTM
• Describe the integration between ReqTracerTM and HDL Designer.
• Enable requirements referencing in ReqTracerTM and HDL Designer.
• Add and paste requirement references in HDL Designer graphical diagrams.
• Modify requirement references display attributes.
• Illustrate two methods to examining and locating requirements in HDL Designer.

HDL Designer Series 471

Tracing Requirements
What Is ReqTracerTM?

What Is ReqTracerTM?

What Is ReqTracerTM?
♦ ReqTracerTM is an interactive requirements tracing and analysis tool.
 Traces requirements from the system level into design implementation
and verification details.

♦ ReqTracerTM can interface to requirements-related information in a

wide variety of data formats such as:
 IBM/Telelogic DOORS ™, office type documents such a Microsoft Word
 Code files such as C++ or VHDL as well as information in standard text
files.

♦ ReqTracerTM provides powerful capabilities to help you increase your

requirement tracing productivity and effectiveness:

 Requirements Capture and Tracing

 Requirements Analysis and Reporting
 Requirements Change Tracking and Management

Notes:

472 HDL Designer Series

Tracing Requirements
ReqTracer Overview

ReqTracer Overview

ReqTracer Overview
♦ Start a new Project

♦ Add Documents

♦ Add covers Project Tree

Covering document:
document that contains Traceability Description Area
references to
requirements that are
Action buttons
defined
in another document

Documents Details Area

Notes:

HDL Designer Series 473

Tracing Requirements
Sample Requirement Documents

Sample Requirement Documents

Covered Covered

Requirement IDs

Notes:

474 HDL Designer Series

Tracing Requirements
ReqTracer: Management View

ReqTracer: Management View

♦ The Management View summarizes the structure of the project and
the coverage ratios.

Notes:

HDL Designer Series 475

Tracing Requirements
ReqTracer: Coverage Analysis View

ReqTracer: Coverage Analysis View

♦ Allows you to select elements from a project document and displays
requirement coverage one level upstream and one level downstream.

Notes:

476 HDL Designer Series

Tracing Requirements
ReqTracer: Impact Analysis View

ReqTracer: Impact Analysis View

♦ Displays traceability information from all downstream and upstream
documents instead of only displaying the immediate downstream
and upstream document.

Notes:

HDL Designer Series 477

Tracing Requirements
ReqTracer: Graphical View

ReqTracer: Graphical View

♦ Displays each document as an object with its traceability elements
displayed in a tree view within the object.

Notes:

478 HDL Designer Series

Tracing Requirements
ReqTracer Integration with HDL Designer

ReqTracer Integration with HDL Designer

♦ ReqTracer’s interface to HDS increases user productivity in tracking
requirements coverage in textual and graphical representations.
♦ ReqTracer is invoked directly from HDS.
♦ HDS is updated with the coverage information when the HDL is
generated and the Design Explorer is refreshed.
♦ Steps:
 Enabling requirements referencing.
 Defining requirements referencing.
 Generating HDL from graphical views.
 Refreshing.

Notes:

HDL Designer Series 479

Tracing Requirements
Enabling Requirements Referencing – ReqTracer

Enabling Requirements Referencing – ReqTracer

♦ Specify the path in ReqTracer to the HDS design to be traced.

1. Open a ReqTracer project.

2. Edit Types in
Configuration
dialog box.

4. Select HDL Designer as Edit tool.

3. Highlight your project.

Notes:

480 HDL Designer Series

Tracing Requirements
Enabling Requirements Referencing – ReqTracer

Enabling Requirements Referencing – ReqTracer (Cont.)

5. Edit the
Project
settings.

7. Select Project Path.

6. Browse to the directory of the

VHDL source (the HDL directory 8. Specify the path to your
in the HDL Designer library). HDS project (.hdp) file.
A1-11 • HDL Designer Series: Tracing Requirements Copyright © 1991-2015 Mentor Graphics Corporation

Notes:

HDL Designer Series 481

Tracing Requirements
Enabling Requirements Referencing – HDS

Enabling Requirements Referencing – HDS

♦ Enable requirements referencing in HDL Designer.
♦ Specify the path to ReqTracer and set generation properties.
1. Turn on. Options > Requirements Referencing

2. Specify path.

3. The requirements
referencing menu
items will appear
the next time
HDS is invoked.

Notes:

482 HDL Designer Series

Tracing Requirements
Enabling Requirements Referencing – HDS

Enabling Requirements Referencing – HDS (Cont.)

Notes:

HDL Designer Series 483

Tracing Requirements
Defining Requirement References

Defining Requirement References

♦ Add requirement references to textual or graphical designs.
Add or paste in
Typed as text graphical file.
in source file.

Notes:

484 HDL Designer Series

Tracing Requirements
Adding Requirement Reference – Graphical Design

Adding Requirement Reference – Graphical Design

1. Add > Requirement Reference

2. Type requirement in box
(similar to comment box).

3. Specify location in
4. Attach to object the generated HDL.
in graphical design.

Notes:

HDL Designer Series 485

Tracing Requirements
Pasting Requirement Reference – Graphical Design

Pasting Requirement Reference – Graphical Design

♦ Paste in graphical editor or design browser. Design Unit, View, or File.

or
2.

The requirement reference

object is added to the file of
the selected object without
2. the file being opened.

Notes:

486 HDL Designer Series

Tracing Requirements
Setting Display Attributes

Setting Display Attributes

Options > Master Preferences > <Graphical Editor> > Appearance

Notes:

HDL Designer Series 487

Tracing Requirements
Generating HDL from Graphical Views

Generating HDL from Graphical Views

Tasks > Generate > …
♦ ReqTracer only deals with textual views.
♦ HDL Designer graphical views need to be converted to text
before ReqTracer starts working.
♦ For all graphical editors, requirements references are
generated in HDL according to their association with a certain
object or diagram.

Notes:

488 HDL Designer Series

Tracing Requirements
Refreshing

Refreshing

Refreshing
View > Refresh (F5)
♦ Finally, refresh the HDS library to view the requirements
coverage information.
♦ HDS invokes ReqTracer to get the coverage information and
display it in the Requirements References Column in the HDS
Design Explorer.

Notes:

HDL Designer Series 489

Tracing Requirements
Examining and Locating Requirements

Examining and Locating Requirements

Find or Replace requirements.

Selecting an object in the read-only

Content pane highlights that object
on the diagram.

Notes:

490 HDL Designer Series

Tracing Requirements
ReqTracer Benefits

ReqTracer Benefits

ReqTracer Benefits
♦ ReqTracer bridges the gap
between design spec and
requirements to enhance both
traditional (directed test) and
advanced verification
productivity and effectiveness.

♦ ReqTracer provides an
interactive tool to help
implement and track a
requirements driven project
development process and
facilitate continuous process
improvement.

Notes:

HDL Designer Series 491

Tracing Requirements
ReqTracer Benefits

492 HDL Designer Series

NOTES:

HDL Designer Series 493

Part Number: 073384

494 HDL Designer Series

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