Syllabus: CSE 247, Computer organization and architecture
School: SET Batch: 2019-2023
Program: B.Tech Current Academic Year: 2019-2020
Branch: CSE/IT Semester: III
1 Course Code CSE247 Course Name
2 Course Title Computer Organization and Architecture
3 Credits 3
4 Contact Hours 3-0-0
(L-T-P)
Course Status Compulsory
5 Course To impart an understanding of the internal organization and operations of a
Objective computer and to introduce the concepts of processor logic design and control
logic design.
6 Course Upon successful completion of this course, the student will be able to:
Outcomes
CO1: Identify the basic structure and functional units of a digital computer
CO2:Study the architecture of Bus and registers
. CO3:Study the design of arithmetic and logic unit and implementation of
fixed point and floating-point arithmetic operations
CO4:Understand basic processing unit and organization of simple processor
including instruction sets, instruction formats and various addressing modes
CO5:Study the two types of control unit techniques
CO6: Describe hierarchical memory systems including cache memories and
select appropriate interfacing standards for I/O devices.
7 Course This course discusses the basic structure of a digital computer and used for
Description understanding the organization of various units such as control unit,
Arithmetic and Logical unit and Memory unit and I/O unit in a digital
computer.
8 Outline syllabus CO Mapping
Unit 1 Computer Organization and Design
A Functional units of digital system and their CO1
interconnections, buses, bus architecture, types of buses
and bus arbitration. Register bus and memory transfer
B Register transfer Language, Registertransfer, Bus & CO1
memory transfer, Logic micro operations, Shift micro
operation.
C Adder-Subtractor- Incrementor, Arithmetic unit, Logic CO1
unit.
Unit 2 Computer Arithmetic
A Representation of numbers in 1’s and 2’s complement, CO1, CO2
Addition and subtractionofs i g n e d numbers.
B Binary Multiplier, Multiplication: Signed operand CO1, CO2
multiplication, Booth algorithm
C Floating point arithmetic representation: addition and CO1, CO2
subtraction.
Unit 3 Processor Organization
A General register organization, stack organization CO3
B Instruction set architecture of a CPU - registers, Instruction CO3
types, formats, instruction execution cycle
C Addressing modes, RISC/CISC CO3
Unit 4 Control Unit
A Introduction to CPU design, Instruction interpretation and CO3, CO4
execution, Micro-operation and their register transfer
language (RTL) specification
B Hardwired control CPU design CO3, CO4
C Microprogrammed control CPU design CO3, CO4
Unit 5 Memory and I/O
A RAM/ROM/Flash memory, Designing Memory System CO1, CO5
using RAM and ROM chips
B Cache memory: Memory hierarchy, performance CO1, CO5
Considerations, mapping techniques
C Input Output: Isolated vs. Memory mapped I/O, CO1, CO5
Programmed I/O, Interrupt driven I/O, Direct Memory
Access
Mode of Theory
examination
Weightage CA MTE ETE
Distribution
25% 25% 50%
Text book/s* 1. M. Morris Mano, Computer System Architecture,
Pearson
Other
1. C. Hamacher, Z. Vranesic and S. Zaky,
References "Computer Organization", McGrawHill, 2002.
2. W. Stallings, "Computer Organization and
Architecture - Designing for Performance",
Prentice Hall of India, 2002.
3. D. A. Patterson and J. L. Hennessy, "Computer
Organization and Design - The
Hardware/Software Interface", Morgan
Kaufmann,1998.
4. J.P. Hayes, "Computer Architecture and
Organization", McGraw-Hill, 1998.
CO and PO Mapping
S. Course Outcome Program Outcomes (PO) & Program
No. Specific Outcomes (PSO)
1. CO1. Identify the basic structure and PO1, PO2, PO3, PO6, PO12, PSO3
functional units of a digital computer.
2. CO2:Study the architecture of Bus and PO1, PO2, PO3, PO6, PO12, PSO3
registers
3. CO3. Study the design of arithmetic and PO1, PO2, PO3, PO6, PO12, PSO3
logic unit and implementation of fixedpoint
and floating-point arithmetic operations
4. CO4. Understand basic processing unit and PO1, PO2, PO3, PO6, PO12, PSO3
organization of simple processor including
instruction sets, instruction formats and
various addressing modes
5. CO5. Study the two types of control unit PO1, PO2, PO3, PO4, PO6, PO12, PSO2,
techniques PSO3
6. CO6. Describe hierarchical memory PO1, PO2, PO3, PO6, PO12, PSO2,
systems including cache memories and PSO3
select appropriate interfacing standards for
I/O devices
PO and PSO mapping with level of strength for Course Name Computer Organization
and Architecture (Course Code CSE 247)
C Cos PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO1 PO1 PO1 PSO PSO PSO
0 1 2 1 2 3
S
E CO1 3 1 1 - - 2 - - - - - 2 - 1 3
2
CO2 3 3 3 - - 3 - - - - - 3 - 2 3
4
7 CO3 3 2 3 - - 2 - - - - - 3 - 2 3
CO4 3 2 2 - - 1 - - - - - 3 - 3 2
CO5 3 3 3 - - 2 - - - - - 3 - 2 2
CO6 3 3 3 - - 2 - - - - - 3 - 1 2
1-Slight (Low) 2-Moderate (Medium) 3-Substantial (High)
