Design Flow Introduction-FPGA

Unit-1
 Syllabus
Design Flow Introduction-FPGA

Introduction to Verilog:
An Introduction: Verilog History, System representation, Number representation and Verilog
ports.

Verilog Data Types: Net, Register and Constant.

Verilog Operators: Logical, Arithmetic, Bitwise, Reduction, Relational, Concatenation and
Conditional.

Modeling Styles: Dataflow Modeling: Boolean Equation-Based Models of Combinational Logic,

Propagation Delay and Continuous Assignments. Structural Modeling: Design of Combinational
Logic, Verilog Structural Models, Module Ports, Top-Down Design and Nested Modules. Gate
level modelling.

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 Introduction to Verilog
HDL?
 Hardware Description language describes the hardware of digital systems in digital
form.
 Design done in hardware at any level.
 Simulation of designs before fabrication.
 With advent of VLSI it is not possible to verify complex design with millions of gates on
a bread board, HDLs came into existence to verify the functionalities of these circuits.

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 Introduction to Verilog cont…
Verilog History:
 Invented in 1983 by Phil Moorby and Prabhu Goel of Gateway Design Automation
Company.
 Verilog was a proprietary software(HDL)
 Gateway was bought by cadence in 1989 and in 1990Verilog was made Public domain.
 1995 Verilog HDL became IEEE standard 1364-1995. It is maintained by Open Verilog
International organization.
 SSIC, MSIC, LSIC, VLSIC (EDA tool) then usage of CAED tool for placement and
routing of programing language.

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 Introduction to Verilog cont…
Verilog History:
 HDL is CAD tool used for model, simulate, design and syntehsise digital logic.
 HDL is used for complex logic realization and implementation.
 Portable and technology independent.
 Easy to debug.

 Verilog HDL- General purpose HDL, easy to learn and use.

 Allows different levels of abstraction(gate, switch, RTL) to be mixed with same model.
 Verilog is case sensitive and all reserve words are in lower case.
 Verilog is maintained by OVI (openVerilog International.

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 Levels of Abstraction
 Behavioral/Algorithmic Level: Highest level of abstraction HDL. Module can be
implemented in terms of desired design without concern of hardware implementation.

 Dataflow Level: Module is deigned based on specifying the data flow. Programmer is
aware of how data flows between the hardware registers and how data is processed in
design.

 Gate Level: Implementation is based on logic gates and interconnection between these
gates.

 Switch Level: Lowest level of abstraction. Module is representation in terms of

switches, nodes and interconnections.
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 Design Flow (FPGA)

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 Introduction to Verilog cont…
Verilog consists of 2 blocks:
 Design Block (Module)
 Testing Block (Stimulus)

Design Block consists of 2 types of approach:

 Top Down Design
 Bottom Up Design

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 Introduction to Verilog cont…
 Syntax is pre-defined, lowercase, identifiers that define the language constructs.
Example : module, endmodule, input, output wire, and, or, not , etc.,
 Any text between two slashes (//) and the end of line is interpreted as a
comment.
 Blank spaces are ignored and names are case sensitive.
 // The rest of the line is a comment
 /* Multiple line comment */
 /* Nesting /* comments */ do NOT work */

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 Port Declaration
 Declaring Ports
Declare type of port
input
output
inout (bidirectional)

Scalar (single bit) - don’t specify a size

input cin;

Vector (multiple bits) - specify size using range

Range is MSB to LSB (left to right)
output [7:0] OUT;
input [0:4] IN;

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 Sample Verilog Code
A module is the building block in Verilog.
 declared by the keyword module and is always terminated by the keyword endmodule
 Each statement is terminated with a semicolon, but there is no semi-colon after
endmodule.
// A simple example

module and2 (c, a ,b);  Circuit

a
c
Verilog Code input a, b; b

output c;

assign c = a & b;

end module
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 Sample Verilog Code cont…
ports names
module name
Example: Half Adder of module

A module half_adder(S, C, A, B);

S
port output S, C;
B types input A, B;
C
wire S, C, A, B;

assign S = A ^ B; module
A S assign C = A & B; contents
Half
B Adder C endmodule

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 Port Declaration cont..
 Multiple ways to declare the ports of a module

module Add_half(c_out, sum, a, b);

output sum, c_out;
input a, b;
…
endmodule

module Add_half(output c_out, sum, input a, b);

…
endmodule

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 Design Block
Top- Down Design:
 Define top level block and then identify the sub blocks to build the top level block.
 Sub block is divided into leaf cell and leaf cell cannot be divided further.

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 Design Block cont…
Bottom-Up Design:
 Identify the building block and these blocks are used for high level block.
 High level block is used to build the top level block.

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 Design Block cont…
Top- Down Design:

Bottom-up Design

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 Number Representation
0 represents low logic level or false condition
1 represents high logic level or true condition
x represents unknown logic level
z represents high impedance logic level

<size>’<radix> <value>
8’h ax = 1010xxxx
No of Binary •  b or B Consecutive chars
12’o 3zx7 = 011zzzxxx111
bits Octal  o or O 0-f, x, z
Decimal  d or D
Hexadecimal  h or H

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 Number Representation cont…
 can insert “_” for readability
 12’b 000_111_010_100
 12’b 000111010100
 12’o 07_24
 Bit extension
 MS bit = 0, x or z  extend this
 4’b x1 = 4’b xx_x1
 MS bit = 1  zero extension
 4’b 1x = 4’b 1xxx

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 Number Representation cont…
 If size is omitted:
 It is inferred from the value or
 It takes the simulation specific number of bits or
 It takes the machine specific number of bits

 If radix is ommitted then decimal is assumed

 15 = <size>’d 15

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 Number Representation cont…

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 Port Declaration(Mulitbit wide) cont…
 Multiple ways to declare the ports of a module

module xor_8bit(out, a, b);

output [7:0] out; port
sizes
input [7:0] a, b;
…
endmodule

module xor_8bit(output [7:0] out, input [7:0] a, b);

…
endmodule

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 Verilog Value Set
 0 represents low logic level or false condition

 1 represents high logic level or true condition

 x represents unknown logic level

 z represents high impedance logic level

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 Verilog Datatypes
Two groups of types, "net data types" and "variable data types.“
 Net- An identifier of "net data type" means that it must be driven.
 Net data types" can take modifiers: signed, scalared, vectored,.

 An identifier of "variable data type" means that it changes value upon assignment and holds
its value until another assignment.
"variable data types" are:- integer, real, realtime, reg, time.
 integer is default 32 bit twos complement integer.
 real is typically a 64 bit IEEE floating point number.
 realtime is of type real used for storing time as a floating point value.
 reg is by default a one bit unsigned value.
 time is typically 64 bit unsigned value that is the simulation time

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 Verilog Datatypes
 NET- physical connection between structural entities
 REGISTER- storage element

Net- It must be driven by the driver ex- Gate or continuous assignment.

Verilog propagates new values once the driver changes the value.

Register- Holds value until new value is assigned.

Used extensively in behaviorally modelling.

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 Net Datatype
 Net are hardware wires driven by logic A wire Y; // declaration
Y
 Equal z when unconnected B assign Y = A & B;

 Various types of nets

 wire wand Y; // declaration
assign Y = A;
 wand (wired-AND) A assign Y = B;
 wor (wired-OR) Y
 tri (tri-state) B
wor Y; // declaration
Y is evaluated, automatically, every time assign Y = A;
A or B changes assign Y = B;

dr
A Y tri Y; // declaration
assign Y = (dr) ? A : z;

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 Net Datatype (Vector) cont…
 Represent buses
wire [3:0] busA;
reg [1:4] busB;
reg [1:0] busC;
 Left number is MS bit
 Vectors can be declared for all types of net data types and for reg data types.
Specifying vectors for integer, real, realtime, and time data types is illegal.
 Slice management
busC[1] = busA[2];
busC[0] = busA[1];
 Vector assignment (by position!!)
busB[1] = busA[3];
busB[2] = busA[2];
busB[3] = busA[1];
busB[4] = busA[0];

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 Register Datatype
 Variables that stores values
 Do not represent real hardware
 Assigned a value only in procedural statements, user defined sequential statements,
tasks or function
 Reg: can not be output of primitive gates, input, inout, output port of module or target
of continuous assignment statement
 Example: reg
reg A, C; // declaration
// assignments are always done inside a procedure
A = 1;
C = A; // C gets the logical value 1
A = 0; // C is still 1
C = 0; // C is now 0
 Register values are updated explicitly!!

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 Array and Memory Datatype
Arrays are allowed for reg, integer, time, real, vector
array_name <subscript>
reg[4:0] port_id[0:7]; // array of 8 ports with port_id with 5 bits wide.
Width size
reg[15:0] data [0:127][0:127]

Memory is one dimensional array

reg mem[0:2047] // Memory is 2k bit size

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 Constant
integer 3, 123456, -7 ;
real 1.0, 0.1,123e-5, 123.0E-5 , -5.2; per IEEE 754-1985 typically 64 bit
string "a string" constant string, no extra characters, no terminator,
***There is no type 'char' or 'string'.
Specifying radix and special values- General structure is: width´radix value
width is integer, automatic extension to 16 bits
radix is d or D for integer (optional)
h or H for hexadecimal
o or O for octal
b or B for bit
Parameter is keyword used for constant.
Ex- parameter port-id=5;
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 Vector
Vectors are are multiple bit types.
"net data types" and the one variable type reg are by
default one bit in length and by default unsigned.
wire will be used as representing all "net data types".
wire[1:12] is a vector type having 12
wire[31:0] is a vector type having 32 bits with the
bits with the most significant bit
most significant bit numbered 31 and the
numbered 1 and the least significant bit
least significant bit numbered zero. This
numbered 12.
type denotes 32 wires.
wire[31:0] a; declares a to be 32 wires.
reg[-10:10] is a vector type having 21
just 'a' is all 32 wires,
bits with a most significant bit -10 and
a[31] is the most significant bit a least significant bit 10.
a[0] is the least significant bit
a[15:8] is eight wires, bits 15 to 8 of 'a' reg signed [7:0] is a vector type for
values from -128 to +127.
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 Modules and Ports
Module Name
Port List, Port Declaration
Parameter(optional)

Declaration of wires, reg, variables

Dataflow- assign
Behavioural- always & initial block
Instanatiation of lower level modules
Tasks & Functions

Endmodule statement

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 Dataflow Modelling
 Continuous assignment:- assign LHS= RHS(Functionality equation)
 Implicit continuous assignment
 Assignment is declared on net
wire out; or wire out= a & b;
assign out= a & b;
 Implicit Net declaration
wire a, b;
assign out= a & b;
 Delay:-
 Regular assignment delay
 Implicit continuous assignment delay
 Net declaration delay

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 System Tasks & Compiler Directives
System Tasks:- Start automatically, based on a combination of start and completion of
tasks on which they are dependent on.
$< keyword>
Keywords
$display- Displays information of variable or string or expression.
$monitor- Monitors variable or string or expression for a value change (* should be
invoked only once).
$finish- Terminates simulation and returns control to OS.
$stop- Suspends simulation and returns control to user.

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 System Tasks & Compiler Directives cont…
Compiler Directive:- Instructions to theVerilog compiler.
‘ <keyword> construct
‘define- directive used to define macro
‘include- include another source code during compilation.
`timescale- simulation time unit and precision for delays.

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 Operators
 Logical Operator
 Bitwise
 Boolean Logical Operator
 Reduction
 Arithmetic Operator
 Relational Operator
 Concatenation Operator and
 Conditional Operator

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 Operators- Logical Operators
 Logical operation is performed using logical operators.
 AND (&&), OR(||), NAND, NOR, NOT, EXOR
 Operators requires 2 operands (except NOT which requires one operand)

 Bitwise Operator- Operation is performed on corresponding bitwise.

&  bitwise AND
|  bitwise OR
~  bitwise NOT
^  bitwise XOR
 ~^ or ^~  bitwise XNOR

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 Operators- Logical Operators cont…
Boolean Logical operators perform function on two operands but result of these
operations is Boolean True(1) and Boolean False(0).
 a && b evaluates to true if a and b are true
 a || b evaluates to true if a or b are true
 !a Converts non-zero value to zero, and vice vers

Reduction Operators performs on single operand.

Result of Reduction Operator is Boolean
y= & x
If X= 1010 then y=(1&0&1&0) = 0

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 Operators- Relational Operators
Relational operators are used to compare the values of two operands.
Result if Relational operator is Boolean i.e. True(1) and False(0)

Operator Description Result Type

== Equality 0, 1, x
!= Inequality 0, 1, x
=== Equaltity inclusive 0, 1
!=== Inequality Inclusive 0, 1
< less than 0, 1, x
<= less than equal to 0, 1, x
> greater than 0, 1, x
>= greater than equal to 0, 1, x

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 Operators- Arithmetic Operators cont…
 +, -, *, /, % Operator Description
a+b a plus b
 If any operand is x the result is x
a-b a minus b
a*b a multiplied by b
a/b a divided by b
a%b a modulo b
 Negative registers:
a ** b a to the power of b
 regs can be assigned negative but are treated as unsigned
reg [15:0] regA;
..
regA = -4’d12; // stored as 216-12 = 65524

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 Operators- Shift Operators
 >>  shift right
 <<  shift left

 Result is same size as first operand, always zero filled

a = 4’b1010;
...
d = a >> 2; // d = 0010
c = a << 1; // c = 0100

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 Operators- Concatenation and Conditional
Operators
 Concatenation
{ } is concatenation operator.
It combines operands mentioned in the operator.

{op1, op2, ..} = concatenates op1, op2, .. to single number

a = 1’b 1;
b = 3’b 010;
c = 3’b 101;
catx = {a, b, c};
 Replication
catr = {4{a}, b, 2{c}};
 Conditional
condition ? value_if_true : value_if_false; (MUX)

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 Operators Precedence

Use parentheses to enforce

priority

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 Programs
Design 2x1 Mux using CAS in Verilog
Design 4x1 Mux using logical operators and conditional statement
Write a Verilog code for following design

Write a Verilog code for 2x2 array multiplier

Write a Verilog code for 2:4 decoder using dataflow and CAS

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 Verilog Primitive
NOT, AND, OR, NAND, NOR, XOR and XNOR
and 0 1 x Z or 0 1 x Z xor 0 1 x Z
0 0 0 0 0 0 0 1 x x 0 0 1 x x
1 0 1 x x 1 1 1 1 1 1 1 0 x x
x 0 x x x x x 1 x x x x x x x
z 0 x x z z 0 1 x z z x x x x

nand 0 1 x Z nor 0 1 x Z xnor 0 1 x Z

0 1 1 1 1 0 1 0 x x 0 1 0 x x
1 1 0 x x 1 0 0 0 0 1 0 1 x x
x 1 x x x x x 0 x x x x x x x
z 1 x x x z x 0 x x z x x x x

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 Verilog Primitive cont…
 NOT, AND, OR, NAND, NOR, XOR and XNOR

NOT buf
0 1 0 0
1 0 1 1
x x x x
z x z z

 bufif0, bufif1, notif0, notif1 gates

These gates have additional control signal(i.e. 3 ports)

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 Components of Simulation
Main Program- Design Block Stimulus Block
Test Bench- Stimulus
Design Block

Top Module- Test Bench

d_ck clk
d_reset reset
c-q q

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 Delay in Verilog
Event Delay- Change in value of signal or a variable during simulation is referred as Event
Propagation Delay- Inertial and Transport delay
and #5 a1(t1, a, b); or assign #5 t1=a & b;
or #2 a2(t2, c, d);
and #4 a3(y, t1, t2);

Inertial Delay: If two events occur on an input of the component with an interval time
less that the defined delay, the output will not reflect either input event.
Transport Delay(Wire Delay):Any event on an input of the component will be
reflected on the output. Delay specified by the user.

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 Program
Write a Verilog code for the given circuit using 2x1 mux whose output is given by the
expression a.(b+c’) when enable.sel’ is 1 and Boolean expression xy’+x’y otherwise.
Write a Verilog code for 8:3 Priority encoder using CAS.
Write a Verilog code for 4 bit wide, 2:1 MUX using conditional statement.
Design 1 bit comparator using CAS.

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 Structural Modelling- Programs
Using Structural style of modelling:-
Write a Verilog code for 4x1 MUX
Design 16x1 MUX using 4x1 MUX
Write a Verilog code for full adder using 2 half adder and 1 or gate.
Sum=(a^b^c), Carry= a.b+ c(a^b)
Write a Verilog code for 4 bit ripple carry adder using full adder logic.
Write a Verilog code for Binary/Adder Subtractor.
Using 1 bit comparator design 4 bit comparator

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 Structural Modelling- Programs cont…
Design 2:4 Decoder with enable input and using 2:4 Decoder write a Verilog code for 3:8
Decoder
Design 4:16 Decoder using 2:4 decoder

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