Transient Delay Characterization of Parity Logic for

Delay-Sensitive Error Detection Applications

Abstract—This research presents a study on the propagation the performance of certain structures [7, 8]. In conventional
delay performance of 2-bit even and odd parity generator and two-term delay modelling, a constant "inertial "characteristic
checker circuits. The primary objective of this study is to of delay in the cell is connected to an output-load related delay
analyze and compare the delay characteristics during high-to- characteristic of the cell's size and structure. With regard to
low and low-to-high transitions across different parity logic overestimated process dispersion, this representation might
designs. All circuits were designed and simulated using the assist designers in concentrating their design performances
Cadence Virtuoso platform, employing the gpdk090 technology [9]. In the submicron range where second-order effects take
node. The parity generator and checker designs were centre stage, this seems to be insufficient. As is frequently
implemented using basic transistor-level CMOS design where
seen, nonlinearity for the propagation delays is caused by
each gate was implemented with carefully balanced pull-up and
coupling effects of inputs and outputs linked to the carriers'
pull-down networks, and transient analysis was carried out to
measure the propagation delay. Our results showed that the
speed saturation. These effects are sufficiently important to
even and odd parity generator circuits have a similar warrant consideration in a rigorous standard cell-delay
propagation delay of 15.2 ps and 15.1 ps, respectively. Further, performance evaluation [10]. So, by switching the circuit
our results also show that even and odd parity checker have a design the delay in gate is influenced operation, and
propagation delay of 34.6 ps and 34.2 ps, respectively. The surroundings in addition to the input-switching signal's wave
variations in delay are attributed to differences in signal shape, which is typically defined as the time it takes for the
transition paths and the specific logic gate configurations controlling gate's output and voltage to change between
involved in each design. This comparative analysis is critical for suitable voltage levels. The delay is also significantly
selecting optimal parity logic in delay-sensitive digital systems, influenced by these signal rise and fall [11].
such as error detection circuits in communication protocols and
memory systems. This work presents a comparative study of propagation
delay in 2-bit even and odd parity generators and checkers,
Keywords—Propagation delay, Parity generator, Parity evaluating their performance under varying simulation
checker, Even parity, Odd parity, Cadence Virtuoso, Static CMOS parameters. The objective is to identify structures with
logic, transient analysis. minimum delay, thereby optimizing them for use in high-
speed, low-latency digital systems. The simulation of these
I. INTRODUCTION circuits was conducted in Cadence Virtuoso simulation
The ongoing growth of wireless technologies, which need environment using gpdk90 technology.
a finite supply of power, has increased the demand for VLSI
circuits with the least propagation delay [1]. In modern digital II. EXPERIMENTAL
circuits, propagation delay is becoming a significant problem. A. Simulation design
Therefore, the primary goal of VLSI designers is to minimize Cadence Virtuoso is a sizable, expert EDA (Electronic
the propagation delay. In fact, the inverter serves as the Design Automation) program that can implement nearly every
foundation of all digital designs [2]. Developing more aspect of layout design, experimental simulation, electronic
complex CMOS structures after its function and features are design, etc. Software like Mentor Graphics, Synopsys, and
thoroughly understood. A major challenge in the creation of
others have comparable features. However, Cadence Virtuoso
high-performance integrated circuits is the generation,
offers more robust functionality for circuit modelling, circuit
distribution, and delay in propagation of the signal. In paper
diagram design, layout design, and wiring than other EDA
[3], the author presents several low power and high-speed tools. Additionally, Cadence creates a process library for
integrated circuit design strategies such as substrate biasing. simulation and exchanges data with other semiconductor
This technique is used for reducing device power consumption
businesses, making it easy for customers to perform
without compromising the speed of the device. The simulation. The process flow for conduction of this research
development of semiconductor technology is mostly
work is based on the flowchart illustrated in Fig. 1.
constrained by the propagation delay [4].
In terms of the process flow, the design begins with
Since propagation delay is one of the most crucial creating the schematic for both even and odd parity generators
performance factors in CMOS digital circuits, it takes a lot of and checkers. After developing the respective schematics,
effort to generate accurate, analytical formulas for timing
each configuration is separately analysed. These designs are
models of simple circuits. In terms of calculation time and
then converted into their respective symbols, which are further
storage costs, using transistor level simulators that represent
utilized to build the test circuits. In these test circuits,
the devices in continuous time, such as SPICE, can be highly appropriate voltage biases and input combinations are applied
costly [5]. As a result, a large portion of previous research has to observe the behaviour of the circuits. Transient analysis is
focused on creating analytical delay models without the need
carried out using the cadence virtuoso to generate the
for costly numerical iterations. As designs approach the necessary output waveforms for each parity type. From these
complexity of the gates, gate level safety characterization in
waveforms, the propagation delay is determined using the
the design space is required to preserve a temporal relationship
built-in calculator functionality of the tool.
between functional blocks. [6]. Much work has been done to
develop accurate and useful models in the cadence libraries The primary aim is to record and compare the propagation
involving CMOS level transistor circuits. Controlling or delay values of even and odd parity generators and checkers.
guiding design options, technology migration, and process By systematically observing the delay characteristics of both
evolution all depend on these models. They are used to assess configurations, this study provides insights into which type of

XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE

parity circuit offers better performance in terms of speed, simulated in Cadence Virtuoso using Boolean expressions
thereby assisting in selecting the optimal design for specific illustrated in Equations (1) and (2). The schematic circuit for
digital applications. even parity generator is shown in Fig. 2(a). The symbol of this
schematic circuit is created and using this symbol the circuit
for even parity checker is implemented as shown in Fig. 2(b).
𝑃𝐸 = 𝐴⨁𝐵 (1)
𝐸𝐸 = 𝐴⨁𝐵⨁𝑃𝐸 (2)
Where, 𝑃𝐸 is the even parity, A and B and the inputs whose
parity has to be determined, and 𝐸𝐸 is the even checker.

(a)

(b)
Fig. 1. Process flow for simulation used in this research.
Fig. 2. (a) Schematic circuit of even parity generator, and (b) even parity
checker implemented in Cadence Virtuoso tool.
B. Even Parity Generator and Checker Circuit Design
Even parity generator is a crucial digital logic circuit used C. Odd Parity Generator and Checker Circuit Design
in error detection systems, where it ensures that the total
number of 1's in a binary message (including the parity bit) is The odd parity generator is a fundamental digital logic
circuit employed in error detection systems. Its primary
even. This helps in detecting single-bit errors during data
function is to ensure that the total number of '1's in a binary
transmission in communication systems. The XOR operation
message (including the parity bit) remains odd, thereby
is inherently suitable for parity generation, as it outputs a logic
high (1) if the number of high inputs is odd, and a logic low enabling the detection of single-bit errors during data
(0) otherwise. Therefore, by applying XOR to all input bits, transmission in communication networks. The XNOR
the circuit produces an output that indicates whether the input operation is particularly well-suited for implementing parity
has even or odd parity. Considering a 2-bit even parity logic. It yields a logic low (0) when the count of high inputs is
odd, and a logic high (1) when the count is even. By applying
generator, the parity bit will be low (0) for inputs 00 and 11,
high (1) for the inputs 01 and 10. The even parity checker, the XNOR operation across all input bits, the circuit
which complements the generator, is designed to verify effectively determines whether the input data exhibits even or
whether the received data, including the transmitted parity bit, odd parity. For instance, in a 2-bit odd parity generator, the
still maintains even parity. The same XOR logic is used in the parity bit is set to high (1) for input combinations 00 and 11,
and low (0) for 01 and 10, thereby maintaining an odd total
checker, but now it takes the received data bits plus the parity
bit as inputs. If the result of the XOR operation is 0, it indicates count of '1's in the output message. Complementing the
generator, the odd parity checker verifies whether the received
that the total number of 1s is even and no error has occurred.
data — including the parity bit — continues to exhibit odd
A result of 1, however, flags a parity mismatch, suggesting a
possible single-bit error during transmission. Both the parity. It uses the same XNOR-based logic, this time
incorporating the parity bit along with the original data bits as
generator and checker circuits were realized using CMOS-
based XOR gates, built from combinations of NMOS and inputs. If the XNOR output is 0, it indicates that the total
number of '1's remains odd, and hence, no transmission error
PMOS transistors. The full circuit was implemented and
is detected. Conversely, an output of 1 signals a parity
mismatch, implying a potential single-bit error in the received essential for maintaining system performance and throughput.
message. Both the parity generator and checker circuits were The analysis included both even and odd parity logic
implemented using CMOS-based XNOR gates, constructed configurations using optimized XOR/XNOR gate
through suitable configurations of NMOS and PMOS arrangements, and the delay values were compared across
transistors using Equations (3) and (4). The schematic circuit different logic styles to determine the most efficient design in
for odd parity generator is shown in Fig. 3(a). The symbol of terms of timing performance.
this schematic circuit is created and using this symbol the
circuit for odd parity checker is implemented as shown in Fig. III. RESULTS AND DISCUSSIONS
3(b). The details of voltage sources used in this research are The primary goal of this work is to study parity generator
illustrated in Table I. and parity checker (both even and odd parity) circuit's
𝑃𝑂 = 𝐴⨀𝐵 (3) schematic and symbol together with its intended
configuration. The propagation delay is the parameter that is
𝐸𝑂 = 𝐴⨀𝐵⨀𝑃𝑂 (4) considered for this research. Computation of delay can be
considered from the time where the input reaches half, that is
50 % of the supply power and when the output also comes
with a similar voltage as seen in Fig. 4.

Fig. 4. Calcultation of propagation delay.

(a)

For input signals that are 5 % of the pulse width, each

simulation has rising and falling times. For every sum and
carry, propagation delays that are rising and declining are
evaluated independently. The biggest delay of all the
(b) transitions is used to calculate the cell delay. The propagation
delay periods τPHL and τPLH, respectively, determine the input-
Fig. 3. (a) Schematic circuit of odd parity generator, and (b) odd parity
checker implemented in Cadence Virtuoso tool. to-output signal delay for the output's low-to-high and high-
to-low transitions. The time needed for the output voltage to
TABLE I. DETAILS OF VOLTAGE SOURCES USED IN THIS WORK. drop from VOH to the V50% level is known as the τPHL, while
the time needed for the output voltage to increase from VOL to
Pulse Rise Fall Initial Final
Voltage Period the V50% level is known as the τPLH. In Equation (5), the
width time time voltage voltage
source (ns)
(ns) (ps) (ps) (V) (V) voltage points V50% are defined [12]:
A 20 10 40 40 0 1.8 1 1
𝑉50% = 𝑉𝑂𝐿 + (𝑉𝑂𝐻 − 𝑉𝑂𝐿 ) = (𝑉𝑂𝐿 + 𝑉𝑂𝐻 ) (5)
2 2
B 40 20 40 40 0 1.8
Consequently, the propagation delay times 𝜏𝑃𝐻𝐿 and 𝜏𝑃𝐿𝐻
PE 80 30 40 40 0 1.8 are taken from Fig. 4 as Equations (6) and (7), respectively.
PO 80 30 40 40 0 1.8 The average propagation delay (𝜏𝑃) is given by Equation (8)
as, [12]:
D. Propagation delay calculation 𝜏𝑃𝐻𝐿 = 𝑏 − 𝑎 (6)
This research focuses on the analysis of propagation delay
in various implementations of even and odd parity generator 𝜏𝑃𝐿𝐻 = 𝑑 − 𝑐 (7)
and checker circuits. Propagation delay, defined as the time 𝜏𝑃 =
𝜏𝑃𝐻𝐿 +𝜏𝑃𝐿𝐻
(8)
taken for a change at the input to produce a corresponding 2
change at the output, is a critical parameter in determining the Where, a is the time when input rises and crosses V50%, b
speed and efficiency of digital error detection systems. In this is the time when output falls and reaches V50%, c is the time
study, the propagation delay was calculated using the transient when input falls and crosses V50%, and d is the time when
response obtained through simulation of parity circuits built output rises and reaches V50%.
using CMOS logic. The delay measurements were taken at the
point where the output transitions from one logic level to As mentioned earlier, the objective of this study is to
another, following a change in input data bits. Since parity analyze and compare the schematic designs and symbol
generators and checkers are often placed in high-speed data representations of 1-bit 2-input even and odd parity generator
transmission systems, minimizing propagation delay is and checker circuits using Cadence EDA tools. The circuits
were simulated under identical conditions to ensure a fair
comparison. The primary performance metric considered in From Table II it can been seen that the propagation delay
this analysis is propagation delay, as it directly influences the even parity generator and odd parity generator circuits are
speed and reliability of digital systems. Through transient 15.2 ps and 15.1 ps, respectively. Further, it can also be
simulations, the propagation delay values were extracted observed that even parity checker and odd parity checker have
using waveform measurements from the calculator tool. Fig. a propagation delay of 34.6 ps and 34.2 ps, respectively. As
5(a) and 5(b) shows the transient analysis of even parity mentioned earlier, the even and odd parity generator circuits
generator and checker circuits implemented in Cadence were designed and implemented using XOR and XNOR gates,
Virtuoso simulation tool. Similarly, Fig. 6(a) and 6(b) respectively. Our results showed that both even and odd parity
illustrates the transient response of odd parity generator and generator circuits had almost same propagation delays. The
checker circuits. Table II summarizes the propagation delay of reason behind this observation can be explained by the internal
all four circuits. circuitry used in implementing the circuits. The similarity in
propagation delay between XOR and XNOR gates arises from
the complexity of their internal transistor-level
implementations, which are quite comparable in structure and
logic depth. To understand this in detail, it is essential to look
into how both gates are built using CMOS logic and why that
affects their timing characteristics. In CMOS digital circuits,
propagation delay is the time taken for a change in input to
cause a change in output. It is primarily governed by three
factors: the number of transistors in series, the overall
(a)
capacitance that needs to be charged/discharged, and the
switching paths for both pull-up (PMOS) and pull-down
(NMOS) networks. XOR and XNOR gates are fundamentally
more complex than basic gates like AND, OR, or NOT,
because their truth tables are non-monotonic and require more
intricate arrangements of transistors to implement. An XOR
gate, for example, outputs high only when the inputs are
different ( 𝐴 ⊕ B = 𝐴̅𝐵 + 𝐴𝐵̅ ), whereas an XNOR gate
(b)
outputs high only when the inputs are the same (𝐴 ⊙ B =
AB + 𝐴̅𝐵̅). Both require multiple paths to evaluate different
Fig. 5. Transient response of, (a) even parity generator, and (b) even parity logic combinations, typically involving 6 to 12 transistors in
checker.
CMOS logic, depending on whether static or dynamic logic is
used.
As observed in standard static CMOS implementations of
XOR and XNOR gates, it can be observed that both circuits
rely on similar logic stages — each requires a combination of
complemented and non-complemented signals (i.e., using
both A and 𝐴̅ , B and 𝐵̅ ) and implements multiplexing-like
logic within the gate. Because of this, their transistor stack
depth and logical effort are quite similar. Logical effort is a
(a) measure of how much harder it is for a gate to drive its output
compared to an inverter, and XOR/XNOR both have high
logical efforts (typically 4 for a 2-input version). This
similarity in internal switching paths and effort means that the
time it takes for a signal to propagate through either gate is
roughly equivalent. Additionally, since both gates involve
complex switching paths and similarly sized transistors (often
mirrored designs), the capacitive loads and the internal node
charges that need to transition are nearly the same. As a result,
(b) the rise time and fall time (tied to PMOS/NMOS performance)
Fig. 6. Transient response of, (a) odd parity generator, and (b) odd parity are balanced in a similar fashion for both gates.
checker.
Moreover, in standard cell libraries (used in VLSI design),
TABLE II. SUMMARY OF PROPAGATION DELAY FOR ALL FOUR
the design of XOR and XNOR gates is often optimized
CIRCUITS IMPLEMENTED IN CADENCE VIRTUOSO. together with matched drive strength and fan-out capability,
to ensure consistent performance regardless of whether a
Time delay (ps) parity check uses XOR or XNOR logic. These cells are also
Falling Rising Propagation
Circuit type
delay delay delay
laid out with similar area and delay budgets. When
(ps) (ps) (ps) characterized for timing in a digital synthesis flow, both gates
Generator 13.4 17.1 15.2
show comparable delay values, typically just a few
Even picoseconds apart. Any minor delay difference between them
parity Checker 43.5 25.7 34.6 (like a couple of picoseconds) is usually due to the final output
Generator 9.2 21.1 15.1
inversion stage in an XNOR gate, which might use an
Odd additional inverter or slightly different arrangement, but this
parity Checker 23.8 44.62 34.2 delay is often negligible. In summary, even and odd parity
generator static CMOS circuits exhibit similar propagation Since propagation delay accumulates with each logic gate the
delays because they share nearly identical CMOS signal must pass through, this additional gate directly
implementations, logic depth, transistor count, and signal contributes to a longer delay. Moreover, in many practical
paths. Their functional complementarity does not translate to implementations, parity checkers may also include extra logic
significant hardware complexity differences, and thus, from to convert the output of the XOR/XNOR network into a
an electrical and timing standpoint, they behave almost meaningful error signal, such as an inverter (to output 0 for
identically in digital circuits. correct and 1 for incorrect) or a latch/flagging mechanism.
This adds another layer of delay, albeit small, on top of the
Furthermore, it can be seen from Table II that the base delay caused by the logic depth. Another subtle but
propagation delay of even and odd parity checker circuits are important factor is that, in typical chain-based
almost identical with values 34.6 ps and 34.2 ps, respectively.
implementations (where XORs/XNORs are cascaded
The reason a one-bit even and odd parity checker has similar linearly), each XOR/XNOR operation introduces a fixed
propagation delay lies in the fact that both perform virtually delay, and the total delay becomes proportional to the number
identical logic operations using almost the same circuit of bits: a parity generator has 1 stage, whereas the parity
structure, differing only in the interpretation of the output or
checker has 2 stages — a difference that increases with input
at most a single additional logic gate. In the case of a one-bit size. Even in optimized tree-based designs (which reduce
parity check, the system receives two inputs: a data bit and a logic depth logarithmically), the parity checker’s depth
parity bit (either even or odd), and it must verify whether the remains greater by at least one stage due to the additional
combination of the two bits satisfies the expected parity
input. Thus, despite using similar types of gates, the parity
condition. To check even or odd parity, the logic operation checker inherently processes more inputs, passes through
essentially reduces to an XOR gate, which outputs 1 if the more logic stages, and potentially includes additional
number of ones in the input is odd and 0 if it's even. For an interpretation circuitry, all of which make its propagation
even parity checker, the XOR of the data and parity bit should
delay consistently higher than that of a parity generator when
be 0 (indicating even number of 1s). For an odd parity checker, implemented using XOR/XNOR logic.
the same XOR result should be 1 (indicating odd number of
1s). From a static CMOS circuit perspective, both checkers IV. CONCLUSION
use the exact same XOR/XNOR gate to process the two
inputs. The output is then either directly interpreted (for even In conclusion, this study provides a comprehensive
parity: output = 0 ⇒ valid; for odd parity: output = 1 ⇒ valid). analysis of the propagation delay performance of 2-bit even
and odd parity generator and checker circuits implemented
In terms of propagation delay, which is the time it takes using transistor-level CMOS design. The results reveal that
for a change in input to reflect as a change in output, the delay while both generator and checker circuits exhibit minimal
is determined by the depth and type of logic gates the signal delay differences between even and odd configurations, parity
passes through. Since both even and odd parity checkers checkers inherently introduce higher propagation delays
involve two XOR and XNOR gates, respectively, the compared to generators due to the additional logic depth and
propagation delay is essentially the XOR and XNOR gate input processing. These findings underscore the importance of
delay. Thus, from a timing analysis standpoint, both even and understanding the underlying delay characteristics when
odd parity checkers for one-bit data have almost identical designing timing-critical digital systems, particularly in the
delay paths, as the functional operation is the same and any context of high-speed error detection applications such as
variation in logic depth is extremely minor. This makes their communication protocols and memory integrity verification.
propagation delays nearly indistinguishable in both theory and The insights gained from this work can guide designers in
real-world hardware implementations. The key takeaway is selecting appropriate parity logic configurations for error
that parity type affects logic interpretation more than logic detection in modern digital circuits.
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