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Anirban Sengupta · Sudeb Dasgupta ·
Virendra Singh · Rohit Sharma ·
Santosh Kumar Vishvakarma (Eds.)

Communications in Computer and Information Science 1066

VLSI Design and Test

23rd International Symposium, VDAT 2019
Indore, India, July 4–6, 2019
Revised Selected Papers
Communications
in Computer and Information Science 1066
Commenced Publication in 2007
Founding and Former Series Editors:
Phoebe Chen, Alfredo Cuzzocrea, Xiaoyong Du, Orhun Kara, Ting Liu,
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Polytechnic Institute of Setúbal, Setúbal, Portugal
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Indian Statistical Institute, Kolkata, India
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St. Petersburg Institute for Informatics and Automation of the Russian
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University at Buffalo, The State University of New York, Buffalo, NY, USA
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Tsinghua University, Beijing, China
More information about this series at http://www.springer.com/series/7899
Anirban Sengupta Sudeb Dasgupta
• •

Virendra Singh Rohit Sharma

• •

Santosh Kumar Vishvakarma (Eds.)

VLSI Design and Test

23rd International Symposium, VDAT 2019
Indore, India, July 4–6, 2019
Revised Selected Papers

123
Editors
Anirban Sengupta, FIET, FBCS Sudeb Dasgupta
Computer Science and Engineering Department of Electronics
Indian Institute of Technology Indore and Communication Engineering
Indore, India Indian Institute of Technology Roorkee
Roorkee, India
Virendra Singh
Department of Electrical Engineering Rohit Sharma
Indian Institute of Technology Bombay Department of Electrical Engineering
Mumbai, India Indian Institute of Technology Ropar
Rupnagar, India
Santosh Kumar Vishvakarma
Electrical Engineering
Indian Institute of Technology Indore
Indore, India

ISSN 1865-0929 ISSN 1865-0937 (electronic)

Communications in Computer and Information Science
ISBN 978-981-32-9766-1 ISBN 978-981-32-9767-8 (eBook)
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 Preface

This book presents the state of the art developments on advances in VLSI for IoT and
consumer electronics. The book is comprised of several important contributions by
leading experts in the field. The chapters presented in this book, as contributions, are
part of the 23rd International Symposium on VLSI Design and Test (VDAT 2019), held
during July 4–6, 2019, in Indore, India. The contributions were rigorously peer reviewed
by a team of leading experts from industry and academia. VDAT 2019 was spearheaded
by the following international leaders: general chairs, Dr. Anirban Sengupta, FIET,
FBCS (IIT Indore) and Dr. Santosh Kumar Vishvakarma (IIT Indore).
Each chapter of this book, adopted from VDAT 2019 proceedings, has been
peer-reviewed by at least 2 reviewers (single-blind) in terms of novelty, technical
correctness, impact of contribution, and advancement to the state of the art. There were
199 submissions in total for VDAT 2019 from around the world and there were 63
accepted papers under oral and poster category. Each of the accepted conference papers
have been lucidly presented as a book chapter in these proceedings. The collection
of these important contributions are grouped into six categories:
• Analog and Mixed Signal Design
• Computing Architecture and Security
• Hardware Design and Optimization
• Low Power VLSI and Memory Design
• Device Modeling
• Hardware Implementation
The Technical Program Committee of VDAT 2019, who performed the review
process, comprised of more than 80 experts nationally and internationally. The authors
who contributed to this book spanned across several countries ranging from India,
USA, Austria, Germany, Italy, Sweden, UK, etc. This truly reflects the international
nature of the contributions compiled under this book.
We sincerely hope that you will enjoy the contributions of the book and that it will
serve as a great reading for experts, students, practitioners, designers, researchers, and
academics. We, the editors, would like to thank all the contributing authors, reviewers,
and other supporting members for their help.

July 2019 Anirban Sengupta

Sudeb Dasgupta
Virendra Singh
Rohit Sharma
Santosh Kumar Vishvakarma
 Organization

Steering Committee
V. Agrawal Auburn University, USA
Jaswinder Ahuja Cadence Noida, India
A. Bharadwaj IISc Bangalore, India
Santanu Chaudhury IIT Jodhpur, India
Satya Gupta SenZopt Bangalore, India
Manoj S. Gaur IIT Jammu, India
M. Huebner BTU, Germany
Milos Krstic IHP, Germany
Roy P. Paily IIT Guwahati, India
Niranjan Pol Seagate Pune, India
V. Ramgopal Rao IIT Delhi, India
Anirban Sengupta IIT Indore, India
Surindra Singh SCL Mohali, India
Sunita Verma MeitY New Delhi, India

Program Committee
Satyadev Ahlawat IIT Bombay, India
Sk Subidh Ali IIT Bhilai, India
Naushad Alam Aligarh Muslim University, India
Ansuman Banerjee Indian Statistical Institute, India
Kunal Banerjee Intel, India
Gaurab Banerjee IISc Bangalore, India
Lava Bhargava MNIT, India
Sitangshu Bhattacharya IIIT Allahabad, India
Fabrizio Bonani Politecnico di Torino, Italy
Dharmendar Boolchandani MNIT, India
Susanta Chakraborty IIEST Shibpur, India
Rajat Subhra Chakraborty IIT Kharagpur, India
Anjan Chakravorty IIT Madras, India
Rajeevan Chandel NIT Hamirpur, India
Shouri Chatterjee IIT Delhi, India
Shaileshsingh Chouhan Aalto University, Finland
Bishnu Prasad Das IIT Roorkee, India
Sudeep Dasgupta IIT Roorkee, India
Masahiro Fujita The University of Tokyo, Japan
Chandan Giri IIEST Shibpur, India
Neeraj Goel IIT Ropar, India
Simona Donati Guerrieri Politecnico di Torino, Dipartimento di Elettronica, Italy
viii Organization

Prasanta Guha IIT Kharagpur, India

Vinayak Hande IIT Ropar, India
Ramrakesh Jangir Government Polytechnic Narwana, India
John Jose IIT Guwahati, India
Hemangee Kapoor IIT Guwahati, India
Sougata Kar NIT Rourkela, India
Chandan Karfa IIT Guwahati, India
Abhijit Karmakar CSIR-CEERI Pilani, India
Baljit Kaur NIT Delhi, India
Brajesh Kumar Kaushik IIT Roorkee, India
Subhadip Kundu Synopsys, India
Kusum Lata LNMIIT Jaipur, India
Trupti Lenka NIT Silchar, India
Manoj Kumar Majumder International Institute of Information Technology,
Naya Raipur, India
Shubhankar Majumdar NIT Meghalaya, India
Sushanta Mandal Centurion University of Technology and Management,
India
Anzhela Matrosova Tomsk State University, Russia
Usha Mehta Nirma University Ahmedabad, India
Nihar Mohapatra IIT Gandhinagar, India
Arijit Mondal IIT Patna, India
Subhankar Mukherjee Cadence Noida, India
Madhu Mutyam IIT Madras, India
Ashutosh Nandi IIT Roorkee, India
Sergei Ostanin Tomsk State University, Russia
Pankaj Kumar Pal NIT Uttarakhand, India
Ajit Panda NIST Berhampur, India
Preeti Ranjan Panda IIT Delhi, India
Brajesh Pandey IIT Bombay, India
Soumya Pandit University of Calcutta, India
Gayadhar Pradhan IIT Patna, India
Hafizur Rahaman IIEST Shibpur, India
Balwinder Raj NIT Jalandhar, India
Ashwani Rana NIT Hamirpur, India
Surendra Rathod IIT Roorkee, India
Karun Rawat IIT Roorkee, India
Sudip Roy IIT Roorkee, India
Debasri Saha University of Calcutta, India
Mounita Saha IIT Kharagpur, India
Vineet Sahula Malaviya National Institute of Technology Jaipur, India
Arnab Sarkar IIT Guwahati, India
Biplab Sarkar IIT Roorkee, India
Pallabi Sarkar VIT University, India
Manoj Saxena Deen Dayal Upadhyaya College and University
of Delhi, India
 Organization ix

Anirban Sengupta IIT Indore, India

Rohit Sharma IIT Ropar, India
Adit Singh Auburn University, USA
Virendra Singh IIT Bombay, India
Ashok Kumar Suhag BML Munjal University Gurgaon, India
Gaurav Trivedi IIT Guwahati, India
Jaynarayan T Tudu Indian Institute of Science, India
Ramesh Vaddi IIT Roorkee, India
Keshavan Varadarajan Samsung Austin R&D Center, USA
Rekha Verma Indian Institute of Information Technology Allahabad,
India
Shivam Verma National Institute of Technology Warangal, India
Santosh Vishvakarma IIT Indore, India
Robert Wille Johannes Kepler University Linz, Austria
Shigeru Yamashita Ritsumeikan University, Japan
Hailong Yao Tsinghua University, China
 Contents

Analog and Mixed Signal Design

Automations and Methodologies for Efficient and Quality Conscious

Analog Layout Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Varun Kumar Dwivedi, Madhvi Sharma, and Chandaka Venu

A 2.4 GHz High Efficiency Capacitive Cross Coupled Common Gate

Class-E Differential Power Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Archana Sunitha and Bhaskar Manickam

A 1.25–20 GHz Wide Tuning Range Frequency Synthesis for 40-Gb/s

SerDes Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Javed S. Gaggatur and Abhishek Chaturvedi

Analyzing Design Parameters of Nano-Magnetic Technology Based

Converter Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Bandan Kumar Bhoi, Neeraj Kumar Misa, Shailesh Singh Chouhan,
and Sarthak Acharya

Design of Current Mode Sigmoid Function and Hyperbolic

Tangent Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Debanjana Datta, Sweta Agarwal, Vikash Kumar, Mayank Raj,
Baidyanath Ray, and Ayan Banerjee

Flexible Adaptive FIR Filter Designs Using LMS Algorithm . . . . . . . . . . . . 61

M. Mohamed Asan Basiri

An Efficient Test and Fault Tolerance Technique for Paper-Based DMFB . . . 72

Chandan Das, Sarit Chakraborty, and Susanta Chakraborty

A Generalized Technique of Automated Pin Sharing on Hexagonal

Electrode Based Digital Microfluidic Biochip Along
with Its Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Amartya Dutta, Riya Majumder, Debasis Dhal, and Rajat Kumar Pal

A Space Efficient Greedy Droplet Routing for Digital

Microfluidics Biochip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Jyotiranjan Swain, Kolluri Rajesh, and Sumanta Pyne

Design of 635 MHz Bandpass Filter Using High-Q Floating

Active Inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Aditya Kumar Hota and Kabiraj Sethi
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