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Test Topics. You can copy these into your notes or let me know if you want them
as a PDF.
4. Cut-off frequency:
The frequency at which the output power drops to half (−3 dB point). For RC
filters, fc=12πRCf_c = \frac{1}{2\pi RC}.
5. Effect of RC on cutoff:
Increasing R or C lowers the cutoff frequency, decreasing them raises it.
8. Circuit diagrams:
11. Applications:
● A basic RC low-pass filter consists of a resistor (R) in series with the input
signal and a capacitor (C) in parallel with the output.
● At low frequencies: The capacitive reactance (XC=2πfC1) is very high,
meaning the capacitor acts almost like an open circuit. Most of the input
voltage appears across the capacitor (the output).
● At high frequencies: The capacitive reactance is very low, meaning the
capacitor acts almost like a short circuit. Most of the input voltage drops
across the resistor, and very little appears across the capacitor (output).
● This behavior gives it its "low-pass" characteristic – it allows low
frequencies to pass through relatively unimpeded while attenuating high
frequencies.
When this condition is true, here's the physical and mathematical explanation:
● Physical Intuition:
○ Slow Charging: Because the time constant (RC) is very large, the
capacitor charges and discharges very slowly compared to the rapid
changes in the input signal.
○ Constant Current Approximation: If the input signal changes
relatively quickly compared to the capacitor's charging rate, the
voltage across the capacitor (output voltage) changes very little over
a short period. This means that the current flowing through the
resistor (which is approximately the input voltage divided by R) is
nearly constant during these short intervals.
○ Charge Accumulation: The charge accumulated on the capacitor is
the integral of the current flowing into it over time (Q=∫idt). Since the
current is approximately proportional to the input voltage (due to the
large R making the voltage drop across C negligible compared to the
input), and the output voltage is proportional to the charge
(Vout=Q/C), the output voltage becomes proportional to the integral
of the input voltage.
0
In summary:
13.
When this condition is true, here's the physical and mathematical explanation:
● Physical Intuition:
○ Rapid Charging/Discharging: Since the time constant (RC) is very
small, the capacitor charges and discharges very rapidly in response
to changes in the input signal.
○ Capacitor as a Short (for changes): When the input voltage
changes quickly, the capacitor quickly charges or discharges to
match the new voltage. Because it responds so quickly (due to the
small RC), the voltage across the capacitor essentially follows the
input voltage very closely. This means the voltage drop across the
resistor (which is the output voltage) is primarily determined by the
current flowing through the capacitor during these rapid changes.
○ Current and Rate of Change: The current through a capacitor is
directly proportional to the rate of change of voltage across it
(i=CdtdVC). Since the voltage across the capacitor is approximately
equal to the input voltage (because the capacitor quickly "passes"
the change), the current is approximately proportional to the
derivative of the input voltage. As the output voltage is taken across
the resistor (Vout=iR), the output voltage becomes proportional to
the derivative of the input voltage.
Key Points:
● Time Constant is Crucial: The differentiator action only occurs when the
circuit's time constant (RC) is very short compared to the period of the
input signal. This ensures that the capacitor can respond quickly to
changes in the input voltage.
● Response to Step Inputs: If you apply a square wave (which has sharp,
instantaneous changes) to an RC differentiator, the output will be sharp
spikes corresponding to the rising and falling edges. This is because the
derivative of a step function is an impulse.
● Practical Limitations: Ideal differentiators are not practically realizable
because they would have infinite gain at infinite frequency, leading to noise
amplification. Real-world RC differentiators are only approximations, and
their effectiveness is limited by frequency range and noise considerations.
For more precise differentiation in practical applications, active
differentiator circuits (using op-amps) are often used, which can provide
better control over gain and frequency response.
● Answer:
○ Simple circuit: Requires only one diode and no center-tapped
transformer (for basic implementation).
○ Low cost: Due to fewer components.
● Answer:
○ Low efficiency: Only half of the AC input cycle is utilized (around
40.6% maximum). The other half is wasted.
○ High ripple factor: The output is very pulsating, containing a
significant AC component. This requires extensive filtering to
produce a smooth DC.
○ Low DC output voltage: The average DC output is relatively low.
○ Poor transformer utilization factor: The transformer is not
efficiently used.
○ DC saturation of transformer core: Can be an issue in
transformer-coupled half-wave rectifiers due to unidirectional current
flow.
○ Lower output frequency: The output ripple frequency is equal to
the input frequency (fout=fin).
● Answer: The PIV for a half-wave rectifier is equal to the peak input
voltage (Vm). This is the maximum reverse voltage the diode has to
withstand when it is not conducting.
12. Explain the working of a full-wave bridge rectifier. * Answer: * During the
positive half-cycle of the AC input, two diodes (e.g., D1 and D2) are
forward-biased and conduct, while the other two (D3 and D4) are reverse-biased
and block. Current flows through D1, the load resistor, and D2. * During the
negative half-cycle of the AC input, the other two diodes (D3 and D4) are
forward-biased and conduct, while D1 and D2 are reverse-biased and block.
Current flows through D3, the load resistor, and D4. * Crucially, the current
always flows in the same direction through the load resistor in both half-cycles,
resulting in a full-wave rectified output.
15. What is the ripple factor for a full-wave rectifier? * Answer: For an
unfiltered full-wave rectifier, the ripple factor (γ) is 0.482. This is significantly
lower than a half-wave rectifier.
16. What is the Peak Inverse Voltage (PIV) for: * a) Center-tapped full-wave
rectifier? * Answer: 2Vm(where Vmis the peak voltage from the center tap to
one end of the secondary winding). * b) Full-wave bridge rectifier? * Answer:
Vm(where Vmis the peak voltage across the entire secondary winding). Note
that two diodes are in series reverse-biased, so each diode withstands Vm/2, but
the PIV rating for the circuit configuration is Vm.
Advanced/Comparative Questions:
17. Why is the ripple factor lower for a full-wave rectifier than for a
half-wave rectifier? * Answer: In a full-wave rectifier, both half-cycles of the
input are converted to DC, meaning the gaps between the rectified pulses are
significantly reduced. The output pulses occur twice as frequently (at 2fin)
compared to the half-wave rectifier (fin). This higher frequency and closer
spacing of pulses result in a smaller variation in the output voltage, hence a lower
ripple factor.
19. Which rectifier would you choose for a sensitive electronic device and
why? * Answer: A full-wave rectifier (preferably bridge type) followed by a
good filter circuit. * Reason 1 (Lower Ripple): Full-wave rectifiers inherently
produce less ripple than half-wave rectifiers, making the filtering task easier. *
Reason 2 (Higher Efficiency): More efficient conversion of AC to DC means
less power loss and heat generation. * Reason 3 (Smoother Output): Sensitive
devices require a very stable and smooth DC supply to operate correctly without
noise or malfunction.
18. Waveforms:
19. Applications:
Used in power supplies to convert AC mains to DC.
🔹 CLAMPING CIRCUITS
A lab viva for clamper circuits will assess your understanding of how they shift DC levels in AC
signals. Here are some common questions and detailed answers:
● Answer:
○ Clipper (Limiter): Modifies the amplitude of a waveform by "clipping off" or
eliminating portions of it that exceed a certain voltage level. It changes the shape
of the waveform.
○ Clamper (DC Restorer/Level Shifter): Shifts the DC level of the entire
waveform up or down without altering its shape or peak-to-peak amplitude. It
preserves the shape of the waveform.
● Answer: The capacitor is the crucial energy storage element. During one half-cycle
(when the diode is forward-biased), it charges to the peak voltage of the input signal
(minus the diode drop). This stored voltage then acts as a DC battery in series with the
input signal during the other half-cycle, effectively shifting the entire waveform up or
down.
● Answer:
○ First Negative Half-Cycle: The input voltage goes negative. The diode becomes
forward-biased (cathode is more negative than anode, which is at 0V). The
capacitor quickly charges through the diode to the peak input voltage (Vm)
(minus the diode's forward voltage drop, VD, so VC≈Vm−VD). The output voltage
across the diode is approximately VD(or 0V for an ideal diode) during this very
short charging period. The capacitor polarity will be positive on the side
connected to the diode/output and negative on the side connected to the input.
○ Subsequent Positive Half-Cycle: The input voltage goes positive. The diode
becomes reverse-biased (anode at 0V is more negative than cathode, which is
now at Vm−VD). The diode acts as an open circuit. The capacitor acts like a DC
voltage source of Vm−VDin series with the input AC voltage. By Kirchhoff's
Voltage Law (KVL), the output voltage becomes Vout=Vin+VC=Vin+(Vm−VD).
○ The entire input waveform is shifted upwards by approximately Vm−VD. The new
minimum output voltage will be at VD(or 0V ideal), and the new maximum will be
2Vm−VD.
8. What is the output waveform of a positive unbiased clamper for a sinusoidal input?
● Answer: The sinusoidal waveform will be shifted upwards. If the input swings from −Vm
to +Vm, the output will swing from VD(or 0V ideal) to 2Vm−VD. The peak-to-peak
voltage remains 2Vm.
Negative Clamper Questions:
9. Draw the circuit diagram of a negative unbiased clamper.
10. Explain the working of a negative unbiased clamper. * Answer: * First Positive
Half-Cycle: The input voltage goes positive. The diode becomes forward-biased (anode is
more positive than cathode, which is at 0V). The capacitor quickly charges through the diode to
the peak input voltage (Vm) (minus the diode's forward voltage drop, VD, so VC≈Vm−VD). The
output voltage across the diode is approximately VD(or 0V for an ideal diode) during this very
short charging period. The capacitor polarity will be negative on the side connected to the
diode/output and positive on the side connected to the input. * Subsequent Negative
Half-Cycle: The input voltage goes negative. The diode becomes reverse-biased (cathode at
0V is more positive than anode, which is now at Vm−VD). The diode acts as an an open circuit.
The capacitor acts like a DC voltage source of Vm−VDin series with the input AC voltage. By
KVL, the output voltage becomes Vout=Vin−VC=Vin−(Vm−VD). (Note the minus sign because
the capacitor's positive terminal is now effectively towards the input, opposing it for the output
side). * The entire input waveform is shifted downwards by approximately Vm−VD. The new
maximum output voltage will be at −VD(or 0V ideal), and the new minimum will be −2Vm+VD.
11. What is the output waveform of a negative unbiased clamper for a sinusoidal input? *
Answer: The sinusoidal waveform will be shifted downwards. If the input swings from −Vmto
+Vm, the output will swing from −Vm−(Vm−VD) to +Vm−(Vm−VD), which simplifies to
−2Vm+VDto VD. The peak-to-peak voltage remains 2Vm.
13. How would you design a positive clamper that clamps the negative peak at +5V? *
Answer: For a positive clamper, the diode's anode is usually towards the output/ground. To
clamp the negative peak at +5V, you would connect a +5V DC source in series with the diode,
such that the diode becomes forward-biased when the voltage across it drops to approximately
+5V. The capacitor would charge during the negative half-cycle (or when the input drops below
+5V) to Vm−VD−5V. The diode would be oriented such that it allows current to flow when the
cathode goes below +5V (e.g., diode anode to +5V, cathode to capacitor-resistor junction).
14. How would you design a negative clamper that clamps the positive peak at -3V? *
Answer: For a negative clamper, the diode's cathode is usually towards the output/ground. To
clamp the positive peak at -3V, you would connect a -3V DC source in series with the diode,
such that the diode becomes forward-biased when the voltage across it rises to approximately
-3V. The capacitor would charge during the positive half-cycle (or when the input rises above
-3V) to Vm−VD−(−3V). The diode would be oriented such that it allows current to flow when the
anode goes above -3V (e.g., diode cathode to -3V, anode to capacitor-resistor junction).
16. What happens if the time constant RC is too small in a clamper circuit? * Answer: If
RC is too small (i.e., the resistor value is too low or capacitor is too small), the capacitor will
discharge significantly during the non-conducting period of the diode. This will lead to a droop
in the clamped waveform, meaning the clamped level won't be perfectly held, and the output
waveform will not be a perfectly shifted version of the input; it will sag.
17. What is the effect of the diode's forward voltage drop (VD) on the clamper output? *
Answer: The diode's forward voltage drop (typically 0.7V for silicon diodes) means that the
capacitor charges to Vm−VD(not simply Vm). Consequently, the clamping level will be offset by
this VD. For example, an unbiased positive clamper will clamp its negative peak at +0.7V
instead of 0V. For small input signals, this effect becomes more significant.
By thoroughly understanding these questions and their answers, you'll be well-prepared for your
EE lab viva on clamper circuits. Remember to also practice drawing the circuits and sketching
the waveforms accurately.
25. Diagrams:
Diode + capacitor. Orientation of diode decides positive/negative clamping.
28. Waveforms:
29. Applications:
TV receivers, communication circuits (DC restoration).
🔹 CLIPPING CIRCUITS
A lab viva for clipper circuits will test your understanding of how they modify waveforms by
removing portions of a signal. Here are common questions and their answers:
● Answer: A clipper circuit is a non-linear waveform shaping circuit that removes or "clips
off" a portion of the input signal that is above or below a certain voltage level. Its primary
function is to limit the amplitude of a waveform to a predetermined maximum or minimum
value without significantly distorting the remaining part of the waveform.
● Answer:
○ Clipper: Modifies the amplitude of the waveform by removing parts of it. It
changes the shape of the waveform.
○ Clamper: Shifts the DC level of the entire waveform up or down without altering
its shape or peak-to-peak amplitude. It preserves the shape of the waveform.
● Answer:
○ Series Clippers: The diode is connected in series with the input signal and the
load.
○ Shunt (Parallel) Clippers: The diode is connected in parallel (shunt) with the
load.
● Answer: (You should be able to draw the circuit: Input -> Diode (cathode towards
output) -> Resistor -> Output)
○ During the positive half-cycle of the input: The diode is reverse-biased
(anode is more negative than cathode). It acts as an open circuit. Ideally, no
current flows, and the output voltage is zero. So, the positive half of the waveform
is clipped.
○ During the negative half-cycle of the input: The diode is forward-biased
(anode is more positive than cathode). It acts as a closed switch (or a 0.7V drop
for practical diode). The negative half of the input signal (minus 0.7V for practical
diode) appears across the output.
○ Output: The positive half is clipped, and the negative half passes through.
● Answer: (You should be able to draw the circuit: Input -> Resistor -> Diode (anode to
output, cathode to ground) || Load Resistor -> Output taken across diode/load)
○ During the positive half-cycle of the input: The diode is reverse-biased
(anode is less positive than cathode, which is at 0V). It acts as an open circuit.
The input signal passes through the resistor to the output relatively unaltered
(assuming load resistor is much larger than series resistor).
○ During the negative half-cycle of the input (when voltage drops below -0.7V
for silicon): The diode becomes forward-biased (anode is more positive than
cathode). It acts as a short circuit (or a -0.7V clamp). Any voltage more negative
than -0.7V is shunted through the diode to ground, causing the output to be
clamped at approximately -0.7V.
○ Output: The positive half passes through, and the negative half is clipped at
approximately -0.7V.
● Answer:
○ Unbiased Clipper: The clipping level is determined solely by the diode's forward
voltage drop (e.g., 0V for an ideal diode, or ±0.7V for a silicon diode). No external
DC voltage source is used to set the clipping level.
○ Biased Clipper: An additional DC voltage source (battery) is connected in series
with the diode. This allows the clipping level to be set to a specific, non-zero
voltage level, either positive or negative, depending on the battery's polarity and
magnitude.
8. Draw a circuit diagram of a biased positive series clipper that clips above +5V.
9. Draw a circuit diagram of a biased negative shunt clipper that clips below -2V.
11. Can Zener diodes be used in clipper circuits? If so, how? * Answer: Yes, Zener diodes
are commonly used in clipper circuits, especially for precise and higher voltage clipping. * In the
forward-biased direction, a Zener diode acts like a regular diode (clipping at ≈0.7V). * In the
reverse-biased direction, a Zener diode breaks down at its specified Zener voltage (VZ). This
property allows it to clip a voltage at VZwhen reverse-biased. * A single Zener diode can
provide dual-level clipping (0.7V in one direction, VZin the other). Two Zener diodes placed
back-to-back can provide symmetrical or asymmetrical clipping at their respective Zener
voltages (plus the forward drop of the other diode).
13. List some common applications of clipper circuits. * Answer: * Waveform Shaping:
Generating square waves from sine waves, or creating specific pulse shapes. * Voltage
Limiting/Protection: Protecting sensitive electronic components from excessive voltage spikes
or overvoltages (e.g., in input stages of amplifiers). * Noise Elimination: Removing unwanted
noise peaks from a signal. * Speech Processing: Limiting speech signals to prevent
over-modulation in communication systems. * Test Equipment: In signal generators to produce
specific waveforms.
14. If you observe a slightly rounded corner at the clipping point on an oscilloscope,
what might be the cause? * Answer: This often indicates the non-ideal behavior of the diode.
The diode does not switch instantaneously from perfect open circuit to perfect short circuit.
There's a small region where it's gradually turning on or off, leading to a "soft" clip rather than a
sharp, ideal clip. Diode capacitance can also contribute at higher frequencies.
15. How would you verify the clipping level in a lab setting? * Answer: By using an
oscilloscope. Apply a sinusoidal input signal (with a peak voltage greater than the expected
clipping level) to the input channel (CH1) and observe the clipped output waveform on the
output channel (CH2). You can then directly measure the peak voltage of the clipped waveform
on the oscilloscope screen. For precise measurement, use the oscilloscope's measurement
functions.
Be prepared to draw circuit diagrams quickly and accurately, and to sketch input and output
waveforms for different clipper configurations. Good luck!
37. Applications:
Protecting circuits from overvoltage, signal conditioning.
🔹 ASTABLE MULTIVIBRATOR
Okay, let's prepare you for a lab viva on the Astable Multivibrator using the IC 555 timer! This is
a very common and important circuit in electronics.
Q3: Why is the IC 555 Timer commonly used for Astable Multivibrator circuits?
Q4: Can you draw the pin diagram of the IC 555 Timer and briefly explain the function of
each pin relevant to an astable circuit?
● Answer: (You should be able to draw the 8-pin DIP package with numbers)
○ Pin 1 (GND): Ground reference.
○ Pin 2 (TRIGGER): Compares the voltage with 1/3 VCC. When voltage drops
below 1/3 VCC, the internal flip-flop sets, making the output (pin 3) HIGH and
starting the capacitor charging.
○ Pin 3 (OUTPUT): The output of the timer, typically a square wave.
○ Pin 4 (RESET): An active-LOW input. If pulled low (below ~0.7V), it forces the
output LOW and resets the internal flip-flop. Usually connected to VCC for
astable operation to prevent accidental resets.
○ Pin 5 (CONTROL VOLTAGE): Allows external voltage to modulate or vary the
threshold and trigger levels. Typically connected to ground via a small capacitor
(0.01µF to 0.1µF) to bypass noise, or left open if not used for modulation.
○ Pin 6 (THRESHOLD): Compares the voltage with 2/3 VCC. When voltage
exceeds 2/3 VCC, the internal flip-flop resets, making the output (pin 3) LOW and
enabling the capacitor to discharge.
○ Pin 7 (DISCHARGE): An open-collector output that rapidly discharges the
external timing capacitor when the output (pin 3) is LOW. It's connected to the
capacitor's charging path.
○ Pin 8 (VCC): Positive supply voltage (typically 4.5V to 16V).
Q5: Briefly describe the main internal blocks of the 555 timer that enable astable
operation.
Q6: Draw the circuit diagram of an Astable Multivibrator using the IC 555 Timer.
Q7: Explain the working of the Astable Multivibrator circuit using the 555 Timer, detailing
the charging and discharging cycles.
● Answer:
○ Initial State (Capacitor Discharged, Output HIGH): When power is applied, the
capacitor C is initially discharged. Pin 2 (Trigger) voltage is below 1/3 VCC. This
sets the internal flip-flop, making the output (Pin 3) HIGH. The discharge
transistor (Pin 7) is OFF.
○ Capacitor Charging (Output HIGH): With the discharge transistor OFF, the
capacitor C begins to charge through RA and RB towards VCC.
○ Threshold Reached (Output LOW): As C charges, its voltage (connected to Pin
6, Threshold) increases. When it reaches 2/3 VCC, the upper comparator resets
the flip-flop. This makes the output (Pin 3) LOW, and the discharge transistor
(Pin 7) turns ON.
○ Capacitor Discharging (Output LOW): With the discharge transistor ON, the
capacitor C now rapidly discharges through RB and Pin 7 (to ground).
○ Trigger Reached (Output HIGH Again): As C discharges, its voltage
(connected to Pin 2, Trigger) decreases. When it drops below 1/3 VCC, the lower
comparator sets the flip-flop again. This makes the output (Pin 3) HIGH again,
and the discharge transistor (Pin 7) turns OFF.
○ The cycle then repeats, leading to continuous oscillation.
● Answer:
○ ON time (THIGHor t1): This is the time the output is HIGH (capacitor charging
from 1/3 VCC to 2/3 VCC).THIGH=0.693×(RA+RB)×C
○ OFF time (TLOWor t2): This is the time the output is LOW (capacitor
discharging from 2/3 VCC to 1/3 VCC).TLOW=0.693×RB×C
○ Total Period (T):T=THIGH+TLOW=0.693×(RA+2RB)×C
Q9: What is the formula for the output frequency (f) of the Astable Multivibrator?
● Answer:
○ f=T1=0.693×(RA+2RB)×C1
○ Which can be approximated as: f≈(RA+2RB)×C1.44
Q10: What is the duty cycle of an Astable Multivibrator, and what is its formula?
● Answer: Duty cycle is the ratio of the ON time to the total period, usually expressed as a
percentage.
○ Duty Cycle (D) = TTHIGH×100%
○ Substituting the formulas: D=0.693×(RA+2RB)×C0.693×(RA+RB)×C×100%
○ D=RA+2RBRA+RB×100%
Q11: Can a standard 555 Astable Multivibrator achieve a duty cycle of exactly 50%
(square wave)? Why or why not?
● Answer: No, a standard 555 Astable Multivibrator cannot achieve an exact 50% duty
cycle.
○ The formula D=RA+2RBRA+RB. Since RA must always be greater than 0
(otherwise the capacitor would charge infinitely fast or get shorted), the
numerator (RA+RB) will always be smaller than the denominator (RA+2RB).
○ This means the ON time (THIGH) will always be longer than the OFF time
(TLOW), resulting in a duty cycle always greater than 50%.
○ The minimum practical duty cycle is slightly above 50% (approaching 50% as
RA≪RB). To achieve a truly 50% duty cycle, modifications (like adding a diode in
parallel with RB or using a CMOS 555 with specific configurations) are needed.
● Answer:
○ Clock generators
○ Pulse generators
○ LED flashers
○ Tone generators (e.g., in toys, alarms)
○ PWM (Pulse Width Modulation) in simple motor speed control (though
specialized PWM ICs are better for precision).
○ Timer circuits (when specific pulse trains are needed).
Q13: What are the main limitations of the 555 Astable Multivibrator?
● Answer:
○ Limited frequency range: Typically up to a few hundred kHz (max ~1MHz for
bipolar, higher for CMOS versions).
○ Duty cycle always > 50% (for standard configuration).
○ Output waveform is not a perfect square wave: Rise and fall times are not
instantaneous, especially at higher frequencies.
○ Sensitivity to power supply variations: Though relatively stable, significant
VCC changes can affect frequency.
○ Temperature sensitivity: Frequency can drift slightly with temperature.
Q14: What would happen if the capacitor C is shorted in an astable 555 circuit?
● Answer: If C is shorted, Pin 2 and Pin 6 would be pulled to ground. This would keep Pin
2 below 1/3 VCC, continuously setting the flip-flop. The output (Pin 3) would remain
HIGH indefinitely, and no oscillation would occur.
● Answer: Leaving Pin 4 floating is not recommended. It's an active-LOW input, meaning
it should be held HIGH to prevent accidental resets. If left floating, it can pick up noise
and cause erratic operation or stop the oscillations. Always connect it to VCC for astable
operation.
Q16: How would you measure the frequency and duty cycle of the astable output in the
lab?
● Answer:
○ Oscilloscope: Connect the oscilloscope probe to Pin 3 (Output). Measure the
time period (T) directly from the waveform (time for one complete cycle).
Frequency f=1/T. Measure THIGHand TLOWfrom the waveform. Duty Cycle =
(THIGH/T)×100%.
○ Frequency Counter: For frequency only, a dedicated frequency counter can be
used, connected to Pin 3.
Remember to be able to draw the circuit, explain its operation clearly, and discuss the formulas
and practical aspects confidently. Good luck!
38. Definition:
A multivibrator with no stable state, it continuously switches between high and
low outputs, generating a square wave.
44. Waveforms:
Output at each transistor collector is a square wave (180° out of phase).
45. Applications:
Timers, clock pulses, flashing LEDs.
Q1: What is a Bipolar Junction Transistor (BJT)? Name its three terminals.
Q2: What are the two types of BJTs, and how do they differ in construction and biasing?
● Answer:
○ NPN Transistor: Consists of a p-type base sandwiched between two n-type
layers (Emitter and Collector). For active region operation, the Base-Emitter (B-E)
junction is forward-biased (Base positive relative to Emitter), and the
Base-Collector (B-C) junction is reverse-biased (Collector positive relative to
Base).
○ PNP Transistor: Consists of an n-type base sandwiched between two p-type
layers. For active region operation, the B-E junction is forward-biased (Base
negative relative to Emitter), and the B-C junction is reverse-biased (Collector
negative relative to Base). Current directions are reversed compared to NPN.
● Answer:
1. Common Emitter (CE): Emitter is common to both input and output.
2. Common Collector (CC) / Emitter Follower: Collector is common to both input
and output.
3. Common Base (CB): Base is common to both input and output.
● Answer: The Common Emitter configuration is the most popular amplifier configuration
because it provides:
○ High voltage gain.
○ High current gain.
○ High power gain (product of voltage and current gain).
○ Medium input impedance.
○ Medium output impedance.
○ It is suitable for general-purpose voltage amplification.
Q5: Draw the circuit diagram of a Common Emitter amplifier with voltage divider biasing.
Label all components.
● Answer: (You should be able to draw this clearly and accurately, including: VCC, R1,
R2, RC, RE, CE (bypass capacitor), C1 (input coupling capacitor), C2 (output coupling
capacitor), input signal, output taken across RC).
● Answer:
○ DC Biasing (Setting the Q-point):
■ The resistors (R1, R2, RC, RE) are chosen to establish a stable DC
operating point (Q-point) for the transistor in the active region.
■ The voltage divider (R1, R2) provides a stable DC voltage to the base
(V_B).
■ The emitter resistor (RE) provides negative feedback for thermal stability,
ensuring the collector current (IC) doesn't vary excessively with
temperature changes or β variations.
■ The collector resistor (RC) sets the collector voltage (VC) and limits the
collector current.
■ The purpose is to ensure the transistor is properly biased so it can amplify
the AC signal linearly without distortion (i.e., not going into saturation or
cutoff).
○ AC Operation (Amplification):
■ Coupling Capacitors (C1, C2): Act as open circuits for DC (blocking bias
voltage from input/output sources) and as short circuits for AC signals
(allowing AC signal to pass through).
■ Bypass Capacitor (CE): Connected in parallel with RE. It acts as an
open circuit for DC, maintaining bias stability, but as a short circuit for AC
signals. This effectively "AC grounds" the emitter, increasing the AC
voltage gain. Without CE, RE would also provide AC negative feedback,
reducing the gain.
■ When an AC input signal is applied to the base, it modulates the forward
bias of the B-E junction.
■ A small change in base current (IB) causes a large change in collector
current (IC=βIB).
■ This large change in ICflows through the collector resistor (RC), causing
a significant voltage drop across it (VRC=IC×RC).
■ Since Vout=VCC−VRC, an increase in ICleads to a decrease in VRC,
and thus a decrease in Vout. Conversely, a decrease in ICleads to an
increase in Vout. This is why there's a phase inversion.
Q7: What is the phase relationship between the input and output voltage in a Common
Emitter amplifier? Explain why.
● Answer: There is a 180-degree phase shift (or inversion) between the input and output
voltage.
○ Explanation: When the input signal goes positive, it increases the forward bias
of the Base-Emitter junction, leading to an increase in base current (IB). This
causes a larger increase in collector current (IC). As ICincreases, the voltage
drop across the collector resistor (RC) also increases (IC×RC). Since the output
voltage is Vout=VCC−(IC×RC), an increasing voltage drop across RCmeans the
output voltage decreases. Thus, a positive-going input results in a negative-going
output, indicating a 180-degree phase shift. The opposite happens for a
negative-going input.
Q8: Define voltage gain (AV) and current gain (AI) for a CE amplifier. Provide their
approximate formulas.
● Answer:
○ Voltage Gain (AV): The ratio of the change in output voltage to the change in
input voltage.
■ AV=ΔVinΔVout≈−re′RC(without emitter bypass capacitor CE) or
AV≈−RERC(with unbypassed emitter resistor RE, where re′is the
intrinsic emitter resistance of the transistor, typically ≈25mV/IE).
■ With CEbypassing RE: AV≈−re′RC
○ Current Gain (AI): The ratio of the change in output current (collector current) to
the change in input current (base current).
■ AI=ΔIBΔIC=βac(or hfe, the AC current gain of the transistor).
Q9: What is the input impedance (Zin) and output impedance (Zout) of a CE amplifier?
● Answer:
○ Input Impedance (Zin): The impedance "looking into" the amplifier from the
input signal source.
■ Zin=R1∣∣R2∣∣(βac×(re′+RE)) (where REis the unbypassed emitter
resistance, if any).
■ If REis fully bypassed by CE, then Zin=R1∣∣R2∣∣(βac×re′).
○ Output Impedance (Zout): The impedance "looking back" into the amplifier from
the load.
■ Zout≈RC(assuming the transistor's output resistance is much higher than
RC).
4. Biasing Methods
Q10: What are the different biasing methods for a BJT? Which one is most commonly
used for CE amplifiers and why?
● Answer:
○ High voltage, current, and power gain.
○ Good for general-purpose voltage amplification.
○ Medium input and output impedances, making it suitable for cascading stages.
○ Relatively simple to design and implement.
● Answer:
○ 180-degree phase shift between input and output, which needs to be
considered in multi-stage designs.
○ High thermal instability (unless properly biased with emitter resistor and
voltage divider).
○ Voltage gain is sensitive to changes in β (though reduced with emitter
degeneration/bypass capacitor).
○ Poor high-frequency response due to internal capacitances (Miller effect).
● Answer:
○ Audio frequency (AF) amplifiers: Used in pre-amplifiers and driver stages due
to their high gain.
○ Radio frequency (RF) amplifiers (tuned common emitter).
○ Switching circuits (operating in saturation and cutoff regions).
○ General-purpose voltage amplification stages in various electronic systems.
● Answer:
○ Purpose: CE provides a low impedance path (effectively an AC short circuit) for
the AC signal to bypass the emitter resistor. This eliminates the AC negative
feedback that RE would otherwise provide, thereby increasing the AC voltage
gain significantly.
○ If removed: The emitter resistor RE would provide AC negative feedback (also
known as emitter degeneration). This would reduce the AC voltage gain, but it
would simultaneously increase the input impedance, improve bandwidth, and
reduce distortion and improve stability.
Q15: How would you determine the Q-point (DC operating point) of a CE amplifier in the
lab?
● Answer:
○ Measure the DC voltages: VB(Base voltage relative to ground), VE(Emitter
voltage relative to ground), and VC(Collector voltage relative to ground) using a
multimeter.
○ Calculate the DC currents:
■ IE=VE/RE
■ IC≈IE(since IBis very small).
■ IB=IC/βDC(if βDCis known or measured).
○ Verify that VBE=VB−VE≈0.7V (for silicon).
○ Verify that VCE=VC−VEis within the active region (VCE>VCE(sat)and not at
VCC). Typically, VCEshould be roughly in the middle of the load line for
maximum unclipped swing.
Q16: What is saturation and cutoff in a BJT? How do they relate to amplification?
● Answer:
○ Cutoff: The transistor is effectively OFF. The Base-Emitter junction is
reverse-biased (or barely forward-biased with insufficient current), IB≈0, IC≈0.
VCE≈VCC. The transistor acts like an open switch between collector and emitter.
○ Saturation: The transistor is fully ON. Both Base-Emitter and Base-Collector
junctions are forward-biased. IBis very high, pushing ICto its maximum possible
value (limited by RC). VCEis very low (VCE(sat), typically 0.1V to 0.3V). The
transistor acts like a closed switch between collector and emitter.
○ Amplification: For linear amplification, the BJT must operate strictly in the
active region, where the B-E junction is forward-biased and the B-C junction is
reverse-biased. In this region, IC=βIB, and the transistor behaves linearly,
amplifying the input signal without clipping or significant distortion. If the input
signal pushes the transistor into cutoff or saturation, the output waveform will be
clipped.
Mastering these questions will demonstrate a solid understanding of Common Emitter BJT
circuits. Good luck with your viva!
46. Definition:
A configuration where the emitter is common to both input and output; widely
used as a voltage amplifier.