Nonlinear Dyn (2025) 113:5511–5535

https://doi.org/10.1007/s11071-024-10538-6

RESEARCH

Design and FPGA implementation of encrypted frame

transmission scheme based on chaotic reverse
synchronization
Qiqin Shi · Yuzhuo Zhao · Qun Ding

Received: 24 August 2024 / Accepted: 19 October 2024 / Published online: 1 November 2024
© The Author(s), under exclusive licence to Springer Nature B.V. 2024

Abstract Chaos exhibits significant characteristics, was designed and implemented in FPGA for the first
including pseudo-randomness and unpredictability. time, with the objective of improving the security of
These properties render chaos a valuable tool in prac- frame transmission. The experimental results demon-
tical applications such as secure communication. Fur- strate that the system is capable of precisely regulating
thermore, chaos synchronization represents a crucial the time synchronization between the sender and the
avenue of research within the field of chaos. The paper receiver. Furthermore, the establishment of synchro-
addresses the issue of the lack of flexibility and prac- nization is rapid, and the transmission speed is consid-
ticality associated with the synchronization method erable, which aligns with the practical requirements of
of discrete chaos synchronization control. To address the project.
the limitations of the discrete chaotic synchroniza-
tion method, this paper proposes a novel approach Keywords Encrypted transmission scheme · Discrete
to reverse synchronization of hyperchaotic Chen sys- backward chaotic synchronization · Chaotic frame
tems based on field-programmable gate arrays. This synchronization · FPGA
method offers a flexible and practical solution that can
facilitate the direct implementation of discrete chaotic
synchronization in real-world applications. Firstly, the 1 Introduction
dynamic behavior of the hyperchaotic Chen system is
analyzed, and a reverse synchronization method for the A chaotic system is a nonlinear system that exhibits
hyperchaotic Chen system is proposed to advance the properties of pseudo-randomness, ergodicity, initial
research of reverse synchronization theory and enhance value sensitivity, and long-term unpredictability. These
the flexibility of controller design. Secondly, based characteristics enable chaotic systems to achieve a high
on the synchronization scheme, an encrypted trans- degree of complexity and variability, making them
mission scheme combined with frame synchronization useful in a range of applications, including secure
communication [1], image processing [2,3], and other
Q. Shi · Y. Zhao · Q. Ding (B)
Electrical Engineering College, Heilongjiang University, 74
fields. A number of technologies based on chaos the-
Xuefu Road, Harbin 150080, China ory have been proposed. Furthermore, due to the fact
e-mail: [email protected] that chaotic systems demonstrate seemingly random
Q. Shi yet inherently deterministic dynamic behaviors, it was
e-mail: [email protected] previously hypothesized by researchers that it was
Y. Zhao impossible to gradually and stably synchronize with
e-mail: [email protected] another chaotic system [4]. Nevertheless, Pecora and

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5512 Q.Shi et al.

Carroll observed the phenomenon of synchronization port for the chaotic communication field, can address
and reached the conclusion that two chaotic systems the issue of chaotic parameter mismatch to a certain
can be synchronized by the application of an appro- extent, and has considerable potential for further devel-
priate control method [5]. In recent times, numer- opment.
ous experts and scholars have identified various forms In [14], an adaptive synchronous sliding mode con-
of chaotic synchronization in disparate chaotic sys- trol method was employed to synchronize the hyper-
tems. These include full synchronization [6], anti- chaotic system. A proportional-integral-derivative (PID)
synchronization [7], projection synchronization [8], controller was utilized to optimize the synchroniza-
adaptive synchronization [9] and other forms of syn- tion control time and synchronization accuracy. Finally,
chronization. FPGA technology was used to realize the hyper-
The study of chaotic communication has been a sig- chaotic system. [15] Active control synchronization
nificant area of research within the field of commu- is employed to realize the four-dimensional hyper-
nication, with numerous techniques based on chaotic chaotic four-wing memristor system, with the safety
synchronization having been proposed. One such tech- signal shielding application realized based on FPGA
nique is chaotic masking, which was first proposed by and numerical simulation design. The experimental
[10]. This method employs a chaotic signal as the car- results demonstrate that the useful signal can be con-
rier at the transmitter, with the intention of conceal- cealed within a chaotic sequence through the utilization
ing the information being transmitted. Following syn- of FPGA, and that the decryption signal exhibits opti-
chronization, the chaotic signal is then utilized at the mal quality. In [16], the Hamiltonian form is employed
receiver to obscure the original signal, thereby facili- to achieve the synchronization of spherical attractors,
tating the recovery of the desired information. In their and an image encryption transmission system is devised
study, [11] employed chaotic keying technology to based on simulation and FPGA. The security analysis
select carrier signals from two or more distinct chaotic indicates that the received image can be fully recov-
attractors for binary message signals. In [12], chaotic ered without the loss of information after decryption.
modulation technology is employed to modulate the [17] designed a synchronization scheme based on adap-
parameters of the chaotic system by utilising the sig- tive observer and adaptive controller to simulate the
nal transmitted by the transmitter. Subsequently, the synchronization of different brain regions, and used
corresponding parameters of the chaotic system are FPGA to complete the digital circuit implementation
extracted by employing the chaotic synchronisation and functional verification of multi-vortex HNN based
signal at the receiver, thereby enabling the recovery on memristor.
of the transmitted signal. However, the sensitivity of The synchronization control method employed in
chaotic synchronization to channel noise and parameter [14–17] represents a highly developed technology
mismatch means that the solutions proposed in [10–12] for regulating chaotic systems. However, the design
cannot be implemented in practice for secure commu- methodology of the controller is relatively complex,
nication. inflexible and exhibits a strong specificity and poor
In the context of contemporary electronic technol- versatility. Yan et al. [18] employed an FPGA to phys-
ogy, characterized by rapid development, Field Pro- ically implement the constructed four-dimensional
grammable Gate Array (FPGA) exhibits a high degree chaotic system, proposed a system combining back-
of flexibility and programmability [13], which can stepping control and multi-switch synchronization,
markedly enhance the operational speed and efficiency and then designed a controller that couples the syn-
of the system. It exhibits robust stability, straight- chronization system and memristor chaotic system.
forward integration with communication devices, and In a further development of the technology, Yan et
rapid execution speed, thereby offering a promising al. [19] proposed a method of reverse realization of
avenue for research in secure communication. Never- generalized synchronization. This involved construct-
theless, discrete chaotic synchronization can be more ing a response system by introducing feedback con-
readily incorporated into digital circuits and computer trol coefficients, which could make the error sys-
systems, which is advantageous for practical applica- tem tend to zero when the coefficients met certain
tions. Consequently, the discrete chaotic synchroniza- conditions. The literature improves the flexibility of
tion system based on FPGA offers robust technical sup- the controller design and exhibits strong universal-

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ity, thereby addressing the issue of excessive perti- 2 Theoretical basis

nency of the synchronous controller to a certain extent.
However, the results are exclusively numerical and 2.1 Reverse synchronization of the hyperchaotic
simulation-based, which limits their practical applica- Chen system
bility.
In conclusion, this paper employs FPGA technol- The hyperchaotic Chen system is a four-dimensional
ogy, puts forth the reverse synchronization theory of chaotic system, as demonstrated in [20]. Its dynamic
the Super Chen system, devises the frame transmission equation is presented in Eq. (1).
scheme in conjunction with chaotic synchronization,
⎧
and establishes an encrypted frame transmission sys- ⎪
⎪ ẋ = a(y − x) + w
⎨
tem with picture as a case study. The principal contri- ẏ = d x − x z + cy
(1)
butions are as follows: ⎪
⎪ ż = x y − bz
⎩
(1) A reverse synchronization theory of the hyper- ẇ = yz + r w
chaotic Chen system is proposed and verified in MAT-
LAB. The results demonstrate that the reverse syn- In this context, the symbols a, b, c, d, and r represent
chronization theory with an error feedback coefficient system parameters, while x, y, z, and w denote four
can achieve complete synchronization between two distinct state variables.
hyperchaotic Chen systems with identical structures. As FPGAs are only capable of processing digital
The synchronization effect is found to be highly effec- signals, the subsequent design and implementation of
tive. the hyperchaotic Chen system using FPGA is based
(2) A novel information encryption transmission on the system parameter values a = 32, b = 4, c =
scheme is proposed, which combines traditional frame 8, d = 8, r = 0.25. The dynamics analysis is carried
synchronization with chaotic synchronization. This out in accordance with these values. When the initial
new scheme makes it more difficult for an unautho- condition is set to (x0 , y0 , z 0 , w0 ) = (1, 2, 3, 4), the
rized third party to decipher the encrypted data, and it Lyapunov exponent of this chaotic system is calculated
also addresses the issue of decryption errors caused by and presented in Fig. 1.
frame loss when the chaotic sequence is encrypted as It can be observed that when the number of iterations
a stream cipher. exceeds 500, the Lyapunov exponent (LE) is greater
(3) The modules comprising the initial key recep- than zero, indicating that the system is in a hyperchaotic
tion, HD multimedia interface display(HDMI), chaotic state. At this juncture, the phase diagram of the hyper-
pseudo-random sequence generator, frame formation chaotic Chen system with the corresponding parame-
and frame splitting, encryption and decryption, infor- ters is presented in Fig. 2.
mation sending and receiving have been designed In accordance with the principles of generalized
and implemented by FPGA. The final stage of the chaos synchronization theory and the nonlinear sys-
process is the encryption and transmission of the tem stability theorem, the [19] put forth a methodol-
image. ogy whereby an error feedback coefficient (EFC) is
The following is a description of the structure of incorporated into the controller with the objective of
the paper: Sect. 2 presents the theoretical foundations reversing the control error system and thereby achiev-
of frame and backward synchronization for hyper- ing chaos synchronization. Upon the introduction of
chaotic Chen systems. The dynamic behavior of the the control coefficients, the error system demonstrates
hyperchaotic Chen system was analyzed, including the a progressive return to a state of zero. This method
phase diagram and Lyapunov exponent, and the back- exhibits notable flexibility and is capable of effec-
ward synchronization was derived. Section 3 presents tively addressing the limitation of most synchroniza-
the design of an encrypted frame transmission sys- tion methods, which are only effective for a specific
tem implemented using FPGA technology. Section 4 chaotic system but fail to maintain synchronization in
presents an analysis of the security of the designed sys- other chaotic systems, resulting in asynchrony or poor
tem. The final section, Sect. 5, presents the conclusions synchronization effects. Nevertheless, this approach
of the study. has only been tested through simulation and lacks prac-
tical applicability. This section proposes a reverse syn-

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5514 Q.Shi et al.

Fig. 1 The LE index of the

hyperchaotic Chen system

Fig. 2 Phase diagram of the hyperchaotic Chen system

chronization method for a hyperchaotic Chen system ⎧

⎪
⎪ ẋ = 32(y − x) + w
based on FPGA, and an encrypted frame transmission ⎨
ẏ = 8x − x z + 8y
system is designed to facilitate the versatility and flexi- (2)
⎪ ż = x y − 4z
⎪
bility of the method. The specific theoretical derivation ⎩
ẇ = yz + 0.25w
is as follows:
For the purposes of this analysis, Eq. (1) is consid-
The controller should be integrated into Eq. (2) as a
ered the primary system, and the following values are
slave system in accordance with the following proce-
assigned to its parameters:
dure:

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Design and FPGA implementation... 5515

⎧
⎪
⎪ ẋ1 = 32(y1 − x1 ) + w1 + ux In the aforementioned derivation formula, the vari-
⎨
ẏ1 = 8x1 − x1 z 1 + 8y1 + u y ables x, y, z, w are iterative, while u represents the con-
(3)
⎪
⎪ ż = x1 y1 − 4z 1 + uz troller and λ is the feedback control coefficient. Let the
⎩ 1
ẇ1 = y1 z 1 + 0.25w1 + uw Lyapunov function of Eq. (7) be as follows

The following definition of systematic error is pro- 1 2

posed: V (e(k)) = (e1 (k)+e2 2 (k)+e3 2 (k)+e4 2 (k))
2
⎧ ≥0 (8)
⎪
⎪ e1 = x − x1
⎨ V (e(k)) = V (e(k + 1)) − V (e(k))
e2 = y − y1
(4) = 21 (e1 2 (k + 1) + e2 2 (k + 1) + e3 2 (k + 1)
⎪ e3
⎪ = z − z1
⎩ +e4 2 (k+1))− 21 (e1 2 (k)+e2 2 (k)+e3 2 (k)+e4 2 (k))
e4 = w − w1
= λ 2−1 (e1 2 (k) + e2 2 (k) + e3 2 (k) + e4 2 (k))
2

Subsequently, upon substituting Eqs. (2) and (3) into (9)

Eq. (4), the resulting error system is obtained, as illus-
trated in Eq. (5). As illustrated in Eq. (9), when |λ| < 1 and
⎧ V (e(k)) < 0, the error system e(k) is asymptoti-
⎪
⎪ ė1 = 32(y − x) + w − 32(y1 − x1 ) − w1 − ux cally stable at zero. This implies that the drive sys-
⎨
ė2 = 8x − x z + 8y − 8x1 + x1 z 1 − 8y1 − u y tem (2) and the response system (3) are asymptoti-
⎪
⎪ ė = x y − 4z − x1 y1 + 4z 1 − uz cally synchronized. In this section, the results derived
⎩ 3
ė4 = yz + 0.25w − y1 z 1 − 0.25w1 − uw in the preceding sections are verified using MATLAB
(5) 2018a. The initial condition is set to the iteration vari-
able x = 1, y = 2, z = 3, w = 4, x1 = 4, y1 =
Subsequently, an EFC λ is introduced to facilitate 3, z 1 = 2, w1 = 1, λ1 = 0.5, λ2 = 0.125 with a
the design of a controller capable of transforming Eq. total of 500 iterations. When λ is 0.5 and 0.125, the
(5), which is advantageous for chaotic synchronization dynamic curves of the error systems e1 , e2 , e3 , e4 are
control. illustrated in Fig. 3. The results demonstrate the viabil-
ity of employing a feedback coefficient to achieve syn-
⎧
⎪
⎪ ux =32(y − x)+w−32(y1 −x1 )−w1 +λ(x − x1 ) chronization. Furthermore, it is evident that as the feed-
⎨
u y = 8x − x z+8y − 8x1 +x1 z 1 −8y1 +λ(y−y1 ) back coefficient decreases, the synchronization process
⎪
⎪ u = x y − 4z − x1 y1 + 4z 1 + λ(z − z 1 ) of the error system becomes more rapid, resulting in a
⎩ z
uw = yz + 0.25w − y1 z 1 − 0.25w1 + λ(w − w1 ) shorter synchronization time.
(6) In this section, Eq. (1) is employed as the driving
system, while the response system is constructed using
Accordingly, the Eq. (5) can be simplified as illus- the generalized projection synchronization method and
trated in Eq. (7), thereby facilitating the desired out- the backward synchronization method with an error
come of negatively impacting the controller. About function, respectively. The synchronization establish-
expansion, the error system can be defined in accor- ment time and synchronization error are then compared
dance with the error feedback coefficient. Thereafter, and analyzed. The simulation results are presented in
the defined error variable can be substituted into the Fig. 4, and a comparison of the results is provided in
general equation of the controller, thereby obtaining Table 1. It can be observed that the backward synchro-
the calculation formula of the controller. This approach nization with the error function has a shorter establish-
allows for greater flexibility in the design of the con- ment time, a faster synchronization speed, and a closer-
troller. to-zero synchronization error. Furthermore, the syn-
chronization accuracy and stability are superior to those
⎧
⎪ ė1 = λ(x − x1 ) = λe1
⎪ achieved by the generalized projection synchronization
⎨
ė2 = λ(y − y1 ) = λe2 method. Additionally, the synchronization method pro-
(7)
⎪
⎪ ė = λ(z − z 1 ) = λe3 posed in this section can accelerate the synchronization
⎩ 3
ė4 = λ(w − w1 ) = λe4 speed and reduce the synchronization error by provid-

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5516 Q.Shi et al.

Fig. 3 The dynamics of the error systems

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Design and FPGA implementation... 5517

Fig. 4 The dynamics of the error systems

Table 1 Comparison table for synchronization establishment time

Discrete chaotic synchronization method State variable Number of iterations Synchronization error

7.8 × 10−
4
Generalized projective synchronization method x1 19
6.7 × 10−
4
x2 17
6.9 × 10−
4
x3 18
6.1 × 10−
4
x4 18
3.7 × 10−
4
Chaotic backward generalized synchronization x1 10
3.4 × 10−
4
x2 8
3.4 × 10−
4
x3 8
3.7 × 10−
4
x4 10

ing a smaller error coefficient, thereby enhancing the the more effective the synchronization, but the lower
flexibility of discrete chaotic generalized synchroniza- the efficiency [22]. A check code is employed to ascer-
tion system construction. tain whether an error has occurred during transmission.
This paper presents a novel approach to utilizing
the first dimensional chaotic sequence among the four-
2.2 Chaotic frame synchronization dimensional pseudo-random sequences generated by
a synchronized master chaotic system as the frame
Frame synchronization technology is a commonplace head, with the remaining three-dimensional sequences
technology in the field of communication, primarily forming the key stream. The three-dimensional key
to enable the receiver to accurately identify the start- stream was spliced and XOR encrypted with the plain-
ing and ending positions of a group of data from the text information, thereby obtaining the ciphertext infor-
received sequence [21]. The most common data frame mation. The frame header was then inserted into the
format is illustrated in Fig. 5. It typically comprises encrypted ciphertext information, thus forming a frame
a frame header, data and a check code. The frame for transmission. In the slave system, a similar four-
header contains either synchronization bytes or syn- dimensional pseudo-random sequence is generated.
chronization signals, with the objective of establishing The first dimension is employed for sliding detection,
the length of each frame. The longer the frame header, whereby the frame header is searched. The remaining

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5518 Q.Shi et al.

Fig. 5 The traditional format for data frames

Fig. 6 Flowchart of the frame transmission scheme combined with chaotic synchronization

three dimensions are then used for decryption of the transmission system will not fail due to a frame being
ciphertext, thus obtaining the plaintext data. The infor- out of sync, resulting in subsequent frame disloca-
mation contained within the continuous data stream is tion and decryption failure. Concurrently, the pseudo-
identified in sequence to ascertain the received data. random sequence of the chaotic system is employed
From the perspective of hardware implementation, the as the frame head, with its frame head undergoing a
design employs the characteristics of a chaotic system constant alteration with the iteration of the chaotic sys-
and chaotic synchronization, utilizing the chaotic syn- tem. This renders the system challenging to decipher.
chronization sequence as the frame head. This ensures Figure 6 illustrates the flow of the designed frame trans-
that the normal decryption of the subsequent frame data mission scheme, while Fig. 7 presents the flow chart of
is not affected when a frame is disrupted or even lost stream cipher encryption and decryption. In these fig-
during transmission. Furthermore, it guarantees that the ures, 1, 2, ..., n represent the number of frames trans-

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Design and FPGA implementation... 5519

Fig. 7 Flow chart of

encryption and decryption
of stream cipher

mitted, while x, y, z, w represent the chaotic sequence 3 Design and implementation of encrypted frame
generated by the master–slave chaotic system. In com- transmission system based on chaotic reverse
parison with the conventional frame synchronization synchronization control
approach, this section employs the attributes of chaotic
synchronization to embed the data within the chaotic 3.1 Synchronous byte and encrypted sequence
signal. The receiver is then able to recover the infor- generation
mation by synchronously receiving the chaotic signal,
thus facilitating secure communication. The generated In this section, the simple Euler algorithm is employed
random sequence is utilized as the frame synchroniza- to discretise each system, thus facilitating the FPGA
tion head sequence, which enables the dynamic update implementation of chaotic reverse synchronisation.
of the key through a slight alteration of the synchro- The driving system and response system are illustrated
nization parameter, thereby enhancing communication in Eqs. (10) and (11), respectively.
security.

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5520 Q.Shi et al.

⎧ represents the rounding operation, and saturation rep-

⎪
⎪ x(k + 1) = [32y(k)−32x(k)+w(k)] × T +x(k)
⎨ resents the saturation cutoff. For digital devices, a right
y(k + 1) = [8x(k)−x(k)z(k)+8y(k)] × T +y(k)
shift of M bits of data indicates division by 2 M . After the
⎪ z(k + 1) = [x(k)y(k) − 4z(k)] × T + z(k)
⎪
⎩ initial key undergoes T0 , T1 , T2 , T3 and T4 five clock
w(k + 1) = [y(k)z(k) + 0.25w(k)] × T + w(k)
cycles, a new effective chaotic iteration value can be
(10)
⎧ generated.
⎪ x1 (k + 1) = [32y1 (k) − 32x1 (k) + w1 (k)]
⎪
⎪ Following the preprocessing of the design for-
⎪
⎪ ×T + x1 (k) + u x
⎪
⎪ mula, the hardware model is constructed using a
⎪
⎪ y (k + 1) = [8x1 (k) − x1 (k)z 1 (k) + 8y1 (k)]
⎪
⎨
1 top-down approach. The requisite synchronization
×T + y1 (k) + u y bytes and encryption sequences are provided by the
⎪
⎪ z 1 (k + 1) = [x1 (k)y1 (k) − 4z 1 (k)]
⎪
⎪
chaotic synchronization system. Figure 9 illustrates
⎪
⎪ ×T + z 1 (k) + u z
⎪
⎪ RTL diagram of chaotic reverse synchronization con-
⎪
⎪ w (k + 1) = [y1 (k)z 1 (k) + 0.25w1 (k)]
⎩ 1 trol, which is composed primarily of the master sys-
×T + w1 (k) + u w tem module (Master_Chen) and the slave system mod-
(11) ule (Slave_Chen). The corresponding signal inter-
face definitions are presented in Table 2. The pri-
The resulting controller, obtained after the introduc-
mary system receives a 128-bit initial key, designated
tion of the EFC, is shown in Eq. (12).
as mkey_in, and generates a four-dimensional 32-bit
⎧ chaotic sequence, comprising the variables x, y, z, w.
⎪ u x (k) = x(k + 1) − x1 (k + 1) − λ(x(k) − x1 (k))
⎪
⎨ Additionally, it produces a valid signal of the pri-
u y (k) = y(k + 1) − y1 (k + 1) − λ(y(k) − y1 (k)) mary chaotic sequence, designated as mc_valid. When
⎪
⎪ u (k) = z(k + 1) − z 1 (k + 1) − λ(z(k) − z 1 (k)) the four-dimensional chaotic sequence mc_valid is
⎩ z
u w (k) = w(k+1) − w1 (k + 1)−λ(w(k) − w1 (k)) valid, the four-dimensional 32-bit chaotic sequences
(12) sx, sy, sz, sw, as well as the 32-bit error sequences
err _x, err _y, err _z, err _w, are produced by the slave
The simplified error system is shown in Eq. (13) system according to the four-dimensional chaotic
sequence output by the master system. These sequences
⎧
⎪
⎪ e1 (k + 1) = λe1 (k) result from reverse synchronization and iterative calcu-
⎨
e2 (k + 1) = λe2 (k) lation of the initial key skey_in for the two systems.
(13)
⎪ e3 (k + 1) = λe3 (k)
⎪ This section is realized by the simulation tool Wave-
⎩
e4 (k + 1) = λe4 (k) form of Vivado 2019.1, and the results are presented
in Fig. 10. Once the initial key is set to mkey_in =
In the aforementioned equations, the variables x, y, 128 h01000000_02000000_03000000_04000000, skey
z, w are state variables, k represents the number of iter- _in = 128 h04000000_03000000_02000000_01000
ations, u is the controller, λ is the EFC, and T is the 000, it can be observed from Fig. 10 that the chaotic
sampling time, which is T = 2−8 in this paper. sequences mc_x, mc_y, mc_z, mc_w and sc_x, sc_y,
The employment of fixed-point operations and the sc_z, sc_w, generated by the master and slave chaotic
substitution of power-two operations with basic shift systems, exhibit pseudo-random behaviour. Further-
operations in FPGA can result in a reduction in the con- more, after iteration, all error values converge to 0 at
sumption of time and hardware resources. Accordingly, 32-bit precision. At a frequency of 200 MHz, the initial
this section presents a methodology for reverse syn- synchronization sequence is generated in 115 ns, with
chronization of the hyperchaotic Chen system, employ- each subsequent iteration taking only 25 ns. At 865 ns,
ing 32-bit signed fixed-point numbers. In order to pre- the error values err or _x, err or _y, err or _z, err or _w
vent data overflow, the decimal part and the integer part reach zero, thus satisfying the designed accuracy cri-
are subjected to preprocessing via rounding and satu- teria. The results demonstrate that the error system is
ration truncation, respectively. Equations(10) and (11) asymptotically stable. The two hyperchaotic systems
are integerized and implemented by writing Verilog are fully synchronised.
HDL, and the corresponding operation architecture dia-
gram is shown in Fig. 8. In the figure, the symbol r ound

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Design and FPGA implementation... 5521

Fig. 8 The operation iteration diagram of the FPGA-based master–slave system

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5522 Q.Shi et al.

Fig. 9 RTL diagram of chaotic reverse synchronization control

Table 2 Chaotic reverse synchronization design port name and description

Port name Direction Bit width Description

clk In 1 System clock

rstn In 1 Reset signal, low valid
mkey_in/ skey_in In 128 Master/slave system initial key
m_start/s_start In 1 Master/slave system initial key valid signal
sx/sy/sz/sw Out 32 Sequence from the slave system
err_x/err_y/err_z/err_w Out 32 Sequence of errors
err_valid/sc_valid Out 1 Error valid signal/synchronous valid signal

3.2 Implementation of encrypted frame transmission into two stages: the synchronization stage (SS) and the
scheme encrypted transmission stage (ETS).
The initial key was first input through the serial
3.2.1 The top-level design of the system port at the transmitter, whereupon the four-dimensional
chaotic sequence x, y, z, w are obtained by driving the
The.coe file is a common file format utilised in the system and subsequently transmitted to the receiver.
Vivado software for the initialisation of memory con- The receiver also inputs the initial key through the serial
tents. The file contains the address of the memory and port and iterates with the received chaotic sequence
is essentially text-based. To facilitate the observation (x, y, z, w) in the response system to obtain the chaotic
of data from both the sending and receiving ends in a sequences (x1 , y1 , z 1 , w1 ). Upon generation of an iden-
more intuitive manner, the image is stored in the mem- tical chaotic sequence by the receiver and transmitter,
ory of the development board in the form of a.coe file, the four LED indicators representing synchronization
serving as an information source, thereby establishing a status are activated and deactivated. The receiver then
continuous and stable data flow for transmission. Given transmits a synchronization success signal syn_sig to
the length of the image sequence, a single transmission the transmitter, signifying that the two systems are fully
would result in a greater number of states within the synchronized.
state machine and occupy a larger memory space. Con- Following synchronization at the transmitter, the
sequently, in this section, the data stream is divided into chaotic sequences y, z, w, generated by the drive sys-
multiple frames and transmitted in a sequential manner. tem, serve to generate the master key pseudorandom
The overarching principle of the design is illus- sequence generator. Additionally, the first 16 bits of the
trated in Fig. 11, which depicts the principal archi- chaotic sequence x are responsible for generating the
tectural components. The overall workflow is divided master synchronization head pseudorandom sequence

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Design and FPGA implementation... 5523

Fig. 10 Simulation waveform of chaotic reverse synchronization control

generator. Then, the sequences y, z, w are subjected to the ciphertext, thereby facilitating the restoration of the
XOR encryption with the plaintext, thereby obtaining plaintext image.
the ciphertext. Subsequently, the ciphertext is divided To facilitate the verification of results, the plaintext
into multiple sections, which are enclosed within the and ciphertext images are output by the HDMI interface
synchronization header, and transmitted to the recip- on the display screen by pressing the relevant key at
ient. At the receiver, a similar chaotic sequence is the transmitter and receiver. This allows for a more
generated by the response system through the method convenient visual design.
of reverse synchronization control. Subsequently, the Furthermore, the comprehensive illustration of the
slave key pseudo-random chaotic sequences y1 , z 1 , w1 overall frame transmission process for this section can
and the slave synchronization head pseudo-random be found in Fig. 12. The sequence receiving module
sequence x1 are designed, respectively. The purpose of (SRM) performs a preprocessing step, wherein the data
x1 is to detect the synchronization head of the received is split and the resulting split data is continuously
ciphertext, and the encrypted data is restored after a suc- passed to the encryption module(EM) for encryption.
cessful detection. Subsequently, the chaotic sequences Subsequently, a frame was constructed by the synchro-
y1 , z 1 , w1 are employed for the purpose of decrypting nisation header and the check bit in the frame formation
module(FFM) and the 113-bit data was transmitted in

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Fig. 11 The top-level architecture of encrypted frame transmission system based on chaotic reverse synchronization

serial in the parallel conversion module(PSCM). The the decryption module(DCM) and subsequently passed
receiver transmits the received data to the detection to the sequence transmission module(STM).
module(DM), where it is converted back into 113-bit
parallel data and subjected to shift detection. Should
3.2.2 FPGA implementation of the system
the synchronisation header be consistent with the pack-
age, the frame synchronisation signal is set to 1, the
The synchronous encryption system described in this
state machine commences operation, and the subse-
paper is implemented using two identical AX7103
quent functions are initiated. In accordance with the
development boards, which serve as the transmit-
prescribed frame structure, the frame splitting mod-
ter and receiver, respectively. The transmitter and
ule(FSM) parses the 96-bit data and 1-bit check bit
receiver are composed of two distinct modules: a
in sequence, under the control of the counter, and per-
synchronization module and a transmission module.
forms a parity check on the parsed data during the pars-
The overall RTL diagram of the sender is illustrated
ing process, subsequently outputting the 1-bit check
in Fig. 13a. The chaos_syn_t x(SPTX) module repre-
result. The remaining 96-bit data is then decrypted in
sents the sender’s synchronisation module, while the
comm_transmitter (CPTX) module corresponds to

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Design and FPGA implementation... 5525

Fig. 12 Flowchart of the encrypted frame transmission scheme

the sender’s encryption transmission module. The func- (IKR) module is analogous to that of the IKT, enabling
tion of SPTX is to generate the chaotic sequence that the reception of the key. Upon the circuit board being
forms the basis of the main system. The CPTX module powered on or reset, the circuit enters a waiting state.
is responsible for encrypting the plaintext and transmit- The IKR then inputs the key to the SPRX for buffer-
ting it. Furthermore, the initial_key_r ec(IKT) mod- ing and awaits the chaotic sequence from the SPTX.
ule serves as the initial key receiving module. And the When the chaotic sequences generated by the master
function of the S_LED module is to facilitate the con- and slave systems are fully synchronised, it is indica-
trol of the illumination. Upon the activation of the cir- tive of the attainment of a synchronisation state at both
cuit board or a reset, the IKT module is responsible for ends. The LED indicator on the development board is
converting the serial data received (r xd) into a 128-bit deactivated, and the synchronisation signal syn_sig is
parallel initial key (t_data). The key is then fed into set to 1 and fed back to SPTX. Upon receipt of the syn-
the SPTX for iterative operation, whereby it generates chronisation success signal by the SPTX, the CPTX
the chaotic sequence x, y, z, w, which is subsequently commenced operation. In contrast, the CPRX module
transmitted to the receiver. At this juncture, the cir- awaits the encrypted data transmitted by CPTX before
cuit is in a waiting synchronisation state. Upon receipt initiating its own operations.
of the synchronisation signal (syn_sig_r x), the LED Among the diagrams presented, that of CPTX is
indicators transition from an active state to an inactive shown in Fig. 14a. The plaintext_storge(PTS) mod-
state, and CPTX commences operation. The plaintext ule is employed for the storage and retrieval of images,
data is XOR encrypted, and then the ciphertext data the trans_ f sm(TFSM) module serves as the state
is transformed in parallel to serial, encapsulated with machine for sending control, the text_encr ypt(TE)
the synchronisation header and detection bit, and then module is utilised for encryption, the parit y_coder
transmitted frame by frame. (PC) module is responsible for frame formation, the
The comprehensive receiver-side RTL diagram is ser _coder (SC) module facilitates parallel and serial
illustrated in Fig. 13b, which encompasses the chaos_ conversion, and the video_out_test_t x(HDMI_OUT
syn_r x(SPRX) and the comm_r eceive(CPRX). SPRX _TX) module is dedicated to displaying encrypted
and SPTX correspond to the slave system module in the and decrypted images at the sender. The PTS divides
chaotic synchronization system, while CPRX serves to the.coe format picture into 96-bit continuous data and
split the received ciphertext data and restore it to plain- stores it in FIFO, subsequently generating the sig-
text. Furthermore, the function of the initial_key_r ec nal ct f _empt y for the FIFO. Upon receipt of the

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Fig. 13 RTL diagram of frame synchronization encrypted transmission system based on chaotic reverse synchronization

ct f _empt y signal by the TFSM module, a clock pulse the sc_en signal, which in turn controls the SC module
signal ct f _r dr eq, is generated and transmitted to initi- to send the data in a serial format, one byte at a time.
ate the reading of the initial 96-bit data. Subsequently, Upon completion of the transmission, the ct f _r dr eq
the TFSM module generates a clock pulse signal, des- signal outputs a clock pulse, initiating a repetition of
ignated te_en, which is transmitted to the TE module the subsequent operation until the entirety of the PTS
and the received chaotic sequence. This signal serves module data has been transmitted.
to encrypt the frame data, resulting in the output of Figure 14b illustrates the RTL diagram of CPRX.
96-bit encrypted data, designated te. Subsequently, a More, the function of the f rame_syn(FS) mod-
clock pulse signal pc_en, is output to control the PC ule is to detect the synchronisation header in the
module for encapsulation. The received 16-bit synchro- data stream.The r ec_ f sm(RFSM) module controls
nisation bytes, 96-bit encrypted data, and 1-bit parity the state machine of each module for the receiver.
are then combined to form a frame, and the resulting The text_decr ypt(TD) module decrypts the cipher-
113-bit data pc, is finally output. This signal controls text. The des_coder (DC) module performs a serial-

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Design and FPGA implementation... 5527

Fig. 14 RTL diagram of the data stream encrypted frame transmission system

parallel conversion. The parit y_check(PCH) mod- to 97-bit data parallel transmission. Subsequently, the
ule splits the frame. The RFSM module controls the PCH module is triggered to unpack the 1-bit parity error
state machine of each module. The HDMI_OUT_RX and 96-bit encrypted data. The TD module is then ini-
module is employed for the purpose of displaying the tiated via the output of the td_en control signal, which
encrypted and decrypted image of the receiver. Upon initiates the corresponding decryption operation in con-
receipt of the data, the FS module initiates the search junction with the decrypted chaotic sequence. Once the
for the synchronization header, shifting from the data decryption process is complete, the FS module initi-
stream to do so. In the event of the detection of the frame ates a further frame header detection and repeats this
header, the pulse signal f s_syn is outputted over the step until no further synchronization headers are iden-
course of a single clock cycle. Upon the assignment tified, indicating that the entirety of the data has been
of the value of 1 to f s_syn, the RFSM module com- received. Upon completion of the data reception pro-
mences its operation. Firstly, the dc_en, which outputs cess, the HDMI_OUT_RX module displays the result-
a single clock cycle, controls the DC module to trans- ing data.
fer the comm_t x received data from serial transmission

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5528 Q.Shi et al.

Fig. 15 Zoom-in display of

plaintext and ciphertext
images

Table 3 Transmitter
Resource Utilization Available Utilization%
resource consumption
LUT 3076 63400 4.85
LUTRAM 250 19000 1.32
FF 4990 126800 3.94
BRAM 82.50 135 61.11
DSP 12 240 5.00
IO 77 285 27.02
BUFG 12 32 37.50
MMCM 2 6 33.33

3.3 Board level verification The results of the FPGA implementation of the syn-
chronous encrypted transmission system are illustrated
Following the completion of the functional simulation, in Fig. 16. The image at the sending end is displayed
it is necessary to proceed with the verification of the on the left computer, which controls the left display
board to confirm that the system is capable of function- screen. The original image and the encrypted image
ing on the actual FPGA development board. This was are transformed by the key control. The image of the
achieved by using two AX7103 development boards receiving end is controlled by the right computer, which
as the transmitter and receiver, respectively, with the also displays the image on the right display screen.
external display serving as the final demonstration of Furthermore, the encrypted and decrypted images are
the results. Figure 15 illustrates the output display result converted by pressing the key, and the data is trans-
of the 128 × 128 Baboon image encryption effect. mitted through the DuPont line between the two ends.
Figure 15a depicts the zoom-in display of the Baboon The error valid signal (err _valid) is employed as the
plaintext image, while Fig. 15b shows the zoom-in dis- trigger condition for the ILA, and the chaotic sequence
play of the encrypted image. The resources employed generator at the receiver captures the error sequences
on the development board for the FPGA implemen- (err or _x[31 : 0], err or _y[31 : 0], err or _z[31 :
tation of the transmitter are detailed in Table 3. The 0], err or _w[31 : 0]), as illustrated in Fig. 17. It can be
resources utilized on the development board for the observed that a period of 150 ns elapses between the
FPGA implementation of the receiver are outlined in reception of the four-dimensional chaotic sequence and
Table 4. the generation of the error sequence. Furthermore, the
four-dimensional error sequence tends towards zero.

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Design and FPGA implementation... 5529

Table 4 Receiver resource

Resource Utilization Available Utilization%
consumption
LUT 4620 63400 7.29
LUTRAM 693 19000 1.32
FF 8106 126800 6.39
BRAM 92 135 68.15
DSP 12 240 5.00
IO 76 285 26.67
BUFG 11 32 34.38
MMCM 2 6 33.33

Fig. 16 FPGA
Implementation Results

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5530 Q.Shi et al.

Fig. 17 Grasps of ILA waveform for chaotic reverse synchronization control

Fig. 18 Histograms of the original and encrypted images

4 Security analysis the encrypted image exhibits a relatively uniform distri-

bution of components between 0 and 300. This suggests
4.1 Encryption effect that the encryption algorithm has effectively obscured
the original pixel values, rendering it challenging for an
4.1.1 Histogram attacker to extract meaningful statistical features from
the encrypted image.
The histogram of the image can be employed to demon-
strate the impact of encryption on the image [23]. 4.1.2 Correlation
This section presents a comparative analysis of the
RGB colour components of the original image and Furthermore, the encryption effect of the image can be
the encrypted image, as illustrated by frequency his- observed in the relationship between adjacent pixels,
tograms. As illustrated in Fig. 18abc, the distribution of as illustrated in [24]. A qualified ciphertext image is
the RGB components of the original image is markedly defined as one in which the correlation between adja-
disparate, suggesting that the image encompasses a cent pixels is close to zero. In this section, 5000 pairs of
wealth of statistical data. As illustrated in Fig. 18def, adjacent pixels are randomly selected from the original
image and the encrypted image, and then encrypted and

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Design and FPGA implementation... 5531

Fig. 19 Correlation detection of original and encrypted images in horizontal, vertical and diagonal directions

decrypted in horizontal, vertical and diagonal direc- the table, the generated sequence has been shown to
tions for the purpose of correlation analysis. The results pass all the NIST test items, thereby indicating that the
of the experiment are presented in Fig. 19. As can be randomness of the sequence meets the requisite stan-
observed in the figure, all the pixels of the original dards.
image are concentrated on the diagonal, and there is a
strong correlation between them. In contrast, the adja-
cent pixels of the encrypted image are distributed uni- 4.1.4 Information entropy analysis
formly across the entire coordinate plane, resulting in
a significantly reduced correlation between pixels. The concept of information entropy is employed to
quantify the uncertainty inherent to any given piece
of information. As uncertainty increases, the entropy
4.1.3 Randomness test value also rises. The definition formula is presented
in Eq. (14), in which is the probability when the grey
The National Institute of Standards and Technology value is m i , and L is the grey level. A value of entropy
(NIST) system testing standards are a widely utilized approaching 8 indicates a high degree of image clutter.
methodology for the assessment of the randomness
level of sequences [25]. In this section, the output
chaotic sequence is subjected to an evaluation by the 
L
NIST-SP800-2 test suite. The selected data set com- H =− P (m i ) log2 P (m i ) (14)
prises 4 × 106 elements, and the significance level is i=0
set to 0.01. A p-value exceeding 0.01 signifies that the
test has been successfully completed. The test results The results of the image information entropy test are
are presented in Table 5. In instances where multiple p presented in Table 6. These results demonstrate that the
values are generated from a single test, the minimum information entropy of each component of the cipher-
value is reported in this section. As can be seen from text image is closer to 8 than that of the original image,

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5532 Q.Shi et al.

Table 5 NIST test results

Test items P value Result
of chaotic pseudo random
sequence NonOverlapping template(min) 0.016991 Pass
Overlapping template 0.815372 Pass
FFT 0.994823 Pass
Frequency 0.307225 Pass
Approximate Entropy 0.454958 Pass
Cumulative Sum 0.952570 Pass
Linear Complexity 0.298329 Pass
Longest Run 0.884922 Pass
Random Excursion(min) 0.015511 Pass
Random Excursions Variant(min) 0.073718 Pass
Block Frequency 0.917273 Pass
Rank 0.448290 Pass
Runs 0.864662 Pass
Serial 0.475586 Pass
Universal 0.061388 Pass

Table 6 Image information

Image information entropy R G B
entropy test results
Original image 7.2063 7.5308 6.8688
Ciphertext image 7.9308 7.9858 7.9849

indicating that the encryption process meets the stan- an increase in transmission rate results in a more seam-
dards and requirements of information hiding. less transmission and a reduction in delay [26]. In this
section, the ILA is employed for signal capture, with
the dc_en signal serving as the trigger condition for the
4.2 Frame synchronization effect ILA. The captured waveform is illustrated in Fig. 20.
The orange waveform represents the frame synchroni-
The synchronisation speed and stability of chaotic sation signal f s_syn, the dark grey line marks the point
synchronisation have a direct impact on the efficacy at which synchronisation is first achieved, which occurs
of frame synchronisation. Consequently, this paper at 1009 ns, and the blue line marks the point at which
employs a performance index of frame synchronisa- the rising edge of f s_syn is achieved. The generation
tion as a means of indirectly assessing the stability of of stable f s_syn requires a mere 113 ns between two
chaotic synchronisation. In this section, a 128 × 128 pulses, indicating that the transmission rate of this sys-
Baboon graph in the form of.coe is utilised as the data tem is 8.44 Mbps, a notably rapid speed and a relatively
source, with a total of 16384 24-bit data points trans- brief establishment time for synchronisation.
mitted.
4.2.2 Frame loss rate
4.2.1 Data transfer rate
The term ’frame loss rate(FLR)’ is used to describe
In the context of word communication systems, data the proportion of frames that are lost during the trans-
transmission rate is defined as the number of data mission or processing of data. A high frame loss rate
frames transmitted per second. It can be observed that will result in incomplete images, which will have a

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Design and FPGA implementation... 5533

Fig. 20 Waveform diagram of ILA grasp signal for frame synchronization signal fs_syn

Table 7 Image information entropy test results

Send times 1 2 3 4 5

Number of frames transmitted 4096 4090 4067 4095 4096

Frame loss rate 0 0.14% 0.71% 0.02% 0

detrimental impact on the visual effect. Given that the was designed. Secondly, an encrypted frame transmis-
system transmits 96-bit data per frame, it is theoret- sion system combining traditional frame synchroniza-
ically feasible to send 4096 frames to convey 16384 tion and chaotic sequence was proposed, which was
24-bit data. In this section, the logic analyser ILA is mainly divided into three stages. First, in the establish-
employed to capture the waveform, ascertain the actual ment stage of chaotic synchronization, after the master
total number of transmitted frames and subsequently and slave system input the key, the four-dimensional
calculate the frame loss rate. This section presents the chaotic systems at both ends were synchronized by the
results of five tests, as detailed in Table 7. As can be controller, and the four-dimensional chaotic sequence
observed from the data presented in the table, the actual was generated, and the synchronization success signal
number of frames transmitted is largely in alignment was generated. Second, frame synchronization stage,
with the theoretical number of frames. Because of the in this stage, the first-dimension chaotic sequence gen-
discrepancy in asynchronous clocks between the vari- erated by the chaotic system acts as a synchroniza-
ous levels of the board, it is inevitable that interference tion head to insert a frame data, and the same chaotic
will occur, which will result in the loss of frames during sequence generated from the system is used to check the
the transmission process. Nevertheless, the information synchronization head from the data stream to achieve
contained within the original image can be discerned in frame synchronization. Thirdly, in the encryption trans-
these five tests. Upon decryption and restoration of the mission stage, the post-3D chaotic sequence of the
received data to the image, the five decrypted, enlarged chaotic system is used to encrypt the input plaintext
images at the receiver are presented in Fig. 21. This image and transmit it. Finally, the encryption effect and
indicates that the system is relatively stable. frame synchronization effect were analyzed by experi-
mental verification in FPGA. The analysis results show
that the synchronization establishment time is short, the
5 Conclusion transmission speed is fast, the encryption effect is good,
and the security is high, which promotes the research
In this paper, we propose an encrypted frame trans- and development of chaotic synchronization in the field
mission scheme based on FPGA with chaotic reverse of secure communication. Nevertheless, this paper also
synchronization. Firstly, a new chaotic reverse synchro- requires the optimal utilization of the storage resources
nization method was proposed, and a controller for the of the development board to address the issue of insuf-
reverse synchronization of hyper-Chen chaotic systems ficient image data transmission.

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5534 Q.Shi et al.

Fig. 21 Decrypted zoomed

images at different frame
loss rates

Author contributions Qiqin(first author):Conceptualization, References

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