eMagin Corporation SXGA-096 CFXL

SXGA-096 CF XL

1280 X 1024 LOW-POWER COLOR XL

AMOLED MICRODISPLAY

DATASHEET
Revision E

For Part Numbers:

EMA-101200-01

eMagin Corporation reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other rights. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. eMagin Corporation cannot assume responsibility for any problem arising out of the use of these circuits

eMagin Corporation 700 South Road, Suite 201 Hopewell Junction , New York 12533 www.emagin.com
eMagin Corporation SXGA-096 CFXL
D11-501537-00 Rev E Datasheet

Revision Level ECN Date Scope

- 2015-151 12-18-2015 Initial Release
A 000280 07-28-2017 Updated eeprom map (Appendix C)
B 12-15-2017 Updated section 9.7.1 (DISPOFF function)
C 000756 11-20-2019 Updated sections 10.3.5 and 10.4.5, updated
eeprom map (Appendix C)
D 01-08-2020 Updated Assembly views (Fig 12 & 13) to
geometric tolerancing standard
Added IDRF register value limit (p 34)
E 000919 02-21-2020 Corrected Table 6-1 for LMAX values
Corrected EEPROM Map section 109.4.5 and
Appendix C for addresses 144d and 145d

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eMagin Corporation SXGA-096 CFXL
D11-501537-00 Rev E Datasheet

TABLE OF CONTENTS

1. INTRODUCTION ..............................................................................................................................................5
2. GENERAL DESCRIPTION .............................................................................................................................. 6
2.1 SXGA-096 COLOR XL MICRODISPLAY ...........................................................................................................6
3. FUNCTIONAL OVERVIEW ............................................................................................................................ 7
4. INPUT / OUTPUT DESCRIPTION .................................................................................................................9
5. PIXEL ARRAY LAYOUT............................................................................................................................... 10
6. ELECTRICAL CHARACTERISTICS .......................................................................................................... 11
6.1 TIMING CHARACTERISTICS ............................................................................................................................ 15
6.1.1 Video Input Timing Diagrams ............................................................................................................. 15
6.1.2 Gamma Sensor Timing Diagram ......................................................................................................... 17
7. OPTICAL CHARACTERISTICS .................................................................................................................. 18
7.1 ROOM TEMPERATURE CHARACTERISTICS ...................................................................................................... 18
7.2 CHARACTERISTICS OVER FULL OPERATIONAL TEMPERATURE RANGE (-46°C TO +71°C) ............................... 19
8. MECHANICAL CHARACTERISTICS ........................................................................................................ 21
9. CARRIER BOARD SCHEMATIC ................................................................................................................. 24
10. DETAILED FUNCTIONAL DESCRIPTION ............................................................................................... 25
10.1 VIDEO INTERFACE ..................................................................................................................................... 25
10.2 D/A CONVERSION ..................................................................................................................................... 28
10.3 FORMAT AND TIMING CONTROL ............................................................................................................... 29
10.3.1 Vertical Position Control ................................................................................................................ 29
10.3.2 Horizontal Position Control ............................................................................................................ 30
10.3.3 Interlaced Modes............................................................................................................................. 30
10.3.4 Stereovision Mode ........................................................................................................................... 30
10.3.5 Row Duty Rate Control ................................................................................................................... 31
10.4 SENSOR FUNCTIONS .................................................................................................................................. 33
10.4.1 Temperature Readout ...................................................................................................................... 33
10.4.2 Luminance Regulation Sensor......................................................................................................... 33
10.4.3 Pixel Bias Sensor ............................................................................................................................ 33
10.4.4 Luminance Control (Dimming) ....................................................................................................... 33
10.4.5 Luminance Setting ........................................................................................................................... 34
10.4.6 Gamma Correction Sensor .............................................................................................................. 35
10.5 DC-DC CONVERTER ................................................................................................................................. 41
10.6 SERIAL INTERFACE .................................................................................................................................... 43
10.7 POWER-ON SEQUENCE .............................................................................................................................. 45
10.7.1 Display Off Function ....................................................................................................................... 46
10.8 POWER SAVINGS MODES ........................................................................................................................... 46
10.9 BUILT-IN TEST PATTERNS ......................................................................................................................... 46
11. REGISTER MAP SUMMARY ....................................................................................................................... 48
12. DETAILED REGISTER DESCRIPTIONS ................................................................................................... 51
12.1 STAT (00H) .............................................................................................................................................. 51
12.2 VINMODE (01H) ..................................................................................................................................... 51
12.3 DISPMODE (02H) .................................................................................................................................... 53
12.4 LFTPOS (03H) .......................................................................................................................................... 54
12.5 RGTPOS (04H) ......................................................................................................................................... 55

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eMagin Corporation SXGA-096 CFXL
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12.6 TOPPOS (05H) ......................................................................................................................................... 55

12.7 BOTPOS (06H) ......................................................................................................................................... 55
12.8 ROWRESET (07H, 08H) ........................................................................................................................... 56
12.9 RAMPCTL (09H) ..................................................................................................................................... 56
12.10 RAMPCM (0AH) ...................................................................................................................................... 57
12.11 VDACMX (0BH) ...................................................................................................................................... 58
12.12 BIASN (0CH) ............................................................................................................................................ 60
12.13 GAMMASET (0DH)................................................................................................................................. 60
12.14 VCOMMODE (0EH) ................................................................................................................................ 61
12.15 VCOMCTL (0FH)..................................................................................................................................... 62
12.16 VGMAX (10H) ......................................................................................................................................... 63
12.17 VCOM (11H) ............................................................................................................................................ 63
12.18 IDRF (12H) ............................................................................................................................................... 64
12.19 DIMCTL (13H) ......................................................................................................................................... 65
12.20 TREFDIV (14H) ....................................................................................................................................... 66
12.21 TEMPOFF (15H) ...................................................................................................................................... 66
12.22 TUPDATE (16H) ...................................................................................................................................... 66
12.23 TEMPOUT (17H) ..................................................................................................................................... 67
12.24 ANGPWRDN (18H) ................................................................................................................................. 69
12.25 SYSPWRDN (19H)................................................................................................................................... 70
12.26 TPMODE (1AH) ....................................................................................................................................... 71
12.27 TPLINWTH (1BH) ................................................................................................................................... 73
12.28 TPCOLSP (1CH)....................................................................................................................................... 73
12.29 TPROWSP (1DH) ..................................................................................................................................... 74
12.30 TPCOLOR (1EH) ...................................................................................................................................... 74
12.31 DLYSEL (1FH) ......................................................................................................................................... 75
12.32 LVDSCTL (20H) ...................................................................................................................................... 76
12.33 SKEW0 (21H, 22H) ................................................................................................................................... 77
12.34 SKEW1 (23H, 24H) ................................................................................................................................... 78
12.35 SKEW2 (25H, 26H) ................................................................................................................................... 78
12.36 SKEW3 (27H, 28H) ................................................................................................................................... 78
12.37 SKFAST (29H) ......................................................................................................................................... 79
12.38 SKSLOW (2AH) ....................................................................................................................................... 79
12.39 SYNCMOD (2BH) .................................................................................................................................... 80
12.40 LUT_ADDR (2CH) ................................................................................................................................... 80
12.41 LUT_DATA (2DH, 2EH) .......................................................................................................................... 80
12.42 LUT_UPDATE (2FH)............................................................................................................................... 81
12.43 RESERVED (30H,31H,32H,33H).................................................................................................................. 81
12.44 RESERVED (34H,35H) ................................................................................................................................ 82
12.45 RESERVED (36H) ....................................................................................................................................... 82
12.46 RESERVED (37H) ....................................................................................................................................... 82
12.47 RESERVED (38H,39H) ................................................................................................................................ 82
12.48 RESERVED (3AH) ...................................................................................................................................... 83
12.49 RESERVED (3BH)....................................................................................................................................... 83
12.50 RESERVED (3CH)....................................................................................................................................... 83
12.51 RESERVED (3DH) ...................................................................................................................................... 83
12.52 RESERVED (40H) ....................................................................................................................................... 84
12.53 RESERVED (41H) ....................................................................................................................................... 84
12.54 RESERVED (42H) ....................................................................................................................................... 84
13. APPENDIX A: APPLICATION SYSTEM DIAGRAM ............................................................................... 85
14. APPENDIX B: LVDS TX DESIGN EXAMPLE ........................................................................................... 86
15. APPENDIX C: EEPROM MEMORY MAP .................................................................................................. 92
16. APPENDIX D: RECOMMENDED REGISTER SETTINGS ...................................................................... 95

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eMagin Corporation SXGA-096 CFXL
D11-501537-00 Rev E Datasheet

1. INTRODUCTION

The SXGA-096 OLED-XL device from eMagin Corporation is an active-matrix organic light emitting
diode (AMOLED) microdisplay intended for near-to-eye applications that demand high brightness, high
resolution, high image quality, compact size, and low power. Combining a total of 4,015,536 active dots,
the SXGA-096 display is built on a single crystal silicon backplane and features eMagin’s proprietary
thin-film OLED XL technology offering extended life and luminance performance.

The active array is comprised of 1292 x 1036 square pixels with a 9.6-micron pitch and a 75% fill factor.
An extra 12 columns and 12 rows (beyond the 1280 x 1024 main array) are provided to enable the active
SXGA-096 display to be shifted by steps of 1 pixel in the X and Y directions for optical alignment
purposes. Additional dummy and test pixels surround the active array. Each full pixel is laid out as three
3.2 x 9.6 micron identical sub-pixels, which together form the 9.6-micron square RGB color group. Three
primary color filter stripes are applied in alignment with the sub-pixels on a white-emissive OLED layer
to form the color display.

The SXGA-096 design features eMagin’s proprietary “Deep Black” architecture that ensures off- pixels
are truly black, automatically optimizes contrast under all conditions, and delivers improved pixel
uniformity. In addition to its flexible matrix addressing circuitry, the SXGA-096 includes an internal 10-
bit DAC that ensures 256 fully gamma-corrected gray levels, an on-chip set of look-up-tables for digital
gamma correction, and a novel pulse-width-modulation (PWM) function that, together with the standard
analog control, provides an extended dimming range. The PWM function also enables an impulse drive
mode of operation that significantly reduces motion artifacts in high speed scene changes.

The SXGA-096 includes a very low-power, low-voltage-differential-signaling (LVDS) serialized

interface for video data transport that minimizes the number of board interconnections and connector size,
reduces electromagnetic emissions (EMI), and enables a lightweight and flexible cable link to a remote
video source. Compatibility with standard LVDS drivers found in most commercially available FPGAs
simplifies the system integrators task.

Detailed device specifications and application information for the SXGA-096 OLED-XL microdisplay
produced by eMagin Corporation are provided in this document.

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eMagin Corporation SXGA-096 CFXL
D11-501537-00 Rev E Datasheet

2. GENERAL DESCRIPTION

2.1 SXGA-096 Color XL Microdisplay

Display Type: Emissive, color XL AMOLED on Silicon

Format: 1280(x3) x 1024 pixels
Total Pixel Array: 1292(x3) x 1036 pixels
Pixel Size & Aspect Ratio: 9.6-micron Square
Fill Factor 75%
Viewing Area 12.4 x 9.945 mm (15.9 mm diagonal (0.62”))
Mechanical Envelope 20.0 x 16.5 x 5.0 mm (w x l x h)
Weight <3 gm.
Gray Levels 256 levels per primary color
Uniformity > 85% end-to-end uniformity
Pixel Spatial Noise <5% (1 sigma)
Contrast Ratio >10,000:1 (at maximum luminance)
Pixel Response Linear with input video signal (using internal gamma LUT)
Dimming Ratio >200:1 analog, >200:1 pwm, >4,000:1 total (maximum)
White Luminance 150 cd/m2 typical, up to 250 cd/m2 @ Ta = 20°C
CIE (White) CIE-X = 0.26 to 0.37, CIE-Y = 0.30 to 0.38
Video Modes SXGA, HD720, DVGA, 8-bit control of active window
Progressive & Interlaced scan
Horizontal (left/right) and vertical (up/down) scan control
Horizontal and vertical image shift by up to 12 pixels
Video Interface Serialized LVDS, 24 Digital RGB (up to 5 twisted line
pairs including the clock pair)
Refresh Rate 30 to 85 Hz
Video Source Clock 120 MHz max
LVDS Clock 480 MHz max
LVDS Data Rate 960 Mbps
Control Interface I2C serial interface (+1.8VDC)
Power Consumption <250 mW typical @ 150 cd/m2 (Ta=+20°C)
Power Supply
VDD5 (analog & array) 5VDC ±5% (700 mA maximum)
VDD1.8 (logic & I/Os) 1.8VDC ±5% (20 mA maximum)
VPG -1.5VDC ±5% (1 mA maximum)

Operating ambient temperature -46 to +71°C

Storage temperature -55 to +90°C
Humidity 85%RH non condensing

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eMagin Corporation SXGA-096 CFXL
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3. FUNCTIONAL OVERVIEW

LVDS Data
(4 pairs) TOP COLUMN SEQUENCERS
LVDS
LUT
RECEIVERS
ODD COLUMN SWITCHES
LVDS CLK
BUFFER
RAMP DAC

ROW SEQUENCER & PWM LOGIC

and
LVDS AMP
BUFFER
ALIGN

VCOM
SERIAL
INTERFACE TIMING
I2C CONTROL OLED ARRAY
LOGIC
1292 x 1036
BUILT-IN
SENSOR
GAMMA FUNCTIONS
TEST LOGIC

5V
BIAS &
1.8V EVEN COLUMN SWITCHES
REFERENCES
DC-DC
-1.5V CONVERTER
BOTTOM COLUMN SEQUENCERS

VCOM
CUK
CONVERTER

Figure 1: Top-level block diagram for SXGA-096

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eMagin Corporation SXGA-096 CFXL
D11-501537-00 Rev E Datasheet

LVDS Cable Link Microdisplay

24b RGB Video

Serial Data _ Clk

LVDS Rx
LVDS Tx
USER OLED

DAC
HS, VS, DE

FPGA ARRAY

LUTs
CLK ALIGN

I2C Serial Bus

5V /1.8V / -1.5V
Sensor Signal
10b
µC A/D

Figure 2: System application diagram

FPGA SXGA-096 Microdisplay

LVDS Tx LVDS Rx
Twisted-pair cable
SKEW COMPENSATION

(upto 4 Data Pairs)

DESERIALIZER

VIdeo Data
SERIALIZER

8:1

(24/bit)
8:1

HSYNC
VSYNC SXGA-150
DE
CORE
LVDS_CLK

Clock Recovery
SCLK PLL & Divider
LVDS_ALIGN
ALIGN

Figure 3: LVDS interface diagram

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eMagin Corporation SXGA-096 CFXL
D11-501537-00 Rev E Datasheet

4. INPUT / OUTPUT DESCRIPTION

Connector J1 is a Hirose DF12D (3.0)-30DP-0.5V

Connector J1
Pin # Pin Name Type Description
1 GND Power Power return terminal.
2 VPG Power Negative voltage bias for array protection switch. (-1.5 V)
3 RD3P LVDS LVDS Digital Data and Sync Input Port.
4 GND Power Power return terminal.
5 RD3N LVDS LVDS Digital Data and Sync Input Port.
6 VDD5 Power Input power for Analog Circuits (5VDC).
7 GND Power Power return terminal.
8 VDD5 Power Input power for VCOM (5VDC).
9 RD2N LVDS LVDS Digital Data and Sync Input Port.
10 VDD5 Power Input power for Pixel Array (5VDC).
11 RD2P LVDS LVDS Digital Data and Sync Input Port.
12 GND Power Power return terminal.
13 GND Power Power return terminal.
14 VDD1.8 Power Input power for logic and I/O pads.
15 RCKN LVDS LVDS source clock.
16 VGN Analog Out Gamma sensor output signal. (0 to +2.5V)
17 RCKP LVDS LVDS source clock.
18 BURN_IN Logic In Activates test mode used for Burn-In.
19 GND Power Power return terminal
20 RESETB Logic In Asynchronous system reset (active low).
21 RD1N LVDS LVDS Digital Data and Sync Input Port.
22 ENABLE Logic In Enable logic input.
23 RD1P LVDS LVDS Digital Data and Sync Input Port.
24 SCL Logic In Clock port for the serial interface. 400 KHz Max.
25 GND Power Power return terminal
26 SDA Logic I/O Data port for the serial interface. Open collector I/O
27 RD0N LVDS LVDS Digital Data and Sync Input Port.
28 SERADD Logic In Serial interface LSB address bit. Must be connected.
29 RD0P LVDS LVDS Digital Data and Sync Input Port.
30 LVDS_ALGN Logic In LVDS logic initialization signal (CMOS input).

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eMagin Corporation SXGA-096 CFXL
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5. PIXEL ARRAY LAYOUT

COLUMN #: 0 1 2 1290 1291

R G B R G B R G B R G B R G B R G B R G B

ROW 0 VCOM GAMMA R G B R G B R G B R G B R G B R G B R G B

Replica Replica

ROW 1 R G B R G B R G B R G B R G B R G B R G B

ROW 2
R G B R G B R G B R G B R G B R G B R G B

R G B R G B R G B R G B R G B R G B R G B

ROW 1033 R G B R G B R G B R G B R G B R G B R G B

ROW 1034 R G B R G B R G B R G B R G B R G B R G B

ROW 1035 R G B R G B R G B R G B R G B R G B R G B

R G B R G B R G B R G B R G B R G B R G B

3 6 6 3 3 1092 x 3 3
Replica VCOM GAMMA Replica Pixel Active Pixel
Dummy Replica Replica Dummy Dummy Pixel Dummy

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eMagin Corporation SXGA-096 CFXL
D11-501537-00 Rev E Datasheet

6. ELECTRICAL CHARACTERISTICS

Table 6-1 : Absolute Maximum Ratings

Symbol Parameter Min Typ. Max. Unit

VDD1.8 Front End Power Supply -0.3 2.5 VDC
VDD5 Array/Analog Power Supply -0.3 5.5 VDC
VCOM Common electrode bias -6 0 VDC
VPG Array Bias Supply -3 0 VDC
VI Input Voltage Range -0.3 VDD+0.3 VDC
VO Output Voltage Range -0.3 VDD+0.3 VDC
PD Power Dissipation 1 W
Tst Storage Temperature -55 +90 °C
Tj Junction Temperature -45 +125 °C
Ilu Latch up current +100 mA
Vesd Electrostatic Discharge – ±2000 V
Human Body Model

Stresses at or above those listed in this table may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other condition above those indicated in the following
tables is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability (except for the reverse bias condition. See below). Prolonged exposure to high temperatures will
shorten the luminance half-life.

Table 6-2 : Recommended Operating Conditions

Symbol Parameter Min Typ. Max. Unit

VDD1.8 Front End Power Supply 1.71 1.8 1.89 VDC
VDD5 Array/Analog Power Supply 4.75 5 5.25 VDC
VCOM Common electrode bias -5 -2.0 0 VDC
VPG Array Bias Supply -3 -1.5 0 VDC
Tst Storage Temperature -55 +90 °C
Ta Ambient Operating Temp. -45 +25 +70 °C
Pdt All Pixels On Power 300 mW
Consumption (+25°C)

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eMagin Corporation SXGA-096 CFXL
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Table 6-3 : DC Characteristics

(Ta = 20°C, VDD1.8 =+1.8V, VDD5 = +5V, GND = 0V)

Symbol Parameter Min Typ. Max. Unit
VDD1.8 Front End Power Supply 1.8 V
VDD5 Array/Analog Power Supply 5 V
VCOM Common electrode bias -6 -1.0 0 V
VPG Array Bias Supply -1.5 V
Vil Digital input low level GND-0.3 0.6 V
Vih Digital input high level 1.2 VDD1.8+0.3 V
Vol Digital output low level GND 0.5 V
Voh Digital output high level VDD1.8-0.2 VDD V
VGN Gamma feedback signal 0 5 V

Table 6-4 : AC Characteristics

(Ta = +20°C, GND = 0V, VDD1.8= +1.8V, VDD5 = +5.0V, VPG = -1.5V,)
Symbol Parameter Min Typ. Max. Unit
SCLK Video Clock Frequency 44 - 120 MHz
CLK_Duty SCLK duty cycle 45 55 %
Fhs Horizontal Sync frequency 30 70 KHz
Fvs Vertical Sync Frequency 30 85 Hz
Tlo Line Overscan (% of line time) 3 %
Tfb Frame Blanking (% of frame time) 1 %
Trst Reset Pulse Width 100 - µs
Cin Digital Pins Input Capacitance 3 pF
Cvpg Pin VPG Input Capacitance 13.6 nF
Pd VDD5 Average VDD5 Power Consumption 160 mW
(SXGA Mode 60 Hz refresh rate)
Pd VDD1.8 Average VDD1.8 Power Consumption 25 mW
(SXGA Mode 60 Hz refresh rate)
Pd VPG Average VPG Power Consumption 1 mW
Pd PDWN Total Power Consumption in PDWN 2.5 mW
(sleep) mode
Ta Ambient Operating Temperature -46 +71 °C

Power consumption measured at 60Hz refresh rate, room ambient temperature and with a TV-
like color test pattern that represents an average video mode (See below Figure 4) and a full
white field equivalent luminance of 150 cd/m2

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eMagin Corporation SXGA-096 CFXL
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Figure 4: Color Test Pattern

Figure 5 shows the typical room temperature power consumption of the display for different
image contents and maximum luminance.

Figure 5: SXGA096 CFXL Power vs. Luminance

Figure 6 shows the typical power consumption (mW) over the operational temperature range
(°C) and a room temperature luminance set to 150 cd/m2 with 50% of the pixels turned on.

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eMagin Corporation SXGA-096 CFXL
D11-501537-00 Rev E Datasheet

Figure 6: Power vs. Temperature

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eMagin Corporation SXGA-096 CFXL
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6.1 Timing Characteristics

6.1.1 Video Input Timing Diagrams

TVF
TVS
VSYNC

HSYNC

TAVS TAV TVIDL

TCLK
SCLK
(pixel clock)

HSYNC

THS TDES TLDATA THIDL

THL
DE

VIDEO

Figure 7: Video Input Timing Diagram

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eMagin Corporation SXGA-096 CFXL
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Table 6-5 : Video Input Timing Characteristics

Parameter Symbol Min. Typ. Max. Unit

1
Clock Frequency FCLK 91 120 MHz
Clock Period TCLK 10.98 ns
Clock Duty DCLK 45 55 %
VSYNC Pulse Width TVS 2 HSYNC period
Time to Active Video Start TAVS 5 HSYNC period
Time to Next Vsync TVIDL 2 HSYNC period
Active Video Lines TAV 526 1024 1036 HSYNC period
HSYNC Pulse Width THS 8 SCLK period
Time to DE Start TDES 12 SCLK period
Time to Next Hsync THIDL 12 SCLK period
Active Video Pixel TLDATA 782 1280 1292 SCLK period
Line Overscan THL 1200 SCLK period
Note 1: SXGA @ 60 0Hz frame rate, Reduced Blanking Mode

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eMagin Corporation SXGA-096 CFXL
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6.1.2 Gamma Sensor Timing Diagram

tFB Active Video Rows tVSDE

VSYNC
tSMP
DataEN

IDSTEP
tACQ
VGN_SAMPLE

VGN_DATA OLD DATA NEW DATA

tVGN tCNV

Figure 8: Gamma Sensor Timing Diagram

Table 6-6 : Gamma Sensor Timing Characteristics

Parameter Symbol Min. Typ. Max. Unit

IDSTEP to VGN Settling Time tVGN 10 ms
Frame Blanking (% of Frame Time) tFB 1 %
VGN Sampling Time tSMP tACQ tVSDE
A/D Acquisition Time tACQ 20 μs
A/D Conversion Time tCNV

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eMagin Corporation SXGA-096 CFXL
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7. OPTICAL CHARACTERISTICS

7.1 Room Temperature Characteristics

Table 7-1 : SXGA-096 XL Color Microdisplay Optical Characteristics

Conditions: Ta = +20ºC, VDD1.8 = +1.8V, VDD5 = +5V, VPG = -1.5V, Refresh rate: 60 Hz
Symbol Parameter Min. Typ. Max. Unit
Front Luminance @ max gray level 120 150(1) 250(2) cd/m2
LMAX
Variability (display to display) (3) 0 3 5 %
Minimum display luminance @ max.
LMIN - 0.2 0.5 cd/m2
gray level(4)
CR White to Black Contrast Ratio 1,000:1 10,000:1 > 50,000:1
CIE-X 0.270 0.310 0.370
CIE White
CIE-Y 0.300 0.360 0.380
CIE-X 0.570 0.600 -
CIE Red
CIE-Y 0.300 0.340 0.370
CIE-X 0.180 0.250 0.330
CIE Green
CIE-Y 0.470 0.550 -
CIE-X - 0.140 0.190
CIE Blue
CIE-Y - 0.150 0.180
GL Gray Levels - 256 256 levels
FR Refresh Rate 30 60 85 Hz
FF Emissive Area/Total Sub-pixel Area 0.75
(5)
ULA End to end large-area uniformity 85 %
(6)
Pixel spatial noise at ½ luminance
SVH 5 %
(1STD)
Time to recognizable image after
TON 0.5 sec
application of power
Note 1: At the center of a display with all pixels on at gray level 255

Note 2: At the center of a display with all pixels on at gray level 255

Note 3: When using on-board eeprom values to set IDRF for the targeted luminance (See 9.4.5)

Note 4: Assumes IDRF = 06, DIMCTL = 64 and use of the PWM dimming mode (see 9.4.4).

Note 5: At gray level 255 and 150 cd/m2 luminance. Luminance uniformity measured between the
nominal values of five 1,000 pixel zones located in the four extreme corners and the center zone of the
display.

Note 6: Spatial noise is measured at half the nominal luminance (~80 cd/m2) and gray level 255. The
measurement is the ratio of the variability (standard deviation) by the mean luminance.

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eMagin Corporation SXGA-096 CFXL
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7.2 Characteristics over full operational temperature range (-46°C to +71°C)

Figure 9 below shows the luminance regulation over the full operational temperature range with the
display operated with 50% of pixels turned on at gray level 255 and a room temperature luminance set to
~ 150 cd/m2.
The typical variability (defined as (Max-Min)/(Max+Min)) is 9%

Figure 9: Luminance stability vs. Temperature

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eMagin Corporation SXGA-096 CFXL
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Figures 9 and 10 show the stability of the White color point (CIE-X and CIE-Y) over the full operational
temperature range at luminance set to 150 cd/m2 at room temperature.

Figure 10: White CIE-X vs. Temperature @ 150 cd/m2

Figure 11: White CIE-Y vs. Temperature @ 150 cd/m2

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eMagin Corporation SXGA-096 CFXL
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8. MECHANICAL CHARACTERISTICS

Connectors J1
Manufacturer: Hirose
Manufacturer Part Number: DF12D(3.0)-30DP-0.5V

Mating Connector Information

Manufacturer: Hirose
Manufacturer Part Number: DF12A(3.0)-30DS-0.5V

Weight: < 3 grams

Printed Circuit Board Material: FR4
Printed Circuit Board Tolerances: ± 0.25 mm (both axes)

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eMagin Corporation SXGA-096 CFXL
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Figure 12: SXGA-096 Microdisplay Assembly

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Figure 13: SXGA-096 Microdisplay Assembly - Detail

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eMagin Corporation SXGA-096 CFXL
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9. CARRIER BOARD SCHEMATIC

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eMagin Corporation SXGA-096 CFXL
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10. DETAILED FUNCTIONAL DESCRIPTION

10.1 Video Interface

RD3P Skew
Compensation Deserializer
RD3N Circuit 8

RD2P Skew
Compensation Deserializer ROUT[7:0]
RD2N Circuit 8 8
Synchronization
Logic GOUT[7:0]
RD1P Skew 8
Compensation Deserializer
RD1N 8 BOUT[7:0]
Circuit 8
VSYNC
RD0P Skew HSYNC
Compensation Deserializer DE
RD0N Circuit 8 ENABLE

Data
Alignment

RCKP Clock Recovery and

Programmable
Delay Divider DCLK
RCKN

LVDS_ALIGN
EN_IN

SCL
Configuration
SDA I2C Slave
Registers Internal Signals
SERAD
(To internal LUTS)

Figure 14: LVDS Receiver Block Diagram

The video interface signals are composed of 4 data pairs and one clock pair, which are the low
voltage differential signaling (LVDS), and one control signal (LVDS_ALIGN), which is a
CMOS signal. It is different from the industry standard LVDS interface protocols. The receiver
input PADs expect the standard LVDS output signaling, but the serialization and protocol is
different. The LVDS data pairs should be 8-bit serialized data. The LVDS clock also should be
the serialized signal in the same way to the data channel with toggle pattern instead of PLL
clock. It always should be 4 times faster than the pixel clock. The LVDS receiver uses both
edges of clock. And it has a special skew compensation circuit to harmonize the skews among
the 4 data pairs and the data alignment logic. The LVDS receiver expects the special skew
compensation patterns through all LVDS channels including the clock channel when power is
applied and the alignment patterns to identify the MSB of the 8-bits serial data at every VSYNC
at least. (Refer to Appendix B)

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Figure 15 shows how the LVDS channels map into data (R,G,B) and control signals

Note that a monochrome white implementation at reduced power is possible by using only
channels RD2 and RD3 and setting bit 6 of register 2 (DISPMODE) to 1.

LVDS Data Channel

Bits
RD0 RD1 RD2 RD3
7 R7 G6 R0 B5
6 R1 G5 DE B4
5 R6 G1 HSYNC B3
4 R5 G0 ENABLE B1
3 R4 G4 VSYNC B0
2 R3 G3 B7 B2
1 R2 G2 G7 B6
0 VDMY1* VDMY2* VDMY3* VDMY4*

* : Dummy bits for line balance

Figure 15: LVDS Data Map

Video Format LVDS Interface

Pixel Clock Video Data No. of Pins LVDS Data rate LVDS Clock
MHz (pairs w. clock) Mbps MHz

SXGA (60Hz) 24bit 5 728.00 364.00

91.00
1280X1024

HD720 (60Hz) 24bit 5 596.00 298.00

74.50
1280X720

Table 10-1: Example LVDS Interface Timing

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Symbol Parameter Conditions Min Typ Max Units

VCM Common Mode Input 1.0 1.8 V
Range
VTH Differential Input VCM = +1.2V +100 mV
High Threshold
VTL Differential Input -100 mV
Low Threshold
IIN Input Current VIN = 1.8V ±10 μA
VIN = 1.0V ±10 μA
FTCLK LVDS Clock SXGA FR=60Hz 364 400 MHz
Frequency
TTTCLK LVDS Clock F = 400MHz 0.68 ns
Transition Time
DCTCLK LVDS Clock Duty F = 400MHz 45 55 %
Cycle
SKWMG Receiver Skew F = 400MHz 200 ps
Margin with Deskew

Table 10-2: LVDS Characteristics

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10.2 D/A Conversion

In this design the conversion of the video input signal into an analog drive signal at the pixel is carried out
in a two-step process during each horizontal clock period. The digital input video data is first transformed
into a precise time delay based on counts of the global RAMP clock. Second, the time delay triggers the
column switch to sample the voltage of a linear ramp and to store the analog value on the column line
capacitor. The selected pixel circuit copies the analog data and uses it for driving the OLED diode until it
is refreshed during the next frame period.

A block diagram of one column drive circuit is shown in Figure 16. The 1292 Display registers form a
line memory that facilitates a pipeline mode of operation in which video data is converted to analog form
and sampled by the pixels in row M during the same line period that video data for row M+1 is loading
into the LOAD registers. At the end of each line period the data in the LOAD registers is transferred in
parallel into the DISPLAY line memory. The externally supplied SCLK clock is used for both loading
input data into the chip and for advancing the global column counter. There is a maximum latency of 2
line periods before data is displayed.

Figure 16: Data sampling for Column N

A timing diagram for the data sampling process is shown in Figure 17 . The internal Ramp Generator
operates at the HSYNC frequency and outputs a linear ramp with a slow rise-time and a fast reset
capability that is buffered and applied to all the pixel array columns simultaneously. The RAMP signal
starts synchronously with HSYNC (after a delay) with a positive slope from a zero voltage level and rises
to a voltage near the VDD5 rail after 1024 SCLK clock cycles as determined by a 10-bit counter. The

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start position of the RAMP can be adjusted via register bits RAMPDLY, its peak value can be set using
register VDACMX, and the duration of the flyback transition can be selected between two options by the
FLYBTIME bit in register RAMPCTL.

SCLK

HSYNC

RAMPCLK_EN
VAN
DAOFFSET

RAMP

0V

RAMPDLY
FLYBTIME

Figure 17: Timing diagram for column data sampling

10.3 Format and Timing Control

Various control signals for the horizontal and vertical sequencers that are needed to implement the
specified video formats are generated in the Timing & Control Logic block. The specific timing
parameters are set by registers VINMODE, DISPMODE, LFTPOS, RGTPOS, TOPPOS and BOTPOS
using the serial interface.

The display starts up with the array in the off-state (black) by default and requires a command to the
DISPOFF register bit via the serial interface to turn the display on. This provides the user with an
opportunity to change the default startup conditions before a video image is displayed.

Bi-directional scanning is supported in both orientations via the DISPMODE register. Bit VSCAN sets
the vertical scan direction, and bit HSCAN sets the horizontal scan direction.

10.3.1 Vertical Position Control

To support the vertical positioning of the display within the extra 12 pixels provided on each column of
the array, an on-chip shift register function is provided in the Row sequencer logic, and controlled by
registers TOPPOS and BOTPOS. The starting row for the active video is determined by register TOPPOS
and the ending row by register BOTPOS, which are set by default so the active window in SXGA mode is
vertically centered in the array. The Vertical positioning logic will blank rows at the beginning and end of
each frame of data to allow a vertical image shift of up to 12 pixels in steps of 1 or 2 pixels in SXGA
mode.

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10.3.2 Horizontal Position Control

To support the horizontal positioning of the display within the extra 12 pixel provided on each row of the
array, an on-chip shift register function is provided after the LUT block, and controlled by registers
LFTPOS and RGTPOS. The Horizontal Shifter adds black pixel data to the beginning and end of each
line of data to allow a horizontal image shift of up to 12 pixels in steps of 1 pixel in SXGA mode.

10.3.3 Interlaced Modes

Bits SCMODE in the DISPMODE register are used to select either progressive (default) or interlaced
modes.

Field status in interlaced mode is provided via the ENABLE input pin. The state of this pin is latched on
the falling edge of VSYNC. When register bit SET_FIELD = “0” then a logic low at the ENABLE pin
indicates that Field 1 (odd field) is active, and a logic high indicates that Field 2 (even field) is active. The
opposite states are indicated when SET_FIELD is set to 1.

10.3.4 Stereovision Mode

The SXGA-096 is designed with binocular stereovision applications in mind. As a result of the fast
OLED response time and the presence of a storage capacitor at each pixel, it has been verified that the
microdisplay can operate at low refresh rates without showing flicker.

This allows the displays to be used with a frame or field sequential (more generally known as time
sequential) stereovision mode using a single video input channel, and therefore providing a simple means
to leverage the capabilities of PC compatible computers using stereo compatible graphics adapters, such
as the NVidia GeForce series. The frame sequential stereovision mode supported should follow the Video
Electronics Standards Association (VESA) Connector and Signal Standards for Stereoscopic Display
Hardware. This standard is available from VESA at www.vesa.org.

The ENABLE input pin allows for a direct implementation of the VESA standard without additional
external components. The microdisplay can be programmed for either an active high or low Enable,
allowing a single signal to be used with two displays. In such a configuration, one display scans and
displays while the other one holds and displays.

The ENABLE input acts, when set low, as a mask for HSYNC and VSYNC. It does not blank the display
but prevents it from acquiring another frame of data until released. This is a real time input. The active
state (high or low logic level) is programmed by the SET_ENABLE bit in the VINMODE resister.

The 3D-MODE bit of the DISPMODE register will be used to set either Time Sequential mode to activate
the stereovision mode of operation (1) or Normal (non-3D) operation (0).

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Frame Sequential Mode:

In Time Sequential Mode each video frame contains information for either the left or right eye. When 3D-
MODE=”1” the SCMODE bits in the DISPMODE register are set to Progressive Scan Mode (00H) for
frame sequential mode. The following description for Frame Sequential operation assumes the source is
in compliance with the VESA standard mentioned above, where the data for the left eye is provided while
the Enable signal is at the logic high level, and the data for the right eye display is provided while the
Enable signal is at the logic low level. The stereovision mode is controlled by both the Enable input pin
and by the SET_ENABLE bit of the VINMODE register. The Enable input signal is sampled into the
circuit by a flip-flop clocked on the falling edge of VSYNC and the sampled value is used for the next
frame. (The Enable signal is generated by the graphics software and may not be synchronized to the
VSYNC signal).

To activate the stereovision mode, the right eye display needs to be configured with Enable active low
(SET_ENABLE= “0”). This will allow the right eye microdisplay to hold the previous frame while the
Enable input is high. The left eye display must be configured with Enable active high
(SET_ENABLE=”1”). Thus the two Enable inputs can be tied together to the incoming Stereo Sync
signal provided by the graphics adapter (or other custom source).

Field Sequential Mode:

In Field Sequential Mode each video field in an interlaced image contains information for either the left
or right eye. Consequently, the resolution is reduced in half for each display.

When 3D-MODE=”1” the SCMODE bits in the DISPMODE register are set to either Interlaced or
Pseudo Interlaced Mode to activate field sequential mode. The operation of the Enable input pin and the
SET_ENABLE bit will be similar to Frame Sequential Mode except that now the Enable input toggles at
the field rate. The polarity of the field corresponding to the active state of the ENABLE input will be set
by the SET_FIELD bit in the VINMODE register. When SET_FIELD=”0” the odd field is applied during
the active state for ENABLE, and the even field is assumed during the active state for ENABLE when
SET_FIELD=”1”.

For standard WVGA operation, the SET_ENABLE bit needs to be set to 0 (logic low), which is the
power-on default value, and the Enable pin input needs to be tied to Ground.

10.3.5 Row Duty Rate Control

The duty rate for a row of data is defined as the fraction of a frame period during which the pixels
maintain a programmed value; for the remainder of the frame period the pixels will be driven to black.

A Row Reset function is provided in the SXGA096 to allow the duty rate of rows to be controlled
between 0 and 100% (default condition). The register ROWRSET[9,0] is used to set the number of Hsync
cycles during which the pixel data is driven to black during a frame period. For ROWRSET=0 the pixel

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data is never driven to black and the duty rate for pixel data is equal to 100% (default). For
ROWRSET=W the pixels in any row are driven to black for the final 2*W Hsync cycles in an active
frame period.

Frame Time

Row N

ROWRSET=W

RS_N

Pixel Value
(ROWRSET=0)

Pixel Value
(ROWRSET=W)

Figure 18 : Timing diagram showing Row Reset functionality.

The operation of the Row Reset function is depicted in the timing diagram shown in Figure 18. All the
pixels contained in ROW N are programmed during the Nth horizontal line scan following the
initialization line scans which occur at the beginning of a video frame. Normally this pixel data is stored
in the pixel and remains unchanged until it is refreshed during the next frame period. When the Row
Reset function is activated, the pulse RS_N is generated at a position determined by the value of register
ROWRSET. For example, when the register value is equal to W the rising edge of RS_N occurs exactly
2*W Hsync cycles after the programming cycle for ROW N. The pulse RS_N sets all the pixels in ROW
N to black until the next programming cycle. All rows in the array will operate at the same duty rate. As a
result the duty rate for all the rows in the pixel array will be given by

2  W  THSYNC
ROW _ DUTY =
TFRAME

This function can be used to control dimming (see section 9.4.5) to extend the display dimming
range. A side benefit of this function, when used for dimming, is that no gamma update is needed
when dimming is done exclusively with the Row Reset function.

Another use of this function is to reduce motion artifacts: the net visual effect of limiting the on-
time of a given row is a reduction in visual persistence. This allows the eye to “forget” the state
of the row prior to its update with potentially new information, and leads to the perception of a
smoother motion when an object in the image changes position from frame to frame.
The exact value of the Row Reset registers for this function are application dependent and the
user must determine what constitutes an acceptable configuration.

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10.4 Sensor Functions

10.4.1 Temperature Readout

An on-chip temperature sensor provides continuous device temperature information via the serial
interface. The sensing circuitry allows for calibration at power-up via dedicated registers, TREFDIV[5,0]
and TEMPOFF[7,0]. The temperature reading is digitized on-chip and stored in a dedicated register,
TEMPOUT[7,0]. A register bit, TSENPD in register ANGPWRDN, is able to power down the sensor.

The temperature sampling period is controlled by register TUPDATE[7,0] which allows the temperature
reading to be updated between every 50msec to 4.25sec when operating at a 60Hz frame rate.

10.4.2 Luminance Regulation Sensor

Register VGMAX[7,0] controls the pixel drive voltage used for regulating the maximum luminance
value. By default this level is set to about 4.95V when the VDD5 supply is equal to 5V to avoid saturating
the video buffers. It can be adjusted over a range of 4 to 5V.

Register VDACMX[7,0] is used to set the maximum value of the internal Ramp DAC generator. This
value should match the internal VGMAX setting for best luminance accuracy and control. The optimum
setting has been determined by measurements to be 7A for normal operating conditions. Refer to section
12.12 for more detail.

10.4.3 Pixel Bias Sensor

Register BIASN[2,0] sets a bias current for the OLED array in order to achieve improved control of black
level and color saturation at the expense of a small increase in power consumption. In the default setting
(BIASN=1) the bias contributes to a 10mW increase of power consumption for the array. It is
recommended to use the BIASN=3 setting for best performance.

10.4.4 Luminance Control (Dimming)

A variable luminance level is achieved by controlling the maximum pixel current while maintaining the
largest possible dynamic range. Dimming control for the display is effected by adjusting the 7-bit register
DIMCTL via the serial interface to provide 128 linear steps in brightness ranging from near zero to the
maximum level set by register IDRF. This functionality is only available for VCOMMODE=0 or 1.

The bits IDRF_COARSE in register IDRF provide a coarse adjustment of the maximum luminance level,
while the IDRF_FINE bits enable the coarse level to be fine-tuned. Figure 19 shows the typical
luminance output at gray level = 255 in a color display for various settings of the IDRF and DIMCTL
registers.

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The maximum useable value of IDRF is 0xDF. Any greater value will result in restarting IDRF at
0x00. (for example, writing 0xEF to IDRF will be equivalent to writing 0x0F to IDRF)

The IDRF functional block design results in duplicate luminance settings (see the detailed IDRF
register description in section 11.18)

Luminance Control Chart (DIMCTL=64h) Luminance Control Chart (IDREF=30h)

Default ~ 80cd/m2 Default ~ 80cd/m2

6 1.4
Normalized Luminance Output

Normalized Luminance Output

5 1.2

1
4

0.8
3
0.6
2
0.4

1
0.2

0 0
0 50 100 150 200 0 20 40 60 80 100 120 140
IDRF(decimal) DIMCTL(decimal)

Figure 19: luminance profile for various IDRF settings

10.4.5 Luminance Setting

The SXGA-096 microdisplay luminance can be set to an absolute value using information included
in the on-board eeprom at addresses 0x8E to 0x90.
The luminance is a linear function of IDRF for values of IDRF greater than 32 (decimal code).)
that can be expressed as:
L = slope x IDRF (decimal) - intercept

The information in registers 8Eh (142d) to 90h (144d) provides the slope and intercept values that
govern the Luminance vs. IDRF linear equation.
Register 0x8E provides the integer part of the slope
Register 0x8F provides the fractional part of the slope
Registers 0x90 and 0x91 provide the origin value (Theoretical luminance value for IDRF = 0. It is
theoretical because the linear equation is only valid for IDRF >20h (32 decimal)). Values for
Origin range from 0 to 65535.
Register 0x91 is the low-byte register
Register 0x90 is the high-byte register

The slope and intercept values are calibrated for each display. With these values, the calculated
luminance is in cd/m2 units (nits).
The accuracy of the calculated value is smaller than or equal to 3% for a luminance up to 200
cd/m2, and better than 5% beyond 200 cd/m2.

This allows precise matching between displays when used in a binocular application, as well as
exceptional consistency of performance from display to display.

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10.4.6 Gamma Correction Sensor

The gamma sensor is provided as an aid to generating a linear optical response from the SXGA-
096 display system. As described previously, an external 256-entry look-up-table is required to
transform input video data into a gamma-corrected data signal for driving the microdisplay input
port. The SXGA-096 display generates an internal real-time representation of the gamma
correction curve for the current operating conditions. This representation is in the form of an
analog voltage waveform which can be sampled one point at a time at the VGN pin for eight
specific values on the curve. A specific value VGNi., corresponding to one of 8 internally fixed
grayscale levels GLi, is selected by setting bit IDSTEP in register GAMMASET via the serial
port. The VGN signal is internally fixed for a full-scale output range of VDD5/2. Eight
sequential measurements are required to complete the gamma table. The gamma table can then
be used to reconstruct an approximation of the ideal gamma correction curve using piece-wise
linear interpolation, or by employing a curve fitting algorithm to achieve more accuracy if
desired. This function is only available for VCOMMODE=00h.

An external A/D converter is required to convert each VGN measurement into digitized form and
to store the values in a microcontroller for further processing. A full frame period following a
change in the IDTEP bit should be provided to allow the VGN signal to settle before sampling it
to 10-bit precision by the external A/D converter. It is recommended to sample the VGN signal
during the frame blanking interval for best results.

The VGN readings are normalized and converted to a 10-bit full-scale word DVGNi[9,0] using
the following expression:

VGN i
DVGN i [9,0] =  1023
VGN MAX

where VGNMAX is VDD5/2. Each of these data values must be further multiplied by a correction
factor CFi to obtain the Gamma table coefficients as follows:

GCi [9,0] = DVGN i  CFi

where empirically determined values for factor CFi are given in Tables 10-3 and 10-4.

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The correction factors need to be adjusted depending on the luminance level in order to produce
the best response.

Table 10-3: Correction Factor values for L ~ 150 cd/m2

CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8

0.76 0.9 0.955 0.96 0.97 0.974 0.978 0.984

Table 10-4: Correction Factor values for L ~ 10 cd/m2

CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8

0.791 0.839 0.888 0.914 0.942 0.971 0.980 1

Using the derived values for GCi and their corresponding grayscale coordinates GLi, the 8-entry
Gamma Correction table consisting of data points Qi = (GLi, GCi) can be constructed. The
outcome of a typical gamma sensor measurement and calculation procedure is shown in Table
10-5, for a white luminance ~150 cd/m2.

Table 10-5: Sample Gamma Correction Table

i 1 2 3 4 5 6 7 8
IDSTEP[0] 0h 1h 2h 3h 4h 5h 6h 7h
VGNi (volt) 1.263 1.288 1.309 1.344 1.415 1.510 1.631 1.798
GCi (dec) 702 416 727 747 786 839 906 999
GLi (dec) 2 4 8 16 32 64 128 255

The full 256-word LUT is derived from the Gamma Coefficient Table using linear interpolation
to generate intermediate data points as illustrated in 7. The input to the LUT for each color of the
video source is represented by the 8-bit signal VIN[7,0], and the output of the LUT (which is
also the input to the microdisplay) is represented by the 10-bit signal DIN[9,0]. For example, the
Y coordinate for the intermediate point Q(x, y) on the line segment formed between the gamma
table points Q6 and Q7 is obtained by:

(X − X6)
Y = Y6 + (Y7 − Y6 ) 
(X7 − X6)

The intermediate points for other line segments are found in similar fashion. A software routine
in the system microcontroller is used to perform the necessary calculations before loading it into
the data-path LUTs in the microdisplay. A buffer LUT is used in the microdisplay to temporarily
store the data as it is transferred from the microcontroller via the serial port. When the buffer

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LUT is full, the data can be rapidly transferred to the data-path LUTs during a frame blanking
time to avoid disturbing the displayed image.

1000

Q7
GC7
Q
Y
800
Q6
GC6

600
DIN[9,0]

400

200

0
0 50 100 150 200 250
GL6 X GL7
VIN[7,0]

Figure 20 : Generating intermediate points by linear interpolation

A smooth transition of the gamma curve at the lowest gray levels is essential for best
performance of the display at the black end of the gray scale. Refer to Figure 21 for an
illustration of the recommended approach for calculating the gamma curve at low gray levels.
The LUT data points for gray levels 1 to 4 can all be generated by linear extrapolation from the
gamma points Q1 and Q2. The LUT data point for gray level 0 (also defined as Q0) is a fixed
value that is user-defined, and normally should be set to a very low value, e.g. 1, to ensure the
best black level. The value for Q0 is shown on the graphical interface screen supplied with the
SXGA-096 design reference kit for user convenience. It is not affected by the gamma sensor
signal and can only be changed manually by user input.

SXGA Auto LUT (color, IDRF=30, DIMCTL=64)

740

720
Q3
700

680 Q2
LUT Values

660
Q1
640
LUT data points for GL=1 and 3 are obtained by linear
extrapolation between gamma points Q1 and Q2.
620
LUT data point for GL=0 is set to 1.
600

580
0 1 2 3 4 5 6 7 8 9 10
GL

Figure 21 : Gamma curve at low gray levels

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Figure 22 and Figure 23 show a typical gray scale response for a Gamma = 1 at different
luminance values (150 cd/m2 and 5 cd/m2)

Figure 22: Typical Luminance Gamma Response

Figure 23: Low Luminance Gamma Response

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An arbitrary optical response function for the microdisplay can be obtained by performing an
additional operation on the gamma coefficients before generating the gamma correction curve as
described previously. For example, the relationship between the output luminance of the display
(y) and the gray level input to the LUT (x) can be defined in terms of the system gamma () by
the following expression:

y = x

The corresponding gamma coefficients are then given by the following expression:


  VGN i 
GCi =   CFi   1023
 VGN MAX 

For the case of a linear optical response (=1) this expression reduces to the simpler form given
previously. Examples of gamma curves generated from the same VGN values for different
settings of the System Gamma parameter are shown in Figure 24 and the corresponding system
response curves for the display are given in Figure 25.

The System Gamma function is implemented in DRK Firmware and is accessible to the user in
the DRK GUI Software .

Gamma Curves for Various System Gamma

1000

System Gamma = 1
900

1.6
800
2
LUT Output

700

600

500

400
0 50 100 150 200 250
Gray Level Input

Figure 24 : Gamma curves for arbitrary System Gamma

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System Response for Various System Gamma

0.9

0.8

0.7
Normalized Luminance

0.6
System Gamma = 1
0.5
1.6
0.4
2
0.3

0.2

0.1

0
0 50 100 150 200 250
Gray Level Input

Figure 25 : Display system response for arbitrary system gamma

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10.5 DC-DC Converter

An on-chip dc to dc converter controller allows for the generation of the OLED cathode supply,
relying on a few external passive components assembled on the display carrier board. The
converter is an adjustable inverter that converts VDD5 to a negative supply used to bias the
OLED via the VCOM input pin. Adjustment is managed by the control logic and registers
VCOM[7,0], VCOMCTL[7,0] and VCOMMODE[3,0].

The converter adjustment comes from two sources:

- A nominal value set in a dedicated register that provides for the room temperature voltage
level.
- The output of an internal VCOM sensor circuit. This feature can be enabled/disabled via
register setting to allow full external control (via register VCOM).

A block level schematic of the Cuk converter that is employed in the SXGA-096 application is
shown in Figure 26.

VDDA(5V) 10uH 0.1uF 10uH

4.7uF
d1n581
8
Isen_en<0>
Mux

Driver
Freq_cnt S Q DRV
CLK Gen R
Duty_cnt
Isen_en<1>

ISEN
Mux VREF3 Rsens (0.25Ω )
MODE
(0.2V)

Automatic Loop Manual Loop

VGMAX
VCOM 0 to -6V
IDMAX SS Sensor
VREF

FB

VCOM_SEN
Soft start 22uF
2

VFB

Manual Setting[7:0] from I2C Registers

VREF1
REF Gen

Figure 26 : Schematic of DC-DC controller function

Three modes of operation, selected via register VCOMMODE, are provided for the controller function.
Mode 1, selected by default (VCOMMODE=0), activates the Automatic Loop which provides VCOM
regulation based on an internal current feedback sensor. In this mode the cathode supply is automatically

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regulated in order to maintain a constant maximum OLED array current over changes in temperature and
luminance. The cathode voltage will tend to rise in absolute value as the luminance level is increased or
the operating temperature is reduced.

Mode 2, selected by setting VCOMMODE=1h, is a hybrid control mode that prevents the absolute value
of the cathode supply from becoming too small at higher temperatures, but allows it to increase at low
temperatures where it is needed to ensure a stable regulated OLED current. Both the AUTO and
MANUAL control loops are running simultaneously in this mode with one taking charge above a user
defined threshold (set by register VCOM) and the other below that threshold. For relatively low
temperatures and high luminance levels the AUTO mode will be in control and the cathode supply will
follow the trajectory shown in Figure 27. If operating conditions try to force the absolute value of the
cathode supply to drop below the threshold, then the control switches to MANUAL mode and the
regulated supply remains fixed at the VCOM level.

VCOM Supply in Mode 2

-6

-5
High Brightness

-4
VCOM (V)

Low Brightness
-3
Threshold

-2

-1

0
-80 -60 -40 -20 0 20 40 60 80 100
Temperature o C

Figure 27 : VCOM supply characteristic in Mode 2

Mode 3, selected by setting VCOMMODE=2h, activates the Manual Loop which provides a fixed
cathode supply based on a cathode voltage feedback signal. The actual value of the cathode voltage is
controlled over a range of 0 to -6V by setting register VCOM. Its default value is about -2.3V. In this
mode the dimming and luminance regulation functions via IDRF and DIMCTL are not operational.
Luminance is controlled directly via the VCOM register setting in this mode instead.

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10.6 Serial Interface

The serial interface consists of a serial controller and registers. The serial controller follows the I2C
protocol. An internal address decoder transfers the content of the data into appropriate registers. The
protocol will follow the address byte followed by register address data byte and register data byte
sequence (3 bytes for each register access):
Serial address with write command
Register address
Register data

The registers are designed to be read/write. Read mode is accomplished via a 4 byte sequence:
Serial address with write command
Register address
Serial address with read command
Register data

RANDOM REGISTER WRITE PROCEDURE

S 0 1 0 0 1 1 x W A A A P
7 bit address register address data
Acknowledge Acknowledge STOP condition
START condition WRITE command Acknowledge

RANDOM REGISTER READ PROCEDURE

S 0 1 0 0 1 1 x W A A S 0 1 0 0 1 1x R A A P
7 bit address register address 7 bit address data
Acknowledge Acknowledge Acknowledge
START condition WRITE command READ condition

NO Acknowledge
STOP condition

The serial controller is capable of slave mode only.

The x in the 7-bit address code is set by the SERADD input pin and is provided to allow a dual display
and single controller configuration.
Slave Address: 010011X where X = 0 or 1 depending on the status of the SERADD pin. This is
summarized in Table 10-5.
Write Mode: Address is 4C (or 4E if SERADD = 1)
Read Mode: Address is 4D (or 4F is SERADD =1)

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Sequential Read/Write Operation

The serial controller allows for both sequential and read operational modes. For either mode, the host
needs only set the initial register address followed by as many data bytes as needed, taking care not to
issue a STOP condition until all desired data bytes have been transmitted (or received).

It is possible to run the I2C interface without source clock or any sync signals.

Interface maximum frequency: 400 KHz.

Table 10-6 : I2C Address Summary

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Address (Hex)
SA R/W
Write 0 1 0 0 1 1 0 0 4C
Read 0 1 0 0 1 1 0 1 4D
Write 0 1 0 0 1 1 1 0 4E
Read 0 1 0 0 1 1 1 1 4F

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10.7 Power-On Sequence

To ensure proper startup and stabilization of the display the following power-on sequence is
recommended:

1. Turn on VDD1.8, VDD5 and VPG supplies (these can be simultaneous)

2. A ramp-up time of 0.2 to 20ms for VDD5 and VDD1.8 is recommended for best performance
3. The ramp-up time for VPG is not critical and it can be turned on anytime
4. Configure the display registers to the desired startup state
5. Turn on the display by setting the DISPOFF bit in register DISPMODE to “0”

Figure 28 shows the timing diagram for the power supplies and control signals during startup when the
display is first turned on. The external supply voltages (VDD5, VDD1.8, and VPG) can all be applied at
the same time as in the diagram. An internal power-on-reset signal is triggered when both the VDD5 and
VDD1.8 voltages exceed a built-in threshold level. After a delay of about 70ms the internal dc-dc
controller is activated which generates a negative supply for the common cathode of the array. The video
display is enabled 20ms later and video is displayed on the array after the DISPOFF bit has been set to
“0” via the serial port. Prior to this moment the pixels in the array are actively driven to the black state.
The pin RESETB must also be logic high before any registers can be written.

VDD1.8

VDD5 (logic)

VDD5 (array)

VCOMMON

VSYNC

DATA Black Level Video Data

Figure 28 : Power-Up sequence for supplies and control.

During the power down operation, the supply rails should be switched off in the reverse order to the
power up sequence. When the POR function detects a drop in the VDD1.8 supply below a minimum
operating threshold it will immediately switch off the Row and Column sequencing circuits. At the same
time the VCOMMON supply will be turned off followed by the 5V array supply. The power-down
sequence is illustrated in Figure 29.

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VDD1.8

VDD5 (logic)

VDD5 (array)

VCOMMON

VSYNC

Figure 29 : Power-Down sequence for supplies and control.

10.7.1 Display Off Function

On power-up the microdisplay sets all internal registers to their default values and holds the array in the
black state until the DISPOFF bit (bit 7) in register DISPMODE is set to 0. The DISPOFF bit, when set to
1, will force all pixels to the off (black) state.
.

10.8 Power Savings Modes

The circuit shall provide power down modes to minimize power consumption. This can occur in two
ways:

• Sleep mode – manually controlled via the PDWN bit in register SYSPWRDN, the entire display
chip is powered down except for the serial interface. The register settings are saved and restored
on power up from this mode.
• Individual block control - many functional blocks have the option to be turned off individually
via control of registers ANGPWRDN and SYSPWRDN.

10.9 Built-In Test Patterns

The IC includes functionality to simplify the external hardware requirements for test of OLED
microdisplays and applications. The display is self-powered for this mode with no external video, sync, or
clock signals required. The display starts in this mode with a simple, flat white field at maximum
luminance by default and without the need for register setting.

The BI mode is activated at start-up when a dedicated pin TMODE is set to logic level 1 or PATTEN bit
in register TPMODE is set high. The internal dc-dc converter oscillator is used to generate the basic
timing sequence (VSYNC, HSYNC, and SCLK). The vertical frequency will be set to 60Hz.

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By default an all-pixels-on pattern will be displayed. The following extra test patterns are included and
are accessed via the serial interface:

• 16 level gray scale, checkerboard, alternating rows and columns, cross-hatch line pattern

Figure 30 illustrates the application setup for the chip in BI mode using the built-in test functionality.

VAN VDD VCOM VPG AGND GND

SDA
SCL Serial Interface
SERADD

REXT Self-Test Generator

Hsync
Ring
Timing Logic Vsync
Osc.
CLK

Pattern
4b DAC RGB Data
Generator

Figure 30 : Block diagram of setup for BI mode

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11. REGISTER MAP SUMMARY

I2C Slave Address : 0100 11x
Reset
Address
Name Access Bit Name Bit # Value Description
(Hex)
(Hex)
00 STAT R REV 2-0 0 Silicon Revision Number
I2C Register Write Disable
WRDISABLE 7 0
0 = Write Enable, 1 = Write Protected (Read Only)
Reserved 6 0 Do Not Change
DVGA video input mode enable
DVGA 5 0
0 = SXGA video mode, 1 = DVGA video mode
ENABLE Active Level
SET_ENABLE 4 0
0 = ENABLE active low, 1 = ENABLE active high
01 VINMODE R/W FIELD Polarity
SET_FIELD 3 0
0 = Odd Field when ENABLE=Active, 1 = Even Field when ENABLE=Active
Auto HSYNC/VSYNC polarity detection enable (Detected polarity overrid
AUTOSYNC 2 1 VSYNCPOL/HSYNCPOL)
0 = Disable , 1 = Enable
VSYNC Polarity
VSYNCPOL 1 1
0 = Negative Sync, 1 = Positive Sync
HSYNC Polarity
HSYNCPOL 0 1
0 = Negative Sync, 1 = Positive Sync
Display Off (BURNIN mode override to ON)
DISPOFF 7 1
0 = Display On, 1 = Display Off
Mono display mode
MONO 6 0 0 = Color display mode, 1 = Mono display mode (Green video input data used as
mono video)
Internal Gamma LUT Enable (BURNIN mode override to Bypass Internal Gamma)
GAMMA_EN 5 1
0 = Bypass Internal Gamma LUT, 1 = use Internal Gamma LUT
02 DISPMODE R/W 3D Display Mode
3D-MODE 4 0
0 = Normal Display, 1 = Time Sequential Mode
Progressive or Interlaced scan mode select
SCMODE 3-2 0
00 = Progressive, 01 = Interlaced, 1X = Pseudo Interaced
Vertical Scan Direction
VSCAN 1 0
0 = Top to Bottom Scan, 1 = Bottom to Top Scan
Horizontal Scan Direction
HSCAN 0 0
0 = Left to Right Scan, 1 = Right to Left Scan
03 LFTPOS R/W 7-0 06 Column Display Left Position
04 RGTPOS R/W 7-0 06 Column Display Right Position
05 TOPPOS R/W 7-0 06 Row Display Top Position
06 BOTPOS R/W 7-0 06 Row Display Bottom Position
07 7-0 Row Duty Control
0
ROWRESET R/W 9-8 0:Disable, Each line displayed ROWRESET*2 Line period
08
12 0 ROWRESET work on UNENABLED frame in 3D mode
RAMPMON 5 0 Internal Ramp Buffer Monitor Enable
Reserved 4 0 Do Not Change
Internal Ramp DAC set All High
RAMPHIGH 3 0
0 = Normal operation, 1 = DAC set All High
09 RAMPCTL R/W
Ramp Fly back Time
FLYBTIME 2 0
0 = 800 nSec, 1 = 500 nSec
Ramp Delay by DCLK
RAMPDLY 1-0 1
00 = -1/2 DCLK, 01 = No Delay, 10 = +1/2 DCLK
Ramp Buffer Current Control
( 0000 = -75%(Don't use), 0001 = -75%, 0010 = -50%,0 011 = -25%,
RAMPBCM 7-4 4
0100 = ±0%, 0101 = +25%, 0110 = +50%, 0111 = +75%,... ), 25% increase for each
step
Ramp Amp Current Control
( 0000 = -75%(Don't use), 0001 = -75%, 0010 = -50%, 0011 = -25%,
RAMPACM 3-0 4
0100 = ±0%, 0101 = +25%, 0110 = +50%, 0111 = +75%,... ), 25% increase for each
step
0B VDACMX R/W 7-0 80 Ramp DAC Max Value Control, -40% ~ +40 %
EXT_VREF 3 0 External VREF Enable
0C BIASN R/W 000 = bias current off
BIASN 2-0 1
001~111 = bias current set to 0.5nA, 1nA, 1.5nA, 2nA, 2.5nA, 3.0 nA, 3.5 nA
VCOM PUMP hold enable when VGN sampling time
PMPHOLD_EN 4 0
0 = Normal pumping, 1 = Pump hold function enable
0D GAMMASET R/W VGN Sample & Hold Enable
VGNSH_EN 3 0
0 = VGN SH Bypass, 1 = Enable VGN SH output
IDSTEP 2-0 0 Current level for gamma sensor
ISEN_EN 3-2 1 VCOM I-Sensor Enable
00 = AUTO1 mode
0E VCOMMODE R/W
VCOMAUTO 1-0 0 01 = AUTO2 mode
10 = MANUAL mode

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VCOM Soft Start Bypass mode
SS_BYPASS 7 0
0 = Soft Start function enable, 1 = Soft Start Bypass
VCOM Clock Duty Control (High:Low)
VCKDUTY 6-4 3
0=1:7, 1=1:3, 2=3:5, 3=1:1, 4=5:3, 5=3:1, 6=7:1, 7=Don't use
0F VCOMCTL R/W
VCOM Clock Select
VCKSEL 3-2 3
0=125KHz, 1=250KHz, 2=500KHz, 3=800KHz
VCOM Soft Start Delay Time Mode
VCOMSS 1-0 1
0 = 2mS, 1 = 4mS, 2 = 8mS, 3 = 16mS
10 VGMAX R/W 7-0 0D Fine adjustment for VGMAX level (default = 4.95V)
11 VCOM R/W 7-0 51 VCOM manual setting (used when VCOMMODE = 01 or 10 , default = -2.3V)
IDRF_COARSE 7-5 0 Coarse adjustment for array reference current
12 IDRF R/W
IDRF_FINE 4-0 0 Fine adjustment for array reference current
13 DIMCTL R/W 6-0 01 Dimming level control (default = 1X IDRF)
14 TREFDIV R/W 5-0 17 Temp. Sensor Reference Clock Divider
15 TEMPOFF R/W 7-0 3A Temp. Sensor Offset
Number of frames per TEMPOUT update (Data range 02H ~ FFH)
16 TUPDATE R/W 7-0 FF Update Time = (TUPDATE+1) * PERIODFRAME
PERIODFRAME = 16.6 mSec when using 60Hz Video
17 TEMPOUT RO 7-0 - Temperature Sensor Readout
ISENPD 7 0 ISEN Power Down
IDMAXPD 6 0 IDMAX Power Down
VCOMPD 5 0 VCOM Power Down
VREFPD 4 0 VREF Power Down
18 ANGPWRDN R/W
GMSENPD 3 0 Gamma Sensor Power Down
VCSENPD 2 0 VCOM Sensor Power Down
TSENPD 1 0 Temperature Sensor Power Down
TREFPD 0 0 Temperature Reference Power Down
All System Power Down (Override all analog power down, except LDOPD, POR50VPD,
PDWN 7 0
POR18VPD)
LVDSPD 6 0 LVDS receiver Power Down
LDOPD 5 0 1.8V LDO Power Down
19 SYSPWRDN R/W RBUFPD 4 0 RAMP Buffer Power Down
RAMPPD 3 0 RAMP DAC AMP Power Down
DACPD 2 0 RAMP DAC Power Down
POR50VPD 1 0 5V POR Power Down
POR18VPD 0 0 1.8V POR Power Down
Enable external clock for Burn-in test mode (0=use internal ring OSC, 1=use external
TPVCLK 4 0
LVDS clock)
PATTEN 3 0 Test Pattern Display Enable when "1"
1A TPMODE R/W Select test pattern for Built-In-Test-Mode (BURNIN pin = 'High' or PATTEN = 1)
000= Burn-in (all white), 001=Color Bar, 010=16 level gray scale
PATTSEL 2-0 0
011=Checker Board, 100=Vertical Line, 101= Horizontal Line, 110=Grid Pattern,
111=Color Screen
1B TPLINWTH R/W 7-0 0 Line Test Pattern Line Width (0=1pixel, 1=2pixel, …, 255=256pixel)
1C TPCOLSP R/W 7-0 0 Line Test Pattern Column Space (0=1pixel, 1=2pixel, …., 255=256pixel)
1D TPROWSP R/W 7-0 0 Line Test Pattern Row Spce (0=1pixel, 1=2pixel, …, 255=256pixel)
When PATTSEL=1,2 :Bit7-Bit0 :Don't care
When PATTSEL=3,4,5,6 :Bit6-Bit4 :Line Test Pattern Background Color (RGB)
1E TPCOLOR R/W 7-0 0
Bit2-Bit0 :Line Test Pattern Background Color (RGB)
When PATTSEL=7, All 8 bits used 256 gray level
Select LVDS Skew Align reference Clock delay
SKWDLY 7-4 0
0 = no delay, 1 = one unit delay, …. ,15 = 15 unit delay
1F DLYSEL R/W
Select clock delay for serial data latch
CLKDLY 3-0 1
0 = no delay, 1 = one unit delay, …. ,15 = 15 unit delay
LVDS Align mode
ALNMOD 2 0
0 = normal Operation, 1 = auto align mode
20 LVDSCTL R/W LVDS Skew mode
SKEWMOD 1-0 0 0 = normal Operation, 1 = auto skew,
2 = manual skew one set for all (use SKEW0), 3 = manual skew separate setting
21 7-0 LVDS data line #0 skew setting (when SKEWMOD=2, SKEW0 override others)
SKEW0 R/W 0
22 15-8 0000h = no delay, 0001 = 1 unit delay, …. FFFFh = 15 unit delay
23 7-0 LVDS data line #1 skew setting
SKEW1 R/W 0
24 15-8 0000h = no delay, 0001 = 1 unit delay, …. FFFFh = 15 unit delay
25 7-0 LVDS data line #2 skew setting
SKEW2 R/W 0
26 15-8 0000h = no delay, 0001 = 1 unit delay, …. FFFFh = 15 unit delay
27 7-0 LVDS data line #3 skew setting
SKEW3 R/W 0
28 15-8 0000h = no delay, 0001 = 1 unit delay, …. FFFFh = 15 unit delay
MSB of SKEW3~SKEW0 read out
29 SKFAST R SKFAST 3-0 -
All "0" = OK, Not all "0" = Error (need increase SKWDLY)
LSB of SKEW3~SKEW0 read out
2A SKSLOW R SKSLOW 3-0 -
All "1" = OK, Not all "1" = Error (need decrease SKWDLY)
define ENABLE/VS pin function
DEFEN 2-1 1
00=not used (all embeded), 01=used as ENABLE, 10=used as VSYNC
2B SYNCMOD R/W
define HS/ALIGN pin function
DEFHS 0 0
0 = use as ALIGN function only, 1 = used as HSYNC and ALIGN function

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2C LUT_ADDR R/W 7-0 0 Gamma Look-Up Table template access Address
2D LUT_DATAL 7-0 0 Gamma Look-Up Table template R/W Data LSB (Auto LUT_ADDR increase)
LUT_DATA R/W
2E LUT_DATAH 9-8 0 Gamma Look-Up Table template R/W Data MSB
UDGAMMA 3 0 Update LUT template ro R,G,B Gamma LUT enable (Auto cleared after update)
2F LUT_UPDATE R/W
UDRGB 2-0 7 Select R,G,B Gamma LUT to update ( ex. 100=R Gamma Update)
30 7-0
Reserved R - Test Purpose
31 10-8
32 7-0
Reserved R - Test Purpose
33 10-8
34 Reserved R/W 7-0 99 Do Not Change
35 Reserved R/W 7-0 99 Do Not Change
36 Reserved R/W 3-0 0 Do Not Change
37 Reserved R/W 6-0 0 Do Not Change
38 Reserved R/W 7-0 0 Do Not Change
39 Reserved R/W 7-0 0 Do Not Change
3A Reserved R/W 7-0 FF Do Not Change
3B Reserved R/W 7-0 0 Do Not Change
3C Reserved R/W 4-0 0 Do Not Change
3D Reserved R/W 2-0 3 Do Not Change
40 Reserved R/W 6-0 0 Do Not Change
41 Reserved R/W 7-0 30 Do Not Change
42 Reserved R/W 6-0 64 Do Not Change

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12. DETAILED REGISTER DESCRIPTIONS

12.1 STAT (00h)

Name STAT
Address 00h
Mode Read Only

Bit Name Bit# Reset Description

Value
REV 2-0 0 Silicon revision number; Rev. 1 = 0

Bits REV in this register indicate the revision number of the silicon backplane design, with 0
corresponding to the first silicon known as Rev. 1.

12.2 VINMODE (01h)

Name VINMODE
Address 01h
Mode Read / Write

Bit Name Bit# Reset Description

Value
WRDISABLE 7 0 I2C register write disable
Reserved 6 0 Do Not Change
DVGA 5 0 VGA Video Input Mode Enable
SET_ENABLE 4 0 ENABLE active level
SET_FIELD 3 0 Field polarity
AUTOSYNC 2 1 Automatic VSYNC/HSYNC Polarity Detection Enable
VSYNCPOL 1 1 VSYNC polarity
HYSYNCPOL 0 1 HSYNC polarity

WRDISABLE:

1 = write protected (all other registers become read only)

0 = write enable (all registers can be updated externally via I2C) (default)

DVGA:

0 = SXGA video mode ( default)

1 = Double VGA video mode

When the video source is the VGA resolution, the SXGA-096 makes the pixel data double internally and
display it in 1280 x 960 pixel area with this register enable.

SET_ENABLE:

0 = the active state of the ENABLE input is set “low” (default)

1 = the active state of the ENABLE input is set “high”

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The ENABLE input pin is used to implement 3D video modes using a single RGB source, with two
consecutive frames carrying information for each eye. The microdisplay can be programmed for either an
active high or low ENABLE input using the SET_ENABLE bit, allowing a single video signal to be used
with two displays. In such a configuration, one display scans and displays, while the other one holds and
displays. The active state of the ENABLE input corresponds to the video data being scanned and
displayed by the microdisplay.

To implement the Frame Sequential 3D Mode according to the VESA Standard for Stereoscopic Display
Hardware, the display for the left eye is programmed with SET_ENABLE=1 and the right eye display is
programmed with SET_ENABLE=0. Consequently, the data for the left eye is supplied and displayed
when ENABLE=1 while the display for the right eye displays the previous frame of data.

The ENABLE input pin is also used to indicate field polarity in non-3D interlaced modes. In this mode
the SET_FIELD bit determines the field polarity when ENABLE is active.

SET_FIELD:

0 = Odd Field when ENABLE=Active (default)

1 = Even Field when ENABLE=Active

The SET_FIELD register determines the field polarity of the video signal when the ENABLE pin is
active.

AUTOSYNC:

0 = Auto Sync detection mode OFF

1 = Auto Sync detection mode ON (default)

VSYNCPOL and HSYNCPOL are overridden by detected sync polarity when AUTOSUNC = 1.

VSYNCPOL:

0 = Negative Sync
1 = Positive Sync (default)

HSYNCPOL:

0 = Negative Sync
1 = Positive Sync (default)

The SYNCPOL registers are used to determine whether the positive or negative edge of the external
synchronization clocks (HSYNC and VSYNC) is used as the active transition by the internal display
sequencers and control logic.

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12.3 DISPMODE (02h)

Name DISPMODE
Address 02h
Mode Read / Write

Bit Name Bit# Reset Description

Value
DISPOFF 7 1 Display On/Off control
MONO 6 0 Mono display mode selection
GAMMA_EN 5 1 Internal Gama LUT enable
3D-MODE 4 0 3D Mode control
SCMODE 3-2 0 Progressive or Interlaced scan mode selection
VSCAN 1 0 Vertical Scan direction
HSCAN 0 0 Horizontal Scan direction

DISPOFF:

0 = Display is turned ON
1 = Display is turned OFF (default)

The display starts in the OFF state by default and requires a command via the serial port to be turned on.

MONO:

0 = Color display mode (default)

1 = Mono display mode

The MONO is used to set monochrome display mode. When MONO = 1, the SXGA-096 only accept the
input data from LVDS channel 1 and 2. Other channels (channel 0, 3) are goes to power down mode.

GAMMA_EN:

0 = Bypass Internal Gamma LUT

1 = Use internal Gamma LUT (default)

3D-MODE:

0 = Normal display mode (default)

1 = Time Sequential 3D mode

These bits are used to set the 3D mode of operation in conjunction with SET_ENABLE (bit #3 of the
VINMODE register) and the Enable input. In Frame Sequential Mode each video frame contains
information for either the left or right eye. When 3D-MODE=”1” the SCMODE bit in the DISPMODE
register is overridden to Progressive Scan Mode (0h). The following description for Frame Sequential
operation assumes the source is in compliance with the VESA standard, where the data for the left eye is
provided while the Enable signal is at the logic high level, and the data for the right eye display is
provided while the Enable signal is at the logic low level. The Enable input signal is sampled into the
circuit by a flip-flop clocked on the falling edge of VSYNC and the sampled value is used for the next

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frame. (The Enable signal is generated by the graphics software and may not be synchronized to the
VSYNC signal).

To activate the stereovision mode, the right eye display needs to be configured with Enable active low
(SET_ENABLE= “0”, bit #3 of the VINMODE register). This will allow the right eye microdisplay to
hold the previous frame while the Enable input is high. The left eye display needs to be configured with
Enable active high (SET_ENABLE=”1”, bit #3 of the VINMODE register). Thus the two Enable inputs
can be tied together to the incoming Stereo Sync signal provided by the graphics adapter (or other custom
source).

SCMODE:

00 = Progressive scan mode (default)

01 = Interlaced scan mode
1X = Pseudo-interlaced mode

Interlaced modes are limited to a maximum of 518 and a minimum of 263 active rows per field.

VSCAN:

0 = Top to Bottom vertical scan direction (default)

1 = Bottom to Top vertical scan direction

HSCAN:

0 = Left to Right horizontal scan direction (default)

1 = Right to Left horizontal scan direction

12.4 LFTPOS (03h)

Name LFTPOS
Address 03h
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 06 Left position of first active column

This register, along with register RGTPOS, is used to set the horizontal position of the active display
window within the 1292 available columns of pixels. In SXGA mode the active window can be moved by
+/-6 pixels from the center (default) position. When LFTPOS is increased, register RGTPOS must be
decreased by the same value so that the sum of the two remains equal.

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12.5 RGTPOS (04h)

Name RGTPOS
Address 04h
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 06 Right position of last active column

This register, along with register LFTPOS, is used to set the horizontal position of the active display
window within the 1292 available columns of pixels. In SXGA mode the active window can be moved by
+/-6 pixels from the center (default) position. When RGTPOS is increased, register LFTPOS must be
decreased by the same value so that the sum of the two remains equal.

12.6 TOPPOS (05h)

Name TOPPOS
Address 05h
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 06 Top position of first active row

This register, along with register BOTPOS, is used to set the vertical position of the active display
window within the 1036 available rows of pixels. In SXGA mode the active window can be moved by +/-
6 pixels from the center (default) position. When TOPPOS is increased, register BOTPOS must be
decreased by the same value so that the sum of the two remains equal.

12.7 BOTPOS (06h)

Name BOTPOS
Address 06h
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 06 Bottom position of last active row

This register, along with register TOPPOS, is used to set the vertical position of the active display
window within the 1036 available rows of pixels. In SXGA mode the active window can be moved by +/-
6 pixels from the center (default) position. When BOTPOS is increased, register TOPPOS must be
decreased by the same value so that the sum of the two remains equal.

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12.8 ROWRESET (07h, 08h)

Name ROWRESET
Address 07h, 08h
Mode Read / Write

Bit Name Bit# Reset Description

Value
ROWRESETL 7-0 0 Row duty rate control (LSB)
(07h)
ROWRESETH 1-0 0 Row duty rate control (MSB)
(08h) 4 0 ROWRESET work on UNENABLED frame in 3D
mode

ROWRESETH:BIT4

0 = Active duty rate can be set 0 ~ 50%, 100% when 3D mode

1 = Active duty rate can be set 50 ~ 100% when 3D mode

This register is used to set the number of line cycles (in steps of 2) during which each row is
active in any frame period. Each row is driven to black during the non-active line cycles.

ROWRESET (dec) Active Line Cycles Active Duty Rate (%) Note
0 all 100 Pixels active for entire frame period
1 2 2*THSYNC/TFRAME 1054 total HS cycles / frame (SXGA/60Hz)
n 2*n 2*n*THSYNC/TFRAME
>527 all 100 Pixels active for entire frame period

12.9 RAMPCTL (09h)

Name RAMPCTL
Address 09h
Mode Read / Write

Bit Name Bit# Reset Description

Value
RAMPMON 5 0 Internal RAMP Amp monitor enable
4 0 Reserved (Do Not Change)
RAMPHIGH 3 0 Set internal RAMP DAC high
FLYBTIME 2 0 RAMP Flyback time
RAMPDLY 1-0 1 RAMP delay in DCLK cycles

RAMPMON:

0 = Disable internal RAMP Buffer monitoring (default)

1 = Enable internal RAMP Buffer monitoring

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The RAMPMON register is used to enable monitoring of the internal RAMP buffer output signal.

RAMPHIGH:

0 = Normal operation (default)

1 = DAC set to all high output

The RAMPHIGH register is used to set internal RAMPDAC to all high output mode for test purposes.

FLYBTIME:

0 = 500 ns (default)
1 = 150 ns

The FLYBTIME register is used to set the fly-back (return to 0) time for the internal RAMP.

RAMPDLY:

00 = - ½ DLCK
01 = no delay (default)
10 = + ½ DCLK

The RAMPDLY2 register is used to adjust the starting position of the internal RAMP.

12.10 RAMPCM (0Ah)

Name RAMPCM
Address 0Ah
Mode Read / Write

Bit Name Bit# Reset Description

Value
RAMPBCM 7-4 4 RAMP Buffer current control
RAMPACM 3-0 4 RAMP Amp current control

RAMPBCM:

0000 = -100% (power down)

0001 = -75%
0010 = -50%
0011 = -25%
0100 = nominal (default)
0101 = +25%
0110 = +50%
0111 = +75%
…

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The RAMPBCM register is used to set the operating bias current for the internal RAMP buffer. The
settings reduce or increase the current by 25 % of the nominal (default) value.

RAMPACM:

0000 = -100% (power down)

0001 = -75%
0010 = -50%
0011 = -25%
0100 = nominal (default)
0101 = +25%
0110 = +50%
0111 = +75%
….

The RAMPACM register is used to set the operating bias current for the internal RAMP amplifier. The
settings reduce or increase the current by 25% percentage of the nominal (default) value.

12.11 VDACMX (0Bh)

Name VDACMX
Address 0Bh
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 80 RAMP DAC maximum value control

Register VDACMX is used to adjust the maximum value of the internal RAMP DAC signal by -40% to
+40% of the nominal value.
NOTE: The normal operating value for VDACMX should be set to 80h.

The typical dependence of display luminance on VDACMX(dec) is shown in Figure 22. The luminance is
seen to saturate for VDACMX greater than about 7Ah in this sample. For normal operation VDACMX
should be set to about 90 to 95% of the saturation value as shown in the figure.

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Figure 31: Luminance dependency on VDACMX

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12.12 BIASN (0Ch)

Name BIASN
Address 0Ch
Mode Read / Write

Bit Name Bit# Reset Description

Value
EXT_VREF 3 0 Enable external VREF
BIASN 2-0 1 Set pixel bias current

EXT_VREF:

1 = enable the external VREF source

0 = use the internal VREF source (default)

Note: This option not available on the current package – use the default setting only.

BIASN:

000 = pixel bias current is turned off

111 = pixel bias current set to maximum

The BIASN register is used to set the sink current applied in each pixel cell. It is recommended to use the
BIASN=03 setting in normal operation.

12.13 GAMMASET (0Dh)

Name GAMMASET
Address 0Dh
Mode Read / Write

Bit Name Bit# Reset Description

Value
PMPHOLD_EN 4 0 VCOM pump hold enable
VGNSH_EN 3 0 VGN sample & hold enable
IDSTEP 2-0 0 Current level for gamma sensor

PMPHOLD_EN:

0 = Normal operation, pump hold disabled (default)

1 = Enable pump hold during VGN sampling time

The PMPHOLD_EN register is used to disable the VCOM converter switch during the VGN sampling
time to reduce noise pickup.

VGNSH_EN:

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0 = Bypass the VGN sample & hold function (default)

1 = Enable the VGN sample & hold function

The VGNSH_EN register is used to activate the internal sample & hold function provided at the VGN
output pin.

IDSTEP:

0h  IDRF/128
1h  IDRF/64
2h  IDRF/32
3h  IDRF/16
4h  IDRF/8
5h  IDRF/4
6h  IDRF/2
7h = IDRF

The IDSTEP register is used to set the current level for the gamma sensor. The corresponding output
voltage is provided at pin VGN.

A minimum of 10msec following an IDSTEP register update should be allowed for the VGN signal to
settle before sampling. In addition, sampling of the VGN signal should be carried out during the Frame
Blanking time.

12.14 VCOMMODE (0Eh)

Name VCOMMODE
Address 0Eh
Mode Read / Write

Bit Name Bit# Reset Description

Value
ISEN_EN 3-2 1 Enable the VCOM current sensor
VCOMAUTO 1-0 0 Set internal VCOM supply mode

ISEN_EN:

00 = Turn off VCOM current sensor

01/11 = Turn on VCOM current sense function

When the ISEN_EN is turned on, the internal VCOM current sense function is enabled.
If it detects overcurrent in VCOM, the internal VCOM dc-dc converter stops the pumping signal(DRV) to
protect external components.

VCOMAUTO:

This register sets the operating mode of the internal VCOM dc-dc converter.

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00 = AUTO1 mode (default)

01 = AUTO2 mode
10 = MANUAL mode

In the AUTO1 mode, the VCOM converter uses an internal current reference to maintain a fixed OLED
current level, which is defined by registers DIMCTL and IDRF.
In the AUTO2 mode, the VCOM converter regulates the OLED current level when the VCOM supply is
below a set threshold (defined by the VCOM register), and clamps the output to the threshold level when
conditions call for a VCOM output above the threshold level.
In the Manual mode, the VCOM converter uses a voltage reference signal to maintain a fixed cathode
supply voltage. The value of the cathode voltage is set by register VCOM.

12.15 VCOMCTL (0Fh)

Name VCOMCTL
Address 0Fh
Mode Read / Write

Bit Name Bit# Reset Description

Value
SS_BYPASS 7 0 Bypass the VCOM soft start mode
VCKDUTY 6-4 3 VCOM clock duty control
VCKSEL 3-2 3 VCOM clock select
VCOMSS 1-0 1 VCOM soft start delay time

SS_BYPASS:

0 = Normal operation, soft-start function enabled (default)

1 = Disable the VCOM soft-start function

VCKDUTY:

0h = 1:7
1h = 1:3
2h = 3:5
3h = 1:1 (default)
4h = 5:3
5h = 3:1
6h = 7:1
7h = don’t use

Register VCKDUTY sets the VCOM clock duty ratio (high-low).

VCKSEL:

0h = 125 kHz
1h = 250 kHz
2h = 500 kHz

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3h = 150 kHz (default)

Register VCKSEL sets the operating frequency of the VCOM clock.

VCOMSS:

0h = 2 ms
1h = 4 ms (default)
2h = 8 ms
3h = 16 ms

Register VCMOSS sets the soft-start duration during startup of the VCOM converter.

12.16 VGMAX (10h)

Name VGMAX
Address 10h
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 0D Fine adjustment for VGMAX level

00h = 5 (VDD5 = 5V)

0Dh = 4.95 (default)
FFh = 4

VGMAX level = VDD5*(1 - 0.2*VGMAX(dec) / 255)

This register sets the pixel voltage at which the maximum OLED current is regulated. It should be slightly
below the VDD5 supply to prevent saturation of the video buffer amplifiers.

12.17 VCOM (11h)

Name VCOM
Address 11h
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 51 VCOM manual setting

Cathode supply as a function of VCOM setting:

VCOM(h) FF F0 E0 D0 C0 B0 A0 90 80 70 60 51* 40 30
Voltage - - - - - - - - - - - - - -
0.29 0.38 0.47 0.59 0.72 0.85 1.0 1.2 1.43 1.7 2.0 2.4 2.97 3.68

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*default value

Register VCOM[7,0] sets the fixed output level for the internal VCOM inverter when VCOMMODE =01
or 10. There is no compensation for the variation in OLED behavior with temperature in this mode of
operation. As a result, a setting at room temperature will not necessarily result in optimal contrast and the
same luminance at other temperatures. The default setting (51h) will result in a cathode supply ≈ -2.3V.
The typical dependency of luminance on the VCOM setting in manual mode is given in Figure 32 for a
color display.

SXGA Color Luminance with Manual VCOM Control (VCOMMODE=02)

1000
Luminance (cd/m2)

100

10

1
50 70 90 110 130 150 170 190 210 230 250
VCOM(dec)

Figure 32 : Typical luminance dependency on manual VCOM setting

12.18 IDRF (12h)

Name IDRF
Address 12h
Mode Read / Write

Bit Name Bit# Reset Description

Value
IDRF_COARSE 7-5 0 Coarse adjustment for array reference current
IDRF_FINE 4-0 0 Fine adjustment for array reference current

IDRF_COARSE:

IC#
0h = 0 (default)
1h = 0.5
2h = 1.5
3h = 2.5

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4h = 3.5

IDRF_FINE:

IF#
00h = 0 (default)
01h = 1/32
…
10h = 16/32
…
1Fh = 31/32

Register IDRF is used to set the maximum OLED current, which determines the luminance level for the
display. The luminance will be directly proportional to the IDRF factor (sum of IC# and IF#) and the
reference luminance LDEF given by the following expression:

LMAX = LDEF*(IC# + IF#) in cd/m2

where the luminance for a color display is LDEF ≈ 240cd/m2 at the recommended settings (see table
below).

IDRF (hex) LMAX / LDEF

0 0
10 0.5
20 0.5
30 1 (recommended)
40 1.5
50 2
60 2.5
70 3
80 3.5

12.19 DIMCTL (13h)

Name DIMCTL
Address 13h
Mode Read / Write

Bit Name Bit# Reset Description

Value
6-0 1 Dimming level control

00h = 0
01h = 1% of LMAX
…
64h = 100% of LMAX
…
7Fh = 127% of LMAX

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This register provides linear control of the display luminance level ranging from 0 to 127% in steps of
1%. The recommended value of 64h is equal to 100% of the luminance defined by register IDRF.

This register is only operational in Auto VCOM mode (VCOMMODE=00).

12.20 TREFDIV (14h)

Name TREFDIV
Address 14h
Mode Read / Write

Bit Name Bit# Reset Description

Value
5-0 17 Temperature sensor reference clock divider adjust

The register TREFDIV is used to adjust the slope of the temperature readout sensor, TEMPOUT, to
correspond to the desired operating range of the display. The default setting is intended to support a full
scale temperature range of -40 to 80oC, although the setting is best determined by a calibration
measurement of the display in its final assembly.

See the description for register TEMPOUT.

12.21 TEMPOFF (15h)

Name TEMPOFF
Address 15h
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 3A Temperature sensor offset adjust

The register TEMPOFF is used to adjust the offset of the temperature readout sensor, TEMPOUT, to
correspond to the desired operating range of the display. The default setting is intended to support a full
scale temperature range of -40 to 80oC, although the setting is best determined by a calibration
measurement of the display in its final assembly.

See the description for register TEMPOUT.

12.22 TUPDATE (16h)

Name TUPDATE
Address 16h
Mode Read / Write

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Bit Name Bit# Reset Description

Value
7-0 FF Number of frames per TEMPOUT update

This register sets the update rate of the Temperature Sensor reading, TEMPOUT. The time between
sensor updates is given by:

Update Time = (TUPDATE(decimal) + 1)*TFRAME

where the frame period TFRAME is equal to 16.6 ms for 60Hz video. The valid range for TUPDATE is 02h
to FFh.

12.23 TEMPOUT (17h)

Name TEMPOUT
Address 17h
Mode Read Only

Bit Name Bit# Reset Description

Value
7-0 - Temperature sensor readout

Register TEMPOUT provides an 8bit digital output that is linearly proportional to the chip temperature.
The VGA display temperature sensor is designed around a P-N junction. The output of the junction is
sampled by an internal current to voltage converter, digitized and stored into a dedicated 8-bit register
TEMPOUT. The sampling rate is controlled by configuration register TUPDATE (16H). By default the
temperature sensor is updated once every 255 frames. Two registers are used to set the sensor gain
(TREFDIV) and sensor offset (TEMPOFF). The temperature sensor can be powered down when not used
by setting TSENPD =1 in the PWRDN register.

The temperature sensor is intended to provide a full-scale reading over a temperature range defined by the
user. Assuming that the desired operating temperature range is defined by TMIN and TMAX, the expected
sensor response would be as follows:

TEMPOUT (dec) = A  temp + B

where temp is the chip temperature in degrees Celsius, and A and B are given by:

255
A=
TMAX − TMIN

− 255  TMIN
B=
TMAX − TMIN

The actual sensor response is determined by registers TREFDIV and TEMPOFF through the following
relationship:

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TEMPOUT(d ) = k1  TREFDIV(d )  temp + k2 + TEMPOFF(d )

The constants k1 and k2 are dependent on properties of the silicon and package assembly. For example,
the average register settings needed to achieve a working temperature range of -60ºC to +80ºC are given
by the following values for package A04-500463-01:

TREFDIV (d ) = 25
TEMPOFF (d ) = 93

Using these values will result in a variation in temperature reading from part to part due to manufacturing
tolerances. To get a reasonably good sensor performance it is usually enough to just find the optimum
value for TEMPOFF which requires only one measurement at room temperature. Increased accuracy can
be obtained for a specific part by performing the calibration measurements described below.

To find the optimum value for TREFDIV do the following:

• Place the display in a temperature controlled environment, e.g. an oven

• Set TREFDIV=25d=19h and TEMPOFF=0
• Set DISPMODE=20h (turn off the display)
• Read TEMPOFF at several ambient temperatures, e.g. 0ºC, 20ºC, 40ºC, 60ºC
• Take the slope to find the sensor response, AMEAS = dTEMPOUT(d)/dtemp
• The optimum value for TREFDIV is then given by

1.82
TREFDIV OPT = 25 
AMEAS

To find the optimum value for TEMPOFF do the following:

• Set TREFDIV=25d=19h (or the optimum value) and TEMPOFF=0

• Set DISPMODE=20h (turn off the display)
• Allow several minutes to stabilize and then read TEMPOUTAMB and the ambient temperature
TAMB
• The optimum value for TEMPOFF is then given by

TEMPOFFOPT = 1.82  TAMB + 109 − TEMPOUT AMB

With these settings, the microdisplay temperature can be found from the sensor reading through the
following relationship:

140
T (C ) =  TEMPOUT (d ) − 60
255

Temperatures below -60ºC will return a TEMPOUT reading of 0 and temperatures above +80ºC will
return a hexadecimal value of FF.

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12.24 ANGPWRDN (18h)

Name ANGPWRDN
Address 18h
Mode Read / Write

Bit Name Bit# Reset Description

Value
ISENPD 7 0 ISEN power down
IDMAXPD 6 0 IDMAX power down
VCOMPD 5 0 VCOM power down
VREFPD 4 0 VREF power down
GMSENPD 3 0 Gamma sensor power down
VCSENPD 2 0 VCOM sensor power down
TSENPD 1 0 Temperature sensor power down
TREFPD 0 0 Temperature reference power down

ISENPD:

1 = VCOM current limit sensor is powered down

0 = normal operation (default)

IDMAXPD:

1 = IDMAX function is powered down

0 = normal operation (default)

VCOMPD:

1 = VCOM generator is powered down

0 = normal operation (default)

VREFPD:

1 = the VREF reference source is powered down

0 = normal operation (default)

GMSENPD:

1 = the Gamma sensor is powered down

0 = normal operation (default)

VCSNEPD:

1 = the VCOM sensor is powered down

0 = normal operation (default)

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TSENPD:

1 = the Temperature Sensor is powered down

0 = the Temperature Sensor is operating normally (default)

TREFPD:

1 = the Temperature reference is powered down

0 = normal operation (default)

12.25 SYSPWRDN (19h)

Name SYSPWRDN
Address 19h
Mode Read / Write

Bit Name Bit# Reset Description

Value
PDWN 7 0 All systems power down
LVDSPD 6 0 LVDS receiver power down
LDOPD 5 0 1.8V LDO power down
RBUFPD 4 0 RAMP Buffer Power Down
RAMPPD 3 0 RAMP DAC amp and buffer power down
DACPD 2 0 RAMP DAC power down
POR50VPD 1 0 5V power-on-reset power down
POR18VPD 0 0 2.5V power-on-reset power down

PDWN:

1 = all systems are powered down

0 = normal operation (default)

By setting the PDWN bit with LDOPD bit to a “1” the chip enters a deep sleep mode in which all
functions including the I2C interface are powered down in order to minimize power consumption. The
data, sync and clock inputs should be inactive and held low to achieve the lowest power consumption. An
on-chip Address Detection circuit monitors the I2C input lines and resets the PDWN bit when it detects
the correct I2C address, restoring the display to operating mode.

All register settings are saved in the power down mode and the display will restart in its previous state
when normal operation is resumed.

LVDSPD:
1 = LVDS receiver is powered down
0 = normal operation (default)

LDOPD:
1 = 1.8V LDO is powered down
0 = 1.8V LDO is enabled (default)

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It is recommended not to use the internal 1.8V LDO, so the LDOPD bit should be set to “1” when
powering up the display.

RBUFPD:

1 = internal RAMP buffer is powered down

0 = normal operation (default)

RAMPPD:

1 = internal RAMP DAC amplifier is powered down

0 = normal operation (default)

DACPD:

1 = internal RAMP DAC is powered down (use when external RAMP option is enabled)
0 = internal RAMP DAC is operational (default)

The internal RAMP DAC generator may be power down if an external RAMP source is used.

POR50VPD:

1 = the 5V power-on-reset circuit is powered down

0 = normal operation (default)

POR18VPD:

1 = the 1.8V power-on-reset circuit is powered down

0 = normal operation (default)

12.26 TPMODE (1Ah)

Name TPMODE
Address 1Ah
Mode Read / Write

Bit Name Bit# Reset Description

Value
TPVCLK 4 0 Enable external clock in Burn-in mode
PATTEN 3 0 Enable test pattern display
PATTSEL 2-0 0 Select test pattern for Burn-In mode

TPVCLK:

0 = Internal ring oscillator is used for test pattern generation (default)

1 = Test pattern generator use the external clock which is LVDS clock

The BI pin is tied high or PATTEN register set to high to activate the Burn-In test mode which can be
used to check display functionality without the presence of external video data or clock signals. In this

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mode the display generates data, syncs and the pixel clock internally for several different video patterns.
The TPMODE register is used to select one of the built-in test patterns in Burn-In mode via the serial
interface.

000 = all white pattern (default)

001 = color bars
010 = gray scale (without gamma correction)
011 = checkerboard pattern
100 = alternating columns pattern
101 = alternating rows pattern
110 = grid pattern
101 = all black
111 = color screen based on TPCOLOR register value.

Use with registers TPLINWTH, TPCOLSP, TPROWSP and TPCOLOR to modify the patterns according
to Figure 33.

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Test Pattern PATTSEL TPLINWTH TPCOLSP TPROWSP TPCOLOR

Name (1BH:2-0) (1CH) (1DH) (1EH) (1FH)
(1FH:2-0) (1FH:6-4)
All White 000 X X X X X
Color Bar 001 X X X X X
Gray Scale 010 X X X X X
Checker 011 X X X 111 000
Board
Alternating 100 LW CS X 111 000
Column
Alternating 101 LW X RS 111 000
Row
Grid Pattern 110 LW CS RS 111 000
All Black 101 X X X 000 000
All White 101 X X X 111 111
All Red 101 X X X 100 100
All Green 101 X X X 010 010
All Blue 101 X X X 001 001
Color Screen 111 X X X 8 bit value applied to all 3
color
Figure 33 : Test Patterns

X: Don’t care, LW: Line Width (0~255), CS: Column Space (0~255), RS: Row Space (0~255)

12.27 TPLINWTH (1Bh)

Name TPLINWTH
Address 1Bh
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 0 Test pattern line width

This register is used to set the line width for the line-type test patterns.

0 = 1 pixel wide (default)

1 = 2 pixel wide
…
255 = 256 pixel wide

12.28 TPCOLSP (1Ch)

Name TPCOLSP
Address 1Ch
Mode Read / Write

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Bit Name Bit# Reset Description

Value
7-0 0 Test pattern column spacing

This register is used to set the column spacing for the column-type test patterns.

0 = 1 pixel space (default)

1 = 2 pixel space
…
255 = 256 pixel space

12.29 TPROWSP (1Dh)

Name TPROWSP
Address 1Dh
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 0 Test pattern row spacing

This register is used to set the row spacing for the row-type test patterns.

0 = 1 pixel space (default)

1 = 2 pixel space
…
255 = 256 pixel space

12.30 TPCOLOR (1Eh)

Name TPCOLOR
Address 1Eh
Mode Read / Write

Bit Name Bit# Reset Description

Value
7:0 0 Test pattern color or 256 gray level

This register is used to set the background and foreground colors (RGB) for certain test patterns.
When PATTSEL is selected to 4,5,or 6, bit2:0 is used as foreground color and bit 6:4 as background
color.
All 8 bits data is applied to RGB data for one of 256 grey level when PATTSEL is selected to 7.

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12.31 DLYSEL (1Fh)

Name DLYSEL
Address 1Fh
Mode Read / Write

Bit Name Bit# Reset Description

Value
SKWDLY 7-4 0 LVDS skew align reference clock delay
CLKDLY 3-0 1 LVDS clock delay for serial data latch

SKWDLY :
0 = Base delay
1 = Base delay + 1 unit delay
…
15 = Base delay + 15 unit delay
CLKDLY :
0 = Base delay
1 = Base delay + 1 unit delay
…
15 = Base delay + 15 unit delay

Rx Data

Rx Clock

SKWDLY(m)
CLKDLY(n)

Skew Comp. Data

Skew Clk

Delay Clk
(DCLK)

Figure 34 : LVDS Skew compensation timing diagram

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12.32 LVDSCTL (20h)

Name LVDSCTL
Address 20h
Mode Read / Write

Bit Name Bit# Reset Description

Value
ALNMOD 2 0 Enable LVDS align mode
SKEWMOD 1-0 0 Select skew compensation mode

ALNMOD :
1 = Enable LVDS align mode
• LVDS Tx should send proper align pattern (10000000) on LVDS_DAT1 with
ALIGN signal
• Don’t set with SKEWMOD = 1 (auto skew compensation mode)
0 = Disable LVDS align mode (stay current align setting and any ALIGN and align pattern
input are ignored)

ALIGN
( ALNMOD = 1)

LVDS_DAT1
Normal Video Data Align Pattern Normal Video Data
(RD1)

Align Pattern Overlap

ALIGN
First bit Mark
LVDS_DAT1
bit3 bit2 bit1 bit0
(RD1)

LVDS_CLK
(RCK)

LVDS_DAT0,2,3
bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3
(RD0,2,3)

Min. two 8-bit serial data period overlap recommended

Figure 35 : LVDS Align pattern

ALNMOD should set after activate ALIGN signal and reset before deactivate ALIGN signal.
It is recommended to use free running HSYNC as ALIGN signal.

ALNMOD

ALIGN (pin)

Figure 36 : ALIGN signal example

SKEWMOD:

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0 = Normal operation mode (stays current skew delay setting and no change)
1 = Automatic skew delay setting mode
• LVDS Tx should send proper Skew compensation pattern (00001111) on all data and
clock
2 = Manual common skew delay setting mode (SKEW1 delay setting is used on all data line
delay)
3 = Manual separate skew delay setting mode

SKEWMOD SKEWMOD = 0, 2 or 3 SKEWMOD = 1 SKEWMOD = 0, 2 or 3

LVDS_CLK

LVDS_DAT0~3 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4

Skew Compensation Pattern

Figure 37 : Skew compensation pattern

The SKEWMOD register operation is only valid while LVDS TX is sending the skew
compensation pattern.

12.33 SKEW0 (21h, 22h)

Name SKEW0
Address 21h, 22h
Mode Read / Write

Bit Name Bit# Reset Description

Value
SKEW0(21h) 7-0 0 data line #0 delay setting lower byte
SKEW0 (22h) 15-8 0 data line #0 delay setting upper byte

00000000 00000000 = Base delay setting

00000000 00000001 = Base + 1 unit delay setting
00000000 00000011 = Base + 2 unit delay setting
00000000 00000111 = Base + 3 unit delay setting
00000000 00001111 = Base + 4 unit delay setting
:
01111111 11111111 = Base + 14 unit delay setting
11111111 11111111 = Base + 15 unit delay setting

I2C register SKEW0~SKEW3 read out are always current working delay value
• SKEWMOD = 0 or 1 : current auto skew compensated values are read
• SKEWMOD = 2 : SKEW0 register value is applied to all other skew resister and read on all
SKEW0~SKEW3
• SKEWMOD = 3 : each SKEWi register values are applied and read

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MUX
OUT
DIN[i] (Skew
SEL
Compensated
LVDS_DAT[i] Delay Chain Data)

SKEWi register
Latch 0,1
readout

MUX
SKEW1 register 2

SKEWi register 3 SEL

SKEWMOD = “1” SKEWMOD

Skew Clk Delay Clk

DCLK
LVDS_CLK Programmable Delay Programmable Delay

SKWDLY(m) CLKDLY(n)

Figure 38 : Skew compensation block diagram

12.34 SKEW1 (23h, 24h)

Name SKEW1
Address 23h, 24h
Mode Read / Write

Bit Name Bit# Reset Description

Value
SKEW1 (24h) 7-0 0 data line #1delay setting lower byte
SKEW1 (25h) 15-8 0 data line #1 delay setting upper byte

12.35 SKEW2 (25h, 26h)

Name SKEW2
Address 25h, 26h
Mode Read / Write

Bit Name Bit# Reset Description

Value
SKEW2 (25h) 7-0 0 data line #2 delay setting lower byte
SKEW2 (25h) 15-8 0 data line #2 delay setting upper byte

12.36 SKEW3 (27h, 28h)

Name SKEW3
Address 27h, 28h
Mode Read / Write

Bit Name Bit# Reset Description

Value
SKEW3 (27h) 7-0 0 data line #3 delay setting lower byte

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SKEW3 (28h) 15-8 0 data line #3 delay setting upper byte

12.37 SKFAST (29h)

Name SKFAST
Address 29h
Mode Read Only

Bit Name Bit# Reset Description

Value
SKFAST 3-0 - All “0’ after skew compensation => OK

Bit 15 of SKEW0 ~ SKEW3. If any of SKFAST bit is read as “1” after skew compensation then that line
comes much faster than selected skew clock. Decrease SKWDLY setting if possible.

SKEW3 Bit0 Bit1 Bit2 Bit3 ~ Bit12 Bit11 Bit14 Bit15

SKEW2 Bit0 Bit1 Bit2 Bit3 ~ Bit12 Bit11 Bit14 Bit15

SKEW1 Bit0 Bit1 Bit2 Bit3 ~ Bit12 Bit11 Bit14 Bit15

SKEW0 Bit0 Bit1 Bit2 Bit3 ~ Bit12 Bit11 Bit14 Bit15

SKSLOW Bit3 Bit2 Bit1 Bit0 SKFAST Bit0 Bit1 Bit2 Bit3

Figure 39 : SKFAST and SKSLOW register mapping

12.38 SKSLOW (2Ah)

Name SKSLOW
Address 2Ah
Mode Read Only

Bit Name Bit# Reset Description

Value
SKSLOW 3-0 0 All “1” after skew compensation => OK

Bit 0 of SKEW0 ~ SKEW3. If any of SKSLOW bit is read as “0” after skew compensation then that line
comes to much slower than selected skew clock. Increase SKWDLY setting if possible.

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12.39 SYNCMOD (2Bh)

Name SYNCMOD
Address 2Bh
Mode Read / Write

Bit Name Bit# Reset Description

Value
DEFEN 2-1 1 Define ENABLE pin function
DEFHS 0 0 Define LVDS_ALGN pin function

DEFEN:
0 = Do not use ENABLE pin (ENABLE & VSYNC signal uses thru LVDS data lines)
1 = ENABLE pin used as ENABLE (Default)
2 = ENABLE pin used as VSYNC
3 = Do not use

DEFHS:
0 = LVDS_ALGN pin used as ALIGN function
1 = LVDS_ALGN pin used as ALIGN & HSYNC function

12.40 LUT_ADDR (2Ch)

Name LUT_ADDR
Address 2Ch
Mode Read / Write

Bit Name Bit# Reset Description

Value
LUT_ADDR 7-0 0 Gamma look-up table template access address

12.41 LUT_DATA (2Dh, 2Eh)

Name LUT_DATA
Address 2Dh, 2Eh
Mode Read / Write

Bit Name Bit# Reset Description

Value
LUT_DATAL 7-0 0 Gamma look-up table template R/W data LSB
(2Dh)
LUT_DATAH 9-8 0 Gamma look-up table template R/W data MSB
(2Eh)

When LUT_DATAL(2Dh) register is written following operations are happen

• Write Gamma look-up table template memory to LUT_DAT (10bit) data at current LUT_ADDR
address
• Increase LUT_ADDR register by 1 after write operation

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When LUT_DATA register are read following data are read

• Current LUT_ADDR address data of Gamma look-up table memory are read

12.42 LUT_UPDATE (2Fh)

Name LUT_UPDATE
Address 2Fh
Mode Read / Write

Bit Name Bit# Reset Description

Value
UDGAMMA 3 0 Update LUT template to R,G,B LUT memory
UDRGB 2-0 7 Select R,G,B Gamma LUT for Update

UDGAMMA:
0 = No operations happen
1 = Enable copy LUT template memory data to selected R,G,B Gamma LUT memory
UDGAMMA register operation
• R,G,B LUT memory update is started at first VSYNC rising edge meet after UDGAMMA
register set to 1
• UDGAMMA register cleared to 0 after update operation end automatically

Set by user Clear automatically

UDGAMMA (2Fh:bit3)

VSYNC

Gamma LUT Template

RGB Gamma LUT

Finish LUT update

Figure 40 : Gamma LUT Update timing

UDRGB:
001 = Select B Gamma LUT memory updated
010 = Select G Gamma LUT memory updated
011 = Select G, B Gamma LUT memory updated
100 = Select R Gamma LUT memory updated
101 = Select R, B Gamma LUT memory updated
110 = Select R, G Gamma LUT memory updated
111 = Select R, G, B Gamma LUT memory updated

12.43 Reserved (30h,31h,32h,33h)

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Name Reserved
Address 30h,31h,32h,33h
Mode Read

Bit Name Bit# Reset Description

Value
7-0 - Reserved

12.44 Reserved (34h,35h)

Name Reserved
Address 34h,35h
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 99 Reserved (Do Not Change)

12.45 Reserved (36h)

Name Reserved
Address 36h
Mode Read / Write

Bit Name Bit# Reset Description

Value
3-0 0 Reserved (Do Not Change)

12.46 Reserved (37h)

Name Reserved
Address 37h
Mode Read / Write

Bit Name Bit# Reset Description

Value
6-0 0 Reserved (Do Not Change)

12.47 Reserved (38h,39h)

Name Reserved

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Address 38h,39h
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 0 Reserved (Do Not Change)

12.48 Reserved (3Ah)

Name Reserved
Address 3Ah
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 FF Reserved (Do Not Change)

12.49 Reserved (3Bh)

Name Reserved
Address 3Bh
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 0 Reserved (Do Not Change)

12.50 Reserved (3Ch)

Name Reserved
Address 3Ch
Mode Read / Write

Bit Name Bit# Reset Description

Value
4-0 0 Reserved (Do Not Change)

12.51 Reserved (3Dh)

Name Reserved
Address 3Dh
Mode Read / Write

Bit Name Bit# Reset Description

Value
2-0 3 Reserved (Do Not Change)

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12.52 Reserved (40h)

Name Reserved
Address 40h
Mode Read / Write

Bit Name Bit# Reset Description

Value
6-0 0 Reserved (Do Not Change)

12.53 Reserved (41h)

Name Reserved
Address 41h
Mode Read / Write

Bit Name Bit# Reset Description

Value
7-0 30 Reserved (Do Not Change)

12.54 Reserved (42h)

Name Reserved
Address 42h
Mode Read / Write

Bit Name Bit# Reset Description

Value
6-0 64 Reserved (Do Not Change)

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13. APPENDIX A: APPLICATION SYSTEM DIAGRAM

Driver Board SXGA096

FPGA LVDS Data

RGB (4 pairs) TOP COLUMN SEQUENCERS
(24 bits) LVDS
LUT
RECEIVERS
Clock & PCLK ODD COLUMN SWITCHES
Sync
VSYNC
LVDS CLK
HDMI Video Input
LVDS TX
Decoder Interface HSYNC RAMP DAC BUFFER

ROW SEQUENCER & PWM LOGIC

24 bits DE and
Video
ENABLE
LVDS AMP
BUFFER
ALIGN

SERIAL VCOM
SERIAL
INTERFACE INTERFACE TIMING
I2C CONTROL OLED ARRAY
µC LOGIC
1292 x 1036
SENSOR BUILT-IN
XOSC SERIAL DIMMING GAMMA FUNCTIONS TEST LOGIC
INTERFACE CONTROL
10 bit
ADC
TEMP GAMMA 5V
EEPROM COMPENSATION CORRECTION BIAS &
1.8V EVEN COLUMN SWITCHES
REFERENCES
DC-DC
-1.5V CONVERTER
BOTTOM COLUMN SEQUENCERS
POWER MODULE

VCOM
CUK
CONVERTER

Figure 41 : Block diagram of application reference system

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14. APPENDIX B: LVDS TX DESIGN EXAMPLE

lvds_txout_5X8.v (attached)
“ 01010101” /“ 10101010” LVDS_CLK

MUX
0
(LVDS_CLOCK) 8 bits Serializer (RCK)
1
RGB[23:0] s
LVDS Port Mapping

LVDS_DAT3

MUX
LVDS_DAT3_REG 0
8 bits Serializer
VCLK 1 (RDP3/N3)
s

LVDS_DAT2

MUX
LVDS_DAT2_REG 0
VS_IN 8 bits Serializer (RDP2/N2)
1
s

MUX
0
HS_IN LVDS_DAT1

MUX
LVDS_DAT1_REG 0
1 8 bits Serializer (RDP1/N1)
s 1
DE_IN s

LVDS_DAT0

MUX
LVDS_DAT0_REG 0
EN_IN 8 bits Serializer (RDP0/N0)
1
s
Alignment Pattern :“ 1000000”
Skew Compensation Pattern
“ 00001111"
Align Control
LVDS_ALIGN

TX_ALNMOD TX_SKEWMOD

Figure 42 : LVDS TX Reference Design

The LVDS TX module should have two I2C registers, which are TX_ALNMOD and
TX_SKEWMOD since LVDS RX requires special alignment and skew compensation patterns.
ALNMOD Register : When it is set, the TX should send the alignment pattern via 2ndLVDS data
channel (LVDS_DAT1) and LVDS_ALIGN signal which is a CMOS output. The alignment
pattern is: “10000000”.
2 VCLK Min.
DE_IN

ALIGN 4 VCLK Min.

(CMOS Output Pin)

LVDS_DAT1
Normal Video Data Align Patterns Normal Video Data
(RD1)

LVDS_CLK 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
(RCK)

MSB Indication

LVDS_DAT1 (RD1)
bit3 bit2 bit1 bit0 1 0 0 0 0 0 0 0 1 0 0 0
(Align Patterns)

LVDS_DAT0,2,3 (RD0,2,3)
bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4
(Normal Video Data)

8 Times Repeat Min.

Figure 43 : LVDS Alignment Pattern and Timing

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SKEWMOD Register : When it is set, the TX should send the skew compensation patterns
through all of the LVDS channel including the clock channel. The skew compensation pattern is
“0001111”.

SKEWMOD Reg SKEWMOD Reg = 1

LVDS_CLK 0000
0000 1111 0000 1111
(RCK)

LVDS_DAT0~3
bit3 bit2 bit1 bit0 0000 1111 0000 0000 1111 bit7 bit6 bit5 bit4
(RD0~3)

Skew Compensation Pattern

Figure 44 : LVDS Skew Compensation Pattern and Timing

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Example RTL Code for LVDS_TXOUT_5X8.v

// Created Tue Nov 26 11:31:11 2013
//--------------------------------------------------------------------------------------------------
//
// Title : LVDS_TXOUT_5X8
// Design : SXGA096_FPGA
// Author : Jae Koh
// Company : eMagin
//
//-------------------------------------------------------------------------------------------------
`timescale 1ns / 10ps

module LVDS_TXOUT_5X8 ( HS_IN ,HS_OUT ,rstn ,DIN ,EN_IN ,EN_OUT ,clk ,DOUT
,DE_IN ,VS_IN ,LVDSCTL ,LVDS_HS ,VS_OUT ,DE_OUT );

input EN_IN ;
wire EN_IN ;
input HS_IN ;
wire HS_IN ;
input [23:0] DIN ;
wire [23:0] DIN ;
input clk ;
wire clk ;
input VS_IN ;
wire VS_IN ;
input DE_IN ;
wire DE_IN ;
input rstn ;
wire rstn ;
input [1:0] LVDSCTL ; // {ALNMOD, SKWMOD}
wire [1:0] LVDSCTL ;

output EN_OUT ;
wire EN_OUT ;
output HS_OUT ;
wire HS_OUT ;
output VS_OUT ;
wire VS_OUT ;
output DE_OUT ;
wire DE_OUT ;
output [39:0] DOUT ;
reg [39:0] DOUT ;
output LVDS_HS ;
reg LVDS_HS ;

reg [87:0] DOUT0 ;

reg [4:0] VSO, DEO, ENO;
reg [7:0] HSO;
wire ALGN;
wire ALNMOD = LVDSCTL[1];
wire SKWMOD = LVDSCTL[0];

assign EN_OUT = ENO[4];

assign VS_OUT = VSO[4];
assign HS_OUT = HSO[4];
assign DE_OUT = DEO[4];

assign ALGN = ~DE_IN & (HS_IN | HSO[3] | HSO[7]) & ALNMOD;

wire [7:0] RIN, GIN, BIN;

assign RIN = DIN[23:16];

assign GIN = DIN[15:8];
assign BIN = DIN[7:0];

always @(DOUT0)
begin
// LVDS_CLK
DOUT[39] <= DOUT0[39];
DOUT[38] <= DOUT0[38];
DOUT[37] <= DOUT0[37];
DOUT[36] <= DOUT0[36];
DOUT[35] <= DOUT0[35];
DOUT[34] <= DOUT0[34];
DOUT[33] <= DOUT0[33];
DOUT[32] <= DOUT0[32];
// LVDS_D[3]
DOUT[31] <= DOUT0[31];
DOUT[30] <= DOUT0[30];
DOUT[29] <= DOUT0[29];
DOUT[28] <= DOUT0[28];
DOUT[27] <= DOUT0[27];
DOUT[26] <= DOUT0[26];
DOUT[25] <= DOUT0[25];
DOUT[24] <= DOUT0[24];
// LVDS_D[2]
DOUT[23] <= DOUT0[23];
DOUT[22] <= DOUT0[22];
DOUT[21] <= DOUT0[21];
DOUT[20] <= DOUT0[20];
DOUT[19] <= DOUT0[19];

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DOUT[18] <= DOUT0[18];
DOUT[17] <= DOUT0[17];
DOUT[16] <= DOUT0[16];
// LVDS_D[1]
DOUT[15] <= DOUT0[15];
DOUT[14] <= DOUT0[14];
DOUT[13] <= DOUT0[13];
DOUT[12] <= DOUT0[12];
DOUT[11] <= DOUT0[11];
DOUT[10] <= DOUT0[10];
DOUT[9] <= DOUT0[9];
DOUT[8] <= DOUT0[8];
// LVDS_D[0]
DOUT[7] <= DOUT0[7];
DOUT[6] <= DOUT0[6];
DOUT[5] <= DOUT0[5];
DOUT[4] <= DOUT0[4];
DOUT[3] <= DOUT0[3];
DOUT[2] <= DOUT0[2];
DOUT[1] <= DOUT0[1];
DOUT[0] <= DOUT0[0];
end

always @(negedge rstn or negedge clk)

if (!rstn)
LVDS_HS <= 0;
else
LVDS_HS <= HSO[2];

always @(negedge rstn or posedge clk)

if (!rstn)
begin
VSO <= 0;
HSO <= 0;
DEO <= 0;
ENO <= 0;
DOUT0 <= 0;
end
else
begin
VSO <= {VSO[3:0], VS_IN};
HSO <= {HSO[6:0], HS_IN};
DEO <= {DEO[3:0], DE_IN};
ENO <= {ENO[3:0], EN_IN};

if (SKWMOD)
begin
DOUT0 <= 40'h0F0F0F0F0F;
end
else
begin
DOUT0[39:32] <= 8'b01010101;
// RD3P/RD3N
DOUT0[31] <= BIN[5];
DOUT0[30] <= BIN[4];
DOUT0[29] <= BIN[3];
DOUT0[28] <= BIN[1];
DOUT0[27] <= BIN[0];
DOUT0[26] <= BIN[2];
DOUT0[25] <= BIN[6];
DOUT0[24] <= ~BIN[6];
// RD2P/RD2N
DOUT0[23] <= RIN[0];
DOUT0[22] <= DE_IN;
DOUT0[21] <= HS_IN;
DOUT0[20] <= EN_IN;
DOUT0[19] <= VS_IN;
DOUT0[18] <= BIN[7];
DOUT0[17] <= GIN[7];
DOUT0[16] <= ~GIN[7];
// RD1P/RD1N
if (ALGN)
begin
DOUT0[15] <= 1;
DOUT0[14] <= 0;
DOUT0[13] <= 0;
DOUT0[12] <= 0;
DOUT0[11] <= 0;
DOUT0[10] <= 0;
DOUT0[9] <= 0;
DOUT0[8] <= 0;
end
else
begin
DOUT0[15] <= GIN[6];
DOUT0[14] <= GIN[5];
DOUT0[13] <= GIN[1];
DOUT0[12] <= GIN[0];
DOUT0[11] <= GIN[4];
DOUT0[10] <= GIN[3];
DOUT0[9] <= GIN[2];
DOUT0[8] <= ~GIN[2];
end
// RD0P/RD0N

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DOUT0[7] <= RIN[7];
DOUT0[6] <= RIN[1];
DOUT0[5] <= RIN[6];
DOUT0[4] <= RIN[5];
DOUT0[3] <= RIN[4];
DOUT0[2] <= RIN[3];
DOUT0[1] <= RIN[2];
DOUT0[0] <= ~RIN[2];
end
end

endmodule

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Power ON
Reset

Auto Skew
Auto Skew Comp.
Comp.

Set TX_SKEWMOD to “ 1”

TX will send aligh pattern throuth all LVDS

channel including Clock channel
Set TX_ALNMOD to “ 1”
TX will send aligh pattern
throuth LVDS_DAT[1]
Set SKWDLY to “ 0”
channel

Set ALNMOD to “ 1” Set SKEWMOD to” 01" : Start Auto Skew Compensation mode

Display On
Set DISPOFF to “0” (SKFAT==0h) && NO Increase SKDLY
(SKSLOW==Fh) ? by 1

YES

Start Display Set SKEWMOD to” 00" : End of Auto Skew Compensation mode

Increase CLKDLY by Current

TX SKDLY
Operation
RX
Set TX_SKEWMOD to “ 0” : Start Normal Display Data out
Operation

end

Figure 45 : LVDS Link Setup Flow Chart for Firmware

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15. APPENDIX C: EEPROM MEMORY MAP

Each SXGA096 micro display contains an EEPROM memory device to serve as non-volatile data storage
for retrieving display specific information, such as its serial number and optimal registers values for proper
operation. The data can be accessed via the same I2C serial interface that is used to communicate with the
micro display. The EEPROM’S serial address is as follows:

SERADD = 0
Write Mode: Address is A6h
Read Mode: Address is A7h
SERADD = 1
Write Mode: Address is AEh
Read Mode: Address is AFh

The first 15 bytes represent the serial number of the SXGA096 micro display. The following 68 bytes
contain sequential data values that can be used to write to the micro display’s internal registers starting with
eeprom address 16 to 84.
Addresses 00 to 15 (decimal) should not be changed as they contain serial number and
traceability information

Addresses 34, 36, 37,141, 142 to145 contain calibrated values specific to each display and
should not be changed
Address 34 contains the IDRF value needed to reach 150 cd/m2 at room ambient
Addresses 36 and 37 contain the on-chip temperature sensor calibration values, needed to
correctly measure the display temperature
Addresses 142-145 contain the information needed to calculate the IDRF needed set an
absolute luminance (in cd/m2) .

Registers defined as RESERVED should not be changed.

Addresses beyond 8Fh are blank and may be used.

NOTE: The EEPROM is not write-protected and care should be taken not to activate the
Write Mode. The values highlighted in gray are measured at the factory and are specific to
each individual device.

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Memory Memory Memory Memory

Addr (Dec) Addr (hex) EEPROM Data Addr (Dec) Addr (hex) EEPROM Data
0 0 Serial Char #0 43 2B TPLINWTH
1 1 Serial Char #1 44 2C TPCOLSP
2 2 Serial Char #2 45 2D TPROWSP
3 3 Serial Char #3 46 2E TPCOLOR
4 4 Serial Char #4 47 2F DLYSEL
5 5 Lot Char#0 48 30 LVDSCTL
6 6 Lot Char#1 49 31 SKEW0L
7 7 Lot Char#2 50 32 SKEW0H
8 8 Lot Char#3 51 33 SKEW1L
9 9 Lot Char#4 52 34 SKEW1H
10 A Lot Char#5 53 35 SKEW2L
11 B Wafer Char#0 54 36 SKEW2H
12 C Wafer Char#1 55 37 SKEW3L
13 D Wafer Char#2 56 38 SKEW3H
14 E Wafer Char#3 57 39 SKFAST
15 F Data Format Version# (00h) 58 3A SKSLOW
16 10 STAT 59 3B SYNCMOD
17 11 VINMODE 60 3C LUT_ADDR
18 12 DISPMODE 61 3D LUT_DATA_L
19 13 LFTPOS 62 3E LUT_DATA_H
20 14 RGTPOS 63 3F LUT_UPDATE
21 15 TOPPOS 64 40 NOFPIXELL
22 16 BOTPOS 65 41 NOFPIXELH
23 17 ROWRESETL 66 42 NOFLINEL
24 18 ROWRESETH 67 43 NOFLINEH
25 19 RAMPCTL 68 44 NVCK0
26 1A RAMPCM 69 45 NVCK1
27 1B VDACMX 70 46 PUPCTL
28 1C BIASN 71 47 HIDNCTL
29 1D GAMMASET 72 48 DIGTEST
30 1E VCOMMODE 73 49 Reserved
31 1F VCOMCTL 74 4A Reserved
32 20 VGMAX 75 4B Reserved
33 21 VCOM 76 4C Reserved
34 22 IDRF 77 4D Reserved
35 23 DIMCTL 78 4E Reserved
36 24 TREFDIV 79 4F DISPMOD_BN
37 25 TEMPOFF 80 50 IDRF_BN
38 26 TUPDATE 81 51 DIMCTL_BN
39 27 TEMPOUT 82 52 Reserved
40 28 ANGPWRDN 83 53 Reserved
41 29 SYSPWRDN 84 54 Reserved
42 2A TPMODE 85 55 VGNA0_HI

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16. APPENDIX D: RECOMMENDED REGISTER SETTINGS

Below are the recommended settings for luminance levels greater than ~ 50 cd/m2

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