TR IB H U V A N U N IV ER SITY

IN STITU TE OF EN G IN EER IN G
P U LC H OW K C A M P U S

A Lab R eport On
Em bedded System s
C om binational Logic D esign U sing V H D L

SU B M ITTED B Y SU B M ITTED TO
N am e: Bikash Pokhrel
Department of Electronics and
R oll N o: 078BEI010
Computer Engineering
Lab D ate: 2081-10-16

Subm ission D ate: 2081-11-12 Signature:

 Lab 4: Combinational Logic Design Using VHDL

Objectives
To enable us to write VHDL code for a Field Programmable Gate Array (FPGA) capable of:

• Implementing combinational circuits

• Implementing test benches to verify the working of combinational circuits

Equipment Required
• Software: Intel Quartus Prime (Altera Quartus), ModelSim Intel FPGA Edition

Theory
Introduction to VHDL
VHDL (Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language
used to model, simulate, and implement digital circuits. It enables designers to describe the behavior and
structure of electronic circuits in a textual form. VHDL supports various abstraction levels, making it suitable
for designing complex digital systems. It is case-insensitive, strongly typed, and supports both concurrent and
sequential modeling, ensuring robust and reusable designs.

Structure of a VHDL Program

A VHDL program is structured into different sections to define and implement a digital circuit. The main
components of a VHDL program are:
• Library and Package Declaration: Specifies predefined or user-defined packages and libraries required
for the design.

• Entity Declaration: Defines the external interface of the circuit, specifying input and output ports.
• Architecture: Describes the internal behavior or structural interconnections of the circuit.
• Configuration: Allows selecting different architectures for an entity.

• Package and Package Body: Enables modularity by defining reusable components, constants, and
functions.

Types of Modeling in VHDL

VHDL supports different modeling styles, each suited for specific design requirements:
• Dataflow Modeling: Describes circuit behavior using concurrent signal assignments and Boolean ex-
pressions. This approach is useful for simple combinational circuits like multiplexers and arithmetic
units.
• Behavioral Modeling: Uses sequential statements inside a process block to describe the functionality
of a circuit. This style is suitable for complex logic like state machines and algorithmic designs.
• Structural Modeling: Represents the circuit as an interconnection of components, mimicking the actual
hardware design by connecting multiple entities.

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Applications of VHDL
VHDL is widely used in digital circuit design due to its flexibility and hardware abstraction capabilities. Some
common applications include:
• Design of combinational and sequential circuits such as adders, multiplexers, counters, and memory units.
• Implementation of digital signal processing (DSP) systems.
• Development of Field Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit
(ASIC) designs.
• Hardware prototyping and simulation before fabrication.

Advantages and Disadvantages of VHDL

Advantages:
• Supports multiple levels of abstraction (behavioral, dataflow, and structural).
• Allows concurrent execution of statements, similar to real hardware operation.

• Provides strong data type checking, reducing errors in design.

• Facilitates code reusability and modularity using packages and libraries.
• Enables easy simulation and verification before hardware implementation.
Disadvantages:

• Complex syntax compared to other hardware description languages.

• Steep learning curve for beginners.
• Requires simulation tools like ModelSim for debugging and testing.

• May have longer synthesis and simulation times for complex designs.

Combinational Logic Circuits and Their Implementation in VHDL

Combinational logic circuits are digital circuits where the output depends only on the present inputs, without
any memory elements or feedback. These circuits are implemented using basic logic gates such as AND, OR,
NOT, NAND, NOR, XOR, and XNOR.
Some common combinational circuits include:
• Adders: Used for binary addition.
• Multiplexers: Select one input from multiple inputs.

• Decoders: Convert binary inputs into a one-hot encoded output.

• Encoders: Perform the reverse operation of a decoder.
• Comparators: Compare binary numbers and generate output based on conditions.

In VHDL, combinational circuits can be described using:

• Dataflow Modeling: Defines circuits using Boolean equations. Example:
architecture dataflow of AND_Gate is
begin
Y <= A and B ;
end dataflow ;

• Behavioral Modeling: Uses a process block to describe logic behavior. Example:

2
 architecture behavioral of AND_Gate is
begin
process (A , B )
begin
if ( A = ’1 ’ and B = ’1 ’) then
Y <= ’1 ’;
else
Y <= ’0 ’;
end if ;
end process ;
end behavioral ;

• Structural Modeling: Interconnects predefined components to form a larger circuit.

By using VHDL, combinational logic circuits can be efficiently designed, simulated, and synthesized into
actual hardware. The ability to describe circuits at multiple abstraction levels makes VHDL a powerful tool
for digital system design.

Problems
Q1. Write a VHDL code to implement the given logic circuit, which has four inputs
(x1, x2, x3, x4) and one output (f). The implementation should be provided in
the following architectural styles:
1. Dataflow Style
2. Behavioral Style
3. Structural Style
Write a VHDL test bench to verify the operation of the logic circuit and provide
a simulation waveform depicting all possible input cases.

Figure 1: Combinational Circuit with Four Inputs and one Output

(a) Dataflow Style

library ieee ;
use ieee . std_logic_1164 . all ;

entity combinational_logic is
port (

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 x1 , x2 , x3 , x4 : in std_logic ;
f : out std_logic
);
end entity combinational_logic ;

architecture Dataflow of combinational_logic is

begin
f <= (( x1 and x2 ) or ( x3 and ( not x2 ) ) ) or ( x4 and x3 and (
not x2 ) ) ;
end architecture Dataflow ;

(b) Behavioral Style

library ieee ;
use ieee . std_logic_1164 . all ;

entity c ombinational_logic_Behavioral is
port (
x1 , x2 , x3 , x4 : in std_logic ;
f : out std_logic
);
end entity combinational_logic_Behavioral ;

architecture Behavioral of combinational_logic_Behavioral is

begin
process ( x1 , x2 , x3 , x4 )
begin
f <= (( x1 and x2 ) or ( x3 and ( not x2 ) ) ) or ( x4 and x3 and
( not x2 ) ) ;
end process ;
end architecture Behavioral ;

(c) Structural Style

library ieee ;
use ieee . std_logic_1164 . all ;

entity c ombinational_logic_Structured is
port (
x1 , x2 , x3 , x4 : in std_logic ;
f : out std_logic
);
end entity combinational_logic_Structured ;

architecture Structural of combinational_logic_Structured is

component and_gate
port ( x , y : in std_logic ; z : out std_logic ) ;
end component ;

component not_gate
port ( x : in std_logic ; z : out std_logic ) ;
end component ;

4
 component or_gate
port ( x , y : in std_logic ; z : out std_logic ) ;
end component ;

signal s1 , s2 , s3 , s4 , s5 , s6 , s7 : std_logic ;

begin
u0 : and_gate port map ( x1 , x2 , s1 ) ;
u1 : not_gate port map ( x2 , s2 ) ;
u3 : and_gate port map ( x3 , s2 , s3 ) ;
u4 : or_gate port map ( s1 , s3 , s4 ) ;
u5 : and_gate port map ( x4 , x3 , s5 ) ;
u6 : and_gate port map ( s2 , s5 , s6 ) ;
u7 : or_gate port map ( s4 , s6 , f ) ;
end architecture Structural ;

Submodules for Structural Modeling

AND Gate

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity and_gate is
Port ( x , y : in STD_LOGIC ;
z : out STD_LOGIC ) ;
end and_gate ;

architecture Behavioral of and_gate is

begin
z <= x and y ;
end Behavioral ;

NOT Gate

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity not_gate is
Port ( x : in STD_LOGIC ;
z : out STD_LOGIC ) ;
end not_gate ;

architecture Behavioral of not_gate is

begin
z <= not x ;
end Behavioral ;

OR Gate

library IEEE ;

5
use IEEE . STD_LOGIC_1164 . ALL ;

entity or_gate is
Port ( x , y : in STD_LOGIC ;
z : out STD_LOGIC ) ;
end or_gate ;

architecture Behavioral of or_gate is

begin
z <= x or y ;
end Behavioral ;

VHDL Test Bench

library ieee ;
use ieee . std_logic_1164 . ALL ;

entity test_q1_th is
end test_q1_th ;

architecture behavior of test_q1_th is

component combinational_logic
port (
x1 , x2 , x3 , x4 : in std_logic ;
f : out std_logic
);
end component ;

signal test_vector : std_logic_vector (3 downto 0) := " 0000 " ;

signal f_tb : std_logic ;

begin
UUT : combinational_logic port map (
x1 = > test_vector (0) ,
x2 = > test_vector (1) ,
x3 = > test_vector (2) ,
x4 = > test_vector (3) ,
f = > f_tb
);

test_vector <= " 0000 " ,

" 0001 " after 100 ns ,
" 0010 " after 200 ns ,
" 0011 " after 300 ns ,
" 0100 " after 400 ns ,
" 0101 " after 500 ns ,
" 0110 " after 600 ns ,
" 0111 " after 700 ns ;
end behavior ;

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Simulation Waveform
After running the test bench in ModelSim or Quartus, the following simulation waveform is obtained, verifying
the circuit operation.

Figure 2: Simulation waveform of the combinational logic circuit

Q2. Write VHDL code to design a logic circuit that implements the truth table of
a BCD-to-Gray code converter.
1. Use Karnaugh maps to simplify the output functions.
2. Provide the following architectural styles:
(a) Dataflow Style
(b) Behavioral Style
(c) Structural Style using only NOR gates
3. Write a VHDL test bench to verify the operation of the logic circuit.
4. Provide a simulation waveform depicting all possible input cases.

a) Dataflow Style

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity bcd_gray_code is
port (
a , b , c , d : in std_logic ;
w , x , y , z : out std_logic
);
end bcd_gray_code ;

architecture Behavioral of bcd_gray_code is

begin

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 w <= a ;
x <= a xor b ;
y <= b xor c ;
z <= c xor d ;
end Behavioral ;

b) Behavioral Style

library ieee ;
use ieee . std_logic_1164 . all ;

entity bcd_gray_code_behavioural is
port (
a , b , c , d : in std_logic ;
w , x , y , z : out std_logic
);
end entity bcd_gray_code_behavioural ;

architecture Behavioral of bcd_gray_code_behavioural is

begin
process (a , b , c , d )
begin
w <= a ;
x <= a xor b ;
y <= b xor c ;
z <= c xor d ;
end process ;
end architecture Behavioral ;

c) Structural Style using only NOR gates

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity bcd_gray_code_structured is
Port ( a , b , c , d : in STD_LOGIC ;
w , x , y , z : out STD_LOGIC ) ;
end bcd_gray_code_structured ;

architecture Structured of bcd_gray_code_structured is

component nor_gate is
Port ( x : in STD_LOGIC ;
y : in STD_LOGIC ;
z : out STD_LOGIC ) ;
end component ;

signal s1 , s2 , s3 , s4 , s5 , s6 , s7 , s8 , s9 , s10 , s11 , s12 , s13

: std_logic ;
begin
w <= a ;

u0 : nor_gate port map (a , a , s1 ) ;

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 u1 : nor_gate port map ( s1 , b , s2 ) ;
u2 : nor_gate port map (b , b , s3 ) ;
u3 : nor_gate port map ( s3 , a , s4 ) ;
u4 : nor_gate port map ( s2 , s4 , s5 ) ;
u5 : nor_gate port map ( s5 , s5 , x ) ;
u6 : nor_gate port map ( s3 , c , s6 ) ;
u7 : nor_gate port map (c , c , s7 ) ;
u8 : nor_gate port map ( s7 , b , s8 ) ;
u9 : nor_gate port map ( s6 , s8 , s9 ) ;
u10 : nor_gate port map ( s9 , s9 , y ) ;
u11 : nor_gate port map ( s7 , d , s10 ) ;
u12 : nor_gate port map (d , d , s11 ) ;
u13 : nor_gate port map ( s11 , c , s12 ) ;
u14 : nor_gate port map ( s10 , s12 , s13 ) ;
u15 : nor_gate port map ( s13 , s13 , z ) ;
end Structured ;

-- Sub - Modules for Structure modeling :

nor_gate
library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity nor_gate is
Port ( x : in STD_LOGIC ;
y : in STD_LOGIC ;
z : out STD_LOGIC ) ;
end nor_gate ;

architecture Behavioral of nor_gate is

begin
z <= not ( x or y ) ;
end Behavioral ;

Test Bench for Verification

LIBRARY ieee ;
USE ieee . std_logic_1164 . ALL ;

ENTITY question_two_th IS
END question_two_th ;

ARCHITECTURE behavior OF question_two_th IS

-- Component Declaration for the Unit Under Test ( UUT )
COMPONENT bcd_gray_code_behavioural
PORT (
a , b , c , d : IN std_logic ;
w , x , y , z : OUT std_logic
);
ENDCOMPONENT ;

signal test_vector : std_logic_vector (3 downto 0) := " 0000 " ;

9
 signal w_tb , x_tb , y_tb , z_tb : std_logic ;
begin
-- Instantiate the Unit Under Test ( UUT )
UUT : bcd_gray_code_behavioural PORT MAP (
a = > test_vector (0) ,
b = > test_vector (1) ,
c = > test_vector (2) ,
d = > test_vector (3) ,
w = > w_tb ,
x = > x_tb ,
y = > y_tb ,
z = > z_tb
);

test_vector <= " 0000 " ,

" 0001 " after 100 ns ,
" 0010 " after 200 ns ,
" 0011 " after 300 ns ,
" 0100 " after 400 ns ,
" 0101 " after 500 ns ,
" 0110 " after 600 ns ,
" 0111 " after 700 ns ,
" 1000 " after 800 ns ,
" 1001 " after 900 ns ,
" 1010 " after 1000 ns ,
" 1011 " after 1100 ns ,
" 1100 " after 1200 ns ,
" 1101 " after 1300 ns ,
" 1110 " after 1400 ns ,
" 1111 " after 1500 ns ;
end behavior ;

Figure 3: Simulation waveform of the combinational logic circuit

Q3. Write a VHDL code to implement the logic function (F) with three input
variables (x1, x2, and x3). The function (F) is equal to 1 if and only if two variables
are equal to 1; otherwise, it is equal to 0.
1. Provide the following architectural styles:
(a) Dataflow Style

10
 (b) Behavioral Style
(c) Structural Style using only NOR gates
2. Write a VHDL test bench to verify the operation of the logic circuit.
3. Provide a simulation waveform depicting all possible input cases.

a) Dataflow Style

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity logic_function_dataflow is
Port ( x1 , x2 , x3 : in STD_LOGIC ;
F : out STD_LOGIC ) ;
end logic_function_dataflow ;

architecture Dataflow of logic_function_dataflow is

begin
F <= (( not x1 ) and x2 and x3 ) or
( x1 and ( not x2 ) and x3 ) or
( x1 and x2 and ( not x3 ) ) ;
end Dataflow ;

b) Behavioral Style

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity logic_function_behavioral is
Port ( x1 , x2 , x3 : in STD_LOGIC ;
F : out STD_LOGIC ) ;
end logic_function_behavioral ;

architecture Behavioral of logic_function_behavioral is

begin
process ( x1 , x2 , x3 )
begin
F <= (( not x1 ) and x2 and x3 ) or
( x1 and ( not x2 ) and x3 ) or
( x1 and x2 and ( not x3 ) ) ;
end process ;
end Behavioral ;

c) Structural Style using only NOR gates

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity logic_function_structural is
Port ( x1 , x2 , x3 : in STD_LOGIC ;
F : out STD_LOGIC ) ;
end logic_function_structural ;

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architecture Structural of logic_function_structural is
component nor_gate is
Port ( a , b , c : in STD_LOGIC ;
z : out STD_LOGIC ) ;
end component ;

signal s1 , s2 , s3 , s4 , s5 , s6 , s7 : std_logic ;
begin
u0 : nor_gate port map ( x1 , x1 , x1 , s1 ) ;
u1 : nor_gate port map ( x2 , x2 , x2 , s2 ) ;
u2 : nor_gate port map ( x3 , x3 , x3 , s3 ) ;
u3 : nor_gate port map ( x1 , s2 , s3 , s4 ) ;
u4 : nor_gate port map ( s1 , x2 , s3 , s5 ) ;
u5 : nor_gate port map ( s1 , s2 , x3 , s6 ) ;
u6 : nor_gate port map ( s4 , s5 , s6 , s7 ) ;
u7 : nor_gate port map ( s7 , s7 , s7 , F ) ;
end Structural ;

Sub-Module for Structured Modeling

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity nor_gate is
Port ( a , b , c : in STD_LOGIC ;
z : out STD_LOGIC ) ;
end nor_gate ;

architecture Behavioral of nor_gate is

begin
z <= not ( a or b or c ) ;
end Behavioral ;

Test Bench for Verification

LIBRARY ieee ;
USE ieee . std_logic_1164 . ALL ;

ENTITY test_logic_function IS
END test_logic_function ;

ARCHITECTURE behavior OF test_logic_function IS

-- Component Declaration for the Unit Under Test ( UUT )
COMPONENT logic_function_dataflow
PORT (
x1 , x2 , x3 : IN std_logic ;
F : OUT std_logic
);
END COMPONENT ;

signal test_vector : std_logic_vector (2 downto 0) := " 000 " ;

12
 signal F_tb : std_logic ;
begin
-- Instantiate the Unit Under Test ( UUT )
uut : logic_function_dataflow PORT MAP (
x1 = > test_vector (0) ,
x2 = > test_vector (1) ,
x3 = > test_vector (2) ,
F = > F_tb
);

test_vector <= " 000 " ,

" 001 " after 100 ns ,
" 010 " after 200 ns ,
" 011 " after 300 ns ,
" 100 " after 400 ns ,
" 101 " after 500 ns ,
" 110 " after 600 ns ,
" 111 " after 700 ns ;
end behavior ;

Figure 4: Simulation waveform

Q4. Write VHDL code to implement the implicit sum of products (SOP) and
product of sums (POS) logic functions.
• Draw a truth table for the function (F), and use Karnaugh maps to simplify.
• Provide the following architectural styles:
1. Dataflow Style
2. Behavioral Style
3. Structural Style using only NOR gates
• Write a VHDL test bench to verify the operation of the logic circuit.

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 • Provide a simulation waveform depicting all possible input cases.

a) Dataflow Style

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity sop_pos_dataflow is
Port ( x1 , x2 , x3 , x4 : in STD_LOGIC ;
f1 , f2 : out STD_LOGIC ) ;
end sop_pos_dataflow ;

architecture Behavioral of sop_pos_dataflow is

begin
f1 <= (( not x1 ) and ( not x3 ) ) or ( x2 and ( not x3 ) ) or ( x1 and
( not x2 ) and x3 ) ;
f2 <= ( x2 or x3 ) and ( x3 or ( not x4 ) ) and (( not x1 ) or ( not
x2 ) or ( not x4 ) ) ;
end Behavioral ;

b) Behavioral Style

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity sop_pos_behavioral is
Port ( x1 , x2 , x3 , x4 : in STD_LOGIC ;
f1 , f2 : out STD_LOGIC ) ;
end sop_pos_behavioral ;

architecture Behavioral of sop_pos_behavioral is

begin
process ( x1 , x2 , x3 , x4 )
begin
f1 <= (( not x1 ) and ( not x3 ) ) or ( x2 and ( not x3 ) ) or ( x1
and ( not x2 ) and x3 ) ;
f2 <= ( x2 and x3 ) and ( x3 or ( not x4 ) ) and (( not x1 ) or (
not x3 ) or ( not x4 ) ) ;
end process ;
end Behavioral ;

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c) Structural Style using only NOR gates

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity sop_pos_dataflow is
Port ( x1 , x2 , x3 , x4 : in STD_LOGIC ;
f1 , f2 : out STD_LOGIC ) ;
end sop_pos_dataflow ;

architecture Behavioral of sop_pos_dataflow is

component nor_gate_2input is
Port ( x , y : in STD_LOGIC ;
f : out STD_LOGIC ) ;
end component ;

component nor_gate_3input is
Port ( e , f , g : in STD_LOGIC ;
h : out STD_LOGIC ) ;
end component ;

signal s1 , s2 , s3 , s4 , s5 , s6 , s7 , s8 , s9 , s10 , s11 :

STD_LOGIC ;
begin
u0 : nor_gate_2input port map (a , c , s1 ) ;
u1 : nor_gate_2input port map (b , b , s2 ) ;
u2 : nor_gate_2input port map ( s2 , c , s3 ) ;
u3 : nor_gate_2input port map (a , a , s4 ) ;
u4 : nor_gate_2input port map (c , c , s5 ) ;
u5 : nor_gate_3input port map ( s4 , b , s5 , s6 ) ;
u6 : nor_gate_3input port map ( s1 , s3 , s6 , s7 ) ;
u7 : nor_gate_2input port map ( s7 , s7 , f1 ) ;
u8 : nor_gate_2input port map (d , d , s8 ) ;
u9 : nor_gate_2input port map (b , c , s9 ) ;
u10 : nor_gate_2input port map (c , s8 , s10 ) ;
u11 : nor_gate_3input port map ( s4 , s2 , s8 , s11 ) ;
u12 : nor_gate_3input port map ( s9 , s10 , s11 , f2 ) ;
end Behavioral ;

Sub-Modules for Structured Modeling

nor gate 2input
library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity nor_gate_2input is
Port ( x : in STD_LOGIC ;
y : in STD_LOGIC ;
f : out STD_LOGIC ) ;
end nor_gate_2input ;

architecture Behavioral of nor_gate_2input is

15
begin
f <= not ( x or y ) ;
end Behavioral ;
nor gate 3input

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity nor_gate_3input is
Port ( e : in STD_LOGIC ;
f : in STD_LOGIC ;
g : in STD_LOGIC ;
h : out STD_LOGIC ) ;
end nor_gate_3input ;

architecture Behavioral of nor_gate_3input is

begin
h <= not ( e or f or g ) ;
end Behavioral ;

VHDL Test Bench

LIBRARY ieee ;
USE ieee . std_logic_1164 . ALL ;

ENTITY test_sop_pos IS
END test_sop_pos ;

ARCHITECTURE behavior OF test_sop_pos IS

COMPONENT sop_pos_dataflow
PORT (
x1 : IN std_logic ;
x2 : IN std_logic ;
x3 : IN std_logic ;
x4 : IN std_logic ;
f1 : OUT std_logic ;
f2 : OUT std_logic
);
END COMPONENT ;

SIGNAL test_vector : std_logic_vector (3 downto 0) := " 0000 " ;

SIGNAL f1_out , f2_out : std_logic ;

BEGIN
uut : sop_pos_dataflow PORT MAP (
x1 = > test_vector (0) ,
x2 = > test_vector (1) ,
x3 = > test_vector (2) ,
x4 = > test_vector (3) ,
f1 = > f1_out ,
f2 = > f2_out
);

16
 test_vector <= " 0000 " ,
" 0001 " after 100 ns ,
" 0010 " after 200 ns ,
" 0011 " after 300 ns ,
" 0100 " after 400 ns ,
" 0101 " after 500 ns ,
" 0110 " after 600 ns ,
" 0111 " after 700 ns ,
" 1000 " after 800 ns ,
" 1001 " after 900 ns ;
END ;

Figure 5: Simulation waveform

Q5. Write VHDL code to implement a 2:1 MUX having inputs x1 and x2, select
line s and output y.
1. Provide the following architectural implementations:
(a) Using WHEN-ELSE statement
(b) Using IF-THEN-ELSE statement
2. Write a VHDL test bench to verify the operation of the 2:1 MUX.
3. Provide a simulation waveform depicting all possible input cases.

a) Using WHEN-ELSE statement

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity mux_2 is

17
Port (
x1 , x2 , s : in STD_LOGIC ;
y : out STD_LOGIC ) ;
end mux_2 ;

architecture Behavioral of mux_2 is

begin
process (s , x1 , x2 )
begin
case s is
when ’0 ’ = >
y <= x1 ;
when ’1 ’ = >
y <= x2 ;
when others = >
y <= ’0 ’;
end case ;
end process ;
end Behavioral ;

b) Using IF-THEN-ELSE statement

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity mux_2b is
Port (
x1 , x2 , s : in STD_LOGIC ;
y : out STD_LOGIC ) ;
end mux_2b ;

architecture Behavioral of mux_2b is

begin
process (s , x1 , x2 )
begin
if s = ’0 ’ then
y <= x1 ;
elsif s = ’1 ’ then
y <= x2 ;
else
y <= ’0 ’;
end if ;
end process ;
end Behavioral ;

Test Bench for Verification

LIBRARY ieee ;
USE ieee . std_logic_1164 . ALL ;

ENTITY test_mux_2b IS
END test_mux_2b ;

18
ARCHITECTURE behavior OF test_mux_2b IS
-- Component Declaration for the Unit Under Test ( UUT )
COMPONENT mux_2b
PORT (
x1 , x2 , s : IN std_logic ;
y : OUT std_logic
);
END COMPONENT ;

signal test_vector : std_logic_vector (2 downto 0) := " 000 " ;

signal y_tb : std_logic ;
begin
-- Instantiate the Unit Under Test ( UUT )
UUT : mux_2b PORT MAP (
x1 = > test_vector (0) ,
x2 = > test_vector (1) ,
s = > test_vector (2) ,
y = > y_tb
);

-- Test vector sequence

test_vector <= " 000 " ,
" 001 " after 100 ns ,
" 010 " after 200 ns ,
" 011 " after 300 ns ,
" 100 " after 400 ns ,
" 101 " after 500 ns ,
" 110 " after 600 ns ,
" 111 " after 700 ns ;
end behavior ;

Figure 6: Simulation waveform

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6. Write VHDL code to implement a 4:1 MUX having inputs x1, x2, x3 and x4,
select lines s1, s0 and output y using three 2:1 multiplexers as the basic building
blocks.
• Use a hierarchical design approach:
1. Create component definitions in separate (.vhd) files
2. Use either Dataflow or Behavioral or Structural design styles
3. Use Structural design style for the 4:1 MUX architecture:
– Make use of 2:1 MUX component declaration
– Make use of 2:1 MUX component instantiation
4. Write a VHDL test bench to verify the operation of the 4:1 MUX.
5. Provide a simulation waveform depicting all possible input cases.

Figure 7: Simulation waveform

a) 2:1 MUX Using Behavioral Design Style

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity MUX_2 is
Port (
x , y , s : in STD_LOGIC ;
z : out STD_LOGIC
);
end MUX_2 ;

architecture Behavioral of MUX_2 is

begin

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 process (s , x , y )
begin
case s is
when ’0 ’ = >
z <= x ;
when ’1 ’ = >
z <= y ;
when others = >
z <= ’0 ’;
end case ;
end process ;
end Behavioral ;

b) 4:1 MUX Using Structural Design Style

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity MUX_4 is
Port (
x1 : in STD_LOGIC ;
x2 : in STD_LOGIC ;
x3 : in STD_LOGIC ;
x4 : in STD_LOGIC ;
s1 : in STD_LOGIC ;
s0 : in STD_LOGIC ;
Y : out STD_LOGIC
);
end MUX_4 ;

architecture Behavioral of MUX_4 is

component MUX_2 is
Port (
x , y , s : in STD_LOGIC ;
z : out STD_LOGIC
);
end component ;

signal s_0 , s_1 : STD_LOGIC ;

begin
u0 : MUX_2 port map ( x1 , x2 , s0 , s_0 ) ;
u1 : MUX_2 port map ( x3 , x4 , s0 , s_1 ) ;
u2 : MUX_2 port map ( s_0 , s_1 , s1 , Y ) ;
end Behavioral ;

Test Bench for 4:1 MUX

LIBRARY ieee ;
USE ieee . std_logic_1164 . ALL ;

ENTITY test_mux_4 IS

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END test_mux_4 ;

ARCHITECTURE behavior OF test_mux_4 IS

COMPONENT MUX_4
PORT (
x1 : IN std_logic ;
x2 : IN std_logic ;
x3 : IN std_logic ;
x4 : IN std_logic ;
s1 : IN std_logic ;
s0 : IN std_logic ;
Y : OUT std_logic
);
END COMPONENT ;

signal test_vector : std_logic_vector (5 downto 0) := " 000000 "

;
signal Y_TB : std_logic ;

BEGIN
uut : MUX_4 PORT MAP (
x1 = > test_vector (0) ,
x2 = > test_vector (1) ,
x3 = > test_vector (2) ,
x4 = > test_vector (3) ,
s1 = > test_vector (4) ,
s0 = > test_vector (5) ,
Y = > Y_TB
);

test_vector <= " 000000 " ,

" 000001 " after 100 ns ,
" 000010 " after 200 ns ,
" 000011 " after 300 ns ,
" 000100 " after 400 ns ,
" 000101 " after 500 ns ,
" 000110 " after 600 ns ,
" 000111 " after 700 ns ,
" 001000 " after 800 ns ,
" 001001 " after 900 ns ,
" 001010 " after 1000 ns ,
" 001011 " after 1100 ns ,
" 001100 " after 1200 ns ,
" 001101 " after 1300 ns ,
" 001110 " after 1400 ns ,
" 001111 " after 1500 ns ; -- for now upto just
001111
END ;

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 Figure 8: Simulation waveform

7. Write VHDL code to implement a 4-bit adder/subtractor using four 1-bit full
adders.
• Use a Structural architecture style with hierarchical design approach:
1. Use 1-bit adder as the basic building block
2. Implement the 4-bit adder/subtractor using four 1-bit full adders.
• Write a VHDL test bench to verify the operation of the 4-bit adder/subtractor.
• Provide a simulation waveform depicting all possible input cases.

a) Use 1-bit adder as the basic building block

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity adder_1b is
Port (
x , y , z : in STD_LOGIC ;
s , c : out STD_LOGIC
);
end adder_1b ;

architecture Behavioral of adder_1 is

begin
s <= ( x xor y ) xor z ;
c <= ( z and ( x xor y ) ) or ( x and y ) ;
end Behavioral ;

b) Implement the 4-bit adder/subtractor using four 1-bit full adders

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library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity adder_4b is
Port (
a , b : in STD_LOGIC_VECTOR (3 downto 0) ;
s : out STD_LOGIC_VECTOR (3 downto 0) ;
c : inout STD_LOGIC_VECTOR (4 downto 0)
);
end adder_4b ;

architecture Behavioral of adder_4b is

component adder_1b is
Port (
x , y , z : in STD_LOGIC ;
s , c : out STD_LOGIC
);
end component ;
begin
u0 : adder_1b port map ( a (0) , b (0) xor c (0) , c (0) , s (0) , c (1) )
;
u1 : adder_1b port map ( a (1) , b (1) xor c (0) , c (1) , s (1) , c (2) )
;
u2 : adder_1b port map ( a (2) , b (2) xor c (0) , c (2) , s (2) , c (3) )
;
u3 : adder_1b port map ( a (3) , b (3) xor c (0) , c (3) , s (3) , c (4) )
;
end Behavioral ;

Test Bench for the 4-bit adder/subtractor

LIBRARY ieee ;
USE ieee . std_logic_1164 . ALL ;

ENTITY test_adder4 IS
END test_adder4 ;

ARCHITECTURE behavior OF test_adder4 IS

COMPONENT adder_4b
PORT (
a : IN STD_LOGIC_VECTOR (3 downto 0) ;
b : IN STD_LOGIC_VECTOR (3 downto 0) ;
s : OUT STD_LOGIC_VECTOR (3 downto 0) ;
c : INOUT STD_LOGIC_VECTOR (4 downto 0)
);
END COMPONENT ;

signal test_vector : STD_LOGIC_VECTOR (8 downto 0) := "

000000000 " ;
signal output1 : STD_LOGIC_VECTOR (3 downto 0) ;
signal output2 : STD_LOGIC_VECTOR (4 downto 1) ;
signal o : STD_LOGIC := ’0 ’;

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BEGIN
uut : adder_4b PORT MAP (
a = > test_vector (3 downto 0) ,
b = > test_vector (7 downto 4) ,
s = > output1 ,
c (0) = > o ,
c (4 downto 1) = > output2
);

test_vector <= " 000000000 " ,

" 000000001 " after 100 ns ,
" 000000010 " after 200 ns ,
" 000000011 " after 300 ns ,
" 000000100 " after 400 ns ,
" 000000101 " after 500 ns ,
" 000000110 " after 600 ns ,
" 000000111 " after 700 ns ,
" 001000000 " after 800 ns ,
" 001000001 " after 900 ns ,
" 001010000 " after 1000 ns ,
" 001010001 " after 1100 ns ,
" 001100000 " after 1200 ns ,
" 001100001 " after 1300 ns ,
" 001110000 " after 1400 ns ,
" 001110001 " after 1500 ns ;
END ;

Figure 9: Simulation waveform

Discussion
In this lab, we wrote VHDL programs for various combinational logic circuits. The circuits implemented
include a BCD to Gray converter, a multiplexer, and an adder. To verify the correctness of these programs, we
wrote test benches and analyzed the waveforms produced during simulation. The programs were written using
different VHDL design styles, including Dataflow, Behavioral, and Structural styles.
In our design, to store a single bit, we used the std logic type, and to store multiple bits, we used
std vector. In some of the programs, we first simplified the Boolean expressions using Karnaugh Maps (K-
map) before implementing them. This helped in reducing the complexity of the logic and ensuring the efficiency
of the designs.
Throughout the coding process, we learned the importance of selecting the appropriate design style and how
to handle different types of logic operations effectively in VHDL. Writing test benches allowed us to verify the

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correctness of the designs and identify potential issues early on. These activities deepened our understanding
of VHDL and combinational circuit design.

Conclusion
In this lab, we successfully wrote VHDL programs for combinational logic circuits such as the BCD to Gray
converter, multiplexer, and adder. We verified the designs through test benches and waveform analysis. By
using various design styles, we gained a deeper understanding of VHDL programming and digital circuit design.

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