SPC582B60x, SPC582B54x,

SPC582B50x
32-bit Power Architecture® microcontroller for automotive ASIL-B
applications
Datasheet - production data

– Cyclic redundancy check (CRC) unit

– End-to-end Error Correction Code
(e2eECC) logic
 Crossbar switch architecture for concurrent
access to peripherals, Flash, or RAM from
multiple bus masters with end-to-end ECC
 Body cross triggering unit (BCTU)
– Triggers ADC conversions from any eMIOS
eTQFP64 (10 x 10 x 1.0 mm) eTQFP100 (14 x 14 x 1.0 mm) channel
– Triggers ADC conversions from up to 2
dedicated PIT_RTIs
– 1 event configuration register dedicated to
each timer event allows to define the
corresponding ADC channel
– Synchronization with ADC to avoid collision
Features  1 enhanced 12-bit SAR analog-to-digital
converters
 AEC-Q100 qualified
– Up to 27 channels
 High performance e200z2 single core
– enhanced diagnosis feature
– 32-bit Power Architecture technology CPU
 Communication interfaces
– Core frequency as high as 80 MHz
– 6 LINFlexD modules
– Variable Length Encoding (VLE)
– 4 deserial serial peripheral interface (DSPI)
– Floating Point, End-to-End Error Correction
modules
 1088 KB (1024 KB code flash + 64 KB data – 7 MCAN interfaces with advanced shared
flash) on-chip flash memory: supports read memory scheme and ISO CAN FD support
during program and erase operations, and
multiple blocks allowing EEPROM emulation  Dual phase-locked loops with stable clock
domain for peripherals and FM modulation
 96 KB on-chip general-purpose SRAM domain for computational shell
 Multi-channel direct memory access controller  Nexus Class 3 debug and trace interface
(eDMA) with 16 channels
 Boot assist Flash (BAF) supports factory
 1 interrupt controller (INTC) programming using a serial bootload through
 Comprehensive new generation ASIL-B safety the asynchronous CAN or LIN/UART.
concept  Enhanced modular IO subsystem (eMIOS): up
– ASIL-B of ISO 26262 to 32 timed I/O channels with 16-bit counter
– FCCU for collection and reaction to failure resolution
notifications  Advanced and flexible supply scheme
– Memory Error Management Unit (MEMU) – On-chip voltage regulator for 1.2 V core
for collection and reporting of error events logic supply.
in memories
 Junction temperature range -40 °C to 150 °C

June 2018 DS11597 Rev 3 1/102

This is information on a product in full production. www.st.com

This datasheet has been downloaded from http://www.digchip.com at this page

 SPC582B60x, SPC582B54x, SPC582B50x

Table 1. Device summary

Part number
Package
1 MB 768 kB 512 kB

eTQFP64 SPC582B60E1 SPC582B54E1 SPC582B50E1

eTQFP100 SPC582B60E3 SPC582B54E3 SPC582B50E3

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SPC582B60x, SPC582B54x, SPC582B50x Table of contents

Table of contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Feature overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 11

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1 Power domains and power up/down sequencing . . . . . . . . . . . . . . . . . 16
3.4 Electromagnetic emission characteristics . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 Temperature profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Device consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8 I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8.1 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8.2 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8.3 I/O pad current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.9 Reset pad (PORST) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 34
3.10 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.10.1 PLL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.10.2 PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.11 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11.1 Crystal oscillator 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11.2 RC oscillator 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.11.3 Low power RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.12 ADC system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.12.1 ADC input description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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4
Table of contents SPC582B60x, SPC582B54x, SPC582B50x

3.12.2 SAR ADC 12 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.13 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.13.1 Power management integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.13.2 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.13.3 Voltage monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.14 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.15 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.15.1 Debug and calibration interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.15.2 DSPI timing with CMOS pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.15.3 CAN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.15.4 UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.15.5 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.1 eTQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.2 eTQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.3 eTQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.4 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.4.1 eTQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.4.2 eTQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.4.3 General notes for specifications at maximum junction temperature . . . 91

5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

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1 Introduction

1.1 Document overview

This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the device. To
ensure a complete understanding of the device functionality, refer also to the device
reference manual and errata sheet.

1.2 Description
The SPC582Bxx microcontroller is the entry member of a new family of devices
superseding the SPC582Bx family.
SPC582Bxx is built on the legacy of the SPC5x products, while introducing new features to
answer the future requirements like the ASIL-B classification, high number of ISO CAN-FD
channels, and provide significant power and performance improvement (MIPS per mW).

1.3 Device feature summary

Table 2 lists a summary of major features for the SPC582Bxx device. The feature column
represents a combination of module names and capabilities of certain modules. A detailed
description of the functionality provided by each on-chip module is given later in this
document.

Table 2. Features List

Feature Description

SPC58 family 40 nm
Number of Cores 1
Single Precision Floating Point Yes
SIMD No
VLE Yes
MPU Yes
CRC Channels 2x4
Software Watchdog Timer (SWT) 1
Core Nexus Class 3+
4 x SCU
Event Processor
4 x PMC
Run control Module Yes
System SRAM 96 KB (including 64 KB of standby RAM)
Flash 1088 KB (1024 code flash + 64 KB data flash)
Flash fetch accelerator 2 x 4 x 256-bit

DS11597 Rev 3 5/102

10
Introduction SPC582B60x, SPC582B54x, SPC582B50x

Table 2. Features List (continued)

Feature Description

DMA channels 16
DMA Nexus Class 3
LINFlexD 6
MCAN (ISO CAN-FD) 7
DSPI 4
I2C 1
8 PIT channels
System Timers 4 AUTOSAR® (STM)
RTC/API
eMIOS 32 channels
BCTU 32 channels
Interrupt controller 1 x 151 sources
ADC (SAR) One 12-bit, up to 27 channels
Self Test Controller Yes
PLL Dual PLL with FM
Integrated linear voltage regulator Yes
integrated switch mode voltage
No
regulator
External Power Supplies 5 V, 3.3 V
Stop Mode
Low Power Modes HALT Mode
Standby Mode

1.4 Block diagram

The figures below show the top-level block diagrams.

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Figure 1. Block Diagram

JTAGM JTAGC DCI SPU NPC

INTC

SWT IAC
e200 z215n3 – 80 MHz
single issue Nexus3p
Main Core

DMA CHMUX
VLE EFPU2

Delayed Lock-step with Redundancy Checkers

16 Ch
eDMA Core Memory Protection Unit
(CMPU)
32 ADD
32 DATA
Instruction Load / Store
32 ADD 32 ADD
E2E ECC 32 DATA 32 DATA

Nexus Data
BIU with E2E ECC
Trace
Decorated Storage Access

32 ADD Instruction Load / Store

32 ADD 32 ADD
32 DATA
32 DATA 32 DATA

M2
AHB_M4
AHB_M6 AHB_M5 M0 M1
Cross Bar Switch (XBAR) AMBA 2.0 v6 AHB – 32 bit
System Memory Protection Unit
S5 S4 S2 S0 S1

32 ADD 32 ADD 32 ADD 32 ADD 32 ADD

32 DATA 32 DATA 32 DATA 32 DATA 32 DATA

Periph. Bridge Periph. Bridge PRAMC_2 PFLASHC 128 Page Line

AIPS_2 AIPS_1 with E2E Set-Associative FLASH
E2E ECC E2E ECC ECC MiniCache 1 MB
with E2E ECC
32 ADD 32 ADD 32 ADD EEPROM
32 DATA 32 DATA 32 DATA 4x16 KB
SRAM Non Volatile Memory
Peripheral Peripheral
Array 2 Multiple RWW partitions
Cluster 2 Cluster 1
96 KB

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Introduction SPC582B60x, SPC582B54x, SPC582B50x

Figure 2. Periphery allocation

BCTU_0 PBRIDGE_2
eMIOS_0 XBAR_1
SAR_ADC_12bit_B0 SMPU_1
I2C_0 XBIC_1
DSPI_0, 2 PCM_0
LINFLEX_0, 2, 10 PFLASH_1
CAN_SUB_0_MESSAGE_RAM INTC_1

CAN_SUB_0_M_CAN_0..3 SWT_2

CCCU STM_2
DTS eDMA_1
JDC PRAM_2
STCU TDM_0
JTAGM
MEMU
IMA
CRC_0
PBRIDGE_2 – Peripheral Cluster 2

DMAMUX_0
PIT_0
RTC/API
WKPU
MC_PCU
PMC_DIG
MC_RGM
RCOSC_DIG
RC1024K_DIG DSPI_1, 3 PBRIDGE_1
OSC_DIG LINFlex_1, 7, 15
PLL_DIG CAN_SUB_1_MESSAGE_RAM
CMU_0_PLL0_XOSC_IRCOSC CAN_SUB_1_M_CAN_1..3
PBRIDGE_1 – Peripheral Cluster 1

MC_CGM FCCU
MC_ME CRC_1
SIUL2 CMU_1_CORE_XBAR
FLASH_0 CMU_2_HPBM
PASS CMU_3_PBRIDGE
SSCM CMU_6_SARADC
CMU_11_FBRIDGE
CMU_12_EMIOS
CMU_14_PFBRIDGE

Note: In this diagram, ON-platform modules are shown in orange color and OFF-platform modules
are shown in blue color.

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1.5 Feature overview

On-chip modules within SPC582Bxx include the following features:
 One main CPU, single issue, 32-bit CPU core complexes (e200z2).
– Power Architecture embedded specification compliance
– Instruction set enhancement allowing variable length encoding (VLE), encoding a
mix of 16-bit and 32-bit instructions, for code size footprint reduction
– Single-precision floating point operations
 1088 KB (1024 KB code flash + 64 KB data flash) on-chip Flash memory
– Supports read during program and erase operations, and multiple blocks allowing
EEPROM emulation
 96 KB on-chip general-purpose SRAM
 Multi channel direct memory access controllers
– 16 eDMA channels
 One interrupt controller (INTC)
 Dual phase-locked loops with stable clock domain for peripherals and FM modulation
domain for computational shell
 Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from
multiple bus masters with end-to-end ECC
 System integration unit lite (SIUL)
 Boot assist Flash (BAF) supports factory programming using a serial bootload through
the asynchronous CAN or LIN/UART.
 Hardware support for safety ASIL-B level related applications
 Enhanced modular IO subsystem (eMIOS): up to 32 timed I/O channels with 16-bit
counter resolution
– Buffered updates
– Support for shifted PWM outputs to minimize occurrence of concurrent edges
– Supports configurable trigger outputs for ADC conversion for synchronization to
channel output waveforms
– Shared or independent time bases
– DMA transfer support available
 Body cross triggering unit (BCTU)
– Triggers ADC conversions from any eMIOS channel
– Triggers ADC conversions from up to 2 dedicated PIT_RTIs
– One event configuration register dedicated to each timer event allows to define the
corresponding ADC channel
– Synchronization with ADC to avoid collision
 One 12-bit SAR analog-to-digital converter
– up to 27 channels
– enhanced diagnosis features
 Four deserial serial peripheral interface (DSPI) modules
 Six LIN and UART communication interface (LINFlexD) modules
– LINFlexD_0 is a Master/Slave
– All others are Masters

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Introduction SPC582B60x, SPC582B54x, SPC582B50x

 Seven modular controller area network (MCAN) modules, all supporting flexible data
rate (ISO CAN-FD)
 Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some
support for 2010 standard
 Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1 and
IEEE 1149.7), 2-pin JTAG interface
 On-chip voltage regulator controller manages the supply voltage down to 1.2 V for core
logic
 Self-test capability

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2 Package pinouts and signal descriptions

Please refer to the SPC582Bxx IO_ definition document.

It includes the following sections:
1. Package pinouts
2. Pin descriptions
a) Power supply and reference voltage pins
b) System pins
c) Generic pins

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Electrical characteristics SPC582B60x, SPC582B54x, SPC582B50x

3 Electrical characteristics

3.1 Introduction
The present document contains the target Electrical Specification for the 40 nm family 32-bit
MCU SPC582Bxx products.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” (Controller Characteristics) is included in the “Symbol”
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” (System Requirement) is included in the
“Symbol” column.
The electrical parameters shown in this document are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 3 are used and
the parameters are tagged accordingly in the tables where appropriate.

Table 3. Parameter classifications

Classification tag Tag description

P Those parameters are guaranteed during production testing on each individual device.
C Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T Those parameters are achieved by design validation on a small sample size from typical
devices.
D Those parameters are derived mainly from simulations.

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3.2 Absolute maximum ratings

Table 4 describes the maximum ratings for the device. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Stress beyond the listed maxima, even momentarily, may affect device reliability or cause
permanent damage to the device.

Table 4. Absolute maximum ratings

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Core voltage
VDD_LV SR D operating life — –0.3 — 1.4 V
range(1)
VDD_HV_IO_MAIN
VDD_HV_IO_FLEX I/O supply
SR D — –0.3 — 6.0 V
VDD_HV_OSC voltage(2)
VDD_HV_FLA
ADC ground Reference to
VSS_HV_ADV SR D –0.3 — 0.3 V
voltage digital ground
ADC Supply Reference to
VDD_HV_ADV SR D –0.3 — 6.0 V
voltage VSS_HV_ADV
SAR ADC
VSS_HV_ADR_S SR D ground — –0.3 — 0.3 V
reference
SAR ADC
Reference to
VDD_HV_ADR_S SR D voltage –0.3 — 6.0 V
VSS_HV_ADR_S
reference
VSS_HV_ADR_S
VSS-VSS_HV_ADR_S SR D differential — –0.3 — 0.3 V
voltage
VSS_HV_ADV
VSS-VSS_HV_ADV SR D differential — –0.3 — 0.3 V
voltage
— –0.3 — 6.0
Relative to Vss –0.3 — —
I/O input voltage
VIN SR D V
range(3) (4) Relative to
VDD_HV_IO and — — 0.3
VDD_HV_ADV
Digital Input pad
TTRIN SR D — — — 1 ms
transition time(5)
Maximum DC
injection current
IINJ SR T for each — –5 — 5 mA
analog/digital
PAD(6)

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Electrical characteristics SPC582B60x, SPC582B54x, SPC582B50x

Table 4. Absolute maximum ratings (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Maximum non-
operating
TSTG SR T Storage — –55 — 125 °C
temperature
range
Maximum non
operating
TPAS SR C temperature — –55 — 150(7) °C
during passive
lifetime
Maximum
No supply; storage
storage time,
temperature in
TSTORAGE SR — assembled part — — 20 years
range –40 °C to
programmed in
60 °C
ECU
Maximum solder
TSDR SR T temperature Pb- — — — 260 °C
free packaged(8)
Moisture
MSL SR T sensitivity — — — 3 —
level(9)
Typical range for
X-rays source
Maximum
during
TXRAY dose SR T cumulated — — 1 grey
inspection:80 ÷
XRAY dose
130 KV; 20 ÷
50 A
1. VDD_LV: allowed 1.335 V - 1.400 V for 60 seconds cumulative time at the given temperature profile. Remaining time allowed
1.260 V - 1.335 V for 10 hours cumulative time at the given temperature profile. Remaining time as defined in Section 3.3:
Operating conditions.
2. VDD_HV: allowed 5.5 V – 6.0 V for 60 seconds cumulative time at the given temperature profile, for 10 hours cumulative
time with the device in reset at the given temperature profile. Remaining time as defined in Section 3.3: Operating
conditions.
3. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current
condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin
to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3 V can be used for nominal
calculations.
4. Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameter IINJ).
5. This limitation applies to pads with digital input buffer enabled. If the digital input buffer is disabled, there are no maximum
limits to the transition time.
6. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in
Section 3.8.3: I/O pad current specifications.
7. 175°C are allowed for limited time. Mission profile with passive lifetime temperature >150°C have to be evaluated by ST to
confirm that are granted by product qualification.
8. Solder profile per IPC/JEDEC J-STD-020D.
9. Moisture sensitivity per JDEC test method A112.

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3.3 Operating conditions

Table 5 describes the operating conditions for the device, and for which all the specifications
in the data sheet are valid, except where explicitly noted. The device operating conditions
must not be exceeded or the functionality of the device is not guaranteed.

Table 5. Operating conditions

Value(1)
Symbol C Parameter Conditions Unit
Min Typ Max

FSYS SR P Operating — — — 80 MHz

system clock
frequency(4)
TJ SR P Operating — –40 — 150 °C
Junction
temperature
TA SR P Operating — –40 — 125 °C
Ambient
temperature
VDD_LV SR P Core supply — 1.14 1.20 1.26(3) (4) V
voltage(2)
VDD_HV_IO_MAIN SR P IO supply — 3.0 — 5.5 V
VDD_HV_IO_FLEX voltage
VDD_HV_FLA
VDD_HV_OSC
VDD_HV_ADV SR P ADC supply — 3.0 — 5.5 V
voltage
VSS_HV_ADV- SR D ADC ground — –25 — 25 mV
VSS differential
voltage
VDD_HV_ADR_S SR P SAR ADC — 3.0 — 5.5 V
reference
C — 2.0 — 3.0
voltage
VDD_HV_ADR_S- SR D SAR ADC — — — 25 mV
VDD_HV_ADV reference
differential
voltage
VSS_HV_ADR_S SR P SAR ADC — VSS_HV_ADV V
ground
reference
voltage
VSS_HV_ADR_S- SR D VSS_HV_ADR_S — –25 — 25 mV
VSS_HV_ADV differential
voltage
VRAMP_HV SR D Slew rate on — — — 100 V/ms
HV power
supply

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Electrical characteristics SPC582B60x, SPC582B54x, SPC582B50x

Table 5. Operating conditions (continued)

Value(1)
Symbol C Parameter Conditions Unit
Min Typ Max

VIN SR P I/O input — 0 — 5.5 V

voltage range
IINJ1 SR T Injection Digital pins and –3.0 — 3.0 mA
current (per analog pins
pin) without
performance
degradation(5)
(6) (7)

IINJ2 SR D Dynamic Digital pins and –10 — 10 mA

Injection analog pins
current (per
pin) with
performance
degradation(7)
(8)

1. The ranges in this table are design targets and actual data may vary in the given range.
2. Core voltage as measured on device pin to guarantee published silicon performance.
3. Core voltage can exceed 1.26 V with the limitations provided in Section 3.2: Absolute maximum ratings, provided that
HVD134_C monitor reset is disabled.
4. 1.260 V - 1.290 V range allowed periodically for supply with sinusoidal shape and average supply value below or equal to
1.236 V at the given temperature profile.
5. Full device lifetime. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these
limits. See Section 3.2: Absolute maximum ratings for maximum input current for reliability requirements.
6. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pins is
above the supply rail, current will be injected through the clamp diode to the supply rails. For external RC network
calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.
7. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in
Section 3.8.3: I/O pad current specifications.
8. Positive and negative Dynamic current injection pulses are allowed up to this limit. I/O and ADC specifications are not
granted. See the dedicated chapters for the different specification limits. See the Absolute Maximum Ratings table for
maximum input current for reliability requirements. Refer to the following pulses definitions: Pulse1 (ISO 7637-2:2011),
Pulse 2a(ISO 7637-2:2011 5.6.2), Pulse 3a (ISO 7637-2:2011 5.6.3), Pulse 3b (ISO 7637-2:2011 5.6.3).

3.3.1 Power domains and power up/down sequencing

The following table shows the constraints and relationships for the different power domains.
Supply1 (on rows) can exceed Supply2 (on columns), only if the cell at the given row and
column is reporting ‘ok’. This limitation is valid during power-up and power-down phases, as
well as during normal device operation.

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Table 6. Device supply relation during power-up/power-down sequence

Supply2

VDD_HV_IO_MAIN
VDD_LV VDD_HV_FLA VDD_HV_ADV VDD_HV_ADR
VDD_HV_OSC

VDD_HV_IO_MAIN ok ok ok
VDD_HV_FLA
VDD_HV_OSC(1)
Supply1

VDD_HV_ADV ok not allowed ok

VDD_HV_ADR ok not allowed not allowed
1. The application shall grant that these supplies are always at the same voltage level.

During power-up, all functional terminals are maintained in a known state as described in
the device pinout IO definition excel file.

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3.4 Electromagnetic emission characteristics

EMC measurements to IC-level IEC standards are available from STMicroelectronics on
request.

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3.5 Electrostatic discharge (ESD)

The following table describes the ESD ratings of the device.

Table 7. ESD ratings(1),(2)

Parameter C Conditions Value Unit

ESD for Human Body Model (HBM)(3) T All pins 2000 V

(4)
ESD for field induced Charged Device Model (CDM) T All pins 500 V
T Corner Pins 750 V
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification
requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature.
Maximum DC parametrics variation within 10% of maximum specification”.
3. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing.
4. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level.

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Electrical characteristics SPC582B60x, SPC582B54x, SPC582B50x

3.6 Temperature profile

The device is qualified in accordance to AEC-Q100 Grade1 requirements, such as HTOL
1,000 h and HTDR 1,000 hrs, TJ = 150 °C.

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3.7 Device consumption

Table 8. Device consumption(1)
Value
Symbol C Parameter Conditions Unit
Min Typ Max

IDD_LKG(2),(3) CC C Leakage current on the TJ = 40 °C — — 2 mA

VDD_LV supply
D TJ = 25 °C — 0.65 1
D TJ = 55 °C — — 2.5
D TJ = 95 °C — — 6
D TJ = 120 °C — — 14
P TJ = 150 °C — — 35
IDD_LV(3) CC P Dynamic current on — — — 50 mA
the VDD_LV supply,
very high consumption
profile(4)
IDD_HV CC P Total current on the fMAX — — 37 mA
VDD_HV supply(4)
IDD_LV_GW CC T Dynamic current on — — — 48 mA
the VDD_LV supply,
gateway profile(5)
IDD_HV_GW CC T Dynamic current on — — — 17 mA
the VDD_HV supply,
gateway profile(5)
IDDHALT(6) CC T Dynamic current on — — 26 37 mA
the VDD_LV supply
+Total current on the
VDD_HV supply
IDDSTOP(7) CC T Dynamic current on — — 6.5 9 mA
the VDD_LV supply
+Total current on the
VDD_HV supply
IDDSTBY8 CC D Total standby mode TJ = 25 °C — 40 90 µA
current on VDD_LV and
C TJ = 40 °C — — 135
VDD_HV supply, 8 KB
D RAM(8) TJ = 55 °C — — 210
D TJ = 120 °C — — 1.2 mA
P TJ = 150 °C — — 2.5
IDDSTBY64 CC D Total standby mode TJ = 25 °C — 55 125 µA
current on VDD_LV and
C TJ = 40 °C — — 190
VDD_HV supply, 64 KB
D RAM(8) TJ = 55 °C — — 290
D TJ = 120 °C — — 1.6 mA
P TJ = 150 °C — — 3.5
1. The ranges in this table are design targets and actual data may vary in the given range.

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Electrical characteristics SPC582B60x, SPC582B54x, SPC582B50x

2. The leakage considered is the sum of core logic and RAM memories. The contribution of analog modules is not considered,
and they are computed in the dynamic IDD_LV and IDD_HV parameters.
3. IDD_LKG (leakage current) and IDD_LV (dynamic current) are reported as separate parameters, to give an indication of the
consumption contributors. The tests used in validation, characterization and production are verifying that the total
consumption (leakage+dynamic) is lower or equal to the sum of the maximum values provided (IDD_LKG+IDD_LV). The
two parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions
and the software profile used.
4. Use case: 1 x e200Z2 @80 MHz, all IPs clock enabled, Flash access with prefetch disabled, Flash consumption includes
parallel read and program/erase, 1xSARADC in continuous conversion, DMA continuously triggered by ADC conversion, 4
DSPI / 3 CAN / 2 LINFlex transmitting, RTC and STM running, 1xEMIOS running (12 channels in OPWMT mode), FIRC,
SIRC, FXOSC, PLL0-1 running. The switching activity estimated for dynamic consumption does not include I/O toggling,
which is highly dependent on the application. Details of the software configuration are separately. The total device
consumption is IDD_LV + IDD_HV + IDD_LKG for the selected temperature.
5. Gateway use case: One core running at 80 MHz, DMA, PLL, FLASH read only 25%, 7xCAN, 1xSARADC.
6. Flash in Low Power. Sysclk at 80 MHz, PLL0_PHI at 80 MHz, XTAL at 8 MHz, FIRC 16 MHz ON, RCOSC1M off. FlexCAN:
instances: 0, 1, 2, 3, 4, 5, 6 ON (configured but no reception or transmission), ADC ON (continuously converting). All others
IPs clock-gated.
7. Sysclk = RC16 MHz, RC16 MHz ON, RC1 MHz ON, PLL OFF. All possible peripherals off and clock gated. Flash in power
down mode.
8. STANDBY mode: device configured for minimum consumption, RC16 MHz off, RC1 MHz on.

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3.8 I/O pad specification

The following table describes the different pad type configurations.

Table 9. I/O pad specification descriptions

Pad type Description

Weak configuration Provides a good compromise between transition time and low electromagnetic emission.
Medium configuration Provides transition fast enough for the serial communication channels with controlled
current to reduce electromagnetic emission.
Strong configuration Provides fast transition speed; used for fast interface.
Very strong Provides maximum speed and controlled symmetric behavior for rise and fall transition.
configuration Used for fast interface requiring fine control of rising/falling edge jitter.
Input only pads These low input leakage pads are associated with the ADC channels.
Standby pads Some pads are active during Standby. Low Power Pads input buffer can only be
configured in TTL mode. When the pads are in Standby mode, the Pad-Keeper feature is
activated: if the pad status is high, the weak pull-up resistor is automatically enabled; if
the pad status is low, the weak pull-down resistor is automatically enabled.

Note: Each I/O pin on the device supports specific drive configurations. See the signal description
table in the device reference manual for the available drive configurations for each I/O pin.
PMC_DIG_VSIO register has to be configured to select the voltage level (3.3 V or 5.0 V) for
each IO segment.
Logic level is configurable in running mode while it is TTL not-configurable in STANDBY for
LP (low power) pads, so if a LP pad is used to wakeup from STANDBY, it should be
configured as TTL also in running mode in order to prevent device wrong behavior in
STANDBY.

3.8.1 I/O input DC characteristics

The following table provides input DC electrical characteristics, as described in Figure 3.

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Figure 3. I/O input electrical characteristics

VIN
VDD

VIH

VHYS

VIL

VINTERNAL
(SIUL register)

Table 10. I/O input electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

TTL

Vihttl SR P Input high level — 2 — VDD_HV_IO V

TTL + 0.3
Vilttl SR P Input low level — –0.3 — 0.8 V
TTL
Vhysttl CC C Input hysteresis — 0.3 — — V
TTL

CMOS

Vihcmos SR P Input high level — 0.65 * VDD — VDD_HV_IO V

CMOS + 0.3
Vilcmos SR P Input low level — –0.3 — 0.35 * VDD V
CMOS
Vhyscmos CC C Input hysteresis — 0.10 * VDD — — V
CMOS

COMMON

ILKG CC P Pad input INPUT-ONLY pads — — 200 nA

leakage TJ = 150 °C
ILKG CC P Pad input STRONG pads — — 1,000 nA
leakage TJ = 150 °C
ILKG CC P Pad input VERY STRONG pads, — — 1,000 nA
leakage TJ = 150 °C

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Table 10. I/O input electrical characteristics (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

CP1 CC D Pad — — — 10 pF
capacitance
Vdrift CC D Input Vil/Vih In a 1 ms period, with a — — 100 mV
temperature temperature variation
drift <30 °C
WFI SR C Wakeup input — — — 20 ns
filtered pulse(1)
WNFI SR C Wakeup input — 400 — — ns
not filtered
pulse(1)
1. In the range from WFI (max) to WNFI (min), pulses can be filtered or not filtered, according to operating temperature and
voltage. Refer to the device pinout IO definition excel file for the list of pins supporting the wakeup filter feature.

Table 11. I/O pull-up/pull-down electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

IWPU CC T Weak pull-up VIN = 1.1 V(1) — — 130 A

current
absolute value
P VIN = 0.69 * 15 — —
VDD_HV_IO(2)
RWPU CC D Weak Pull-up VDD_HV_IO = 5.0 V ± 33 — 93 K
resistance 10%
RWPU CC D Weak Pull-up VDD_HV_IO = 3.3 V ± 19 — 62 K
resistance 10%
IWPD CC T Weak pull- VIN = 0.69 * — — 130 A
down current VDD_HV_IO(1)
absolute value
P VIN = 0.9 V(2) 15 — —

RWPD CC D Weak Pull- VDD_HV_IO = 5.0 V ± 29 — 60 K

down 10%
resistance
RWPD CC D Weak Pull- VDD_HV_IO = 3.3 V ± 19 — 60 K
down 10%
resistance
1. Maximum current when forcing a change in the pin level opposite to the pull configuration.
2. Minimum current when keeping the same pin level state than the pull configuration.

Note: When the device enters into standby mode, the LP pads have the input buffer switched-on.
As a consequence, if the pad input voltage VIN is VSS<VIN<VDD_HV, an additional
consumption can be measured in the VDD_HV domain. The highest consumption can be
seen around mid-range (VIN ~=VDD_HV/2), 2-3mA depending on process, voltage and

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temperature.
This situation may occur if the PAD is used as a ADC input channel, and VSS<VIN<VDD_HV.
The applications should ensure that LP pads are always set to VDD_HV or VSS, to avoid
the extra consumption. Please refer to the device pinout IO definition excel file to identify the
low-power pads which also have an ADC function.

3.8.2 I/O output DC characteristics

Figure 4 provides description of output DC electrical characteristics.

Figure 4. I/O output DC electrical characteristics definition

VINTERNAL
(SIUL register)

VHYS

Vout tSKEW20-80

90%
80%

20%
10%

tR20-80
tF20-80
tR10-90
tF10-90

tTR(max) = MAX(tR10-90; tF10-90) tTR20-80(max) = MAX(tR20-80; tF20-80)

tTR(min) = MIN(tR10-90; tF10-90) tTR20-80(min) = MIN(tR20-80; tF20-80)
tSKEW20-80 = tR20-80-tF20-80
tSKEW10-90 = tR10-90-tF10-90

The following tables provide DC characteristics for bidirectional pads:

 Table 12 provides output driver characteristics for I/O pads when in WEAK/SLOW
configuration.
 Table 13 provides output driver characteristics for I/O pads when in MEDIUM
configuration.
 Table 14 provides output driver characteristics for I/O pads when in STRONG/FAST
configuration.
 Table 15 provides output driver characteristics for I/O pads when in VERY
STRONG/VERY FAST configuration.
Note: 10%/90% is the default condition for any parameter if not explicitly mentioned differently.

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Table 12. WEAK/SLOW I/O output characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Vol_W CC D Output low Iol = 0.5 mA — — 0.1*VDD V

voltage for Weak VDD = 5.0 V ± 10%
type PADs VDD = 3.3 V ± 10%
Voh_W CC D Output high Ioh = 0.5 mA 0.9*VDD — — V
voltage for Weak VDD = 5.0 V ± 10%
type PADs VDD = 3.3 V ± 10%
R_W CC P Output VDD = 5.0 V ± 10% 380 — 1040 
impedance for
VDD = 3.3 V ± 10% 250 — 700
Weak type PADs
Fmax_W CC T Maximum output CL = 25 pF — — 2 MHz
frequency for VDD = 5.0 V ± 10%
Weak type PADs V = 3.3 V ± 10%
DD

CL = 50 pF — — 1 MHz
VDD = 5.0 V ± 10%
VDD = 3.3 V ± 10%
tTR_W CC T Transition time CL = 25 pF 25 — 120 ns
output pin VDD = 5.0 V + 10%
weak VDD = 3.3 V + 10%
configuration,
10%-90% CL = 50 pF 50 — 240 ns
VDD = 5.0 V ± 10%
VDD = 3.3 V ± 10%
tSKEW_W CC T Difference — — — 25 %
between rise
and fall time,
90%-10%
IDCMAX_W CC D Maximum DC VDD = 5.0 V ± 10% — — 0.5 mA
current VDD = 3.3 V ± 10%

Table 13. MEDIUM I/O output characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Vol_M CC D Output low Iol = 2.0 mA — — 0.1*VDD V

voltage for VDD =5.0 V ± 10%
Medium type VDD =3.3 V ± 10%
PADs
Voh_M CC D Output high Ioh=2.0 mA 0.9*VDD — — V
voltage for VDD = 5.0 V ± 10%
Medium type VDD = 3.3 V ± 10%
PADs

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Table 13. MEDIUM I/O output characteristics (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

R_M CC P Output VDD = 5.0 V ± 10% 90 — 260 

impedance for
VDD = 3.3 V ± 10% 60 — 170
Medium type
PADs
Fmax_M CC T Maximum output CL = 25 pF — — 12 MHz
frequency for VDD = 5.0 V ± 10%
Medium type VDD = 3.3 V ± 10%
PADs
CL = 50 pF — — 6 MHz
VDD = 5.0 V ± 10%
VDD = 3.3 V ± 10%
tTR_M CC T Transition time CL = 25 pF 8 — 30 ns
output pin VDD = 5.0 V ± 10%
MEDIUM VDD = 3.3 V ± 10%
configuration,
10%-90% CL = 50 pF 12 — 60 ns
VDD = 5.0 V ± 10%
VDD = 3.3 V ± 10%
tSKEW_M CC T Difference — — — 25 %
between rise
and fall time,
90%-10%
IDCMAX_M CC D Maximum DC VDD = 5.0 V ± 10% — — 2 mA
current VDD = 3.3 V ± 10%

Table 14. STRONG/FAST I/O output characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Vol_S CC D Output low Iol = 8.0 mA — — 0.1*VDD V

voltage for VDD = 5.0 V ± 10%
Strong type
Iol = 5.5 mA — — 0.15*VDD V
PADs
VDD =3 .3 V ± 10%
Voh_S CC D Output high Ioh = 8.0 mA 0.9*VDD — — V
voltage for VDD = 5.0 V ± 10%
Strong type
Ioh = 5.5 mA 0.85*VDD — — V
PADs
VDD = 3.3 V ± 10%
R_S CC P Output VDD = 5.0 V ± 10% 20 — 65 
impedance for
VDD = 3.3 V ± 10% 28 — 90
Strong type
PADs

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Table 14. STRONG/FAST I/O output characteristics (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Fmax_S CC T Maximum output CL = 25 pF — — 50 MHz

frequency for VDD=5.0 V ± 10%
Strong type
PADs CL = 50 pF — — 25 MHz
VDD=5.0 V ± 10%
CL = 25 pF — — 25 MHz
VDD = 3.3 V ± 10%
CL = 50 pF — — 12.5 MHz
VDD = 3.3 V ± 10%
tTR_S CC T Transition time CL = 25 pF 3 — 10 ns
output pin VDD = 5.0 V ± 10%
STRONG
configuration, CL = 50 pF 5 — 16
10%-90% VDD = 5.0 V ± 10%
CL = 25 pF 1.5 — 15
VDD = 3.3 V ± 10%
CL = 50 pF 2.5 — 26
VDD = 3.3 V ± 10%
IDCMAX_S CC D Maximum DC VDD = 5 V ± 10% — — 8 mA
current
VDD = 3.3 V ± 10% — — 5.5
tSKEW_S CC T Difference — — — 25 %
between rise
and fall time,
90%-10%

Table 15. VERY STRONG/VERY FAST I/O output characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Vol_V CC D Output low Iol = 9.0 mA — — 0.1*VDD V

voltage for Very VDD =5.0 V ± 10%
Strong type
Iol = 9.0 mA — — 0.15*VDD V
PADs
VDD =3.3 V ± 10%
Voh_V CC D Output high Ioh = 9.0 mA 0.9*VDD — — V
voltage for Very VDD = 5.0 V ± 10%
Strong type
Ioh = 9.0 mA 0.85*VDD — — V
PADs
VDD = 3.3 V ± 10%
R_V CC P Output VDD = 5.0 V ± 10% 20 — 60 
impedance for
VDD = 3.3 V ± 10% 18 — 50
Very Strong type
PADs

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Table 15. VERY STRONG/VERY FAST I/O output characteristics (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Fmax_V CC T Maximum output CL = 25 pF — — 50 MHz

frequency for VDD = 5.0 V ± 10%
Very Strong type
PADs CL = 50 pF — — 25 MHz
VDD = 5.0 V ± 10%
CL = 25 pF — — 50 MHz
VDD = 3.3 V ± 10%
CL = 50 pF — — 25 MHz
VDD = 3.3 V ± 10%
tTR_V CC T 10–90% CL = 25 pF 1 — 6 ns
threshold VDD = 5.0 V ± 10%
transition time
output pin VERY CL = 50 pF 3 — 12
STRONG VDD = 5.0 V ± 10%
configuration
CL = 25 pF 1.5 — 6
VDD = 3.3 V ± 10%
CL = 50 pF 3 — 11
VDD = 3.3 V ± 10%
tTR20-80_V CC T 20–80% CL = 25 pF 0.8 — 4.5 ns
threshold VDD = 5.0 V ± 10%
transition time
output pin VERY CL = 15 pF 1 — 4.5
STRONG VDD = 3.3 V ± 10%
configuration
(Flexray
Standard)
tTRTTL_V CC T TTL threshold CL = 25 pF 0.88 — 5 ns
transition time VDD = 3.3 V ± 10%
for output pin in
VERY STRONG
configuration
(Ethernet
standard)
tTR20-80_V CC T Sum of CL = 25 pF — — 9 ns
transition time VDD = 5.0 V ± 10%
20–80% output
pin VERY CL = 15 pF — — 9
STRONG VDD = 3.3 V ± 10%
configuration
tSKEW_V CC T Difference CL = 25 pF 0 — 1.2 ns
between rise VDD = 5.0 V ± 10%
and fall delay
IDCMAX_V CC D Maximum DC VDD = 5.0 V±10% — — 9 mA
current VDD = 3.3 V ± 10%

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3.8.3 I/O pad current specifications

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a VDD/VSS supply pair as described in the device pinout IO definition excel
file.
Table 16 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment
should remain below the IRMSSEG maximum value.
In order to ensure device functionality, the sum of the dynamic and static current of the I/O
on a single segment should remain below the IDYNSEG maximum value.
Pad mapping on each segment can be optimized using the pad usage information provided
on the I/O Signal Description table.

Table 16. I/O consumption(1)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Average consumption(2)

IRMSSEG SR D Sum of all the DC I/O current — — — 80 mA

within a supply segment
IRMS_W CC D RMS I/O current for WEAK CL = 25 pF, 2 MHz, — — 1.1 mA
configuration VDD = 5.0 V ± 10 %
CL = 50 pF, 1 MHz, — — 1.1
VDD = 5.0 V ± 10 %
CL = 25 pF, 2 MHz, — — 1.0
VDD = 3.3 V ± 10 %
CL = 25 pF, 1 MHz, — — 1.0
VDD = 3.3 V ± 10%
IRMS_M CC D RMS I/O current for MEDIUM CL = 25 pF, 12 MHz, — — 5.5 mA
configuration VDD = 5.0 V ± 10%
CL = 50 pF, 6 MHz, — — 5.5
VDD = 5.0 V ± 10%
CL = 25 pF, 12 MHz, — — 4.2
VDD = 3.3 V ± 10%
CL = 25 pF, 6 MHz, — — 4.2
VDD = 3.3 V ± 10%
IRMS_S CC D RMS I/O current for STRONG CL = 25 pF, 50 MHz, — — 21 mA
configuration VDD = 5.0 V ± 10%
CL = 50 pF, 25 MHz, — — 21
VDD = 5.0 V ± 10%
CL = 25 pF, 25 MHz, — — 10
VDD = 3.3 V ± 10%
CL = 25 pF, 12.5 MHz, — — 10
VDD = 3.3 V ± 10%

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Table 16. I/O consumption(1) (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

IRMS_V CC D RMS I/O current for VERY CL = 25 pF, 50 MHz, — — 23 mA

STRONG configuration VDD = 5.0 V ± 10%
CL = 50 pF, 25 MHz, — — 23
VDD = 5.0 V ± 10%
CL = 25 pF, 50 MHz, — — 16
VDD = 3.3 V ± 10%
CL = 25 pF, 25 MHz, — — 16
VDD = 3.3 V ± 10%

Dynamic consumption(3)

IDYN_SEG SR D Sum of all the dynamic and DC VDD = 5.0 V ± 10% — — 195 mA
I/O current within a supply
VDD = 3.3 V ± 10% — — 150
segment
IDYN_W CC D Dynamic I/O current for WEAK CL = 25 pF, VDD = 5.0 V ± — — 16.7 mA
configuration 10%
CL = 50 pF, VDD = 5.0 V ± — — 16.8
10%
CL = 25 pF, VDD = 3.3 V ± — — 12.9
10%
CL = 50 pF, VDD = 3.3 V ± — — 12.9
10%
IDYN_M CC D Dynamic I/O current for CL = 25 pF, VDD = 5.0 V ± — — 18.2 mA
MEDIUM configuration 10%
CL = 50 pF, VDD = 5.0 V ± — — 18.4
10%
CL = 25 pF, VDD = 3.3 V ± — — 14.3
10%
CL = 50 pF, VDD = 3.3 V ± — — 16.4
10%
IDYN_S CC D Dynamic I/O current for CL = 25 pF, VDD = 5.0 V ± — — 57 mA
STRONG configuration 10%
CL = 50 pF, VDD = 5.0 V ± — — 63.5
10%
CL = 25 pF, VDD = 3.3 V ± — — 31
10%
CL = 50 pF, VDD = 3.3 V ± — — 33.5
10%

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Table 16. I/O consumption(1) (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

IDYN_V CC D Dynamic I/O current for VERY CL = 25 pF, VDD = 5.0 V ± — — 62 mA

STRONG configuration 10%
CL = 50 pF, VDD = 5.0 V ± — — 70
10%
CL = 25 pF, VDD = 3.3 V ± — — 52
10%
CL = 50 pF, VDD = 3.3 V ± — — 55
10%
1. I/O current consumption specifications for the 4.5 V  VDD_HV_IO  5.5 V range are valid for VSIO_[VSIO_xx] = 1, and
VSIO[VSIO_xx] = 0 for 3.0 V  VDD_HV_IO  3.6 V.
2. Average consumption in one pad toggling cycle.
3. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. When possible (timed
output) it is recommended to delay transition between pads by few cycles to reduce noise and consumption.

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3.9 Reset pad (PORST) electrical characteristics

The device implements dedicated bidirectional reset pins as below specified. PORST pin
does not require active control. It is possible to implement an external pull-up to ensure
correct reset exit sequence. Recommended value is 4.7 K.

Figure 5. Startup Reset requirements

VDD

VDDMIN

VDD_POR

PORST

VIH

VIL

device start-up phase

PORST undriven device reset
PORST driven low
device reset by by internal power-on reset forced by external circuitry
internal power-on reset

Figure 6 describes device behavior depending on supply signal on PORST:

1. PORST low pulse has too low amplitude: it is filtered by input buffer hysteresis. Device
remains in current state.
2. PORST low pulse has too short duration: it is filtered by low pass filter. Device remains
in current state.
3. PORST low pulse is generating a reset:
a) PORST low but initially filtered during at least WFRST. Device remains initially in
current state.
b) PORST potentially filtered until WNFRST. Device state is unknown. It may either
be reset or remains in current state depending on extra condition (temperature,
voltage, device).
c) PORST asserted for longer than WNFRST. Device is under reset.

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Figure 6. Noise filtering on reset signal

VPORST

VDD

VIH
VHYS

VIL

internal
reset

filtered by
filtered by filtered by unknown reset
hysteresis lowpass filter lowpass filter state device under hardware reset

WFRST WFRST
WNFRST

1 2 3a 3b 3c

Table 17. Reset PAD electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

VIHRES SR P Input high level VDD_HV = 5.0 V ± 10% 2 — VDD_HV_IO V

TTL VDD_HV = 3.3 V ±10% +0.3

VILRES SR P Input low level VDD_HV = 5.0 V ± 10% -0.3 — 0.8 V

TTL
VDD_HV = 3.3 V ± 10% -0.3 — 0.6
VHYSRES CC C Input hysteresis VDD_HV = 5.0 V ± 10% 0.3 — — V
TTL
VDD_HV = 3.3 V ± 10% 0.2 — —
VDD_POR CC D Minimum supply VDD_HV = 5.0 V ± 10% — — 1.6 V
for strong pull-
VDD_HV = 3.3 V ± 10% — — 1.05
down activation

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Electrical characteristics SPC582B60x, SPC582B54x, SPC582B50x

Table 17. Reset PAD electrical characteristics (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

IOL_R CC P Strong pull-down VDD_HV = 5.0 V ± 10% 12 — — mA

current (1)
VDD_HV = 3.3 V ± 10% 8 — —
(2) A
IWPU CC P Weak pull-up VIN = 1.1 V — — 130
current absolute VDD_HV = 5.0 V ± 10%
value
P VIN = 1.1 V — — 70
VDD_HV = 3.3 V ± 10%
P VIN = 0.69 * 15 — —
VDD_HV_IO(3)
VDD_HV = 5.0 V ± 10%
P VIN = 0.69 * VDD_HV_IO 15 — —
VDD_HV = 3.3 V ± 10%
IWPD CC P Weak pull-down VIN = 0.69 * — — 130 A
current absolute VDD_HV_IO(2)
value VDD_HV = 5.0 V ± 10%
P VIN = 0.69 * — — 80
VDD_HV_IO(2)
VDD_HV = 3.3 V ± 10%
P VIN = 0.9 V 15 — —
VDD_HV = 5.0 V ± 10%
P VIN = 0.9 V 15 — —
VDD_HVDD_HV = 3.3 V
± 10%
WFRST CC P Input filtered VDD_HV = 5.0 V ± 10% — — 500 ns
pulse
P VDD_HV = 3.3 V ± 10% — — 600
WNFRST CC P Input not filtered VDD_HV = 5.0 V ± 10% 2000 — — ns
pulse
P VDD_HV = 3.3 V ± 10% 3000 — —
1. Iol_r applies to PORST: Strong Pull-down is active on PHASE0 for PORST. Refer to the device pinout IO definition excel file
for details regarding pin usage.
2. Maximum current when forcing a change in the pin level opposite to the pull configuration.
3. Minimum current when keeping the same pin level state than the pull configuration.

Table 18. Reset Pad state during power-up and reset

PAD POWER-UP State RESET state DEFAULT state(1) STANDBY state

PORST Strong pull-down Weak pull-down Weak pull-down Weak pull-up

1. Before SW Configuration. Please refer to the Device Reference Manual, Reset Generation Module (MC_RGM) Functional
Description chapter for the details of the power-up phases.

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3.10 PLLs
Two phase-locked loop (PLL) modules are implemented to generate system and auxiliary
clocks on the device.
Figure 7 depicts the integration of the two PLLs. Please, refer to device Reference Manual
for more detailed schematic.

Figure 7. PLLs integration

IRCOSC PLL0_PHI
PLL0 PLL0_PHI1

XOSC

PLL1_PHI
PLL1

3.10.1 PLL0
Table 19. PLL0 electrical characteristics
Value
Symbol C Parameter Conditions Unit
Min Typ Max

fPLL0IN SR — PLL0 input clock(1) — 8 — 44 MHz

PLL0 input clock duty
PLL0IN SR — — 40 — 60 %
cycle(1)
PLL0 PFD (Phase
fINFIN SR — Frequency Detector) input — 8 — 20 MHz
clock frequency
fPLL0VCO CC P PLL0 VCO frequency — 600 — 1400 MHz
fPLL0PHI0 CC D PLL0 output frequency — 4.762 — FSYS(2) MHz
fPLL0PHI1 CC D PLL0 output clock PHI1 — 20 — 175(3) MHz
tPLL0LOCK CC P PLL0 lock time — — — 100 µs
PLL0_PHI0 single period
jitter fPLL0PHI0 = 400 MHz,
PLL0PHI0SPJ |(4) CC D — — 200 ps
fPLL0IN = 20 MHz 6-sigma pk-pk
(resonator)

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Table 19. PLL0 electrical characteristics (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

PLL0_PHI1 single period

(4) jitter fPLL0PHI1 = 40 MHz,
PLL0PHI1SPJ| CC T — — 300(5) ps
fPLL0IN = 20 MHz 6-sigma pk-pk
(resonator)
10 periods
accumulated jitter
(80 MHz equivalent — — ±250 ps
frequency), 6-sigma
pk-pk
PLL0 output long term
16 periods
jitter(5)
(4) accumulated jitter
PLL0LTJ CC T fPLL0IN = 20 MHz (50 MHz equivalent — — ±300 ps
(resonator), VCO frequency), 6-sigma
frequency = 800 MHz pk-pk
long term jitter
(< 1 MHz equivalent
— — ±500 ps
frequency), 6-sigma
pk-pk)
IPLL0 CC T PLL0 consumption FINE LOCK state — — 6 mA
1. PLL0IN clock retrieved directly from either internal RCOSC or external FXOSC clock. Input characteristics are granted
when using internal RCOSC or external oscillator is used in functional mode.
2. Please refer to Section 3.3: Operating conditions for the maximum operating frequency.
3. If the PLL0_PHI1 is used as an input for PLL1, then the PLL0_PHI1 frequency shall obey the maximum input frequency
limit set for PLL1 (87.5 MHz, according to Table 20).
4. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to
the output CLKOUT pin.
5. VDD_LV noise due to application in the range VDD_LV = 1.20 V±5%, with frequency below PLL bandwidth (40 kHz) will be
filtered.

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3.10.2 PLL1
PLL1 is a frequency modulated PLL with Spread Spectrum Clock Generation (SSCG)
support.

Table 20. PLL1 electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

fPLL1IN SR — PLL1 input clock(1) — 37.5 — 87.5 MHz

PLL1 input clock duty
PLL1IN SR — — 35 — 65 %
cycle(1)
PLL1 PFD (Phase
fINFIN SR — Frequency Detector) — 37.5 87.5 MHz
input clock frequency
fPLL1VCO CC P PLL1 VCO frequency — 600 — 1400 MHz
fPLL1PHI0 CC D PLL1 output clock PHI0 — 4.762 — FSYS(2) MHz
tPLL1LOCK CC P PLL1 lock time — — — 50 µs
PLL1 modulation
fPLL1MOD CC T — — — 250 kHz
frequency

PLL1 modulation depth Center spread(3) 0.25 — 2 %

PLL1MOD| CC T
(when enabled) Down spread 0.5 — 4 %
PLL1PHI0SPJ| PLL1_PHI0 single period fPLL1PHI0 =
(4) CC T — — 500(5) ps
peak to peak jitter 200 MHz, 6-sigma
IPLL1 CC T PLL1 consumption FINE LOCK state — — 5 mA
1. PLL1IN clock retrieved directly from either internal PLL0 or external FXOSC clock. Input characteristics are granted when
using internal PPL0 or external oscillator is used in functional mode.
2. Please refer to Section 3.3: Operating conditions for the maximum operating frequency.
3. The device maximum operating frequency FSYS (max) includes the frequency modulation. If center modulation is selected,
the FSYS must be below the maximum by MD (Modulation Depth Percentage), such that FSYS(max)=FSYS(1+MD%).
Please refer to the Reference Manual for the PLL programming details.
4. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to
the output CLKOUT pin.
5. 1.25 V±5%, application noise below 40 kHz at VDD_LV pin - no frequency modulation.

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3.11 Oscillators

3.11.1 Crystal oscillator 40 MHz

Table 21. External 40 MHz oscillator electrical specifications

Value
Symbol C Parameter Conditions Unit
Min Max

fXTAL CC D Crystal Frequency — 4(2) 8 MHz

Range(1)
>8 20
>20 40
(3),(4)
tcst CC T Crystal start-up time TJ = 150 °C — 5 ms
trec CC D Crystal recovery time(5) — — 0.5 ms
VIHEXT CC D EXTAL input high VREF = 0.29 * VDD_HV_OSC VREF + — V
voltage(6) (External 0.75
Reference)
VILEXT CC D EXTAL input low VREF = 0.29 * VDD_HV_OSC — VREF - V
voltage(6) (External 0.75
Reference)
CS_EXTAL CC D Total on-chip stray — 3 7 pF
capacitance on EXTAL
pin(7)
CS_XTAL CC D Total on-chip stray — 3 7 pF
capacitance on XTAL
pin(7)
gm CC P Oscillator fXTAL 4 8 MHz 3.9 13.6 mA/V
Transconductance freq_sel[2:0] = 000
D fXTAL  5 - 10 MHz 5 17.5
freq_sel[2:0] = 001
D fXTAL  10  15 MHz 8.6 29.3
freq_sel[2:0] = 010
P fXTAL 15 - 20 MHz 14.4 48
freq_sel[2:0] = 011
D fXTAL  20 - 25 MHz 21.2 69
freq_sel[2:0] = 100
D fXTAL  25  30 MHz 27 86
freq_sel[2:0] = 101
D fXTAL 30 - 35 MHz 33.5 115
freq_sel[2:0] = 110
P fXTAL 35 - 40 MHz 33.5 115
freq_sel[2:0] = 111
VEXTAL CC D Oscillation Amplitude on TJ = –40 °C to 150 °C 0.5 1.8 V
the EXTAL pin after
startup(8)

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Table 21. External 40 MHz oscillator electrical specifications (continued)

Value
Symbol C Parameter Conditions Unit
Min Max

VHYS CC D Comparator Hysteresis TJ = –40 °C to 150 °C 0.1 1.0 V

IXTAL (8),(9)
CC D XTAL current TJ = –40 °C to 150 °C — 14 mA
1. The range is selectable by UTEST miscellaneous DCF client XOSC_FREQ_SEL.
2. The XTAL frequency, if used to feed the PPL0 (or PLL1), shall obey the minimum input frequency limit set for PLL0 (or
PLL1).
3. This value is determined by the crystal manufacturer and board design, and it can potentially be higher than the maximum
provided.
4. Proper PC board layout procedures must be followed to achieve specifications.
5. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load
capacitor value.
6. Applies to an external clock input and not to crystal mode.
7. See crystal manufacturer’s specification for recommended load capacitor (CL) values.The external oscillator requires
external load capacitors when operating from 8 MHz to 16 MHz. Account for on-chip stray capacitance (CS_EXTAL/CS_XTAL)
and PCB capacitance when selecting a load capacitor value. When operating at 20 MHz/40 MHz, the integrated load
capacitor value is selected via S/W to match the crystal manufacturer’s specification, while accounting for on-chip and PCB
capacitance.
8. Amplitude on the EXTAL pin after startup is determined by the ALC block, that is the Automatic Level Control Circuit. The
function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation in order to
reduce power, distortion, and RFI, and to avoid over driving the crystal. The operating point of the ALC is dependent on the
crystal value and loading conditions.
9. IXTAL is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum
current during startup of the oscillator.

3.11.2 RC oscillator 16 MHz

Table 22. Internal RC oscillator electrical specifications

Value
Symbol C Parameter Conditions Unit
Min Typ Max

fTarget CC D IRC target frequency — — 16 — MHz

fvar_noT CC P IRC frequency variation T < 150 °C –5 — 5 %
without temperature
compensation
fvar_T CC T IRC frequency variation T < 150 °C –3 — 3 %
with temperature
compensation
fvar_SW T IRC software trimming Trimming –0.5 +0.3 0.5 %
accuracy temperature
Tstart_noT CC T Startup time to reach within Factory — — 5 µs
fvar_noT trimming
already
applied

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Electrical characteristics SPC582B60x, SPC582B54x, SPC582B50x

Table 22. Internal RC oscillator electrical specifications (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Tstart_T CC T Startup time to reach within Factory — — 120 µs

fvar_T trimming
already
applied
IFIRC CC T Current consumption on HV After Tstart_T — — 600 µA
power supply(1)
1. The consumption reported considers the sum of the RC oscillator 16 MHz IP, and the core logic clocked by the IP during
Standby mode.

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3.11.3 Low power RC oscillator

Table 23. 1024 kHz internal RC oscillator electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Fsirc CC T Slow Internal — — 1024 — kHz

RC oscillator
frequency
fvar_T CC P Frequency –40 °C < T < –9 — +9 %
variation across 150 °C
temperature
fvar_V CC P Frequency –40 °C < T < –5 — +5 %
variation across 150 °C
voltage
Isirc CC T Slow Internal T = 55 °C — — 6 µA
RC oscillator
current
Tsirc CC T Start up time, — — — 12 µS
after switching
ON the internal
regulator.

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Electrical characteristics SPC582B60x, SPC582B54x, SPC582B50x

3.12 ADC system

3.12.1 ADC input description

Figure 8 shows the input equivalent circuit for SARn and SARB channels.

Figure 8. Input equivalent circuit (Fast SARn and SARB channels)

INTERNAL CIRCUIT SCHEME

VDD
Channel
Sampling
Selection

RSW1 RAD

CP1 CP2 CS

RCMSW Common mode

RSW1: Channel Selection Switch Impedance switch
RAD: Sampling Switch Impedance
CP : Pin Capacitance (two contributions, CP1 and CP2)
RCMRL Common mode
CS : Sampling Capacitance resistive ladder

RCMSW: Common mode switch

VCM
RCMRL: Common mode resistive ladder
VCM : Common mode voltage (~0.5 VDD)

The above figure can be used as approximation circuitry for external filtering definition.

Table 24. ADC pin specification(1)

Value
Symbol C Parameter Conditions Unit
Min Max

R20K CC D Internal voltage reference source — 16 30 K

impedance.
ILKG CC — Input leakage current, two ADC See IO chapter Table 10: I/O input electrical
channels on input-only pin. characteristics, parameter ILKG
IINJ1 SR — Injection current on analog input See Operating Conditions chapter Table 5:
preserving functionality at full or Operating conditions, IINJ1 parameter.
degraded performances.
CHV_ADC SR D VDD_HV_ADV external capacitance. See Power Management chapter Table 27: External
components integration, CADC parameter.
CP1 CC D Pad capacitance See IO chapter Table 10: I/O input electrical
characteristics, parameter CP1
CP2 CC D Internal routing capacitance — — 2 pF
CS CC D SAR ADC sampling capacitance — — 5 pF
RSWn CC D Analog switches resistance — 0 1.8 k

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Table 24. ADC pin specification(1) (continued)

Value
Symbol C Parameter Conditions Unit
Min Max

RAD CC D ADC input analog switches SARn 12bit — 0.8 k

resistance
RCMSW CC D Common mode switch resistance sum of the two — 9 k
resistances
RCMRL CC D Common mode resistive ladder k
RSAFEPD(2) CC D Discharge resistance for ADC VDD_HV_IO = 5.0 V ± 10% — 300 
input-only pins (strong pull-down
VDD_HV_IO = 3.3 V ± 10% — 500 
for safety)
1. All specifications in this table valid for the full input voltage range for the analog inputs.
2. It enables discharge of up to 100 nF from 5 V every 300 ms. Please refer to the device pinout IO definition excel file for the
pads supporting it.

3.12.2 SAR ADC 12 bit electrical specification

The SARn ADCs are 12-bit Successive Approximation Register analog-to-digital converters
with full capacitive DAC. The SARn architecture allows input channel multiplexing.

Table 25. SARn ADC electrical specification(1)

Value
Symbol C Parameter Conditions Unit
Min Max

fADCK SR P Clock frequency Standard frequency mode 7.5 13.33 MHz

T High frequency mode >13.33 16.0
tADCINIT SR — ADC initialization time — 1.5 — µs
tADCBIASINIT SR — ADC BIAS — 5 — µs
initialization time
tADCPRECH SR T ADC decharge time Fast channel 1/fADCK — µs
Standard channel 2/fADCK —
VPRECH SR D Decharge voltage TJ < 150 °C 0 0.25 V
precision
R20K CC D Internal voltage — 16 30 K
reference source
impedance
VINTREF CC P Internal reference Applies to all internal 0.20 0.20 V
voltage precision reference points
(VSS_HV_ADR,
1/3 * VDD_HV_ADR,
2/3 * VDD_HV_ADR,
VDD_HV_ADR)

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Electrical characteristics SPC582B60x, SPC582B54x, SPC582B50x

Table 25. SARn ADC electrical specification(1) (continued)

Value
Symbol C Parameter Conditions Unit
Min Max

tADCSAMPLE SR P ADC sample time(2) Fast channel – 12-bit 6/fADCK — µs

configuration
D Fast channel – 10-bit 6/fADCK
configuration mode 1(3)
(Standard frequency mode
only)
Fast channel – 10-bit 5/fADCK
configuration mode 2(4)
(Standard frequency mode
only)
Fast channel – 10-bit 6/fADCK
configuration mode 3(5)
(High frequency mode only)
Standard channel– 12-bit 12/fADCK
configuration
Standard channel– 10-bit 12/fADCK
configuration mode 1(3)
(Standard frequency mode
only)
Standard channel – 10-bit 10/fADCK
configuration mode 2(4)
(Standard frequency mode
only)
Standard channel – 10-bit 12/fADCK
configuration mode 3(5)
(High frequency mode only)
Conversion of BIAS test 40/fADCK
channels through 20 k
input.
tADCEVAL SR P ADC evaluation time 12-bit configuration 12/fADCK — µs
D 10-bit configuration 10/fADCK —
(6),(7)
IADCREFH CC T ADC high reference Run mode — 7 µA
current (average across all codes)
Power Down mode — 1
IADCREFL(7) CC D ADC low reference Run mode — 15 µA
current VDD_HV_ADR_S  5.5 V
Power Down mode — 1
VDD_HV_ADR_S  5.5 V
IADV_S(7) CC P VDD_HV_ADV power Run mode — 4.0 mA
supply current
D Power Down mode — 0.04

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Table 25. SARn ADC electrical specification(1) (continued)

Value
Symbol C Parameter Conditions Unit
Min Max

TUE12 CC T Total unadjusted error TJ < 150 °C, –4 4 LSB

in 12-bit VDD_HV_ADV > 3 V, (12b)
configuration(8) VDD_HV_ADR_S > 3 V
P TJ < 150 °C, –6 6
VDD_HV_ADV > 3 V,
VDD_HV_ADR_S > 3 V
T TJ < 150 °C, –6 6
VDD_HV_ADV > 3 V,
3 V > VDD_HV_ADR_S > 2 V
D High frequency mode, –12 12
TJ < 150 °C,
VDD_HV_ADV > 3 V,
VDD_HV_ADR_S > 3 V
TUE10 CC D Total unadjusted error Mode 1, TJ < 150 °C, –1.5 1.5 LSB
in 10-bit VDD_HV_ADV > 3 V (10b)
configuration(8) VDD_HV_ADR_S > 3 V
D Mode 1, TJ < 150 °C, –2.0 2.0
VDD_HV_ADV > 3 V,
3 V > VDD_HV_ADR_S > 2 V
C Mode 2, TJ < 150 °C, –3.0 3.0
VDD_HV_ADV > 3 V
VDD_HV_ADR_S > 3 V
C Mode 3, TJ < 150 °C, –4.0 4.0
VDD_HV_ADV > 3 V
VDD_HV_ADR_S > 3 V

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Electrical characteristics SPC582B60x, SPC582B54x, SPC582B50x

Table 25. SARn ADC electrical specification(1) (continued)

Value
Symbol C Parameter Conditions Unit
Min Max

TUE12 CC D TUE degradation due VIN < VDD_HV_ADV –1 1 LSB

to VDD_HV_ADR offset VDD_HV_ADR  VDD_HV_ADV (12b)
with respect to [0:25 mV]
VDD_HV_ADV
VIN < VDD_HV_ADV –2 2
VDD_HV_ADR  VDD_HV_ADV
[25:50 mV]
VIN < VDD_HV_ADV –4 4
VDD_HV_ADR  VDD_HV_ADV
[50:75 mV]
VIN < VDD_HV_ADV –6 6
VDD_HV_ADR  VDD_HV_ADV
[75:100 mV]
VDD_HV_ADV < VIN < –2.5 2.5
VDD_HV_ADR
VDD_HV_ADR  VDD_HV_ADV
[0:25 mV]
VDD_HV_ADV < VIN < –4 4
VDD_HV_ADR
VDD_HV_ADR  VDD_HV_ADV
[25:50 mV]
VDD_HV_ADV < VIN < –7 7
VDD_HV_ADR
VDD_HV_ADR  VDD_HV_ADV
[50:75 mV]
VDD_HV_ADV < VIN < –12 12
VDD_HV_ADR
VDD_HV_ADR  VDD_HV_ADV
[75:100 mV]
DNL(8) CC P Differential non- Standard frequency mode, –1 2 LSB
linearity VDD_HV_ADV > 4 V (12b)
VDD_HV_ADR_S > 4 V
T High frequency mode, –1 2
VDD_HV_ADV > 4 V
VDD_HV_ADR_S > 4 V
1. Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.
2. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal
sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within
the sampling window. Please refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC
sizing and calculating the sampling window duration.
3. Mode1: 6 sampling cycles + 10 conversion cycles at 13.33 MHz.
4. Mode2: 5 sampling cycles + 10 conversion cycles at 13.33 MHz.
5. Mode3: 6 sampling cycles + 10 conversion cycles at 16 MHz.

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6. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven
by the transfer of charge between internal capacitances during the conversion.
7. Current parameter values are for a single ADC.
8. TUE and DNL are granted with injection current within the range defined in Table 24, for parameters classified as T and D.

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Electrical characteristics SPC582B60x, SPC582B54x, SPC582B50x

3.13 Power management

The power management module monitors the different power supplies as well as it
generates the required internal supplies. The device can operate in the following
configurations:

Table 26. Power management regulators

Internal Internal
Internal linear linear Internal
External Auxiliary Clamp
Device SMPS regulator regulator standby
regulator regulator regulator
regulator external internal regulator(1)
ballast ballast

SPC582Bxx — — — X — — X
1. Standby regulator is automatically activated when the device enters standby mode.

3.13.1 Power management integration

Use the integration schemes provided below to ensure the proper device function,
according to the selected regulator configuration.
The internal regulators are supplied by VDD_HV_IO_MAIN supply and are used to generate
VDD_LV supply.
Place capacitances on the board as near as possible to the associated pins and limit the
serial inductance of the board to less than 5 nH.
It is recommended to use the internal regulators only to supply the device itself.

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Figure 9. Internal regulator with internal ballast mode

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Figure 10. Standby regulator with internal ballast mode

&)/$

&%9

9''B+9B)/$

9''B+9B,2

966
&( 9''B+9B,2

6WDQGE\ 5HJ &+9Q

9''B/9
966

&/9Q
966

966B+9B$'9 9''B+9B$'9

&$'&

Table 27. External components integration

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Common Components

CE SR D Internal voltage regulator stability — — 1 — µF

external capacitance(2) (3)
RE SR D Stability capacitor equivalent Total resistance including — — 50 m
serial resistance board track
CLVn SR D Internal voltage regulator Each VDD_LV/VSS pair — 47 — nF
decoupling external
capacitance(3) (4) (5)
RLVn SR D Stability capacitor equivalent — — — 50 m
serial resistance

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Table 27. External components integration (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

CBV SR D Bulk capacitance for HV supply(3) — — 4.7 — µF

CHVn SR D Decoupling capacitance for on all VDD_HV_IO/VSS and — 100 — nF
ballast and IOs(3) VDD_HV_ADR/VSS pairs
CFLA SR D Decoupling capacitance for Flash — — 10 — nF
supply(6)
CADC SR D ADC supply external VDD_HV_ADV/VSS_HV_ADV — 0.5 — µF
capacitance(2) pair
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TJ = –40 / 150 °C, unless otherwise specified.
2. Recommended X7R or X5R ceramic –50% / +35% variation across process, temperature, voltage and after aging.
3. CE capacitance is required both in internal and external regulator mode.
4. For noise filtering, add a high frequency bypass capacitance of 10 nF.
5. Forapplications it is recommended to implement at least 5 CLV capacitances.
6. Recommended X7R capacitors. For noise filtering, add a high frequency bypass capacitance of 100 nF.

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3.13.2 Voltage regulators

Table 28. Linear regulator specifications

Value
Symbol C Parameter Conditions Unit
Min Typ Max

VMREG CC P Main regulator output voltage Power-up, before 1.13 1.21 1.29 V
trimming, no load
CC P After trimming, 1.09 1.19 1.26
maximum load
IDDMREG CC T Main regulator current provided to — — — 85 mA
VDD_LV domain

The maximum current required by

the device (IDD_LV) may exceed
the maximum current which can
be provided by the internal linear
regulator. In this case, the internal
regulator mode cannot be used.
IDDCLAMP CC D Main regulator rush current Power-up condition — — 40 mA
sinked from VDD_HV_IO_MAIN
domain during VDD_LV domain
loading
IDDMREG CC T Main regulator output current 20 µs observation -50 — 50 mA
variation window
IMREGINT CC D Main regulator current IMREG = max — — 1.1 mA
consumption
D IMREG = 0 mA — — 1.1

Table 29. Standby regulator specifications

Value
Symbol C Parameter Conditions Unit
Min Typ Max

VSBY CC P Standby regulator output voltage After trimming, 0.92 0.98 1.19 V
maximum load
IDDSBY CC T Standby regulator current — — 0.984 5 mA
provided to VDD_LV domain

3.13.3 Voltage monitors

The monitors and their associated levels for the device are given in Table 30. Figure 11
illustrates the workings of voltage monitoring threshold.

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Figure 11. Voltage monitor threshold definition

VDD_xxx

VHVD

VLVD

TVMFILTER TVMFILTER

HVD TRIGGER
(INTERNAL)

TVMFILTER TVMFILTER

LVD TRIGGER
(INTERNAL)

Table 30. Voltage monitor electrical characteristics

Value(1)
Symbol C Supply/Parameter Conditions Unit
Min Typ Max

PowerOn Reset HV
VPOR200_C CC P VDD_HV_IO_MAIN — 1.80 2.02 2.40 V
Minimum Voltage Detectors HV
VMVD270_C CC P VDD_HV_IO_MAIN — 2.71 2.76 2.80 V
VMVD270_F CC P VDD_HV_FLA — 2.71 2.76 2.80 V
VMVD270_SBY CC P VDD_HV_IO_MAIN (in Standby) — 2.68 2.76 2.84 V
Low Voltage Detectors HV
VLVD290_C CC P VDD_HV_IO_MAIN — 2.89 2.94 2.99 V
VLVD290_F CC P VDD_HV_FLA — 2.89 2.94 2.99 V
VLVD290_AS CC P VDD_HV_ADV (ADCSAR pad) — 2.89 2.94 2.99 V
VLVD400_AS CC P VDD_HV_ADV (ADCSAR pad) — 4.15 4.23 4.31 V
VLVD400_IM CC P VDD_HV_IO_MAIN — 4.15 4.23 4.31 V

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Table 30. Voltage monitor electrical characteristics (continued)

Value(1)
Symbol C Supply/Parameter Conditions Unit
Min Typ Max

Minimum Voltage Detectors LV

VMVD082_C CC P VDD_LV — 0.85 0.88 0.91 V
VMVD094_C CC P VDD_LV — 0.98 1.00 1.02 V
VMVD094_FA CC P VDD_LV (Flash) — 1.00 1.02 1.04 V
VMVD094_FB CC P VDD_LV (Flash) — 1.00 1.02 1.04 V
Low Voltage Detectors LV
VLVD100_C CC P VDD_LV — 1.06 1.08 1.11 V
VLVD100_SB CC P VDD_LV (In Standby) — 0.91 0.93 0.95 V
VLVD100_F CC P VDD_LV (Flash) — 1.08 1.10 1.12 V
High Voltage Detectors LV
VHVD134_C CC P VDD_LV — 1.28 1.31 1.33 V
Upper Voltage Detectors LV
VUVD140_C CC P VDD_LV — 1.34 1.37 1.39 V
Common
TVMFILTER CC D Voltage monitor filter(2) — 5 — 25 s
1. The values reported are Trimmed values, where applicable.
2. See Figure 11. Transitions shorter than minimum are filtered. Transitions longer than maximum are not filtered, and will be
delayed by TVMFILTER time. Transitions between minimum and maximum can be filtered or not filtered, according to
temperature, process and voltage variations.

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3.14 Flash
The following table shows the Wait State configuration.

Table 31. Wait State configuration

RWSC CORE FREQUENCY (MHZ)

2 80
1 54
0 27

The following table shows the Program/Erase Characteristics.

Table 32. Flash memory program and erase specifications

Value

Lifetime
Initial max
Symbol Characteristics(1)(2) Typical max(5) Unit
Typ(3) C end of C
All
25 °C life(4) < 1 K < 250 K
(6) temp C
(7) cycles cycles

Double Word (64 bits)

tdwprogram program time (Partition 0, 2 & 43 C 130 — — 140 500 C µs
3) [Packaged part]
tpprogram Page (256 bits) program time 72 C 240 — — 240 1000 C µs
Page (256 bits) program time
tpprogrameep (partition 0, 2 & 3) [Packaged 83 C 264 — — 276 1000 C µs
part]
Quad Page (1024 bits)
tqprogram 220 C 1040 1200 P 850 2000 C µs
program time
Quad Page (1024 bits)
tqprogrameep program time (partition 0, 2 & 245 C 1140 1320 P 978 2000 C µs
3) [Packaged part]
16 KB block pre-program and
t16kpperase 190 C 450 500 P 190 1000 — C ms
erase time
32 KB block pre-program and
t32kpperase 250 C 520 600 P 230 1200 — C ms
erase time
64 KB block pre-program and
t64kpperase 360 C 700 750 P 420 1600 — C ms
erase time
128 KB block pre-program
t128kpperase 600 C 1300 1600 P 800 4000 — C ms
and erase time
256 KB block pre-program
t256kpperase 1050 C 1800 2400 P 1600 4000 — C ms
and erase time
t16kprogram 16 KB block program time 25 C 45 50 P 40 1000 — C ms
t32kprogram 32 KB block program time 50 C 90 100 P 75 1200 — C ms

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Table 32. Flash memory program and erase specifications (continued)

Value

Lifetime
Initial max
Symbol Characteristics (1)(2) Typical max(5) Unit
Typ(3) C end of C
All
25 °C life(4) < 1 K < 250 K
(6) temp C
(7) cycles cycles

t64kprogram 64 KB block program time 100 C 175 200 P 150 1600 — C ms

t128kprogram 128 KB block program time 200 C 350 430 P 300 2000 — C ms
t256kprogram 256 KB block program time 400 C 700 850 P 590 4000 — C ms
Program 64 KB Data Flash -
t64kprogrameep EEPROM (partition 2) 140 C 200 230 P 256 1750 C ms
[Packaged part]
Erase 64 KB Data Flash -
t64keraseeep EEPROM (partition 2) 300 C 700 825 P 800 3600 C ms
[Packaged part]
s/M
ttr Program rate(8) 2.2 C 2.8 3.40 C 2.4 — C
B
s/M
tpr Erase rate(8) 4.8 C 7.2 9.6 C 6.4 — C
B
s/M
ttprfm Program rate Factory Mode(8) 1.12 C 1.4 1.6 C — — C
B
s/M
terfm Erase rate Factory Mode(8) 4.0 C 5.2 5.8 C — — C
B
tffprogram Full flash programming time(9) 19.8 C 29.3 36.3 P 25.4 — — C s
tfferase Full flash erasing time(9) 41.2 C 66.0 82.4 P 66.0 — — C s
Erase suspend request
tESRT 200 T — — — — — — µs
rate(10)
Program suspend request
tPSRT 30 T — — — — — — µs
rate(10)
Array Integrity Check - Margin
tAMRT 15 T — — — — — — µs
Read suspend request rate
tPSUS Program suspend latency(11) — — — — — — 12 T µs
tESUS Erase suspend latency(11) — — — — — — 22 T µs
Array Integrity Check (10.0
tAIC0S 70 T — — — — — — — ms
MB, sequential)(12)
Array Integrity Check (256
tAIC256KS 1.5 T — — — — — — — ms
KB, sequential)(12)
Array Integrity Check (6.0 MB,
tAIC0P 4.0 T — — — — — — — s
proprietary)(12)

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Table 32. Flash memory program and erase specifications (continued)

Value

Lifetime
Initial max
Symbol Characteristics (1)(2) Typical max(5) Unit
Typ(3) C end of C
All
25 °C life(4) < 1 K < 250 K
(6) temp C
(7) cycles cycles

Margin Read (6.0 MB,

tMR0S 200 T — — — — — — — ms
sequential)(12)
Margin Read (256 KB,
tMR256KS 4.0 T — — — — — — — ms
sequential)(12)
1. Characteristics are valid both for Data Flash and Code Flash, unless specified in the characteristics column.
2. Actual hardware operation times; this does not include software overhead.
3. Typical program and erase times assume nominal supply values and operation at 25 °C.
4. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations. These values are characteristic, but
not tested.
5. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified
number of program/erase cycles. These maximum values are characterized but not tested or guaranteed.
6. Initial factory condition: < 100 program/erase cycles, 25 °C typical junction temperature and nominal (± 5%) supply
voltages.
7. Initial maximum “All temp” program and erase times provide guidance for time-out limits used in the factory and apply for
less than or equal to 100 program or erase cycles, –40 °C < TJ < 150 °C junction temperature and nominal (± 5%) supply
voltages.
8. Rate computed based on 256 KB sectors.
9. Only code sectors, not including EEPROM.
10. Time between suspend resume and next suspend. Value stated actually represents Min value specification.
11. Timings guaranteed by design.
12. AIC is done using system clock, thus all timing is dependent on system frequency and number of wait states. Timing in the
table is calculated at max frequency.

All the Flash operations require the presence of the system clock for internal
synchronization. About 50 synchronization cycles are needed: this means that the timings of
the previous table can be longer if a low frequency system clock is used.

Table 33. Flash memory Life Specification

Value
Symbol Characteristics(1) (2) Unit
Min C Typ C

NCER16K 16 KB CODE Flash endurance 10 — 100 — Kcycles

NCER32K 32 KB CODE Flash endurance 10 — 100 — Kcycles
NCER64K 64 KB CODE Flash endurance 10 — 100 — Kcycles
NCER128K 128 KB CODE Flash endurance 1 — 100 — Kcycles
256 KB CODE Flash endurance 1 — 100 — Kcycles
NCER256K
256 KB CODE Flash endurance(3) 10 — 100 — Kcycles
NDER64K 64 KB DATA EEPROM Flash endurance 250 — — — Kcycles

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Table 33. Flash memory Life Specification (continued)

Value
Symbol Characteristics(1) (2) Unit
Min C Typ C

tDR1k Minimum data retention Blocks with 0 - 1,000 P/E cycles 25 — — — Years
Minimum data retention Blocks with 1,001 - 10,000 P/E
tDR10k 20 — — — Years
cycles
Minimum data retention Blocks with 10,001 - 100,000 P/E
tDR100k 15 — — — Years
cycles
Minimum data retention Blocks with 100,001 - 250,000 P/E
tDR250k 10 — — — Years
cycles
1. Program and erase cycles supported across specified temperature specs.
2. It is recommended that the application enables the core chace memory.
3. 10K cycles on 4-256 KB blocks is not intended for production. Reduced reliability and degraded erase time are possible.

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3.15 AC Specifications
All AC timing specifications are valid up to 150 °C, except where explicitly noted.

3.15.1 Debug and calibration interface timing

3.15.1.1 JTAG interface timing

Table 34. JTAG pin AC electrical characteristics(1),(2)

Value
# Symbol C Characteristic Unit
Min Max

1 tJCYC CC D TCK cycle time 100 — ns

2 tJDC CC T TCK clock pulse width 40 60 %
3 tTCKRISE CC D TCK rise and fall times (40%–70%) — 3 ns
4 tTMSS, tTDIS CC D TMS, TDI data setup time 5 — ns
5 tTMSH, tTDIH CC D TMS, TDI data hold time 5 — ns
6 tTDOV CC D TCK low to TDO data valid — 15(3) ns
7 tTDOI CC D TCK low to TDO data invalid 0 — ns
8 tTDOHZ CC D TCK low to TDO high impedance — 15 ns
9 tJCMPPW CC D JCOMP assertion time 100 — ns
10 tJCMPS CC D JCOMP setup time to TCK low 40 — ns
11 tBSDV CC D TCK falling edge to output valid — 600(4) ns
12 tBSDVZ CC D TCK falling edge to output valid out of high impedance — 600 ns
13 tBSDHZ CC D TCK falling edge to output high impedance — 600 ns
14 tBSDST CC D Boundary scan input valid to TCK rising edge 15 — ns
15 tBSDHT CC D TCK rising edge to boundary scan input invalid 15 — ns
1. These specifications apply to JTAG boundary scan only. See Table 35 for functional specifications.
2. JTAG timing specified at VDD_HV_IO_JTAG = 4.0 to 5.5 V and max. loading per pad type as specified in the I/O section of the
datasheet.
3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

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Figure 12. JTAG test clock input timing

TCK

2
3 2

1 3

Figure 13. JTAG test access port timing

TCK

TMS, TDI

7 8

TDO

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Figure 14. JTAG JCOMP timing

TCK

10
JCOMP

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Figure 15. JTAG boundary scan timing

TCK

11 13

Output
Signals

12

Output
Signals

14
15

Input
Signals

3.15.1.2 Nexus interface timing

Table 35. Nexus debug port timing(1)

Value
# Symbol C Characteristic Unit
Min Max

7 tEVTIPW CC D EVTI pulse width 4 — tCYC(2)

8 tEVTOPW CC D EVTO pulse width 40 — ns
9 tTCYC CC D TCK cycle time 2(3),(4) — tCYC(2)
9 tTCYC CC D Absolute minimum TCK cycle time(5) (TDO sampled on posedge 40(6) — ns
of TCK)
Absolute minimum TCK cycle time(7) (TDO sampled on negedge 20(6) —
of TCK)
11 tNTDIS CC D TDI data setup time 5 — ns

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Table 35. Nexus debug port timing(1) (continued)

Value
# Symbol C Characteristic Unit
Min Max

12 tNTDIH CC D TDI data hold time 5 — ns

13 tNTMSS CC D TMS data setup time 5 — ns
14 tNTMSH CC D TMS data hold time 5 — ns
(8)
15 — CC D TDO propagation delay from falling edge of TCK — 16 ns
16 — CC D TDO hold time with respect to TCK falling edge (minimum TDO 2.25 — ns
propagation delay)
1. Nexus timing specified at VDD_HV_IO_JTAG = 3.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O
section of the data sheet.
2. tCYC is system clock period.
3. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less
than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency
being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number
greater than or equal to that specified here.
4. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute
minimum TCK period specification.
5. This value is TDO propagation time 36 ns + 4 ns setup time to sampling edge.
6. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the
design (system frequency / 4) depending on the actual system frequency being used.
7. This value is TDO propagation time 16n s + 4 ns setup time to sampling edge.
8. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

Figure 16. Nexus output timing

MCKO

6
MDO
MSEO Output Data Valid
EVTO

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Figure 17. Nexus event trigger and test clock timings

TCK
EVTI
EVTO 9

TCK
EVTI
EVTO 9 7 7

8 8

Figure 18. Nexus TDI, TMS, TDO timing

TCK

11

13
12

14

TMS, TDI

15

16

TDO

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3.15.1.3 External interrupt timing (IRQ pin)

Table 36. External interrupt timing

Characteristic Symbol Min Max Unit

IRQ Pulse Width Low tIPWL 3 — tcyc

IRQ Pulse Width High tIPWH 3 — tcyc
(1)
IRQ Edge to Edge Time tICYC 6 — tcyc
1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

Figure 19. External interrupt timing

IRQ

1 2

Figure 20. External interrupt timing

D_CLKOUT

IRQ

1 2

3.15.2 DSPI timing with CMOS pads

DSPI channel frequency support is shown in Table 37. Timing specifications are shown in
tables below.

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Table 37. DSPI channel frequency support(1)

Max usable
DSPI use mode frequency
(MHz)(2),(3)

CMOS (Master Full duplex – Classic timing (Table 38) DSPI_0, DSPI_1, 10
mode) DSPI_2, DSPI_3,
Full duplex – Modified timing (Table 39) DSPI_0, DSPI_1, 10
DSPI_2, DSPI_3,
Output only mode (SCK/SOUT/PCS) (Table 38 and DSPI_0, DSPI_1, 10
Table 39) DSPI_2, DSPI_3,
Output only mode TSB mode (SCK/SOUT/PCS) DSPI_0, DSPI_1, 10
DSPI_2, DSPI_3,
CMOS (Slave mode Full duplex) (Table 40) — 10
1. Each DSPI module can be configured to use different pins for the interface. Please see the device pinout IO definition excel
file for the available combinations. It is not possible to reach the maximum performance with every possible combination of
pins.
2. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.
3. Maximum usable frequency does not take into account external device propagation delay.

3.15.2.1 DSPI master mode full duplex timing with CMOS pads

3.15.2.1.1 DSPI CMOS master mode — classic timing

Table 38. DSPI CMOS master classic timing (full duplex and output only)
MTFE = 0, CPHA = 0 or 1(1)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

1 tSCK CC D SCK cycle time SCK drive strength

Very strong 25 pF 59.0 — ns
Strong 50 pF 80.0 —
Medium 50 pF 200.0 —
2 tCSC CC D PCS to SCK SCK and PCS drive strength
delay
Very strong 25 pF (N(4) × tSYS(5)) – — ns
16
Strong 50 pF (N(4) × tSYS(5)) – —
16
Medium 50 pF (N(4) × tSYS(5)) – —
16
PCS medium PCS = 50 pF (N(4) × tSYS(5)) – —
and SCK SCK = 50 pF 29
strong

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Table 38. DSPI CMOS master classic timing (full duplex and output only)
MTFE = 0, CPHA = 0 or 1(1) (continued)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

3 tASC CC D After SCK delay SCK and PCS drive strength

Very strong PCS = 0 pF (M(6) × tSYS(5)) – — ns
SCK = 50 pF 35
Strong PCS = 0 pF (M(6) × tSYS(5)) – —
SCK = 50 pF 35
Medium PCS = 0 pF (M(6) × tSYS(5)) – —
SCK = 50 pF 35
PCS medium PCS = 0 pF (M(6) × tSYS(5)) – —
and SCK SCK = 50 pF 35
strong
4 tSDC CC D SCK duty SCK drive strength
cycle(7) 1/ 1/
Very strong 0 pF 2tSCK –2 2tSCK +2 ns
Strong 0 pF 1/ 1/
2tSCK –2 2tSCK +2
1/ 1/
Medium 0 pF 2tSCK –5 2tSCK +5
PCS strobe timing
5 tPCS CC D PCSx to PCSS PCS and PCSS drive strength
C time(8)
Strong 25 pF 16.0 — ns
6 tPAS CC D PCSS to PCSx PCS and PCSS drive strength
C time(8)
Strong 25 pF 16.0 — ns
SIN setup time
7 tSUI CC D SIN setup time to SCK drive strength
SCK(9)
Very strong 25 pF 25.0 — ns
Strong 50 pF 31.0 —
Medium 50 pF 52.0 —
SIN hold time
8 tHI CC D SIN hold time SCK drive strength
from SCK(9)
Very strong 0 pF –1.0 — ns
Strong 0 pF –1.0 —
Medium 0 pF –1.0 —
SOUT data valid time (after SCK edge)
9 tSUO CC D SOUT data valid SOUT and SCK drive strength
time from
Very strong 25 pF — 7.0 ns
SCK(10)
Strong 50 pF — 8.0
Medium 50 pF — 16.0

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Table 38. DSPI CMOS master classic timing (full duplex and output only)
MTFE = 0, CPHA = 0 or 1(1) (continued)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

SOUT data hold time (after SCK edge)

10 tHO CC D SOUT data hold SOUT and SCK drive strength
time after
Very strong 25 pF –7.7 — ns
SCK(10)
Strong 50 pF –11.0 —
Medium 50 pF –15.0 —
1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
2. All timing values for output signals in this table are measured to 50% of the output voltage.
3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
4. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).
5. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS = 10 ns).
6. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).
7. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
8. PCSx and PCSS using same pad configuration.
9. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL voltage thresholds.
10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.

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Figure 21. DSPI CMOS master mode — classic timing, CPHA = 0

tCSC tASC

PCSx

tSDC tSCK

SCK Output
(CPOL = 0)
tSDC

SCK Output
(CPOL = 1)
tSUI
tHI

SIN First Data Data Last Data

tSUO tHO

SOUT First Data Data Last Data

Figure 22. DSPI CMOS master mode — classic timing, CPHA = 1

3&6[

6&.2XWSXW
&32/  

6&.2XWSXW
&3 2/ 

W68, W+,

6,1 )LUVW'DWD 'DWD /DVW'DWD

W682 W+2

6287 )LUVW'DWD 'DWD /DVW'DWD

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Electrical characteristics SPC582B60x, SPC582B54x, SPC582B50x

Figure 23. DSPI PCS strobe (PCSS) timing (master mode)

tPCSC tPASC

PCSS

PCSx

3.15.2.1.2 DSPI CMOS master mode — modified timing

Table 39. DSPI CMOS master modified timing (full duplex and output only)
MTFE = 1, CPHA = 0 or 1(1)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

1 tSCK CC D SCK cycle time SCK drive strength

Very strong 25 pF 33.0 — ns
Strong 50 pF 80.0 —
Medium 50 pF 200.0 —
2 tCSC CC D PCS to SCK SCK and PCS drive
delay strength
Very strong 25 pF (N(4) × tSYS(5)) – 16 — ns
(4) (5))
Strong 50 pF (N × tSYS – 16 —
(4) (5)
Medium 50 pF (N × tSYS ) – 16 —
PCS PCS = 50 pF (N(4) × tSYS(5)) – 29 —
medium and SCK = 50 pF
SCK strong
3 tASC CC D After SCK delay SCK and PCS drive
strength
Very strong PCS = 0 pF (M(6) × tSYS(5)) – 35 — ns
SCK = 50 pF
Strong PCS = 0 pF (M(6) × tSYS(5)) – 35 —
SCK = 50 pF
Medium PCS = 0 pF (M(6) × tSYS(5)) – 35 —
SCK = 50 pF
PCS PCS = 0 pF (M(6) × tSYS(5)) – 35 —
medium and SCK = 50 pF
SCK strong
4 tSDC CC D SCK duty cycle(7) SCK drive strength
Very strong 0 pF 1/ 1/ t
2tSCK –2 2 SCK +2 ns
1/ 1/ t
Strong 0 pF 2tSCK –2 2 SCK +2
1/ 1/ t
Medium 0 pF 2tSCK –5 2 SCK +5

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Table 39. DSPI CMOS master modified timing (full duplex and output only)
MTFE = 1, CPHA = 0 or 1(1) (continued)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

PCS strobe timing

5 tPCSC CC D PCSx to PCSS PCS and PCSS drive
time(8) strength
Strong 25 pF 16.0 — ns
6 tPASC CC D PCSS to PCSx PCS and PCSS drive
time(8) strength
Strong 25 pF 16.0 — ns
SIN setup time
7 tSUI CC D SIN setup time to SCK drive strength
SCK
Very strong 25 pF 25 – (P(10) × tSYS(5)) — ns
CPHA = 0(9)
(10)
Strong 50 pF 31 – (P × tSYS(5)) —
Medium 50 pF 52 – —
(P(10) × tSYS(5))
SIN setup time to SCK drive strength
SCK
Very strong 25 pF 25.0 — ns
CPHA = 1(9)
Strong 50 pF 31.0 —
Medium 50 pF 52.0 —
SIN hold time
8 tHI CC D SIN hold time SCK drive strength
from SCK
Very strong 0 pF –1 + (P(9) × tSYS(4)) — ns
CPHA = 09
(9) (4)
Strong 0 pF –1 + (P × tSYS ) —
Medium 0 pF –1 + (P(9) × tSYS (4)) —
SIN hold time SCK drive strength
from SCK
Very strong 0 pF –1.0 — ns
CPHA = 19
Strong 0 pF –1.0 —
Medium 0 pF –1.0 —

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Table 39. DSPI CMOS master modified timing (full duplex and output only)
MTFE = 1, CPHA = 0 or 1(1) (continued)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

SOUT data valid time (after SCK edge)

9 tSUO CC D SOUT data valid SOUT and SCK drive
time from SCK strength
CPHA = 0(10)
Very strong 25 pF — 7.0 + tSYS(5) ns
Strong 50 pF — 8.0 + tSYS(5)
Medium 50 pF — 16.0 + tSYS(5)
SOUT data valid SOUT and SCK drive
time from SCK strength
CPHA = 1(10)
Very strong 25 pF — 7.0 ns
Strong 50 pF — 8.0
Medium 50 pF — 16.0
SOUT data hold time (after SCK edge)
10 tHO CC D SOUT data hold SOUT and SCK drive
time after SCK strength
CPHA = 0(11)
Very strong 25 pF –7.7 + tSYS(5) — ns
Strong 50 pF –11.0 + tSYS(5) —
Medium 50 pF –15.0 + tSYS(5) —
SOUT data hold SOUT and SCK drive
time after SCK strength
CPHA = 1(11)
Very strong 25 pF –7.7 — ns
Strong 50 pF –11.0 —
Medium 50 pF –15.0 —
1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
2. All timing values for output signals in this table are measured to 50% of the output voltage.
3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
4. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).
5. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS = 10 ns).
6. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).
7. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
8. PCSx and PCSS using same pad configuration.
9. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL voltage thresholds.

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10. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_
MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1.
11. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.

Figure 24. DSPI CMOS master mode — modified timing, CPHA = 0

tCSC tASC

PCSx

tSDC tSCK

SCK Output
(CPOL = 0)
tSDC

SCK Output
(CPOL = 1)
tSUI
tHI

SIN First Data Data Last Data

tSUO tHO

SOUT First Data Data Last Data

Figure 25. DSPI CMOS master mode — modified timing, CPHA = 1

PCSx

SCK Output
(CPOL = 0)

SCK Output
(CPOL = 1)

tSUI tHI tHI

SIN First Data Data Last Data

tSUO tHO

SOUT First Data Data Last Data

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Figure 26. DSPI PCS strobe (PCSS) timing (master mode)

tPCSC tPASC

PCSS

PCSx

3.15.2.2 Slave mode timing

Table 40. DSPI CMOS slave timing — full duplex — normal and modified transfer formats
(MTFE = 0/1)
Condition
# Symbol C Characteristic Min Max Unit
Pad Drive Load

1 tSCK CC D SCK Cycle Time(1) — — 62 — ns

2 tCSC SR D SS to SCK Delay(1) — — 16 — ns
3 tASC SR D SCK to SS Delay(1) — — 16 — ns
4 tSDC CC D SCK Duty Cycle(1) — — 30 — ns
5 tA CC D Slave Access Time(1) (2) (3) Very 25 pF — 50 ns
(SS active to SOUT driven) strong
Strong 50 pF — 50 ns
Medium 50 pF — 60 ns
6 tDIS CC D Slave SOUT Disable Time(1) Very 25 pF — 5 ns
(2) (3) strong
(SS inactive to SOUT High-
Strong 50 pF — 5 ns
Z or invalid)
Medium 50 pF — 10 ns
9 tSUI CC D Data Setup Time for — — 10 — ns
Inputs(1)
10 tHI CC D Data Hold Time for Inputs(1) — — 10 — ns
11 tSUO CC D SOUT Valid Time(1) (2) (3) Very 25 pF — 30 ns
(after SCK edge) strong
Strong 50 pF — 30 ns
Medium 50 pF — 50 ns
(1) (2) (3)
12 tHO CC D SOUT Hold Time Very 25 pF 2.5 — ns
(after SCK edge) strong
Strong 50 pF 2.5 — ns
Medium 50 pF 2.5 — ns
1. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL voltage thresholds.
2. All timing values for output signals in this table, are measured to 50% of the output voltage.
3. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

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Figure 27. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 0

tASC
tCSC
SS

tSCK

SCK Input tSDC

(CPOL = 0)
tSDC

SCK Input
(CPOL = 1)

tA tSUO tHO
tDIS

SOUT First Data Data Last Data

tSUI tHI

SIN First Data Data Last Data

Figure 28. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 1

SS

SCK Input
(CPOL = 0)

SCK Input
(CPOL = 1)
tSUO
tA
tHO tDIS

SOUT First Data Data Last Data

tSUI
tHI

SIN First Data Data Last Data

3.15.3 CAN timing

The following table describes the CAN timing.

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Table 41. CAN timing

Value
Symbol C Parameter Condition Unit
Min Typ Max

tP(RX:TX) CC D CAN Medium type pads 25pF load — — 70 ns

controller
CC D Medium type pads 50pF load — — 80
propagation
CC D delay time STRONG, VERY STRONG type pads — — 60
standard 25pF load
pads
CC D STRONG, VERY STRONG type pads — — 65
50pF load
tPLP(RX:TX) CC D CAN Medium type pads 25pF load — — 90 ns
controller
CC D Medium type pads 50pF load — — 100
propagation
CC D delay time STRONG, VERY STRONG type pads — — 80
low power 25pF load
pads
CC D STRONG, VERY STRONG type pads — — 85
50pF load

3.15.4 UART timing

UART channel frequency support is shown in the following table.

Table 42. UART frequency support

LINFlexD clock
Max usable frequency
frequency LIN_CLK Oversampling rate Voting scheme
(Mbaud)
(MHz)

80 16 3:1 majority voting 5

8 10
6 Limited voting on one 13.33
sample with configurable
5 16
sampling point
4 20
100 16 3:1 majority voting 6.25
8 12.5
6 Limited voting on one 16.67
sample with configurable
5 20
sampling point
4 25

3.15.5 I2C timing

The I2C AC timing specifications are provided in the following tables.

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Table 43. I2C input timing specifications — SCL and SDA(1)

Value
No. Symbol C Parameter Unit
Min Max

1 — CC D Start condition hold time 2 — PER_CLK

Cycle(2)
2 — CC D Clock low time 8 — PER_CLK Cycle
3 — CC D Bus free time between Start and Stop condition 4.7 — µs
4 — CC D Data hold time 0.0 — ns
5 — CC D Clock high time 4 — PER_CLK Cycle
6 — CC D Data setup time 0.0 — ns
7 — CC D Start condition setup time (for repeated start condition only) 2 — PER_CLK Cycle
8 — CC D Stop condition setup time 2 — PER_CLK Cycle
2
1. I C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower than
1 ns (10% – 90%).
2. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the
device reference manual for more detail.

Table 44. I2C output timing specifications — SCL and SDA(1),(2),(3),(4)

Value
No. Symbol C Parameter Unit
Min Max

1 — CC D Start condition hold time 6 — PER_CLK

Cycle(5)
2 — CC D Clock low time 10 — PER_CLK Cycle
3 — CC D Bus free time between Start and Stop condition 4.7 — µs
4 — CC D Data hold time 7 — PER_CLK Cycle
5 — CC D Clock high time 10 — PER_CLK Cycle
6 — CC D Data setup time 2 — PER_CLK Cycle
7 — CC D Start condition setup time (for repeated start condition only) 20 — PER_CLK Cycle
8 — CC D Stop condition setup time 10 — PER_CLK Cycle
1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
2. Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
4. Programming the IBFD register (I2C bus Frequency Divider) with the maximum frequency results in the minimum output
timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.
The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD register.
5. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the
device reference manual for more detail.

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Figure 29. I2C input/output timing

2 5

SCL
6 8
4
1 3
7
SDA

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4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
The following table lists the case numbers for SPC582Bxx.

Table 45. Package case numbers

Package Type Device Type Package reference

eTQFP64 Production 7278840

eTQFP100 Production 7357321
eTQFP144(1) Emulation 7386636
1. eTQFP144 package is for emulation purpose only and not suitable for production. This package is not AEC-Q100 qualified.

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4.1 eTQFP64 package information

Figure 30. eTQFP64 package outline

MECHANICAL PACKAGE DRAWINGS

eTQFP64 10x10x1.0 - 4.3x4.3 mm

FOOT PRINT 1.0 mm EXPOSED PAD DOWN
PACKAGE CODE :9I
JEDEC/EIAJ REFERENCE NUMBER : JEDEC MS-026-ACD-HD
REFERENCE : 7278840

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Table 46. eTQFP64 package mechanical data

Dimensions

Symbol Millimeters Inches(1)

Min Typ Max Min Typ Max

A(2) — — 1.20 — — 0.047

A1(3) 0.05 — 0.15 0.002 — 0.006
(2)
A2 0.95 1.00 1.05 0.037 0.039 0.041
b(4),(5) 0.17 0.22 0.27 0.007 0.009 0.0106
(5)
b1 0.17 0.20 0.23 0.007 0.0079 0.0091
c(5) 0.9 — 0.20 0.0354 — 0.0079
c1(5) 0.9 — 0.16 0.0354 — 0.0062
(6)
D 12 0.4724
D1(7),(8) 10 0.3937(2)(5)
D2(9) — — 4.65 — — 0.1830
(10)
D3 2.90 — — 0.1141 — —
e 0.5 0.0197
E(6) 12 0.4724
E1(7),(8) 10 0.3937
E2(9) — — 4.65 — — 0.1830
(10)
E3 2.90 — — 0.1141 — —
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1 0.0394
N 64 2.5197
R1 0.08 — — 0.0031 — —
R2 0.08 — 0.20 0.0031 — 0.0079
S 0.20 — — 0.0079 — —
1. Values in inches are converted from millimeters (mm) and rounded to four decimal digits.
2. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude
beyond that surface.
3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
4. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed
the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum
space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
6. To be determined at setting datum plane C.
7. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side.
D1 and E1 are Maximum plastic body size dimensions including mold mismatch.
8. The Top package body size may be smaller than the bottom package size by much as 0.15 mm.
9. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located.
It includes all metal protrusions from exposed pad itself.

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10. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to
be free from resin flashes/bleeds, bordered by internal edge of inner groove.

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4.2 eTQFP100 package information

Figure 31. eTQFP100 package outline

MECHANICAL PACKAGE DRAWINGS

eTQFP100 BODY 14x14x1.0 - 5.0x5.0 mm

FOOT PRINT 1.0 mm EXPOSED PAD DOWN
PACKAGE CODE :YE
JEDEC/EIAJ REFERENCE NUMBER : JEDEC MS-026-AED-HD
REFERENCE : 7357321

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Table 47. eTQFP100 package mechanical data

Dimensions

Symbol Millimeters Inches(1)

Min Typ Max Min Typ Max

A(2) — — 1.20 — — 0.0472

A1(3) 0.05 — 0.15 0.0019 — 0.0059
(2)
A2 0.95 1.00 1.05 0.0374 0.0394 0.0413
b(4),(5) 0.17 0.22 0.27 0.0067 0.0087 0.0106
b1(5) 0.17 0.20 0.23 0.0067 0.0079 0.0091
(5)
c 0.09 — 0.20 0.0035 — 0.0079
(5)
c1 0.09 — 0.16 0.0035 — 0.0063
D(6) 16.00 0.6299
(7),(8)
D1 14.00 0.5512
D2(9) — — 5.35 — — 0.2106
(10)
D3 3.6 — — 0.1417 — —
E(6) 16.00 0.6299
E1(7),(8) 14.00 0.5512
(9)
E2 — — 5.35 — — 0.2106
(10)
E3 3.6 — — 0.1417 — —
e 0.50 0.0197
L(11) 0.45 0.60 0.75 0.0178 0.0236 0.0295
L1 1.00 0.0394
aaa(12),(13) 0.20 0.0079
bbb(12),(13) 0.20 0.0079
(12),(13)
ccc 0.08 0.0031
ddd(12),(13) 0.08 0.0031
1. Values in inches are converted from millimeters (mm) and rounded to four decimal digits.
2. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude
beyond that surface.
3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
4. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed
the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum
space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
6. To be determined at seating datum plane C.
7. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.
8. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side.
D1 and E1 are maximum plastic body size dimensions including mold mismatch.
9. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located.
It includes all metal protrusions from exposed pad itself.

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10. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to
be free from resin flashes/bleeds, bordered by internal edge of inner groove.
11. L dimension is measured at gauge plane at 0.25 above the seating plane.
12. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
13. Tolerance.

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4.3 eTQFP144 package information

Figure 32. eTQFP144 package outline

PACKAGE MECHANICAL DRAWINGS

eTQFP 144L BODY 20x20x1.0

FOOT PRINT 1.0 EXPOSED PAD DOWN
PACKAGE CODE : X6
JEDEC/EIAJ REFERENCE NUMBER : JEDEC MS-026-AFB-HD
REFERENCE : 7386636

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Table 48. eTQFP144 package mechanical data

Dimensions

Symbol Millimeters Inches(1)

Min Typ Max Min Typ Max

A — — 1.20 — — 0.047
A1 0.05 — 0.15 0.002 — 0.006
A2 0.95 1.00 1.05 0.037 0.039 0.041
b 0.17 0.22 0.27 0.007 0.009 0.011
c 0.09 — 0.20 0.004 — 0.008
D 21.80 22.00 22.20 0.858 0.866 0.874
D1 19.80 20.00 20.20 0.780 0.787 0.795
(2)
D2 5.1 6.5 6.77 — — 0.262
D3 — 17.50 — — 0.689 —
E 21.80 22.00 22.20 0.858 0.866 0.874
E1 19.80 20.00 20.20 0.780 0.787 0.795
E2 5.1 6.5 6.77 — — 0.262
E3(2) — 17.50 — — 0.689 —
e — 0.50 — — 0.020 —
(3)
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 — 1.00 — — 0.039 —
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
(4)
ccc 0.08 0.003
1. Values in inches are converted from millimeters (mm) and rounded to four decimal digits.
2. The size of exposed pad is variable depending of leadframe design pad size.
3. L dimension is measured at gauge plane at 0.25 above the seating plane.
4. Tolerance.

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4.4 Package thermal characteristics

The following tables describe the thermal characteristics of the device. The parameters in
this chapter have been evaluated by considering the device consumption configuration
reported in the Section 3.7: Device consumption

4.4.1 eTQFP64

Table 49. Thermal characteristics for 64 exposed pad eTQFP package(1)

Symbol C Parameter Conditions Value Unit

RJA CC D Junction-to-Ambient, Natural Convection(2) Four layer board (2s2p) 43.9 °C/W
(3)
RJB CC D Junction-to-board — 23.8 °C/W
RJCtop CC D Junction-to-case top(4) — 28.9 °C/W
RJCbottom CC D Junction-to-case bottom(5) — 12.8 °C/W
JT CC D Junction-to-package top(6) Natural convection 11.5 °C/W
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation
without any interface resistance.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.

4.4.2 eTQFP100

Table 50. Thermal characteristics for 100 exposed pad eTQFP package(1)
Symbol C Parameter Conditions Value Unit
(2)
RJA CC D Junction-to-Ambient, Natural Convection Four layer board (2s2p) 43.3 °C/W
RJB CC D Junction-to-board(3) — 26.1 °C/W
(4)
RJCtop CC D Junction-to-case top — 27 °C/W
(5)
RJCbottom CC D Junction-to-case bottom — 12.6 °C/W
JT CC D Junction-to-package top(6) Natural convection 11.4 °C/W
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation
without any interface resistance.

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6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.

4.4.3 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from the equation:

Equation 1
TJ = TA + (RJA * PD)
where:
TA = ambient temperature for the package (°C)
RJA = junction-to-ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards
to provide consistent values for estimations and comparisons. The differences between the
values determined for the single-layer (1s) board compared to a four-layer board that has
two signal layers, a power and a ground plane (2s2p), demonstrate that the effective
thermal resistance is not a constant. The thermal resistance depends on the:
 Construction of the application board (number of planes)
 Effective size of the board which cools the component
 Quality of the thermal and electrical connections to the planes
 Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using
fewer vias to connect the package to the planes reduces the thermal performance. Thinner
planes also reduce the thermal performance. When the clearance between the vias leaves
the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for
the tightly packed printed circuit board. The value obtained on a board with the internal
planes is usually within the normal range if the application board has:
 One oz. (35 micron nominal thickness) internal planes
 Components are well separated
 Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the
surrounding components. In addition, the ambient temperature varies widely within the
application. For many natural convection and especially closed box applications, the board
temperature at the perimeter (edge) of the package is approximately the same as the local
air temperature near the device. Specifying the local ambient conditions explicitly as the
board temperature provides a more precise description of the local ambient conditions that
determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following
equation:

Equation 2
TJ = TB + (RJB * PD)

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where:
TB = board temperature for the package perimeter (°C)
RJB = junction-to-board thermal resistance (°C/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, the
junction temperature is predictable if the application board is similar to the thermal test
condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance
plus a case-to-ambient thermal resistance:

Equation 3
RJA = RJC + RCA
where:
RJA = junction-to-ambient thermal resistance (°C/W)
RJC = junction-to-case thermal resistance (°C/W)
RCA = case to ambient thermal resistance (°C/W)
RJC is device related and is not affected by other factors. The thermal environment can be
controlled to change the case-to-ambient thermal resistance, RCA. For example, change
the air flow around the device, add a heat sink, change the mounting arrangement on the
printed circuit board, or change the thermal dissipation on the printed circuit board
surrounding the device. This description is most useful for packages with heat sinks where
90% of the heat flow is through the case to heat sink to ambient. For most packages, a
better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board
thermal resistance and the junction-to-case thermal resistance. The junction-to-case
thermal resistance describes when using a heat sink or where a substantial amount of heat
is dissipated from the top of the package. The junction-to-board thermal resistance
describes the thermal performance when most of the heat is conducted to the printed circuit
board. This model can be used to generate simple estimations and for computational fluid
dynamics (CFD) thermal models. More accurate compact Flotherm models can be
generated upon request.
To determine the junction temperature of the device in the application on a prototype board,
use the thermal characterization parameter (JT) to determine the junction temperature by
measuring the temperature at the top center of the package case using the following
equation:

Equation 4
TJ = TT + (JT x PD)
where:
TT = thermocouple temperature on top of the package (°C)
JT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured in compliance with the JESD51-2
specification using a 40-gauge type T thermocouple epoxied to the top center of the
package case. Position the thermocouple so that the thermocouple junction rests on the
package. Place a small amount of epoxy on the thermocouple junction and approximately 1

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mm of wire extending from the junction. Place the thermocouple wire flat against the
package case to avoid measurement errors caused by the cooling effects of the
thermocouple wire.
When board temperature is perfectly defined below the device, it is possible to use the
thermal characterization parameter (JPB) to determine the junction temperature by
measuring the temperature at the bottom center of the package case (exposed pad) using
the following equation:

Equation 5
TJ = TB + (JPB x PD)
where:
TT = thermocouple temperature on bottom of the package (°C)
JT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)

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5 Ordering information

Figure 33. Ordering information scheme

Example code:
SPC58 2 B 60 E3 M H X 1 X
Product identifier Core Product Memory Package Frequency Custom Reserved Silicon Packing
version revision

Y = Tray
X = Tape and Reel (pin 1 top right)

0 = 1st version
1 = 2nd version

0 = 3x standard CAN
D = 3x ISO CAN FD
G = 7x standard CAN
H = 7x ISO CAN FD

A = 48 MHz at 105 oC
B = 64 MHz at 105 oC
C = 80 MHz at 105 oC
K = 48 MHz at 125 oC
L = 64 MHz at 125 oC
M = 80 MHz at 125 oC

E3 = eTQFP100
E1 = eTQFP64

60 = 1 MB
54 = 768 KB
50 = 512 KB

B = SPC582Bx family

2 = Single computing e200z2 core

SPC58 = Power Architecture in 40 nm

Note: eTQFP144 package (SPC582B60E5-ENG) is available for emulation purpose only (with NEXUS port I/O).

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Table 51. Code Flash options

SPC582B54 SPC582B50
SPC582B60 (1M) Partition Start address End address
(768K) (512K)

16 16 16 0 0x00FC0000 0x00FC3FFF
16 16 16 0 0x00FC4000 0x00FC7FFF
16 16 16 0 0x00FC8000 0x00FCBFFF
16 16 16 0 0x00FCC000 0x00FCFFFF
32 32 32 0 0x00FD0000 0x00FD7FFF
32 32 32 0 0x00FD8000 0x00FDFFFF
64 64 64 0 0x00FE0000 0x00FEFFFF
64 64 64 0 0x00FF0000 0x00FFFFFF
128 128 128 0 0x01000000 0x0101FFFF
128 128 128 0 0x01020000 0x0103FFFF
128 128 NA 0 0x01040000 0x0105FFFF
128 128 NA 0 0x01060000 0x0107FFFF
128 NA NA 0 0x01080000 0x0109FFFF
128 NA NA 0 0x010A0000 0x010BFFFF

Table 52. RAM options

SPC582B60 SPC582B54 SPC582B50
Type Start address End address
96(1) 80(1) 64(1)

PRAMC_2
8 8 8 0x400A8000 0x400A9FFF
(STBY)
PRAMC_2
24 24 24 0x400AA000 0x400AFFFF
(STBY)
PRAMC_2
32 32 32 0x400B0000 0x400B7FFF
(STBY)
16 16 NA PRAMC_2 0x400B8000 0x400BBFFF
16 NA NA PRAMC_2 0x400BC000 0x400BFFFF
1. Total KRAM (SRAM).

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Revision history SPC582B60x, SPC582B54x, SPC582B50x

6 Revision history

Table 53. Document revision history

Date Revision Changes

07-April-2016 1 Initial version.

The following are the changes in this version of the Datasheet.

– Removed QFN32 package from the document.

– Replaced RPNs SPC582B60E1, SPC582B60E3, and SPC582B60Q2
with “SPC582B60x, SPC582B54x, and SPC582B50x”
Table 1: Device summary:
– Updated the table.
Section 3.1: Introduction:
– Removed text “The IPs and...for the details”.
– Removed the two notes.
Table 3: Parameter classifications:
– Updated the description of classification tag “T”.
Table 4: Absolute maximum ratings:
– For parameter “IINJ”, text “DC” removed from description.
– Added text “Exposure to absolute ... reliability”
– Added text “even momentarily”
– Updated values in conditions column.
– Added parameter TTRIN.
29-Jun-2017 2
– For parameter “TSTG”, maximum value updated from “175” to “125”
– Added new parameter “TPAS”
– For parameter “IINJ”, description updated from “maximum...PAD” to
“maximum DC...pad”
Table 5: Operating Conditions:
– Footnote “1.260 V - 1.290 V range .. temperature profile” updated to Text
“... average supply value below or equal to 1.236 V ...”
– For parameter “IINJ1” description, text “DC” removed.
– For parameter “VDD_LV”, changed the classification from “D” to “P”
– Removed note “Core voltage as ....”
– Added parameter IINJ2.
– Removed parameter “VRAMP_LV”.
– Updated the table footnote “Positive and negative Dynamic current....”
Table 6: Device supply relation during power-up/power-down sequence:
– “VDD_HV_PMC” updated to “VDD_HV_OSC”.
– Parameter “VDD_LV” removed
Section 3.4: Electromagnetic emission characteristics:
– Updated this section.

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Table 53. Document revision history (continued)

Date Revision Changes

Table 8: Device consumption:

– Updated the table and its values.
Section 3.8.2: I/O output DC characteristics:
– “WEAK” to “WEAK/SLOW”
– “STRONG” to “STRONG/FAST”
– “VERY STRONG” to “VERY STRONG / VERY FAST”
– Added note “10%/90% is the....”
Table 14: I/O input electrical characteristics:
– Parameter “ILKG” (Medium Pads (P), TJ=150°C/360 mA) removed.
Table 11: I/O pull-up/pull-down electrical characteristics:
– Added note “When the device enters into standby mode... an ADC
function.”
Table 12: WEAK/SLOW I/O output characteristics:
– Added “10%-90% in description of parameter “tTR_W”.
– For parameter “Fmax_W”, updated condition “25 pF load” to “CL=25pF”
– For parameter “tTR_S”, changed min value (25 pF load) from “4” to “3”
– Changed min value (50 pF load) from “6” to “5”
– For parameter “|tSKEW_W|”, changed max value from “30” to “25”.
Table 13: MEDIUM I/O output characteristics:
– Added “10%-90% in description of parameter “tTR_M”.
– For parameter “|tSKEW_W|”, changed max value from “30” to “25”.
29-Jun-2017 2 (cont’) Table 14: STRONG/FAST I/O output characteristics:
– Added “10%-90% in description of parameter “tTR_S”.
– Parameter “IDCMAX_S” updated:
– Condition added “VDD=5V+10%
– Condition added “VDD=3.3V+10%, Max value updated to 5.5mA
– For parameter “|tSKEW_W|”, changed max value from “30” to “25”.
Table 16: I/O consumption:
– Updated all the max values of parameters IDYN_W and IDYN_M
Section 3.8.3: I/O pad current specifications:
– Replaced all occurences of “50 pF load” with “CL=50pF”.
– Removed note “The external ballast....”
Table 19: PLL0 electrical characteristics:
– For parameter “IPLL0”, classification changed from “C” to “T”.
– Footnote “Jitter values...measurement” added for parameters:
– PLL0PHI0SPJ|
– PLL0PHI1SPJ|
– PLL0LTJ
Table 20: PLL1 electrical characteristics:
– For parameter “IPLL1”, classification changed from “C” to “T”.
– Footnote “Jitter values...measurement” added for parameter
“PLL1PHI0SPJ|”
– Removed figure “Test circuit”

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Table 53. Document revision history (continued)

Date Revision Changes

Table 21: External 40 MHz oscillator electrical specifications:

– Footnote “Ixatl is the oscillator...Test circuit is shown in Figure 8” modified
to “Ixatl is the oscillator...startup of the oscillator”.
– Minimum value of parameter “VIHEXT” updated from “VREF+0.6” to
“VREF+0.75”
– Maximum value of parameter “VILEXT” updated from “VREF-0.6” to
“VREF-0.75”
– Parameter “gm”, value “D” updated to “P” for “fXTAL < 8 MHz”, and “D” for
others.
– Footnote “This parameter is...100% tested” updated to “Applies to an...to
crystal mode”. Also added to parameter “VI
– For parameters “VIHEXT” and “VILEXT”, Condition “–” updated to “VREF =
0.29 * VDD_HV_OSC”
– Classification for parameters “CS_EXTAL” and “CS_EXTAL” changed from
“T” to “D”.
– Updated classification, conditions, min and max values for parameter
“gm”.
– Min and Max value of parameters CS_EXTAL and CS_XTAL updated to “3”
(min) and “7” (max).
Renamed the section “RC oscillator 1024 kHz” to Section 3.11.3: Low
power RC oscillator
Table 22: Internal RC oscillator electrical specifications:
29-Jun-2017 2 (cont’)
– For parameter “IFIRC”, replaced max value of 300 with 600.
– Added footnote to the description.
– For parameter IFIRC, changed the max value to 600 and added footnote.
– Min, Typ and Max value of ”fvar_SW” updated from “-1”, “-”, “1” to “-0.5”,
“+0.3” and “0.5” respectively.
Table 23: 1024 kHz internal RC oscillator electrical characteristics:
– For parameter “fvar_V”, minimum and maximum value updated from “-
0.05” and “+0.05” to “-5” and “+5”.
– For parameter “fvar_T”, and “fvar_V “ changed the cassification to “P”.
Table 24: ADC pin specification:
– For ILKG, changed condition “C” to “—”.
– For parameter CP2, updated the max value to “1”.
Table 25: SARn ADC electrical specification:
– Classification for parameter “IADCREFH” changed from “C” to “T”.
– For parameter fADCK (High frequency mode), changed min value from
“7.5” to “> 13.33”.
– Deleted footnote “Values are subject to change (possibly improved to ±2
LSB) after characterization”
Table 28: Linear regulator specifications:
– Updated the min and typ values of parameter VMREG (After trimming,
maximum load).

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Table 53. Document revision history (continued)

Date Revision Changes

Table 29: Standby regulator specifications:

– Updated the min and max values for parameter VSBY.
– For parameter IDDSBY, added “0.984” to typ column.
Table 30: Voltage monitor electrical characteristics:
– Updated the Typ value of parameter VPOR200_C
– Updated the min, typ, and max values of parameter VLVD100_SB,.
– Updated the min and max values for parameter VMVD270_SBY.
– Removed “PowerOn Reset LV”
Updated Section 3.14: Flash
Updated Figure 8: Input equivalent circuit (Fast SARn and SARB
channels)
Updated Figure 22: DSPI CMOS master mode — classic timing,
CPHA = 1
Table 35: Nexus debug port timing:
– Classification of parameters “tEVTIPW” and “tEVTOPW” changed from “P”
to “D”.
Table 38: DSPI CMOS master classic timing (full duplex and output
29-Jun-2017 2 (cont’) only) — MTFE = 0, CPHA = 0 or 1:
– Changed the Min value of tSCK (very strong) from 33 to 59.
Added Section 3.15.3: CAN timing
Table 46: eTQFP64 package mechanical data:
– Updated the values.
Table 47: eTQFP100 package mechanical data:
– Updated the values.
Table 48: eTQFP144 package mechanical data:
– Updated the values.
Table 37: DSPI channel frequency support:
– Added column to show slower and faster frequencies..
Table 49: Thermal characteristics for 64 exposed pad eTQFP package:
– Removed parameter RJMA.
Table 50: Thermal characteristics for 100 exposed pad eTQFP package:
– Removed parameter RJMA.
– Updated the values of all the parameters.
Table 51: Thermal characteristics for 144 exposed pad eTQFP package:
– Removed parameter RJMA.

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Table 53. Document revision history (continued)

Date Revision Changes

The following are the changes in this version of the Datasheet.

Replaced reference to IO_definition excel file by “the device pin out IO

definition excel file”, throughout the document.
Minor formatting changes throughout the document.
Section 2: Package pinouts and signal descriptions:
Changed introduction sentence since the pinout excel file will no longer be
attached to the Datasheet.
Table 6: Device supply relation during power-up/power-down sequence:
Added a note “The application.....” to parameter VDD_HV_OSC
Table 8: Device consumption:
– “IDD_LKG”: added footnote “IDD_LKG and IDD_LV are reported as...”
– “IDD_LV”: added Footnote “IDD_LKG and IDD_LV are reported as...”
– Updated table footnote 4.
– Updated all the typical and maximum values for IDD_LKG, IDDSTBY8, and
IDDSTBY64 parameters.
Table 9: I/O pad specification descriptions:
Removed latest sentence at Standby pads description.
Table 14: STRONG/FAST I/O output characteristics:
Updated values for tTR_S for condition CL = 25 pF and CL = 50 pF
04-Jun-2018 3
Table 15: VERY STRONG/VERY FAST I/O output characteristics:
– “tTR20-80” replaced by “tTR20-8_V”
– “tTRTTL” replaced by “tTRTTL_V”
– “tTR20-80” replaced by “tTR20-80_V”
Table 19: PLL0 electrical characteristics:
– Added “fINFIN”
– Symbol “fINFIN” : changed “C” by “—” in column “C”
– PLL0PHI0SPJ|: changed “T” by “D” and added pk-pk to Conditions value
– PLL0PHI1SPJ|: added pk-pk to Conditions value
– The maximum value of fPLL0PHI0 is changed from “400” to “FSYS” with a
footnote.
Table 20: PLL1 electrical characteristics:
Added “fINFIN”.
Table 21: External 40 MHz oscillator electrical specifications:
– Changed “i.e.” by “that is” in note “Amplitude on the EXTAL...
– Changed table footnote 3 by: This value is determined by the crystal
manufacturer and board design, and it can potentially be higher than the
maximum provided.
– Table footnote 1 updated: “DCF clients XOSC_LF_EN and
XOSC_EN_40MHZ” changed by “XOSC_FREQ_SEL”

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Table 53. Document revision history (continued)

Date Revision Changes

Table 24: ADC pin specification:

– Updated Max value for CS
– For parameter CP2, updated the max value from “1” to “2”.
– Changed Max value = 1 by 2 for Cp2 SARB channels
Table 25: SARn ADC electrical specification:
– Added symbols tADCINIT and tADCBIASINIT
– Column “C” splitted and added “D” for IADV_S
Figure 11: Voltage monitor threshold definition:
Right blue line adjusted on the top figure.
Section 3.13.1: Power management integration:
Added sentence “It is recommended...device itself”.
04-Jun-2018 3 (cont’d) Table 28: Linear regulator specifications:
Updated values for symbol “IDDMREG”, Min: 50 changed to -50.
Section 3.14: Flash:
Updated the section.
Table 41: CAN timing:
Added columns for “CC” and “D”.
Section 4.4: Package thermal characteristics:
Removed table “Thermal characteristics for 144 exposed pad eTQFP
package”
Figure 33: Ordering information scheme:
For Packing, replaced “R” with “X” and removed description related to “R”.
Updated the description of “X”.
Added Table 52: RAM options and Table 51: Code Flash options.

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