Topology Comparison For Solid State
Topology Comparison For Solid State
I. INTRODUCTION
AC Load
DC Load
Storage
PHEV
PV
the high frequency (HF) transformer [1], the SST will make
use of state-of-the-art Power Electronics devices that will help
it achieve efficiency comparable to that of a regular
transformer of the same ratings. However, the SST will Fig. 2. Integration of DES, DER and intelligent loads through the SST.
provide additional functionalities such as on-demand reactive
II. SST CONFIGURATIONS
the appropriate configuration according to the specific needs A modular two-stage configuration is shown in Fig. 5 where
was introduced in [3]. In this classification, as seen in Fig. 3, only the AC-DC stage is modular. As in the previous case, in
four SST configurations that cover all the possible SST this configuration, the voltage and current sharing may not be
topologies are identified: a) single-stage with no DC link, b) intrinsic since it depends on the type of AC-DC converter.
two-stage with low voltage DC (LVDC) link, c) two-stage
LVDC
with high voltage DC (HVDC) link, and d) three-stage with + +
both HVDC and LVDC links. Since the DC link of the third Vi/n
-
Vo
-
Idc/n
+
Vi/n
-
Li
LVDC link Double-Phase Inverter LC Filter
400 V Load
Lo
HFT
Co
Grid CL
Co
Lo
Fig. 12. Modular three-stage SST based on a Four-level Rectifier and three DC-DC Full-bridge converters.
10
1.14
5
1.12 0
LV Vdclink (V) -5
410
-10
405
400 -15
4
100
1.12
0
-100 1.1
0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57
-200 Time (sec)
ILdab(A)
Fig. 15. Simulation results from average model demonstrating on-demand
2
reactive power support capability.
0
-2
Vo+(V), Io+(A)
0.24 0.25 0.26 0.27 0.28 0.29 200
Time (sec)
100
Fig. 13. Three-stage DAB based SST switching model waveforms (refer to 0
-200
Vi(kV), Ii(A)
10
Vi(kV), Ii(A) 5
15 0
10 -5
5 -10
0 LV Vdclink (V)
405
-5
-10
400
-15
Vo+(V), Io+(A)
200
395
4
x 10 HV Vdclink (V)
100 1.2
0
1.15
-100
1.1
-200 0.48 0.5 0.52 0.54 0.56 0.58 0.6 0.62 0.64 0.66
4
x 10 HV Vdclink (V) Time (sec)
1.16
1.15 Fig. 16. Simulation results from average model demonstrating reverse power
1.14 flow from PV to the grid through the SST (initially the load is larger than the
1.13 PV generation, and at 0.5 s a step drop in load is simulated leading to injection
1.12 of excess PV power into the grid.)
1.11
1.1
0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 VI. CONCLUSIONS
Time (sec)
A topology comparison of six representative SST
Fig. 14. Simulation results from average model demonstrating voltage sag
topologies has been presented herein. The single-stage
ride-through capability.
topologies do not represent a significant advantage in terms of
switch count, and provide limited functionalities as compared
to the three-stage topologies. The three-stage DAB based
topology provides all the desired SST functionalities while
simplifying the control design. The LVDC link in this
configuration provides a convenient port to interface DER and
8
DES. The simulation results from the average model of this [18] Subhashish Bhattacharya, Tiefu Zhao, Gangyao Wang, Sumit Dutta,
Seunghun Baek, Yu Du, Babak Parkhideh, Xiaohu Zhou, and Alex Q.
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