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Please read this disclaimer before
proceeding:
This document is confidential and intended solely for the educational purpose
of RMK Group of Educational Institutions. If you have received this document
through email in error, please notify the system manager. This document
contains proprietary information and is intended only to the respective group /
learning community as intended. If you are not the addressee you should not
disseminate, distribute or copy through e-mail. Please notify the sender
immediately by e-mail if you have received this document by mistake and delete
this document from your system. If you are not the intended recipient you are
notified that disclosing, copying, distributing or taking any action in reliance on
the contents of this information is strictly prohibited.

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R.M.K. ENGINEERING COLLEGE

22EC920 DESIGN VERIFICATION

AND DEBUGGING

Department: ECE
Batch/Year: BATCH 2022-2026/III

Created by:
Ms.P.SANTHOSHINI M.E.,(PhD).,
Table of Contents
1. Course Objectives

To introduce logic and fault simulation and testability measures.

To study the design for testability.
To know about interfacing and testing of memory.
To introduce power management techniques in testing.
To study testability in analog circuits.
 2.Pre Requisites

For learning this course, D e s i g n V e r i f i c a t i o n a n d D e b u g g i n g ,the basic

concepts are discussed in the earlier semesters as follows

Semester – III

22EC302
ANALOG ELECTRONICS

Semester - I Semester - II

22PH102 22EC201
PHYSICS FOR ELECTRONICS ELECTRON DEVICES AND
ENGINEERING CIRCUIT THEORY
 3.Syllabus

22EC920 DESIGN VERIFICATION AND DEBUGGING LTPC

3003
UNIT I TEST REQUIREMENTS AND METRICS
9

Validation platforms- SOC design methodology, IP components, Integration, Clocking,

I/Os and interfaces, Device modes, Logic, memories, analog, I/Os, power
management; Test requirements-Test handoffs, Testers Where DUT and DFT fit into
design / framework; Test_x0002_ATPG, DFT, BIST, COF, TTR; Test cost metrics and
test economics; Logic fault models_x0002_SAF, TDF, PDF, Iddq, StBDG, Dy-BDG,
SDD; Basics of test generation and faultsimulation_x0002_Combinational circuits,
Sequential; Specific algorithmic approaches, CAD framework, Optimisations.

UNIT II SCAN DESIGN AND BIST 9

Scan Design- Scan design requirements, Types of scan and control mechanisms,
Test pattern construction for scan, Managing scan in IPs and SOCs, Scan design
optimisations, Partitioning, Clocking requirements for scan and delay fault testing,
Speed of operation; BIST – Framework, Controller configurations, FSMs, LFSRs,
STUMPS architecture, Scan compression and bounds, Test per cycle, Test per scan,
Self-testing and self-checking circuits, Online test.

UNIT III MEMORY TEST AND TEST INTERFACES 9

Memory Test -Memory fault models, Functional architecture as applicable to test, Test
of memories, Test of logic around memories, BIST controller configuration, Test of
logicaround memories, DFT and architecture enhancements, Algorithmic optimisations;
Test Interfaces_x0002_Test control requirements, Test interfaces - 1500, JTAG,
Hierarchical, serial control, Module/ IP test, SOC test, Board test, System test,
Boundary scan.
 3.Syllabus
22EC920 DESIGN VERIFICATION AND DEBUGGING
LTPC 3003

UNIT IV DESIGN CONSIDERATIONS AND POWER MANAGEMENT DURING

TEST 9
Design Considerations- Design considerations, Physical design congestion,
Partitioning,
Clocks, Test modes, Pins, Test scheduling, Embedded test, Architecture
improvements, Test in the presence of security; Power management during test-
Methods for low power test, ATPG methods, DFT methods, Scan methods, Low power
compression, Test of power management, Implications of power excursions,
Optimisations.
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UNIT V ANALOG TEST
Test requirements. DFT methods. BIST methods. Test versus measurement. Defect
tests versus performance tests. Tests for specific modules - PLL, I/Os, ADC, DAC,
SerDes, etc. RF test requirements.

Total Periods: 45
4. Course Outcomes

After successful completion of the course, the students should be able to

Highest
CO No. Course Outcomes Cognitive
Level

CO1 Understand logic and fault simulation requirements and K2

testability measures
Understand the Design for Testability
CO2 K3

Develop interfacing and memory testing

CO3 K3

CO4 Understand the various design consideration during test K3

Perform testing with power management techniques.

CO5 K2

CO6 Carry-out fault Detection in analog circuits K3

 5. CO – PO /PSO Mapping

Program Specific
Program Outcomes
Outcomes

Course Level K3,

of K5
Outcomes CO K3 K4 K4 K5 A3 A2 A3 A3 A3 A3 A2 K6 K5 K6
K6
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO PSO PSO
1 2 3

C205.1 K2 2 1 - - - - - - - - - - 1 - -
C205.2 K3 3 2 - - - 1 - - - - 1 1 1 1 -
C205.3 K3 3 2 1 1 - 1 - - - - 1 1 1 1 -
C205.4 K3 3 2 - - - - - - - - 1 1 1 1 -
C205.5 K2 2 1 - - - - - - - - - - 1 - -
K3 - - - - - - - - - -
C205.6 3 2 - -
C205 3 2 1 1 1 1 1 1 1 -
6.1 LECTURE PLAN
6.2. Activity Based Learning

Design a collaborative activity where students create and

simulate a basic scan chain using flip-flops and LFSRs,
then analyze its effectiveness in detecting faults through
test pattern construction and fault simulation.
6.3 Lecture Notes

UNIT II
SCAN DESIGN AND BIST
Links to Videos and Learning Materials

Topic Link

https://youtu.be/SMLQGlkRV3g
Scan Design
Managing https://youtu.be/HAz4AKgZy5c
scan in IPs

https://youtu.be/6iE34GhzPJI
Managing
scan in SOCs

https://youtu.be/Mhc60f2WmgY?list=PLypASgTPYF9W7rcCHs9by
BIST zjvzPX7d5brb
6.3: ASSIGNMENT
6.4: Part-A: Q & A
 : Part-B: Questions

S. Question K CO
No. Level
1 Explain the design requirements and implementation of a scan chain in K2 CO3
sequential circuits, including its challenges and optimizations.

2 Describe the various types of scan designs and their control mechanisms. K2 CO3
Discuss the trade-offs between full scan and partial scan designs.

3 Elaborate on the process of test pattern construction for scan-based K2 CO3

testing. How are these patterns applied and analyzed in SoCs?

4 Discuss the concept of scan partitioning. How does it improve testability K2 CO3
and performance in complex SoC designs?

5 Explain the clocking requirements for scan design, focusing on K2 CO3

synchronization, power management, and timing constraints.

6 Define delay fault testing and describe its implementation in scan K2 CO3
designs. Highlight the significance of delay testing in ensuring circuit
performance

7 What is Built-In Self-Test (BIST)? Discuss its framework, key components, K2 CO3
and advantages in modern digital systems.

8 Explain the working of Linear Feedback Shift Registers (LFSRs) in K2 CO3

BIST. How are they used to generate test patterns and analyze
responses?
9 Compare and contrast test-per-scan and test-per-cycle approaches in K2 CO3
BIST. Which method is better suited for high-speed circuits and why?

10 Compare and contrast test-per-scan and test-per-cycle approaches in K2 CO3

BIST. Which method is better suited for high-speed circuits and why?
6.6: Supportive online Certification courses

SWAYAM NPTEL:
TOPIC : Digital VLSI Testing

COURSERA:
TOPIC: Digital Systems Design with FPGA

EDX:
TOPIC: Design for Testability (DFT) and ATPG

UDEMY:
TOPIC: VLSI Design and Verification
6.7 : Real time Applications in day to day life and to
Industry
 7. Assessment Schedule

Assessment Proposed Date Actual Date

Unit 1 Assignment
Assessment
Unit Test 1

Unit 2 Assignment
Assessment
Internal Assessment 1

Retest for IA 1

Unit 3 Assignment
Assessment
Unit Test 2

Unit 4 Assignment
Assessment
Internal Assessment 2

Retest for IA 2

Unit 5 Assignment
Assessment
Revision Test 1

Revision Test 2

Model Exam

Remodel Exam

University Exam
8. Prescribed Text Books & Reference Books

TEXT BOOK:

1. M. L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing for

Digital Memory and Mixed Signal VLSI Circuits, Springer, 2005

2. M. Abramovici, M.A. Breuer and A.D. Friedman, "Digital Systems and

Testable Design", Jaico Publishing House

3 Swarup Bhunia, Sandip Ray and Susmita Sur-kolay, Fundamentals of IP and

SoC Security: Design Verification and Debug, Springer 2017.

REFERENCES:

1. H. Fujiwara, Logic Testing and Design for Testability, MIT Press, 1985

2. M. Abramovici, M. Breuer, and A. Friedman, Digital System Testing and Testable

Design, IEEE Press, 1994.

3. M. Huth and M. Ryan, Logic in Computer Science, Cambridge Univ. Press, 2004.

4. T. Kropf, Introduction to Formal Hardware Verification, Springer Verlag, 2000.

5. P.K. Lala, "Digital Circuit Testing and Testability", Academic Press, 2002

NPTEL LINK: https:// onlinecourses.nptel.ac.in/noc20_ee76/preview

Mini-projects suggestions
.

Thank you

Disclaimer:

This document is confidential and intended solely for the educational purpose of RMK
Group of Educational Institutions. If you have received this document through email
in error, please notify the system manager. This document contains proprietary
information and is intended only to the respective group / learning community as
intended. If you are not the addressee you should not disseminate, distribute or copy
through e-mail. Please notify the sender immediately by e-mail if you have received
this document by mistake and delete this document from your system. If you are not
the intended recipient you are notified that disclosing, copying, distributing or taking
any action in reliance on the contents of this information is strictly prohibited.

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