PROBLEMS

Computer Simulation Problems files on the website. Note that if a particular parameter value
is not specified in the problem statement, you are to make a
Problems identified by this icon are intended to
reasonable assumption.
demonstrate the value of using SPICE simulation to verify
hand analysis and design, and to investigate important issues
Section 6.1: Basic Principles
such as allowable signal swing and amplifier nonlinear
distortion. Instructions to assist in setting up simulations for 6.1 For the MOS amplifier of Fig. 6.2(a) with VDD = 5 V,
2
all the indicated problems can be found in the corresponding Vt = 0.5 V, kn = 10 mA/V , and RD = 20 k, determine the

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 457

3V

CHAPTER 6
coordinates of the active-region segment (AB) of the VTC
[Fig. 6.2(b)].

D 6.2 It is required to bias the MOS amplifier of Fig. 6.3 10 k

at point Q for which VOV = 0.2 V and VDS = 1 V. Find
the required value of RD when VDD = 5 V, Vt = 0.5 vO
2
V, and kn = 10 mA/V . Also specify the coordinates of
vI

PROBLEMS
the VTC end point B. What is the small-signal volt-
10 k
age gain of this amplifier? Assuming linear operation,
what is the maximum allowable negative signal swing
at the output? What is the corresponding peak input
signal?
Figure P6.6
D *6.3 Design the MOS amplifier of Fig. 6.4(a) to obtain
maximum gain while allowing for an output voltage swing of
at least ±0.2 V. Let VDD = 2 V, and use an overdrive voltage *6.7 Consider the amplifier circuit of Fig. 6.6 when operated
of approximately 0.2 V. with a supply voltage VCC = +3V.
(a) Specify VDS at the bias point. (a) What is the theoretical maximum voltage gain that this
(b) What is the gain achieved? What is the signal amplitude amplifier can provide?
v̂gs that results in the 0.2-V signal amplitude at the (b) What value of VCE must this amplifier be biased at to
output? provide a voltage gain of –60 V/V?
(c) If the dc bias current in the drain is to be 100 µA, what (c) If the dc collector current IC at the bias point in (b) is to
value of RD is needed? be 0.5 mA, what value of RC should be used?
 2
(d) If kn = 400 µA/V , what W/L ratio is required for the (d) What is the value of VBE required to provide the bias point
−15
MOSFET? mentioned above? Assume that the BJT has IS = 10 A.
6.4 A BJT amplifier circuit such as that in Fig. 6.6 (e) If a sine-wave signal vbe with a 5-mV peak amplitude
is operated with VCC = + 5 V and is biased at VCE = is superimposed on VBE , find the corresponding output
+1 V. Find the voltage gain, the maximum allowed out- voltage signal vce that will be superimposed on VCE
put negative swing without the transistor entering sat- assuming linear operation around the bias point.
uration, and the corresponding maximum input signal (f) Characterize the signal current ic that will be superim-
permitted. posed on the dc bias current IC .
(g) What is the value of the dc base current IB at the bias
6.5 A designer considers a number of low-voltage BJT point? Assume β = 100. Characterize the signal current
amplifier designs utilizing power supplies with voltage VCC ib that will be superimposed on the base current IB .
of 1.0, 1.5, 2.0, or 3.0 V. For transistors that saturate at (h) Dividing the amplitude of vbe by the amplitude of ib , eval-
VCE = 0.3 V, what is the largest possible voltage gain uate the incremental (or small-signal) input resistance of
achievable with each of these supply voltages? If in each the amplifier.
case biasing is adjusted so that VCE = VCC /2, what gains (i) Sketch and clearly label correlated graphs for vBE , vCE ,
are achieved? If a negative-going output signal swing iC , and iB versus time. Note that each graph consists
of 0.4 V is required, at what VCE should the transistor of a dc or average value and a superimposed sine
be biased to obtain maximum gain? What is the gain wave. Be careful of the phase relationships of the sine
achieved with each of the supply voltages? (Notice that waves.
all of these gains are independent of the value of IC
chosen!) D 6.8 For the MOS amplifier of Fig. 6.2(a) with VDD = 5 V
2
and kn = 5 mA/V , it is required to have the end point of the
6.6 The transistor in the circuit of Fig. P6.6 is biased at a dc VTC, point B, at VDS = 0.5 V. What value of RD is required? If
collector current of 0.2 mA. What is the voltage gain? (Hint: the transistor is replaced with another having twice the value
Use Thévenin’s theorem to convert the circuit to the form in of the transconductance parameter kn , what new value of RD
Fig. 6.6.) is needed?
 458 Chapter 6 Transistor Amplifiers

6.9 The MOS amplifier of Fig. 6.4(a), when operated with output signal peak v̂o achievable while the transistor remains
PROBLEMS

VDD = 2 V, has a maximum small-signal voltage gain saturated is

magnitude of 14 V/V. Find VOV and VDS for bias point Q at 
  1
which a voltage gain of −12 V/V is obtained. v̂o = VDS − VOV 1+  
A v 
6.10 Consider the amplifier of Fig. 6.4(a) for the case VDD =
 2
5 V, RD = 24 k, kn (W/L) = 1 mA/V , and Vt = 1 V. For VDD = 5 V and VOV = 0.5 V, provide a table of values
for Av , v̂o , and the corresponding v̂i for VDS = 1 V, 1.5 V,
CHAPTER 6

(a) Find the coordinates of the two end points of the  2

2 V, and 2.5 V. If kn (W/L) = 1 mA/V , find ID and RD for the
saturation-region segment of the amplifier transfer char- design for which VDS = 1 V.
acteristic, that is, points A and B in Fig. 6.4(b).
(b) If the amplifier is biased to operate with an overdrive *6.13 Figure P6.9 shows an amplifier in which the load
voltage VOV of 0.5 V, find the coordinates of the bias resistor RD has been replaced with another NMOS transistor
point Q on the transfer characteristic. Also, find the value Q2 connected as a two-terminal device. Note that because
of ID and of the incremental gain Av at the bias point. vDG of Q2 is zero, it will be operating in saturation at all
(c) For the situation in (b), and disregarding the distortion times, even when vI = 0 and iD2 = iD1 = 0. Note also that the
caused by the MOSFET’s square-law characteristic, two transistors conduct equal drain currents. Using iD1 = iD2 ,
what is the largest amplitude of a sine-wave voltage show that for the range of vI over which Q1 is operating in
signal that can be applied at the input while the transistor saturation, that is, forthe output voltage will be given by
remains in saturation? What is the amplitude of the
Vt1 ≤ vI ≤ vO + Vt1
output voltage signal that results? What gain value  
does the combination of these amplitudes imply? By (W/L)1 (W/L)1
vO = VDD − Vt + V− v
what percentage is this gain value different from the (W/L)2 t (W/L)2 I
incremental gain value calculated above? Why is there
a difference? VDD

6.11 Various measurements are made on an NMOS ampli-

fier for which the drain resistor RD is 20 k. First, dc
measurements show the voltage across the drain resistor, VRD , iD2
to be 1.5 V and the gate-to-source bias voltage to be 0.7 V.
Then, ac measurements with small signals show the voltage Q2
gain to be –10 V/V. What is the value of Vt for this transistor?
 2 vO
If the process transconductance parameter kn is 200 µA/V ,
what is the MOSFET’s W/L? iD1

*6.12 The expression for the incremental voltage gain Av vI Q1

given in Eq. (6.16) can be written as

 
2 VDD − VDS
Av = − Figure P6.9
VOV
where we have assumed Vt1 = Vt2 = Vt . Thus the circuit
functions as a linear amplifier, even for large input signals.
where VDS is the bias voltage at the drain. This indicates
For (W/L)1 = (50 µm/0.5 µm) and (W/L)2 = (5 µm/0.5 µm),
that for given values of VDD and VOV , the gain magnitude
find the voltage gain.
can be increased by biasing the transistor at a lower VDS .
This, however, reduces the allowable output signal swing in 6.14 For the amplifier circuit in Fig. 6.6 with VCC = + 5 V
the negative direction. Assuming linear operation around and RC = 1 k, find VCE and the voltage gain at the following
the bias point, show that the largest possible negative dc collector bias currents: 0.5 mA, 1 mA, 2.5 mA, 4 mA, and

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 459

CHAPTER 6
4.5 mA. For each, give the maximum possible positive- and *6.18 In deriving the expression for small-signal volt-
negative-output signal swings as determined by the need to age gain Av in Eq. (6.21) we neglected the Early effect.
keep the transistor in the active region. Present your results Derive this expression including the Early effect by
in a table. substituting

D 6.15 Consider the CE amplifier circuit of Fig. 6.6 when

 
operated with a dc supply VCC = +5 V. It is required to find vBE /VT v
iC = IS e 1 + CE
the point at which the transistor should be biased; that is, find VA

PROBLEMS
the value of VCE so that the output sine-wave signal vce result-
ing from an input sine-wave signal vbe of 5-mV peak ampli-  
in Eq. (6.4) and including the factor 1 + VCE /VA in
tude has the maximum possible magnitude. What is the peak
Eq. (6.11). Show that the gain expression changes to
amplitude of the output sine wave and the value of the gain
obtained? Assume linear operation around the bias point.
 
(Hint: To obtain the maximum possible output amplitude for −I C RC /VT VCC − VCE VT
Av = =−
a given input, you need to bias the transistor as close to the I R V − VCE
1+ C C 1 + CC
edge of saturation as possible without entering saturation at VA + VCE VA + VCE
any time, that is, without vCE decreasing below 0.3 V.)

D *6.16 A BJT amplifier such as that in Fig. 6.6 is to be For the case VCC = 5 V and VCE = 3 V, what is the gain
designed to support relatively undistorted sine-wave output without and with the Early effect taken into account?
signals of peak amplitudes P volts without the BJT entering Let VA = 100 V.
saturation or cutoff and to have the largest possible voltage
gain, denoted Av V/V. Show that the minimum supply 6.19 When the amplifier circuit of Fig. 6.6 is biased with
voltage VCC needed is given by a certain VBE , the dc voltage at the collector is found
to be +1 V. For VCC = +3 V and RC = 2 k, find IC
  and the small-signal voltage gain. For a change vBE =
VCC = VCEsat + P + Av VT
+5 mV, calculate the resulting vO . Calculate it two ways:
Also, find VCC , specified to the nearest 0.5 V, for the by using the transistor exponential characteristic iC , and
following situations: approximately, using the small-signal voltage gain. Repeat
for vBE = −5 mV. Summarize your results in a table.
(a) Av = −20 V/V, P = 0.2 V
(b) Av = −50 V/V, P = 0.5 V 6.20 The essence of transistor operation is that a change
(c) Av = −100 V/V, P = 0.5 V in vBE , vBE , produces a change in iC , iC . By keep-
(d) Av = −100 V/V, P = 1.0 V ing vBE small, iC is approximately linearly related to
(e) Av = −200 V/V, P = 1.0 V vBE , iC = gm vBE , where gm is known as the transistor
(f) Av = −500 V/V, P = 1.0 V transconductance. By passing iC through RC , an output
(g) Av = −500 V/V, P = 2.0 V voltage signal vO is obtained. Use the expression for the
small-signal voltage gain in Eq. (6.20) to derive an expres-
6.17 Sketch and label the voltage-transfer characteristic of sion for gm . Find the value of gm for a transistor biased at
the pnp amplifier shown in Fig. P6.17. IC = 0.5 mA.

6.21 The purpose of this problem is to illustrate the applica-

tion of graphical analysis to the circuit shown in Fig. P6.21.
vI Sketch iC −vCE characteristic curves for the BJT for iB =
10 µA, 20 µA, 30 µA, and 40 µA. Assume the lines to be
vO horizontal (i.e., neglect the Early effect), and let β = 100.
For VCC = 5 V and RC = 1 k, sketch the load line.
RC
What peak-to-peak collector voltage swing will result for
iB varying over the range 10 µA to 40 µA? If the BJT is
VCC = 5 V biased at VCE = 12 VCC , find the value of IC and IB . If at this
current VBE = 0.7 V and if RB = 100 k, find the required
Figure P6.17 value of VBB .
 460 Chapter 6 Transistor Amplifiers

VCC V and RD = 10 k. If the gain is to be −10 V/V, what

PROBLEMS

gm is required? Bias the amplifier as close to the edge of

the saturation region as possible consistent with the required
VBB iC RC signal swing. Specify the required values of VOV and ID . If
 2
kn = 380 µA/V what W/L ratio is required? If Vt = 0.4 V,
find VGS .
RB 6.25 For the NMOS amplifier in Fig. P6.25, replace the
CHAPTER 6

transistor with its T equivalent circuit, assuming λ = 0.

vCE
Derive expressions for the voltage gains vs /vi and vd /vi .
iB

Figure P6.21

**6.22 Sketch the iC −vCE characteristics of an npn transistor

having β = 100 and VA = 100 V. Sketch characteristic curves
for iB = 20 µA, 50 µA, 80 µA, and 100 µA. For the purpose
of this sketch, assume that iC = β iB at vCE = 0. Also, sketch
the load line obtained for VCC = 10 V and RC = 1 k. If the dc
bias current into the base is 50 µA, write the equation for the
corresponding iC −vCE curve. Also, write the equation for the
load line, and solve the two equations to obtain VCE and IC .
If the input signal causes a sinusoidal signal of 30-µA peak
amplitude to be superimposed on IB , find the corresponding
signal components of iC and vCE . Figure P6.25

 6.26
 In the circuit of Fig. P6.26, the NMOS transistor
Section 6.2: Small-Signal Operation has Vt  = 0.8 V and VA = 20 V and operates with VD = 1 V.
and Models What is the voltage gain vo /vi ? What do VD and the gain
become for I increased to 1 mA?
6.23 For the amplifier in Fig. 6.10, let VDD = 2 V, RD =
 2
15 k,Vt = 0.5 V, kn = 0.4 mA/V , W/L = 12.5, VGS = 0.7
V, and λ = 0.

(a) Find the dc current ID and the dc voltage VDS . 200

(b) Find gm .
(c) Find the voltage gain. vo
(d) If vgs = 0.015 sin ωt volts, find vds assuming that 22 M
the small-signal approximation holds. What are the
15 k
minimum and maximum values of vDS ?
(e) Use Eq. (6.28) to determine the various components of
2
iD . Using the identity sin ωt = 12 − 12 cos 2ωt, determine
the second-harmonic distortion defined as the ratio of the
component of iD of frequency 2ω to the component of iD Figure P6.26
of frequency ω, multiplied by 100.
6.27 Figure P6.27 shows a discrete-circuit amplifier. The
D 6.24 The NMOS amplifier of Fig. 6.10 is to be designed input signal vsig is coupled to the gate through a very
to provide a 0.2-V peak output signal. Assume VDD = 1.8 large capacitor (shown as infinite). The transistor source is

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 461

15 V

CHAPTER 6
10 M 16 k

vo
Rsig = 200 k  vgs

PROBLEMS
16 k


vsig 

5 M 7 k

Rin

Figure P6.27

Transistor a b c d e f g
α 1.000 0.90
β 100 ∞
IC (mA) 1.00 1.00
IE (mA) 1.00 5
IB (mA) 0.020 1.10
gm (mA/V) 700
re () 25 100
rπ () 10.1 k

connected to ground at signal frequencies via a very large collector current iC and total collector voltage vC using the
capacitor (shown as infinite). The output voltage signal that exponential iC –vBE relationship. For this situation, what are
develops at the drain is coupled to a load resistance via a very vbe and vc ? Calculate the voltage gain vc /vbe . Compare with
large capacitor (shown as infinite). All capacitors behave as the value obtained using the small-signal approximation, that
short circuits for signals and as open circuits for dc. is, –gm RC .
2
(a) If the transistor has Vt = 1 V, and kn = 4 mA/V , verify 6.29 A pnp BJT is biased to operate at IC = 1.0 mA. What is
that the bias circuit establishes VGS = 1.5 V, ID = 0.5 mA, the associated value of gm ? If β = 100, what is the value of
and VD = +7.0 V. That is, assume these values, and the small-signal resistance seen looking into the emitter (re )?
verify that they are consistent with the values of the Into the base (rπ )? If the collector is connected to a 5-k
circuit components and the device parameters. load, with a signal of 5-mV peak applied between base and
(b) Find gm and ro if VA = 100 V. emitter, what output signal voltage results?
(c) Draw a complete small-signal equivalent circuit for
the amplifier, assuming all capacitors behave as short 6.30 The table above summarizes some of the basic
circuits at signal frequencies. attributes of a number of BJTs of different types, operating
(d) Find Rin , vgs /vsig , vo /vgs , and vo /vsig . as amplifiers under various conditions. Provide the missing
entries.
6.28 An npn BJT with grounded emitter is operated with
VBE = 0.700 V, at which the collector current is 0.5 mA. A 6.31 A BJT is biased to operate in the active mode at a dc
5-k resistor connects the collector to a +5-V supply. What collector current of 1 mA. It has a β of 100 and VA of 100 V.
is the resulting collector voltage VC ? Now, if a signal applied Give the four small-signal models (Figs. 6.26 and 6.28) of
to the base raises vBE to 705 mV, find the resulting total the BJT complete with the values of their parameters.
 462 Chapter 6 Transistor Amplifiers

6.32 The transistor amplifier in Fig. P6.32 is biased with a 6.34 Figure P6.34 shows a transistor with the collector
PROBLEMS

current source I and has a very high β. Find the dc voltage connected to the base. The bias arrangement is not shown.
at the collector, VC . Also, find the value of re . Replace the Since a zero vBC implies operation in the active mode, the
transistor with the T model of Fig. 6.27(b) (note that the dc BJT can be replaced by one of the small-signal models
current source I should be replaced with an open circuit). of Figs. 6.25 and 6.27. Use the model of Fig. 6.27(b) and
Hence find the voltage gain vc /vi . show that the resulting two-terminal device, known as a
3
diode-connected transistor, has a small-signal resistance r
CHAPTER 6

equal to re .

10 k ix

vx

I 0.2 mA
v
r = ix
x

Figure P6.32 Figure P6.34

6.33 Figure P6.33 shows the circuit of an amplifier fed with 6.35 For the circuit shown in Fig. P6.35, draw a complete
a signal source vsig with a source resistance Rsig . The bias small-signal equivalent circuit using an appropriate T model
for the BJT (use α = 0.99). You should show the values of
all components, including the model parameters. What is
the input resistance Rin ? Calculate the overall voltage gain
Rsig ib  
vo /vsig .

5V
RC
vo
vsig
v
12 k RC
C2
vo
Rin
RL
Figure P6.33 Q1
12 k
Rsig C1
circuitry is not shown. Replace the BJT with its hybrid-π
equivalent circuit of Fig. 6.25(a). Find the input resistance
75
Rin ≡ vπ /ib , the voltage transmission from source to amplifier
input, vπ /vsig , and the voltage gain from base to collector,
vsig 0.33 mA
vo /vπ . Use these to show that the overall voltage gain vo /vsig
is given by
Rin
vo βRC
=−
vsig rπ + Rsig Figure P6.35

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 463

CHAPTER 6
D *6.36 Design an amplifier using the configuration of parameters (gm and ro ) for both an NMOS and a PMOS
Fig. 6.31(a). The power supplies available are ±5 V. The transistor having W/L = 10 µm/0.5 µm and operating at ID
input signal source has a resistance of 50 , and it is = 100 µA. Also, find the overdrive voltage at which each
required that the amplifier input resistance match this device must be operating.
value. (Note that Rin = re RE  re .) The amplifier is to
6.42 Consider a transistor biased to operate in the active
have the greatest possible voltage gain and the largest
mode at a dc collector current IC . Calculate the collector
possible output signal but retain small-signal linear oper-
signal current as a fraction of IC (i.e., ic /IC ) for input signals

PROBLEMS
ation (i.e., the signal component across the base–emitter
vbe of +1 mV, –1 mV, +2 mV, –2 mV, +5 mV, –5 mV,
junction should be limited to no more than 10 mV).
+8 mV, –8 mV, +10 mV, –10 mV, +12 mV, and –12 mV.
Find appropriate values for RE and RC . What is the
In each case do the calculation two ways:
value of voltage gain realized from signal source to out-
put? (a) using the exponential characteristic, and
(b) using the small-signal approximation.
6.37 This problem investigates the nonlinear distortion
introduced by a MOSFET amplifier. Let the signal vgs Present your results in the form of a table that includes
be a sine wave with amplitude Vgs , and substitute vgs = a column for the error introduced by the small-signal
Vgs sin ωt in Eq. (6.28). Using the trigonometric identity approximation. Comment on the range of validity of the
2
sin θ = 12 − 12 cos 2θ , show that the ratio of the signal small-signal approximation.
at frequency 2ω to that at frequency ω, expressed as a
percentage (known as the second-harmonic distortion) is 6.43 A transistor with β = 100 is biased to operate at a dc
collector current of 0.5 mA. Find the values of gm , rπ , and re .
1 Vgs
Second-harmonic distortion = × 100 Repeat for a bias current of 50 µA.
4 VOV
D 6.44 A designer wishes to create a BJT amplifier with
If in a particular application Vgs is 10 mV, find the minimum
a gm of 30 mA/V and a base input resistance of 3000  or
overdrive voltage at which the transistor should be operated
more. What collector-bias current should he choose? What is
so that the second-harmonic distortion is kept to less
the minimum β he can tolerate for the transistor used?
than 1%.
6.45 A transistor operating with nominal gm of 40 mA/V
6.38 Consider the FET amplifier of Fig. 6.10 for the case
2 has a β that ranges from 50 to 150. Also, the bias circuit,
Vt = 0.4 V, kn = 5 mA/V , VGS = 0.6 V, VDD = 1.8 V, and
being less than ideal, allows a ±20% variation in IC . What
RD = 10 k.
are the extreme values found of the resistance looking into
(a) Find the dc quantities ID and VDS . the base?
(b) Calculate the value of gm at the bias point.
6.46 In the circuit of Fig. 6.21, VBE is adjusted so that VC =
(c) Calculate the value of the voltage gain.
−1 1 V. If VCC = 3 V, RC = 2 k, and a signal vbe = 0.005 sin ωt
(d) If the MOSFET has λ = 0.1 V , find ro at the bias point
volts is applied, find expressions for the total instantaneous
and calculate the voltage gain.
quantities iC (t), vC (t), and iB (t). Assume linear operation. The
2
6.39 An NMOS transistor has μn Cox = 400 µA/V , W/L = transistor has β = 100. What is the voltage gain?
20, Vt = 0.5 V, and VA = 5 V. Find gm and ro when (a) D *6.47 We wish to design the amplifier circuit of Fig. 6.21
the bias voltage VGS = 0.75 V, (b) the bias current ID = under the constraint that VCC is fixed. Let the input signal
0.5 mA. vbe = V̂be sin ωt, where V̂be is the maximum value for
2
6.40 An NMOS technology has μn Co x = 250 µA/V and acceptable linearity. For the design that results in the largest
Vt = 0.5 V. For a transistor with L = 0.5 µm, find the value signal at the collector, without the BJT leaving the active
of W that results in gm = 2 mA/V at ID = 0.25 mA. Also, find region, show that

the required VGS .   V̂be
RC IC = VCC − 0.3 1+
6.41 For a 0.18-µm CMOS fabrication process: Vtn = 0.5 V, VT
2 2
Vtp = –0.5 V, μn Co x = 400 µA/V , μp Co x = 100 µA/V ,Co x
= 8.6 fF/µm , VA (n-channel devices) = 5L (µm), and VA 
2
and find an expression for the voltage gain obtained. For
(p-channel devices) = 6L (µm). Find the small-signal model VCC = 3 V and V̂be = 5 mV, find the dc voltage at the collector,
 464 Chapter 6 Transistor Amplifiers

5V
the amplitude of the output voltage signal, and the voltage
PROBLEMS

gain.
1.5 V
10 mA
6.48 Using the T model of Fig. 6.27(a), show that the input
resistance between base and emitter, looking into the base, is 10 k
equal to rπ . Rsig vb

6.49 Show that the collector current provided by the model 1k

CHAPTER 6

of Fig. 6.27(b) is equal to that provided by the model in vo

vsig
Fig. 6.27(a). RC
100
6.50 Show that the hybrid-π model of Fig. 6.25(b) is the
Rin Rib
incremental version of the large-signal model of Fig. 4.5(d).
6.51 Show that the T model of Fig. 6.27(b) is the incremen- Figure P6.54
tal version of the large-signal model of Fig. 4.5(b). 6.55 Consider the augmented hybrid-π model shown in
6.52 For the conceptual circuit shown in Fig. 6.24, Fig. 6.26(a). Disregarding how biasing is to be done, what is
RC = 2 k, gm = 50 mA/V, and β = 100. If a peak-to-peak the largest possible voltage gain available for a signal source
output voltage of 1 V is measured at the collector, what are connected directly to the base and a very-high-resistance
the peak-to-peak values of vbe and ib ? load? Calculate the value of the maximum possible gain for
VA = 25 V and VA = 125 V.
6.53 Figure P6.53 shows a particular configuration of
BJT amplifiers known as “emitter follower.” The bias D 6.56 Redesign the circuit of Fig. 6.31(a) by raising the
arrangement is not shown. Replace the BJT with its T resistor values by a factor of n to increase the resistance seen
equivalent-circuit model of Fig. 6.27(b). Show that by the input vi to 75 . What value of voltage gain results?
  Grounded-base circuits of this kind are used in systems
vi
Rin ≡ = (β + 1) re + Re such as cable TV, in which, for highest-quality signaling,
ib
load resistances need to be “matched” to the equivalent
vo Re
= resistances of the interconnecting cables.
vi Re + r e
*6.57 The transistor in the circuit shown in Fig. P6.57 (see
page 465) is biased to operate in the active mode. Assuming
that β is very large, find the collector bias current IC . Replace
ib the transistor with the small-signal equivalent-circuit model
of Fig. 6.27(b) (remember to replace the dc power sup-
ply with a short circuit). Analyze the resulting amplifier
equivalentcircuit to show that
vi vo1 RE
v i = RE + r e
Re
vo
vo2 −αRC
v i = RE + r e
Rin
Find the values of these voltage gains (for α  1). Now, if
Figure P6.53 the terminal labeled vo1 is connected to ground, what does the
voltage gain vo2 /vi become?
6.54 In the circuit shown in Fig. P6.54, the transistor has a
β of 200. What is the dc voltage at the collector? Replacing
Section 6.3: Basic Configurations
the BJT with one of the hybrid-π models (neglecting ro ),
draw the equivalent circuit of the amplifier. Find the input D 6.58 Specify the parameters Rin , Av o , and Ro of an
 
resistances Rib and Rin and the overall voltage gain vo /vsig . amplifier that is to be connected between a 100-k source
For an output signal of ±0.4 V, what values of vsig and vb are and a 2-k load and is required to meet the following
required? specifications:

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 465

5V between base and emitter is to be limited to 5 mV, what v̂sig

CHAPTER 6
is allowed, and what output voltage signal appears across the
load?
3.3
6.63 The overall voltage gain of a CS amplifier with a
resistance Rs = 200  in the source lead is measured and
found to be −10 V/V. When Rs is shorted, but the circuit

PROBLEMS
operation remains linear, the gain doubles. What must gm
and RD be? What value of Rs is needed to obtain an overall
voltage gain of −16 V/V?
3.6
6.64 A CE amplifier uses a BJT with β = 100 biased at
IC = 0.5 mA and has a collector resistance RC = 15 k and a
resistance Re = 200  connected in the emitter. Find Rin , Av o ,
Figure P6.57 and Ro . If the amplifier is fed with a signal source having
a resistance of 10 k, and a load resistance RL = 15 k is
(a) No more than 5% of the signal strength is lost in the connected to the output terminal, find the resulting Av and
connection to the amplifier input; Gv . If the peak voltage of the sine wave appearing between
(b) If the load resistance changes from the nominal value of base and emitter is to be limited to 5 mV, what v̂sig is allowed,
2 k to a low value of 1 k, the change in output voltage and what output voltage signal appears across the load?
is limited to 5% of nominal value; and
(c) The nominal overall voltage gain is 10 V/V. 6.65 A CG amplifier when fed with a signal source having
Rsig = 100  is found to have an overall voltage gain of
6.59 An amplifier has an input resistance of 100 k, a 12 V/V. When a 100- resistance is added in series with
short-circuit transconductance of 10 mA/V, and an output the signal generator, the overall voltage gain decreases to
resistance of 100 k. Find the open-circuit voltage gain Av o , 10 V/V. What must gm of the MOSFET be? If the MOSFET
and the overall voltage gain Gv when the amplifier is fed with is biased at ID = 0.25 mA, at what overdrive voltage must it
a voltage source having Rsig = 100 k, and a load resistance be operating?
RL = 100 k is connected at the output.
6.66 For the circuit in Fig. P6.66, let Rsig re and α  1.
6.60 A CS amplifier utilizes a MOSFET with μn Co x =
2 Find vo .
400 µA/V and W/L = 10. It is biased at ID = 320 µA and
uses RD = 10 k. Find Rin , Av o , and Ro . Also, if a load
resistance of 10 k is connected to the output, what overall
voltage gain Gv is realized? Now, if a 0.2-V peak sine-wave
signal is required at the output, what must the peak amplitude RC vo
of vsig be?

6.61 Two identical CS amplifiers are connected in cascade.

The first stage is fed with a source vsig having a resistance
Rsig = 200 k. A load resistance RL = 10 k is connected
to the drain of the second stage. Each MOSFET is biased isig Rsig
at ID = 0.3 mA and operates with VOV = 0.2 V. Each stage
utilizes a drain resistance RD = 10 k.

(a) Sketch the equivalent circuit of the two-stage amplifier.

(b) Calculate the overall voltage gain Gv .
Figure P6.66
6.62 A CE amplifier utilizes a BJT with β = 100 biased at
IC = 0.5 mA; it has a collector resistance RC = 10 k. Find
Rin , Ro , and Av o . If the amplifier is fed with a signal source D 6.67 A source follower is required to deliver a 0.5-V peak
having a resistance of 10 k, and a load resistance RL = 10 sinusoid to a 2-k load. If the peak amplitude of vgs is to
k is connected to the output terminal, find the resulting be limited to 50 mV, and the MOSFET transconductance
2
Av and Gv . If the peak voltage of the sine wave appearing parameter kn is 5 mA/V , what is the lowest value of ID at
 466 Chapter 6 Transistor Amplifiers

which the MOSFET can be biased? At this bias current, what Also find the current gain, defined as the ratio of the load
PROBLEMS

are the maximum and minimum currents that the MOSFET current to the current drawn from the signal source.
will be conducting (at the positive and negative peaks of
6.72 An alternative equivalent circuit of an amplifier fed
the output sine wave)? What must the peak amplitude
with a signal source (vsig , Rsig ) and connected to a load RL
of vsig be?
is shown in Fig. P6.72. Here Gv o is the open-circuit overall
D 6.68 An emitter follower is required to deliver a 0.5-V voltage gain,
peak sinusoid to a 2-k load. If the peak amplitude of vbe 
CHAPTER 6

vo 
is to be limited to 5 mV, what is the lowest value of IE at Gv o = v 
sig R = ∞
L
which the BJT can be biased? At this bias current, what are
the maximum and minimum currents that the BJT will be and Rout is the output resistance with vsig set to zero. This is
conducting (at the positive and negative peaks of the output different from Ro . Show that
sine wave)? If the resistance of the signal source is 200 k,
what value of Gv is obtained? Thus determine the required
Ri
amplitude of vsig . Assume β = 100. Gv o = A
Ri + Rsig v o
6.69 For the Darlington follower in Fig. 6.48(b) let Q2 be 
where Ri = Rin R = ∞ .
biased at a collector current of 10 mA and let β1 = β2 = 100. L
Also show that the overall voltage gain is
If Rsig = 1 M and RL = 1 k, find Gvo , Rout , and Gv .
RL
6.70 For the general amplifier circuit shown in Fig. P6.70 Gv = Gv o
RL + Rout
neglect the Early effect.
*6.73 Most practical amplifiers have internal feedback that
(a) Find expressions for vc /vsig and ve /vsig . makes them non-unilateral. In such a case, Rin depends
(b) If vsig is disconnected from node X, node X is grounded, on RL . To illustrate this point we show in Fig. P6.73 the
and node Y is disconnected from ground and connected equivalent circuit of an amplifier where a feedback resistance
to vsig , find the new expression for vc /vsig . Rf models the internal feedback mechanism that is present in
this amplifier. It is Rf that makes the amplifier non-unilateral.
ic Show that
vc    
Rf + R2 RL
Rin = R1  
RB ib 1 + gm R2 RL
X  
RC 1 − 1/ gm Rf
Av o = −gm R2  
1 + R2 /Rf
ie ve
Ro = R2 Rf
vsig RE Evaluate Rin , Av o , and Ro for the case R1 = 100 k, Rf =
1 M, gm = 100 mA/V, R2 = 100 , and RL = 1 k.
Y Which of the amplifier characteristic parameters is most
affected by Rf (that is, relative to the case with Rf = ∞)?
For Rsig = 100 k determine the overall voltage gain, Gv ,
Figure P6.70
with and without Rf present.

6.74 Calculate the overall voltage gain of a CS amplifier

6.71 An amplifier with an input resistance of 100 k,
fed with a 1-M source and connected to a 10-k load.
an open-circuit voltage gain of 100 V/V, and an output
The MOSFET has gm = 2 mA/V, and a drain resistance
resistance of 100  is connected between a 20-k signal
RD = 10 k is utilized.
source and a 2-k load. Find the overall voltage gain Gv .

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 467

io

CHAPTER 6
Rsig Rout

 
vsig  vi Rin  RL vo

Gvovsig
 

PROBLEMS
Figure P6.72

Rsig ii Rf

 
vsig  vi R1 g mvi R2 RL vo

 

Rin

Figure P6.73

D 6.75 A common-source amplifier utilizes a MOSFET 50 to

 150, what value of bias current IC would result in
operated at VOV = 0.25 V. The amplifier feeds a load Gv  falling in a range of ±20% of a new nominal value?
 
resistance RL = 15 k. The designer selects RD = 2RL . If it What is the nominal value of Gv  in this case?
is required to realize an overall voltage gain Gv of −10 V/V
6.77 Two identical CE amplifiers are connected in cascade.
what gm is needed? Also specify the bias current ID . If, to
The first stage is fed with a source vsig having a resistance
increase the output signal swing, RD is reduced to RD = RL ,
Rsig = 10 k. A load resistance RL = 10 k is connected
what does Gv become?
to the collector of the second stage. Each BJT is biased at
D *6.76 In this problem we investigate the effect of the IC = 0.25 mA and has β = 100. Each stage utilizes a collector
inevitable variability of β on the realized gain of the CE resistance RC = 10 k.
amplifier. For this purpose, use the overall gain expression
in Eq. (6.114). (a) Sketch the equivalent circuit of the two-stage amplifier.
(b) Find the overall voltage gain, vo2 /vsig .

  R
Gv  =   L  6.78 A MOSFET connected in the CS configuration has
Rsig /β + 1/gm
a transconductance gm = 5 mA/V. When a resistance Rs is

where RL = RL RC . connected in the source lead, the effective transconductance

Consider the case RL = 10 k and Rsig = 10 k, and let is reduced to 2 mA/V. What do you estimate the value of Rs
the BJT be biased at IC = 1 mA. The BJT has a nominal β of to be?
100.
  D 6.79 A CS amplifier using an NMOS transistor with gm =
(a) What is the nominal value of Gv ? 2 mA/V is found to have an overall voltage gain of −10 V/V.
(b) If β can be anywhere between
  50 and 150, what is the What value should a resistance Rs inserted in the source lead
corresponding range of Gv ?   have to reduce the overall voltage gain to −5 V/V?
(c) If in a particular design, it is required to maintain Gv 
within ±20% of its nominal value, what is the maximum D 6.80 Design a CE amplifier with a resistance Re in the
allowable range of β? emitter to meet the following specifications:
(d) If it is not possible to restrict β to the range found in
(c), and the designer has to contend with β in the range (i) Input resistance Rin = 15 k.
 468 Chapter 6 Transistor Amplifiers

2
(ii) When fed from a signal source with a peak amplitude kn = 10 mA/V , at what current ID must it be biased? At what
PROBLEMS

of 0.15 V and a source resistance of 30 k, the peak overdrive voltage is the MOSFET operating?
amplitude of vπ is 5 mV.
6.86 An emitter follower with a BJT biased at IC = 5 mA
Specify Re and the bias current IC . The BJT has β = 74. and having β = 200 is connected between a source with Rsig =
If the total resistance in the collector is 6 k, find the 10 k and a load RL = 200 .
overall voltage gain Gv and the peak amplitude of the output
(a) Find Rin , vb /vsig , and vo /vsig .
signal vo .
CHAPTER 6

(b) If the signal amplitude across the base–emitter junction

D 6.81 Including an emitter resistance Re reduces the is to be limited to 10 mV, what is the corresponding
variability of the gain Gv due to the inevitable wide variance amplitude of vsig and vo ?
in the value of β. Consider a CE amplifier operating between (c) Find the open-circuit voltage gain Gv o and the output
a signal source with Rsig = 10 k and a total collector resistance Rout . Use these values first to verify the value
resistance RC RL of 10 k. The BJT is biased at IC = 1 mA of Gv obtained in (a), then to find the value of Gv
and its β is specified to be nominally 100 but can lie in the obtained with RL reduced to 150 .
range of 50 to
 150. First determine the nominal value and the 6.87 An emitter follower, when driven from a 10-k source,
range of Gv  without resistance
 Re . Then select a value for Re was found to have an output resistance Rout of 125 .
that will ensure that Gv  be within ±20% of its new nominal   The output resistance increased to 225  when the source
value. Specify the value of Re , the new nominal value of Gv , resistance was doubled. Find the overall voltage gain when
and the expected range of Gv . the follower is driven by a 10-k source and loaded with a
1-k resistor.
6.82 A CG amplifier using an NMOS transistor for which
gm = 5 mA/V has a 5-k drain resistance RD and a 5-k load 6.88 When the Early effect is neglected, the overall voltage
resistance RL . The amplifier is driven by a voltage source gain of a CE amplifier with a collector resistance RC =
with a 250- resistance. What is the input resistance of the 10 k is calculated to be −100 V/V. If the BJT is biased
amplifier? What is the overall voltage gain Gv ? By what at IC = 1 mA and the Early voltage is 125 V, provide a better
factor must the bias current ID of the MOSFET be changed estimate of the voltage gain Gv .
so that Rin matches Rsig ?
6.89 Show that when ro is taken into account, the voltage
D 6.83 A CB amplifier is operating with RL = 5 k, RC = gain of the source follower becomes
5 k, and Rsig = 50 . At what current IC should the transistor vo RL r o
Gv ≡ =  1
be biased for the input resistance Rin to equal that of the signal vsig RL r o +
source? What is the resulting overall voltage gain? Assume gm
α  1. Now, with RL removed, the voltage gain is carefully mea-
sured and found to be 0.98. Then, when RL is connected
6.84 A CB amplifier biased at IE = 0.2 mA with RC = RL = and its value is varied, it is found that the gain is halved at
10 k is driven by a signal source with Rsig = 0.5 k. Find RL = 500 . If the amplifier remained linear throughout this
the overall voltage gain Gv . If the maximum signal amplitude measurement, what must the values of gm and ro be?
of the voltage between base and emitter is limited to 10 mV,
what are the corresponding amplitudes of vsig and vo ? Assume D *6.90 In this problem, we investigate the effect of chang-
α  1. ing the bias current IC on the overall voltage gain Gv of a CE
amplifier. Consider a CE amplifier operating with a signal
6.85 A source follower is required to connect a source Rsig = 10 k and with RC ||RL = 10 k. The BJT is
high-resistance source to a load whose resistance is specified to have β = 100 and VA = 25 V. Use Eq. (6.114)
nominally 2 k but can be as low as 1.5 k and as high (with ro included
 in parallel with RC and RL in the numerator)
as 5 k. What is the maximum output resistance that to find Gv  at IC = 0.1 mA, 0.2 mA, 0.5 mA, 1.0 mA, and
the source follower must have if the output voltage is to 1.25 mA. Observe the effect of ro on limiting  
 Gv as IC is
remain within ±10% of nominal value? If the MOSFET has increased. Find the value of IC that results in Gv  = 50 V/V.

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 469

Section 6.4: Biasing

CHAPTER 6
For each case, specify the values of VG , VD , VS , R1 , R2 , RS ,
and RD .
D 6.91 Consider the classical biasing scheme shown in
Fig. 6.50(c), using a 9-V supply. For the MOSFET, Vt = D 6.95 Figure P6.95 shows a variation of the feedback-bias
2
0.7 V, λ = 0, and kn = 5 mA/V . Arrange that the drain circuit of Fig. 6.52. Using a 5-V supply with an NMOS
2
current is 0.2 mA, with about one-third of the supply voltage transistor for which Vt = 0.8 V, kn = 8 mA/V , and λ = 0,
across each of RS and RD . Use 22 M for the larger of RG1 provide a design that biases the transistor at ID = 1 mA, with
and RG2 . What are the values of RG1 , RG2 , RS , and RD that VDS large enough to allow saturation operation for a 2-V

PROBLEMS
you have chosen? Specify them to two significant digits. For negative signal swing at the drain. Use 22 M as the largest
your design, how far is the drain voltage from the edge of resistor in the feedback-bias network. What values of RD ,
saturation? RG1 , and RG2 have you chosen? Specify all resistors to two
significant digits.
D 6.92 Using the circuit topology displayed in Fig. 6.50(e),
arrange to bias the NMOS transistor at ID = 0.5 mA with VDD
VD midway between cutoff and the beginning of triode
operation. The available supplies are ±5 V. For the NMOS
2
transistor, Vt = 1.0 V, λ = 0, and kn = 1 mA/V . Use a RD
gate-bias resistor of 10 M. Specify RS and RD to two
RG1
significant digits.

6.93 An NMOS transistor is connected in the bias circuit of

Fig. 6.50(c), with VG = 5 V and RS = 3 k. The transistor
2
has Vt = 1 V and kn = 2 mA/V . What bias current results?
If a transistor for which kn is 50% higher is used, what is the RG2
resulting percentage increase in ID ?

D 6.94 Design the circuit in Fig. P6.94 so that the

transistor operates in saturation with VD biased 1 V from the
Figure P6.95
edge of the triode region, with ID = 1 mA and VD = 3 V, for
each of the following two devices (use a 10-µA current in D 6.96 Consider the single-supply bias network shown in
the voltage divider): Fig. 6.54(a). Provide a design using a 9-V supply in which
 
(a) Vt  = 1 V and kp W/L = 0.5 mA/V
 2 the supply voltage is equally split between RC , VCE , and RE
  
(b) Vt = 2 V and kp W/L = 1.25 mA/V
2 with a collector current of 0.6 mA. The transistor β is spec-
ified to have a minimum value of 90. Use a voltage-divider
current of IE /10, or slightly higher. Since a reasonable design
10 V
should operate for the best transistors for which β is very
high, do your initial design with β = ∞. Then choose suitable
5% resistors (see Appendix J), making the choice in a way
R1 RS that will result in a VBB that is slightly higher than the ideal
value. Specify the values you have chosen for RE , RC , R1 ,
and R2 . Now, find VB , VE , VC , and IC for your final design
VS
using β = 90.
VG
D 6.97 Design the circuit in Fig. 6.55 using ±1.5-V sup-
VD
plies, IC = 0.2 mA, and VC placed 1 V above VE . The transis-
tor to be used has a minimum β of 50. Design for the device
R2 RD with the lowest β and use the largest value for RB consistent
with limiting the voltage drop across it to approximately
one-tenth the voltage drop across RE . Use standard 5% resis-
tors (see Appendix J). Evaluate your design by calculating
Figure P6.94 IC , VE , VB , and VC for the two cases: β = ∞ and β = 50.
 470 Chapter 6 Transistor Amplifiers

D *6.98 (a) Using a 3-V power supply, design the feedback D 6.100 For the circuit in Fig. P6.100 find the value of R
PROBLEMS

bias circuit of Fig. 6.56 to provide IC = 1 mA and VC = VCC /2 that will result in IO  0.5 mA. What is thelargest
 voltage
for β = 100. that can be applied to the collector? Assume VBE  = 0.7 V.
(b) Select standard 5% resistor values, and reevaluate VC and
IC for β = 100.
(c) Find VC and IC for β = ∞.
(d) To improve the situation that occurs when high-β
CHAPTER 6

transistors are used, we have to arrange for an additional

current to flow through RB . We can do this by connecting
a resistor between base and emitter, as shown in Fig. P6.98.

Design this circuit for β = 100. Use a current through RB2

equal to the base current. Now, what values of VC and IC
result with β = ∞?
VCC

RC Figure P6.100

D *6.101 In an electronic instrument using the biasing

VC
IC scheme shown in Fig. 6.50(c), a manufacturing error reduces
RB1 RS to zero. Let VDD = 15 V, RG1 = 10 M, and RG2 = 5.1 M.
What is the value of VG created? If supplier specifications
2
allow kn to vary from 0.2 to 0.3 mA/V and Vt to vary
from 1.0 V to 1.5 V, what are the extreme values of ID that
RB2 may result? What value of RS should have been installed
to limit the maximum value of ID to 1.5 mA? Choose an
appropriate standard 5% resistor value (refer to Appendix J).
Figure P6.98 What extreme values of current now result?

6.99 The circuit in Fig. P6.99 provides a constant current 6.102 The bias circuit of Fig. 6.50(c) is used in a
IO as long as the circuit to which the collector is connected design with VG = 5 V and RS = 2 k. For a MOSFET with
2
maintains the BJT in the active mode. Show that kn = 2 mA/V , the source voltage is 2 V. What must Vt be for
 
VCC R2 / R1 + R2 − VBE this device? In a device for which Vt is 0.5 V less, what does
IO = α   VS become? What bias current results?
RE + R1 R2 /(β + 1)
D 6.103 Design the circuit of Fig. 6.50(e) for a MOSFET
2
having Vt = 1 V and kn = 4 mA/V . Let VDD = VSS = 5 V.
Design for a dc bias current of 0.5 mA and for the largest
possible voltage gain (and thus the largest possible RD )
consistent with allowing a 2-V peak-to-peak voltage swing
at the drain. Assume that the signal voltage on the source
terminal of the FET is zero.

D **6.104 A very useful way to characterize the stability

of the bias current ID is to evaluate the sensitivity of ID
relative to a particular transistor parameter whose variability
Figure P6.99 might be large. The sensitivity of ID relative to the MOSFET

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 471


parameter K ≡ 12 k (W/L) is defined as 6.106 In the circuit of Fig. 6.52, let RG = 10 M,

CHAPTER 6
RD = 5 k, and VDD = 5 V. For each of the following two
I ∂ID /ID ∂I K
SKD ≡ = D transistors, find the voltages VD and VG .
∂K/K ∂K ID
2
and its value, when multiplied by the variability (or toler- (a) Vt = 0.7 V and kn = 5 mA/V
2
ance) of K, provides the corresponding expected variability (b) Vt = 1.5 V and kn = 10 mA/V
of ID ,   D 6.107 Using the feedback bias arrangement shown in

PROBLEMS
ID I K
= SKD Fig. 6.52 with a 5-V supply and an NMOS device for which
ID K 2
Vt = 1 V and kn = 10 mA/V , find RD to establish a drain
The purpose of this problem is to investigate the use of
current of 0.2 mA.
the sensitivity function in the design of the bias circuit of
Fig. 6.50(e).
D 6.108 For the circuit in Fig. 6.53(a), neglect the base
(a) Show that when Vt is constant, current IB in comparison with the current in the voltage
   divider. It is required to bias the transistor at IC = 1 mA,
I
SKD = 1 1 + 2 KID RS
which requires selecting RB1 and RB2 so that VBE = 0.710 V.
2 If VCC = 3 V, what must the ratio RB1 /RB2 be? Now, if RB1 and
(b) For a MOSFET having K = 100 µA/V with a variability
RB2 are 1% resistors, that is, each can be in the range of 0.99
of ±10% and Vt = 1 V, find the value of RS that would
to 1.01 of its nominal value, what is the range obtained for
result in ID = 100 µA with a variability of ±1%. Also,
VBE ? What is the corresponding range of IC ? If RC = 2 k,
find VGS and the required value of VSS .
what is the range obtained for VCE ? Comment on the efficacy
(c) Using the same MOSFET as in (a), if the available
of this biasing arrangement.
supply VSS = 5 V, find the value of RS for ID = 100 µA.
Evaluate the sensitivity function, and give the expected
variability of ID in this case. D 6.109 It is required to bias the transistor in the circuit of
Fig. 6.53(b) at IC = 1 mA. The transistor β is specified to be
D *6.105 The variability (ID /ID ) in the bias current ID due nominally 100, but it can fall in the range of 50 to 150. For
to the variability (Vt /Vt ) in the threshold voltage Vt can be VCC = +3 V and RC = 2 k, find the required value of RB to
evaluated from   achieve IC = 1 mA for the “nominal” transistor. What is the
ID I Vt
= SVDt expected range for IC and VCE ? Comment on the efficacy of
ID Vt
this bias design.
I
where SVDt , the sensitivity of ID relative to Vt , is defined as

I ∂ID Vt D 6.110 This problem investigates an alternative solution

SVDt = to the design problem specified in Problem 6.97. You are
∂Vt ID
required to design the bias circuit in Fig. 6.54(a) for the
case VCC = 9 V. Design for the supply voltage equally split
(a) For a MOSFET biased with a fixed VGS , show that
between RC , VCE , and RE with a collector current of IC = 0.5
I 2Vt mA. Your design should be based on a minimum value of 80
SVDt = −
VOV for the transistor β. Use a current in R1 equal to IC /10. Begin
and find the variability in ID for Vt = 0.5 V and Vt /Vt = your design by finding RE = VE /IE and then find RC , R1 , and
±5%. Let the MOSFET be biased at VOV = 0.25 V. R2 . Choose suitable 5% resistors (see Appendix J). Specify
(b) For a MOSFET biased with a fixed gate voltage VG the values you have chosen for RE , RC , R1 , and R2 , and find
and a resistance RS included in the source lead, show IE , IC , VB , and VC .
that
I 2Vt D *6.111 You are required to design the bias circuit of
SVDt = − Fig. 6.54(a) for a BJT whose nominal β = 100.
VOV + 2ID RS
 
For the same parameters given in (a), find the required (a) Find the largest ratio RB /RE that will guarantee IE
value of (ID RS ) and VG to limit ID /ID to ±5%. What remains within ±5% of its nominal value for β as low
value of RS is needed if ID is 100 µA? as 50 and as high as 150.
 472 Chapter 6 Transistor Amplifiers

(b) If the resistance ratio found in (a) is used, find an D *6.115 For the circuit in Fig. P6.115, assuming all tran-
 
PROBLEMS

expression for the voltage VBB ≡ VCC R2 / R1 + R2 that sistors to be identical with β infinite, derive an expression
will result in a voltage drop of VCC /3 across RE . for the output current IO , and show that by selecting R1 = R2
(c) For VCC = 5 V, find the required values of R1 , R2 , and RE and keeping the currents in all junctions equal, the current IO
to obtain IE = 0.5 mA and to satisfy the requirement for will be
stability of IE in (a). VCC
(d) Find RC so that VCE = 1.0 V for β equal to its nominal IO =
2RE
CHAPTER 6

value.
which is independent of VBE . What must the relationship of
Check your design by evaluating the resulting range of IE . RE to R1 and R2 be? For VCC = 10 V and VBE = 0.7 V, design
the circuit to obtain an output current of 0.5 mA. What is the
D *6.112 Utilizing ±3-V power supplies, it is required to
lowest voltage that can be applied to the collector of Q3 ?
design a version of the circuit in Fig. 6.55 in which the signal
will be coupled to the emitter and thus RB can be set to zero.
Find values for RE and RC so that a dc emitter current of
0.4 mA is obtained and so that the gain is maximized while
allowing ±1 V of signal swing at the collector. If temperature
increases from the nominal value of 25°C to 125°C, estimate
the percentage change in collector bias current. In addition
to the –2 mV/°C change in VBE , assume that the transistor β
changes over this temperature range from 50 to 150.

D 6.113 Using a 3-V power supply, design a version

of the circuit of Fig. 6.56 to provide a dc emitter current of
0.5 mA and to allow a ±1-V signal swing at the collector.
The BJT has a nominal β = 100. Use standard 5% resistor
values (see Appendix J). If the actual BJT used has β = 50,
what emitter current is obtained? Also, what is the allowable
signal swing at the collector? Repeat for β = 150.

D 6.114 A circuit that can provide a very large voltage gain

for a high-resistance load is shown in Fig. P6.114. Find the Figure P6.115
values of I and RB to bias the BJT at IC = 1 mA and VC =
1.5 V. Let β = 100. Section 6.5: Discrete-Circuit Amplifiers
VCC
6.116 The NMOS transistor in the CS amplifier shown
in Fig. 6.57(a) has Vt = 0.75 V and VA = 50 V. Also, VDD =
5 V, RG1 = 750 k, RG2 = 500 k, RD = 10 k, RS = 4 k,
I Rsig = 100 k, and RL = 10 k.
(a) Neglecting the Early effect, verify that the MOSFET is
VC
IC operating in saturation with ID = 0.25 mA and VOV =
RB 0.25 V. What must the MOSFET’s kn be? What is the
dc voltage at the drain?
(b) Find Rin and Gv .
(c) If vsig is a sinusoid with a peak amplitude v̂sig , find the
maximum allowable value of v̂sig for which the tran-
sistor remains in saturation. What is the corresponding
Figure P6.114 amplitude of the output voltage?

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 473

CHAPTER 6
(d) What is the value of resistance R that needs to be inserted (c) If the output of the source follower in (a) is connected
in series with capacitor CS in order to allow us to double to the input of the common-gate amplifier in (b), use the
the input signal v̂sig ? What output voltage now results? results of (a) and (b) to obtain the overall voltage gain
vo /vi .
D *6.117 The MOSFET in the circuit of Fig. P6.117 has
2
Vt = 0.8 V, kn = 5 mA/V , and VA = 40 V.

(a) Find the values of RS , RD , and RG so that ID = 0.4 mA, the

vi

PROBLEMS
largest possible value for RD is used while a maximum
signal swing at the drain of ±0.8 V is possible, and the 
input resistance at the gate is 10 M. Neglect the Early vo1
effect.
(b) Find the values of gm and ro at the bias point. 10 k
(c) If terminal Z is grounded, terminal X is connected to a
signal source with a resistance of 1 M, and terminal
Y is connected to a load resistance of 10 k, find the
voltage gain from signal source to load. (a)
(d) If terminal Y is grounded, find the voltage gain from X
to Z with Z open-circuited. What is the output resistance
of the source follower?
(e) If terminal X is grounded and terminal Z is connected 5 k
to a current source delivering a signal current of 50 µA 
and having a resistance of 100 k, find the voltage signal vo
that can be measured at Y. For simplicity, neglect the
effect of ro . 2 k
5 V
v i2

RD 10 k

Y

X
(b)

RG Z Figure P6.118

RS D 6.119 Using the topology of Fig. 6.58(a), design an

amplifier to operate between a 2-k source and a 2-k load
with a gain vo /vsig of – 40 V/V. The power supply available
5 V is 15 V. Use an emitter current of approximately 2 mA and
a current of about one-tenth of that in the voltage divider
Figure P6.117
that feeds the base, with the dc voltage at the base about
*6.118 one-third of the supply. The transistor available has β = 100.
Use standard 5% resistors (see Appendix J).
(a) The NMOS transistor in the source-follower circuit of
Fig. P6.118(a) has gm = 10 mA/V and a large ro . Find D 6.120 In the circuit of Fig. P6.120, vsig is a small
the open-circuit voltage gain and the output resistance. sine-wave signal with zero average. The transistor β is 100.
(b) The NMOS transistor in the common-gate amplifier of
Fig. P6.118(b) has gm = 10 mA/V and a large ro . Find (a) Find the value of RE to establish a dc emitter current of
the input resistance and the voltage gain. about 0.2 mA.
 474 Chapter 6 Transistor Amplifiers

(b) Find RC to establish a dc collector voltage of about D 6.122 For the circuit in Fig. P6.122, find the input
PROBLEMS

+0.5 V. resistance Rin and the voltage gain vo /vsig . Assume that the
(c) For RL = 10 k, draw the small-signal equivalent cir- source provides a small signal vsig and that β = 100.
cuit of the amplifier and determine its overall voltage
gain.

3V 0.5 mA
CHAPTER 6

5k

Rsig 5 k
Rsig 50

vsig
vsig

Rin

Figure P6.122
3V
6.123 For the emitter-follower circuit shown in Fig. P6.123,
Figure P6.120 the BJT used is specified to have β values in the range of
50 to 200 (a distressing situation for the circuit designer).
6.121 In the circuit of Fig. P6.121, the BJT is biased with
a constant-current source, and vsig is a small sine-wave +3V
signal. Find Rin and the gain vo /vsig . Assume β = 100. If the
amplitude of the signal vbe is to be limited to 5 mV, what
is the largest signal at the input? What is the corresponding
signal at the output?

vsig

10 k
in

10 k
10 k

Figure P6.123
100 k
For the two extreme values of β (β = 50 and β = 200),
0.2 mA
find:

(a) IE , VE , and VB
(b) the input resistance Rin
Figure P6.121 (c) the voltage gain vo /vsig

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 475

VDD

CHAPTER 6
6.124 Calculate the overall voltage gain Gv of a
common-source amplifier for which gm = 5 mA/V, ro =
50 k, RD = 10 k, and RG1 ||RG2 = 10 M. The amplifier is
fed from a signal source with a Thévenin resistance of 1 M, RD
and the amplifier output is coupled to a load resistance of vo
20 k.
Q2
50- coaxial cable
D *6.125 The PMOS transistor in the CSamplifier of

PROBLEMS

Fig. P6.125 has Vtp = −0.75 V and a very large VA . vd1
id
(a) Select a value
 for RS to bias the transistor at ID =
0.5 mA and VOV  = 0.25 V. Assume vsig to have a zero Ri2 = 50 
vi Q1
dc component.
(b) Select a value for RD that results in Gv = −12 V/V. 5 mV

2.5 V
Figure P6.126

RS D *6.127 The MOSFET in the amplifier circuit of

2
CS Fig. P6.127 has Vt = 0.6 V, kn = 5 mA/V , and VA = 60 V.
The signal vsig has a zero average.
Rsig
(a) It is required to bias the transistor to operate at an
CC
vo overdrive voltage VOV = 0.2 V. What must the dc
vsig  voltage at the drain be? Calculate the dc drain current ID

RD taking into account VA . Now, what value must the drain
resistance RD have?
(b) Calculate the values of gm and ro at the bias point
2.5 V
established in (a).
Figure P6.125 (c) Using the small-signal equivalent circuit of the amplifier,
show that the voltage gain is given by
(c) Find the largest sinusoid v̂sig that the amplifier can handle
while remaining in the saturation region. What is the vo R2 /R1
=−
corresponding signal at the output? vsig 1 + R2 /R1
(d) If, to obtain reasonably linear operation, v̂sig is limited 1+
gm (RD ro R2 )(1 − 1/gm R2 )
to 50 mV, what value can RD be increased to while
maintaining saturation-region operation? What is the and find the value of the gain.
new value of Gv ?
VDD = + 10 V
6.126 Figure P6.126 shows a scheme for coupling and
amplifying a high-frequency pulse signal. The circuit uses
two MOSFETs whose bias details are not shown and a 50- RD
coaxial cable. Transistor Q1 operates as a CS amplifier and R2
Q2 as a CG amplifier. For proper operation, transistor Q2 vo
is required to present a 50- resistance to the cable. This R1 2 M
situation is known as “proper termination” of the cable and
500 k
ensures that there will be no signal reflection coming back
on the cable. When the cable is properly terminated, its input vsig 
resistance is 50 . What must gm2 be? If Q1 is biased at the 
same point as Q2 , what is the amplitude of the current pulses
in the drain of Q1 ? What is the amplitude of the voltage
pulses at the drain of Q1 ? What value of RD is required to
provide 1-V pulses at the drain of Q2 ? Figure P6.127
 476 Chapter 6 Transistor Amplifiers

P.S. This feedback amplifier and the gain expression should RE = 2.4 k, and RC = 3.9 k. The transistor has β = 100.
PROBLEMS

remind you of an op amp utilized in the inverting configura- Calculate the dc bias current IC . If the amplifier operates
tion. We will study feedback formally in Chapter 10. between a source for which Rsig = 2 k and a load of 2 k,
replace the transistor with its hybrid-π model, and find the
D *6.128 The MOSFET in the amplifier circuit of
2 values of Rin , and the overall voltage gain vo /vsig .
Fig. P6.128 has Vt = 0.6 V and kn = 5 mA/V . We will
assume that VA is sufficiently large so that we can ignore the
Early effect. The input signal vsig has a zero average.
CHAPTER 6

(a) It is required to bias the transistor to operate at an

overdrive voltage VOV = 0.2 V. What must the dc voltage
at the drain be? Calculate the dc drain current ID . What
value must RD have?
(b) Calculate the value of gm at the bias point.
(c) Use the small-signal equivalent circuit of the amplifier
to show that
vo 1 + (R2 /R1 )
=
vsig (1 + R2 /R1 )
1+
and gm RD Figure P6.129
 
1  R1
Rin = 1 + gm RD D 6.130 A designer, having examined the situation
gm R1 + R2 described in Problem 6.129 and estimating the available
where gain to be approximately –36.3 V/V, wants to explore

RD = RD (R1 + R2 ) the possibility of improvement by reducing the loading
of the source by the amplifier input. As an experiment,
(d) Evaluate vo /vsig and Rin .
the designer varies the resistance levels by a factor of
approximately 3: R1 to 82 k, R2 to 47 k, RE to 7.2 k,
VDD = + 10 V
and RC to 12 k (standard values of 5%-tolerance resistors).
With VCC = 15 V, Rsig = 2 k, RL = 2 k, and β = 100, what
does the gain become? Comment.
RD
R2 D *6.131 The CE amplifier circuit of Fig. P6.131 is biased
vo with a constant-current source I. It is required to design
0.5 M
the circuit (i.e., find values for I, RB , and RC ) to meet the
following specifications:

(a) Rin  10 k.

R1 0.5 M
 vsig (b) The dc voltage drop across RB is approximately 0.2 V.
 (c) The open-circuit voltage gain from base to collector is
the maximum possible, consistent with the requirement
Rin that the collector voltage never fall by more than
approximately 0.4 V below the base voltage with the
Figure P6.128
signal between base and emitter being as high as 5 mV.
P.S. This feedback amplifier circuit and the gain formula
Assume that vsig is a sinusoidal source, the available supply
should remind you of an op amp connected in the nonin-
VCC = 5 V, and the transistor has β = 100. Use standard 5%
verting configuration. We will study feedback formally in
resistance values, and specify the value of I to one significant
Chapter 10.
digit. What base-to-collector open-circuit voltage gain does
6.129 For the common-emitter amplifier shown in your design provide? If Rsig = RL = 20 k, what is the overall
Fig. P6.129, let VCC = 15 V, R1 = 27 k, R2 = 15 k, voltage gain?

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 477

6.133 The BJT in the circuit of Fig. P6.133 has β = 100.

CHAPTER 6
(a) Find the dc collector current and the dc voltage at the
collector.
(b) Replacing the transistor by its T model, draw the
small-signal equivalent circuit of the amplifier. Analyze
the resulting circuit to determine the voltage gain vo /vi .

PROBLEMS
Rin

Figure P6.131

*6.132 The amplifier of Fig. P6.132 consists of two iden-

tical common-emitter amplifiers connected in cascade.
Observe that the input resistance of the second stage, Rin2 ,
constitutes the load resistance of the first stage.

(a) For VCC = 15 V, R1 = 100 k, R2 = 47 k, RE = 3.9 k,

RC = 6.8 k, and β = 100, determine the dc collector
Figure P6.133
current and dc collector voltage of each transistor.
(b) Draw the small-signal equivalent circuit of the entire
amplifier and give the values of all its components. 6.134 For the emitter follower in Fig. P6.134, the signal
(c) Find Rin1 and vb1 /vsig for Rsig = 5 k. source is directly coupled to the transistor base. If the dc
component of vsig is zero, find the dc emitter current. Assume
(d) Find Rin2 and vb2 /vb1 .
β = 100. Neglecting ro , find Rin , the voltage gain vo /vsig , the
(e) For RL = 2 k, find vo /vb2 .
current gain io /ii , and the output resistance Rout .
(f) Find the overall voltage gain vo /vsig .

Rsig

vsig

in in

Figure P6.132
 478 Chapter 6 Transistor Amplifiers

3 (a) Find the dc emitter currents of Q1 and Q2 . Also, find the

PROBLEMS

dc voltages VB1 and VB2 .

(b) If a load resistance RL = 1 k is connected to the output
terminal, find the voltage gain from the base to the
emitter of Q2 , vo /vb2 , and find the input resistance Rib2
looking into the base of Q2 . (Hint: Consider Q2 as an
emitter follower fed by a voltage vb2 at its base.)
CHAPTER 6

2
vsig
5

Rin Rout

Figure P6.134

**6.135 For the circuit in Fig. P6.135, called a boot-

strapped follower:

(a) Find the dc emitter current and gm , re , and rπ .

Use β = 100.
(b) Replace the BJT with its T model (neglecting ro ), and
analyze the circuit to determine the input resistance Rin
and the voltage gain vo /vsig . 50 A
(c) Repeat (b) for the case when capacitor CB is Rin 5 mA
open-circuited. Compare the results with those obtained
in (b) to find the advantages of bootstrapping.

Figure P6.136

(c) Replacing Q2 with its input resistance Rib2 found in (b),

analyze the circuit of emitter follower Q1 to determine
its input resistance Rin and the gain from its base to its
emitter, ve1 /vb1 .
(d) If the circuit is fed with a source having a 100-k
resistance, find the transmission to the base of Q1 ,
vb1 /vsig .
(e) Find the overall voltage gain vo /vsig .

D
 6.137
 A CE amplifier has a midband voltage gain of
AM  = 100 V/V, a lower 3-dB frequency of fL = 100 Hz, and
a higher 3-dB frequency fH = 500 kHz. In Chapter 9 we will
learn that connecting a resistance Re in the emitter of the BJT
Figure P6.135  
results in lowering fL and raising fH by the factor 1 + gm Re .
*6.136 For the follower circuit in Fig. P6.136, let transistor If the BJT is biased at IC = 1 mA, find Re that will result in fH
Q1 have β = 50 and transistor Q2 have β = 100, and neglect at least equal to 2 MHz. What will the new values of fL and
the effect of ro . Use VBE = 0.7 V. AM be?

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem