GANAPATI BHAT

9164254741
[email protected]

PROFILE:
Verification Engineer with 5+ years of experience in ASIC/FPGA design verification. Strong
background in building UVM-based environments from scratch, verifying complex IPs and SoCs
including AXI, SPI, Ethernet, and custom protocols. Proven track record in achieving functional and
code coverage closure. Hands-on experience with FPGA bring-up, protocol modeling, and team-level
ownership.

SKILLS:
● Languages: SystemVerilog (UVM), Verilog, C, Python.
● Verification: UVM, Constrained-Random Testing, Coverage Closure.
● Tools: QuestaSim, Vivado, Xcelium.
● Methodologies: ASIC/FPGA Verification, Directed & Random Testing.

PROFESSIONAL EXPERIENCE:
● Random asm code generator for a Processor:
⮚ Very Long Instruction Word processor with up to 8 instructions per clock featuring a 32-
bit Integer unit.
⮚ Created a constraint random testbench which first initializes registers and memories with
random value and places the random instructions as per spec.
⮚ Created sv models which mimics instruction behavior and generates expected output.
⮚ Generated asm code is fed to processor RTL and results are compared against sv model
output.

● Verification of a VLIW processor using UVM environment:

⮚ Created UVM testbench from the scratch.
⮚ Created test plan to cover all packet formats.
⮚ Added constraints as per spec to generate random VLIW packets.
⮚ Using a specific tool expected output and PMEM files were generated. Generated PMEM
file was used to drive instructions to RTL and results were compared with expected output
file.
⮚ Using randomly generated packets analyzed code coverage of the design. Added some
directed test cases and achieved ~91% code coverage.
⮚ Added functional coverage to check whether all VLIW packets are covered or not.
Achieved 100% coverage here.
⮚ Added functional coverage to check different fields and modes of instructions. Achieved
70% coverage here.
⮚ Added constraints to check some conditions in the design.
● DMA Interface testing:
⮚ Created a linear testbench to verify DMA interface. Design was supporting multiple data
modification options such as bit reverse, interleave etc. based on register configuration.
⮚ Created an AXI interface drive logic to configure the registers and select type of operation.
⮚ Parallelly created a sv model which converts data as per spec. Gave random input data and
common register configuration to both RTL and reference modules. Compared the end
results by tapping specific memory locations.

● Distributed Unit:
⮚ Gone through standard docs and learnt multiple packet formats supported in ORAN 7.2x split.
⮚ Involved in design architecture planning.
⮚ Created a sample C code to extract eCPRI packets.
⮚ Used Swerv-EH1 core as testbench to run C code and estimate cycle counts.
⮚ Learnt Vivado tool usage, made necessary design changes and generated new bit files.
⮚ Dumped bit file on VCU118 evaluation board and validated design using some standard
test case with QDMA linux- drivers.

● N66, N71 Radio Unit:

⮚ Gone through standard docs to understand the concept of ORAN and eCPRI protocol.
⮚ Design was using the AXI channel to program internal registers. Built agent for AXI to
handle this programming.
⮚ Connected multiple C models in testbench to use as standard reference model. Also using
defines, drove standard input files and compared with expected data.

● R&D Project:
⮚ UVM testbench creation from scratch by using Xilinx PCIe VIP as part of the test
environment.
⮚ A basic valid and ready based protocol was used to feed data to RTL. Design then converts
this data to PCIe data format and sends it out.
⮚ Collect these data using PCIe VIP add some metadata on top of received data packets and
transfer the packets back to design where further data processing takes place.

● Replacing SPI verification IP with homegrown IP:

⮚ In a completely verified SoC design SPI was used to transfer initial control information. To
verify this module SPI Verification IP(VIP) was used. My task was to replace this VIP with a
homegrown testbench.
⮚ Completely owned this activity and built a UVM testbench from scratch to drive data to SoC.
⮚ Connected this testbench with SoC and successfully ran all test cases which were created and
tested using VIP.

● R&D Project:
⮚ Design contained multiple input and output interfaces. Out of which one was the SPI interface
and other was using valid, ready and start ports for packet transfer.
⮚ Created UVM testbench and created a test plan to verify this data path.
⮚ Created a virtual sequence to start multiple sequences in the environment.
 WORK EXPERIENCE:
❖ Saankhya Labs Private Limited, Bangalore
Position : Member of technical staff
Duration : 1st Aug 2019 to 24th Sep 2024.

❖ Tejas Networks
Position : Senior Engineer
Duration : 25th Sep 2024 to present.

EDUCATION:
Sl.No College Name Board/University Stream Percentage Year of
/GPA passing
01 R V College of Visvesvaraya BE in Electronics 8.14 2019
Engineering, Technologica and Communication
Banglore l University
02 Shree Vidyadhiraj Department of Diploma in 87.47 2016
Polytechnic, Technical Electronics and
Kumta Education Communication