Micro Processor & Micro Controllers

19BM302

Mr. M Krishna Chennakesava Rao,

Asst. Professor, Dept. of ECE,
VFSTR University

24-Aug-22 1
 Micro Processor & Micro Controllers

Output Input Output

Input Micro
Device Device Device
Device CPU Processor

MEMORY MEMORY

Schematic Diagram of Digital Computer Schematic Diagram of Micro Computer

Ref: B Ram

24-Aug-22 2
 Block diagram of Micro Computer

Data Bus

Input
Device

I/O
Ports CPU MEMORY
Control Bus Control Bus

Output
Device

Address Bus

Ref: Douglas V Hall

24-Aug-22 3
 Schematic Diagram / Internal parts of Micro Processor

Accumulator

ALU General & Special Purpose

Registers

Timing and Control Unit

Ref: B Ram

24-Aug-22 4
Micro Processor & Micro Controllers
Syllabus Overview

UNIT 1 - 8086 MICROPROCESSOR

UNIT 2 - 8051 MICROCONTROLLER
UNIT 3 - ARM ARCHITECTURE
UNIT 4 - ARM INSTRUCTION SET
UNIT 5 - APPLICATION IN MEDICINE

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Micro Processor & Micro Controllers
Syllabus Overview

UNIT 1 - 8086 MICROPROCESSOR

• Evolution of microprocessors
• 8086 microprocessor architecture
• Register organization
• Memory segmentation, Physical address calculation
• Addressing modes
• Pin description of 8086
• Instruction set.

UNIT 2 - 8051 MICROCONTROLLER :

• 8051 microcontroller architecture, Pin diagram,
• Internal and external memory organization
• Addressing modes of 8051
• Interrupts of 8051
• Interfacing external memory to 8051
• 8051 instruction set and assembly language programming
• Example programs.
24-Aug-22 6
 Micro Processor & Micro Controllers
Syllabus Overview

UNIT 3 - ARM ARCHITECTURE

RISC Vs CISC systems, ARM philosophy, ARM7TDMI core architecture, Programmer’s
model, ARM state register set, THUMB state register set, Current program status
register, ARM 7TDMI operating modes, Mode bits, Exceptions, Interrupt vector table,
Interrupt processing.
UNIT 4 - ARM INSTRUCTION SET
ARM assembly language, Instruction syntax, ARM Instruction set, Data processing,
Branch, Load/Store Instructions, Miscellaneous instructions.

UNIT 5 - APPLICATION IN MEDICINE

• Mobile phone based biosignal recording,
• Design of pulse oximeter circuit using ARM microcontroller,
• Design of heart rate monitoring circuit using ARM microcontroller.

24-Aug-22 7
TEXT BOOKS:

1. Douglas V.Hall, “Microprocessors and Interfacing”, 2nd edition, TMH, 2003.

2. Mazidi “The 8051 Microcontroller and Embedded Systems Using Assembly and C”,
2nd edition, Pearson education.

3. Andrew N. Sloss, Donimic Symes, Chris Wright, “ARM System Developer’s Guide”,
Elsevier, 1st edition, 2007.

REFERENCE BOOKS:

1. A K Ray and K M Bhurchandi, “Advanced Microprocessors and Peripherals”, 2nd edn,

TMH, 2006.

2. Raj Kamal, “Microcontroller architecture, programming, Interfacing and System

Design”, 1st edition, Pearson Education, 2005.

3. Barry B.Brey, “Intel Microprocessor Architecture, Programming and Interfacing

8086/ 8088- 80186, 80286, 80386 and 80486”, 1st edition, PHI, 1995.

4. Lyla B Das , “Embedded Systems ”, 1st edn, Pearson 2012.

 UNIT - 1

Introduction to 8086 Micro Processor

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 Introduction to 8086 Micro Processor
Unit-1 Topics:

 Evolution Of Microprocessors,
 8086 Microprocessor, Architecture,
 Register Model,
 Memory Segmentation,
 Physical Address Generation,
 Addressing Modes,
 Pin Diagram
 Instruction Set,
 Interrupts of 8086,
 Interrupt Vector Table.

24-Aug-22 10
 Definition of microprocessor:

Microprocessors can be defined based on 3 things. They are

i. Based on the application of the device.

The CPU of any microcomputer is called microprocessor.

ii. Based on the name of the device.

A small device which is able to do data processing is called microprocessor.

iii. Based on the construction and operation of the device.

Microprocessor is a VLSI/ULSI chip.
It accepts binary data from either an i/p device or from the memory and
it access the instruction from the memory and it perform the operation of the
received data according to the instruction & produces the results those are sent to
either an o/p device or memory.

24-Aug-22 11
 Evolution of Microprocessors

History of microprocessors: - Main parameter  word length

Definitions of word length: -

The no. of bits processed by the CPU at a time are called word length.

(or)

The no. of bits transmitted or received by the CPU at a time.

(or)

The no. of bits identified by the CPU at a time are called word length.

24-Aug-22 12
 Fifth Generation Pentium
64 bit processors

History Fourth Generation

During 1980s
Low power version of HMOS technology
Third Generation (HCMOS)
During 1978 32 bit processors
HMOS technology  Faster speed, Higher Physical memory space 224 bytes = 16 MB
packing density Virtual memory space 240 bytes = 1 TB
16 bit processors  40/ 48/ 64 pins Floating point hardware
Easier to program Supports increased number of addressing
Dynamically relatable programs modes
Processor has multiply/ divide arithmetic
hardware Intel 80386
More powerful interrupt handling
capabilities
Second Generation
Flexible I/O port addressing
During 1973
NMOS technology  Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors  16 pins nesting
8 and 16 bit processors  40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are
multiplexed Intel 8085 (8 bit processor)
Intel 4004,4040 (4 bit processors)
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 Features of 8086: -
1. It is a 16-bit Microprocessor. So that it has 16 bit ALU, 16 bit registers and internal
data bus and 16 bit external data bus. i.e., It’s ALU, internal registers works on 16-bit
binary word. It make s faster processing.

2. It was implemented in the year 1978 by Intel corp. by using HMOS

(hybrid metal oxide semi-conductor or high speed MOS or high density MOS) technology.

3. 8086 processor has 20 address lines A19-A0, and 16 data lines D15-D0.

8086 has 20 bit address lines to access memory. Hence it can access 220 = 1 MB memory location.
8086 has 16-bit address lines to access I/O devices, hence it can access 216 = 64K I/O location

3. 8086 processor has 20 address lines A19-A0, and 16 data lines D15-D0.
The data lines are multiplexed with lower order 16 address lines, and then
the multiplexed address and data lines areAD15-AD0.
The remaining higher order 4 address lines A16-A19 are multiplexing with the status
Lines S3-S6.
4. It has three versions based on the frequency of operation
a) 8086 : 5MHz b) 8086-2: 8MHz c) 8086-1: 10 MHz
5. 8086 processor is available in 40-pin DIP(Dual in line Package).
24-Aug-22 14
Features of 8086: - cont’d…

6. 8086 processor supports 256 interrupts.

7. It supports full duplex asynchronous serial communication and half duplex

Synchronous serial communication.

8. 8086 processor have 4 general purpose registers, 4 segment registers,

3 pointer registers, 2 index registers and 1 flag register. (Total : 14 registers)
Size of all these registers is 16-bit.

9. 8086 processor supports segmented version of memory ( 220 =1MB size).

Size of each segment is 64KB. (220 = 24 216 = 24. 64KB= Sixteen 64KB logical segments)

10. 8086 operates in two different modes.

(1) Minimum mode or Single-Processor mode and
(2) Maximum mode or Multi-Processor mode.

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 Architecture of 8086 Microprocessor
Register organization of 8086
Why Registers ?

 To hold data, variables, intermediate results temporarily

 for counters (CX ), to store OFFSET address (BX)

Registers in 8086

 8086 has Fourteen, 16-bit Registers.

In 8086, registers are categorized into 4 types

1. General Data Registers (4) 2. Segment Registers (4) 3. Flag Register (1)
4. Pointers and Index Registers (5)
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 Architecture of 8086 Microprocessor
Register organization of 8086
AX AH AL Accumulator SP
CS

Base  used to BP
DS FLAGS
BX BH BL store OFFSET for
forming physical / PSW
address ES SI
CX CH CL Counter in string &
loop instructions SS DI
DX DH DL Destination/
Implicit IP
Segment registers

General data register

Pointers and index registers
X specifies 16-bits
H specifies higher 8-bits
L specifies lower 8-bits
24-Aug-22 17
 Architecture of 8086 Microprocessor
Register organization of 8086
The registers AX, BX, CX, and DX are the general purpose 16-bit registers.
AX Register: Accumulator register consists of two 8-bit registers AL and AH, which
can be combined together and used as a 16- bit register AX. AL in this case contains
the low-order byte of the word, and AH contains the high-order byte.
Accumulator can be used for I/O operations, rotate and string manipulation.

BX Register: This register is mainly used as a base register.

It holds the starting base location of a memory region within a data segment.
It is used as offset storage for forming physical address in case of certain
addressing mode.

CX Register: It is used as default counter or count register in case of string and

loop instructions.

DX Register: Data register can be used as a port number in I/O operations and implicit
operand or destination in case of few instructions. In integer 32-bit multiply and divide
instruction the DX register contains high-order word of the initial or resulting number.
24-Aug-22 18
 Register organization of 8086 cont’d…
Segment Registers of 8086
 8086 processor addresses segmented version of memory ( 220 =1MB size).
Size of each segment is 64KB. (220 = 24 216 = 24. 64KB= Sixteen 64KB logical segments)
 Physical address =[ Base address x 10 ] + OFFSET address

Memory Segments of 8086 Segment Registers

24-Aug-22 19
 Register organization of 8086 cont’d…
Pointers and Index Registers of 8086

SP Stack Pointer  Holds address of the top of the stack.

 Stores OFFSET within a segment
BP Base Pointer Stores OFFSET within a segment

IP Instruction Pointer Stores the address of the next instruction

to be fetched
SI Source Index  Stores OFFSET
 also used as general purpose registers
DI Destination index  used for string related operations

24-Aug-22 20
8086 Microprocessor
Architecture Registers and Special Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations

BX Base register Used to hold base value in base addressing mode to access memory
data

CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP instructions

DX Data Register Used to hold data for multiplication and division operations

SP Stack Pointer Used to hold the offset address of top stack memory

BP Base Pointer Used to hold the base value in base addressing using SS register to
access data from stack memory

SI Source Index Used to hold index value of source operand (data) for string
instructions

DI Destination Index Used to hold the index value of destination operand (data) for string
operations 21
 Register organization of 8086 cont’d…

Flag Register of 8086 FLAGS/ PSW

U U U U OF DF IF TF SF ZF U AC U PF U CY

9 active flags can be divided into 2 groups.

Conditional flags----6 b) Control flags----3

OV=overflow flag DF=direction flag TF=trap flag IF=interrupt flag SF=sign flag
ZF=zero flag AC=auxiliary carry flag PF=parity flag CY=carry flag

 Flag Register determines the current state of the processor.

 They are modified automatically by CPU after mathematical operations.
 It allows to determine the type of the result.
 Determines the conditions to transfer control to other parts of the program.

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 8086 Microprocessor
Execution Unit (EU)

Flag Register
Architecture Auxiliary Carry Flag

This is set, if there is a carry from the

Carry Flag

lowest nibble, i.e, bit three during This flag is set, when there is
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto decrementing mode. 23
 Architecture of 8086 Microprocessor
The 8086 CPU is divided into two independent functional units:
•Bus Interface Unit (BIU)
•Execution Unit (EU) Ref: Hall
 Architecture of 8086 Microprocessor
Functions of Bus Interface Unit
1. It sends address of the memory or I/O.
2. It fetches instruction from memory.
3. It reads data from port/memory.
4. It writes data into port/memory.
5. It supports instruction queuing.
6. It provides the address relocation facility.
Note:
 BIU contains the circuit for physical address calculations
and
 a pre-decoding instruction byte queue (6 Bytes long)

24-Aug-22 25
 Architecture of 8086 Microprocessor
Instruction Queue
 To increase the execution speed,

 BIU fetches as many as six instruction bytes ahead to time from memory.

 All six bytes are then held in first in first out ( FIFO) 6 byte register called instruction queue.

 Then all bytes have to be given to EU one by one.

This pre fetching operation of BIU may be in parallel with execution operation of EU,

which improves the speed execution of the instruction.

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 PIPELINING
Fetching the next instruction while the current instruction
executes is called pipelining.

It increases the speed of operation of microprocessor 8086

24-Aug-22 27
 Architecture of 8086 Microprocessor
Execution Unit (EU)
The functions of execution unit are:
• To tell BIU where to fetch the instructions or data from.
• To decode the instructions.
• To execute the instructions.
• The EU contains the control circuitry to perform various internal operations.
• A decoder in EU decodes the instruction fetched memory to generate
different internal or external control signals required to perform the operation.
• EU has 16-bit ALU, which can perform arithmetic and logical operations on 8-bit
as well as 16-bit.

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 Architecture of 8086 Microprocessor
Execution Unit (EU)

EU has the following functional parts these are

a). ALU
b). Register Set.
c). Operand & Flag Register.
d). Control System.

24-Aug-22 29
 Architecture of 8086 Microprocessor
ALU in Execution Unit (EU)
a).ALU (Arithmetic and Logical Unit):- It performs Arithmetic and Logical operations on
8 bits/16bits. The Bit Capacity of ALU is 16bits.

It can do the following arithmetic operations :

i) Addition ii) Subtraction iii) Multiplication

iv) Division v) Increment vi) Decrement

Arithmetic operations may be performed on four types of numbers

Unsigned binary numbers Signed binary numbers (Integers)

Unsigned packed decimal numbers Unsigned unpacked decimal numbers

The ALU can also perform logical operations such as

i) NOT ii) AND iii) OR iv) EX-OR v) TEST vi) Logical Shift

vii) Arithmetic Shift viii) Circular Shift (or) Rotate

24-Aug-22 30
 Architecture of 8086 Microprocessor
Control Unit & Registers in Execution Unit (EU)

b). Control System: - It is divided into 2 parts. They are

Decoding circuit----it decodes the instruction.

Timing circuit---- it generates control signals at appropriate times.

c). Register Set:- It is used to hold the 16-bit information.

The information is address, data or result of some operation.

d). Operand & Flag Register: -

Operand holds the result produced by ALU.
Flags are also called as PSW (program status word) of 8086.
Each single bit is called flag.

24-Aug-22 31
 Advantages due to Memory Segmentation
• In 8086 microprocessor, memory is divided into 4 segments.
• It allows the memory addressing capacity to be 1 Mbyte even though the
address associated with individual instruction is only 16-bit.
• It allows instruction code, data, stack and portion of program to be more
than 64 KB long by using more than one code, data, stack segment, and
extra segment.
• It facilitates use of separate memory areas for program, data and stack.
• It permits a program or its data to be put in different areas of memory, each
time the program is executed i.e. program can be relocated which is very
useful in multiprogramming.
• Program can work on several data sets by reloading the DS register.

24-Aug-22 32
 Architecture of 8086 Microprocessor
Memory Segments of 8086

Memory Segments of 8086 Segment Registers

24-Aug-22 Ref: Hall 33
 Memory Segments of 8086 cont’d…

Segment Registers generate memory address when combined with other in the microprocessor.

In 8086 microprocessor, memory is divided into 4 segments as follow:

Code Segment (CS): The CS register is used for addressing a memory location in the
Code Segment of the memory, where the executable program is stored.

Data Segment (DS): The DS contains most data used by program. Data are accessed in the
Data Segment by an offset address or the content of other register that holds the offset
address.

Stack Segment (SS): SS defined the area of memory used for the stack.

Extra Segment (ES): ES is additional data segment that is used by some of the string to hold
the destination data.

24-Aug-22 34
 Physical Address Generation
 8086 processor addresses segmented version of memory ( 220 =1MB size).

Size of each segment is 64KB. (220 = 24 216 = 24. 64KB= Sixteen 64KB logical segments)

 All 4 segment registers give the base addresses of selected segments.

 Segments starting address are like00000H, 10000H, 20000H, 30000H…. F0000H

 Offset address range in any segment is from 0000H to FFFF

 Address range of total 1MB is from 00000H to FFFFFH

 Physical address =[ Base address * 10 ] + OFFSET address

No. of locations are getting down from segment base to desired address in the segment
is called Offset Address or Effective address.

Physical Address means actual location address in the memory system.

Note: Here base address will be shifted LEFT by 4-bit positions.

24-Aug-22 35
 Physical Address Generation : Tutorials
1. a) If the code segment for an 8086 program starts at address 70400H. What number
will be in the CS register? Assuming this same code segment base, what physical
address will a code byte be fetched from, if the Instruction Pointer(IP) contains
539CH?
2. What physical address is represented by
a) 4370: 561EH b) 7A32 : 0028H

3. If the Stack segment register contains 3000H and the stack pointer register contains
8434H, What is the physical address of the top of the stack?

4. If the 8086 execution unit calculates an effective address of 14A3H and DS contains
7000H, What Physical Address will the BIU produce?

5. If SS:SP form as 5000: FFE0H. Find physical address.

6. If CS=348AH: IP=4214H. Then find the 20-bit physical address .

CS 3 4 8 A 0
IP + 4 2 1 4
PA 3 8 A B 4
24-Aug-22 36
 Instruction Format:

Label OPCODE Operand Comment

Field Field
Field Field
OPCODE Destination Operand , Source operand

Next: ADD AL, 07H ; Add 07h

to
content
of AL
register

24-Aug-22 37
 Addressing Modes of 8086
 The different ways in which a processor can access data are called
addressing modes

 8086 accesses code bytes using contents of CS & IP register

 8086 accesses stack using contents of SS & SP register

 Addressing Modes of 8086 cont’d…

• Source of data can be

– Immediate data
– A specified register
– A memory location specified in 1 of many(24)
different ways

• Destination of data can be

– A specified register
– A memory location specified in 1 of many (24)
different ways
 Addressing Modes
 An Addressing mode shows how the data is represented in the instruction.

 8086 supports 15 addressing modes.

1. Immediate AM
2. Register AM
3. Memory Addressing Modes:
i. Direct AM ii. Register Indirect AM iii. Register Relative AM iv. Indexed AM
v. Based Indexed AM vi. Based Indexed Displacement AM
4. Implied AM
5. I/O AM : a) I/O Direct AM b) I/O Indirect AM
6. Segment AM :
i. Intra Segment Direct AM ii. Inter Segment Direct AM
iii. Intra Segment Indirect AM iv. Inter Segment Indirect AM

24-Aug-22 40
 Addressing Modes
 An Addressing mode shows how the data is represented in the instruction.

 8086 supports 15 addressing modes.

1. Immediate AM 2. Register AM
3. Direct AM 4. Register Indirect AM
5. Register Relative AM 6. Based Indexed AM
7. Based Indexed Displacement AM 8. Implied AM
9. I/O Direct AM 10. I/O Indirect AM
11. Indexed AM 12. Intra Segment Direct AM
13. Inter Segment Direct AM 14. Intra Segment Indirect AM
15. Inter Segment Indirect AM
24-Aug-22 41
 Ref: Brey
BX=0300H, SI=0200H, ARRAY=1000H , DS=1000H

Type Instruction Source Address Generation Destination

Immediate MOV CH,3AH Data 3AH Register CH

Register MOV AX,BX Register BX Register AX

Direct MOV [1234H],AX Register AX DS*10H + Disp Memory Address

1000*10H+ 1234 11234H

Register MOV [BX], CL Register CL DS*10H + BX Memory Address

Indirect 1000*10H+ 0300H 10300H

24-Aug-22 42
 BX=0300H, SI=0200H, ARRAY=1000H , DS=1000H

Type Instruction Source Address Generation Destination

Base MOV [BX + SI], BP Register BP DS*10H + BX+SI Memory

Index 1000*10H+ 0300H+0200H Address 10500H

Register MOV CL, [BX+4] Memory DS*10H + BX Register CL

Relative Address 1000*10H+ 0300H+4
10304H

Base MOV Array[BX + SI], DX Register DX DS*10H + Array+ BX+SI Memory

Relative 1000*10H+ 1000H+ Address 11500H
Index 0300H+0200H

24-Aug-22 43
 BX=0300H, SI=0200H, ARRAY=1000H , DS=1000H

Type Instruction Source Address Generation Destination

Scaled MOV [BX +2* SI], AX Register AX DS*10H + BX+ 2*SI Memory
Index 1000*10H+ 0300H+0400H Address 10700H

24-Aug-22 44
 Addressing Modes cont’d…

1. Immediate Addressing Mode: -

 The data is directly placed in the source operand field of an instruction.
 The immediate data size is either 8bit or 16bit.
 The length of the instruction for this AM is either 3byte or 4byte,
if data is moved to register.
Ex: MOV BX, 2050H
 If data is moved to a memory location, then the length of instruction is
from 3bytes-6bytes.
Ex: MOV [BX], 2050H
The direct data 2050H will be copied to the Memory location for which
BX gives EA.
24-Aug-22 45
 Addressing Modes cont’d…

2. Register Addressing Mode: -

 Here data is represented in the source operand field, through

a register.

 We can use any register except IP.

 Length of this AM instruction is 2bytes.

Ex:
MOV AX, BX ; 16-bit data transfer

MOV AL, BL ; 8-bit data transfer

24-Aug-22 46
 Addressing Modes cont’d…

3. Direct Addressing Mode: -

 The address of the data is directly placed in the operand fields

of an instruction.
 Here the address of the data is nothing but the memory location address,
i.e, OFFSET or Effective Address.

Ex: MOV AX, [2050]

4. Register Indirect Addressing Mode: -

 The address of the data is indirectly represented in operand fields

of the instruction by using registers.
 The registers must be BX, BP registers.

Ex: MOV AX, [BX].

24-Aug-22 47
 Addressing Modes cont’d…

5. Register Relative Addressing Mode: -

 The operand address is provided by the combination of base address

and displacement value.

Ex: MOV AX, 50H[BX]

6. Based Indexed Addressing Mode: -

 The operand address is provided by combination of base register

and index register.

Ex: MOV AX, [BX][SI]

24-Aug-22 48
 Addressing Modes cont’d…

7. Based Indexed Displacement Addressing Mode: -

 The operand address is provided by the combination of base register and

index register and displacement value.

Ex: MOV AX, 50H[BX][SI]

8. Implied Addressing Mode: -

 The operand is implicitly represented in operation code of an instruction.

 Length of the instruction in this AM is 1byte.

Ex: STD (set DF)

STC (set CF)

24-Aug-22 49
 Addressing Modes cont’d…

9. I/O Direct Addressing Mode: -

 The I/O device address is directly placed in the operand field of

instruction.

Ex: IN AX, 2050H

OUT 3050H, AL

10. I/O Indirect Addressing Mode: -

 The device address placed in operand filed through a register

in the instruction.

Ex: IN AL, [DX]

24-Aug-22 50
 Addressing Modes cont’d…
11. Indexed Addressing Mode: -
 Here the data address is represented in the operand field through an index register
in an instruction.

 It is useful when the processor executes string related operations.

 It is similar to register indirect AM.

Ex: MOV AX, [SI].

24-Aug-22 51
 Addressing Modes cont’d…

12. Intra Segment Direct Addressing Mode: -

 If the both source and destination appears in same segment then it is called
intra segment.

 The destination address is directly placed in the operand field of the instruction.

Ex: JMP 2050H

13. Inter Segment Direct Addressing Mode: -

 If the both source and destination appears in different segment then it is called
inter segment.

 The destination address is directly placed in the operand field of the instruction.

Ex: JMP 3000:4050H.

24-Aug-22 52
 Addressing Modes cont’d…

14. Intra Segment Indirect Addressing Mode: -

In this AM, the destination address is represented in the operand filed

through a register or a memory location in an instruction.

Ex: JMP word ptr [2050H]

15. Inter Segment Indirect Addressing Mode: -

In this AM, the destination address is represented in the operand filed

through a register or a memory location in an instruction.

Ex: JMP dword ptr [2000H]

24-Aug-22 53
 Instruction Set of 8086

24-Aug-22 54
 Instruction Set of 8086:-

 Instructions in the instruction set of 8086 are classified into different types,

Based on number of operand address fields in the instruction.

Based on type of operation.

24-Aug-22 55
 Instruction Set of 8086:- cont’d…

Based on Number of Operand Fields in the Instruction

In this type , instructions can be divided into 3 groups.

1. Zero operand address field Instructions

2. One operand address field Instructions

3. Two operand address field Instructions

24-Aug-22 56
 Instruction Set of 8086:- cont’d…

1. Zero operand address field instructions

 There is no operand fields in the instruction.

 Op-code part only exists in the instruction.

Ex:- NOP, HLT, STC, WAIT etc.

2. One operand address field instructions

 Only one operand exists in the instruction.

 The another operand for the instruction are the default registers (AX or DX)
and these are not represented in the operand field of the instruction.

Ex:- IN AL, OUT AX, DIV BX, and MUL CL etc.

24-Aug-22 57
 Instruction Set of 8086:- cont’d…

3. Two operand address field instructions

 Both operands are directly represented in the operand fields of instruction.

Ex:- MOV AX,BX

ADD AX, DX
SUB AX, [BP] etc.

24-Aug-22 58
 Instruction Set of 8086:- cont’d…

Based on Type of Operation: -

In this type of classification instructions can be divided into 9 groups.

1. Data Transfer instructions 2. Arithmetic Instructions

3. Logical Instructions 4. Shift and Rotate Instructions
5. Branching Instruction 6. Flag Manipulation Instructions
7. Loop Related Instructions 8. Machine Control Instructions
9. String Related Instructions

24-Aug-22 59
 Instruction Set of 8086:- cont’d…

1. Data Transfer Instructions:-

 Data Transfer instructions are also called as

Data Movement Instructions or
Data Copying Instructions.

 If the processor executes any Data Transfer Instruction there is

no effect on the Flag Register Status.

The Data Transfer Instructions are those, which transfers the DATA
(means copy of data) from any one source to any one destination.

The 8086 processor doesn’t support the following types of Data transfer Operations

• Memory to Memory data transfer

• Immediate data to any Segment Register

24-Aug-22 60
 Instruction Set of 8086:- cont’d…

1. Data Transfer Instructions:-

General – Purpose Simple Input and Special Address Flag

Byte or Word Output Port Transfer Transfer
Transfer Transfer Instructions Instructions
Instructions Instructions

MOV IN LEA LAHF

PUSH OUT LDS SAHF
POP LES PUSHF
XCHG POPF
XLAT

24-Aug-22 61
 1. Data Transfer Instructions cont’d…

1.1. General – Purpose Byte or Word Transfer Instructions

MOV: - Copy byte or word from specified source to specified destination.

 The source operand is either an immediate data or a register or a memory location.

 The destination is either a register or a memory location.
Ex: - MOV CX, 037A H
MOV AL, BL
MOVBX, [0301H]
Note: Both source and Destination can’t be memory locations

PUSH: - Copy specified word to top of stack.

 The specified word is any 16-bit register content or any memory location contents.
 For this instruction execution the content of SP is decrement by ‘2’.

Ex: - PUSH BX
PUSH [1250H]
24-Aug-22 62
 1. Data Transfer Instructions cont’d…

1.1. General – Purpose Byte or Word Transfer Instructions

POP: - Copy word form top of stack to specified destination.

 Destination can be a general purpose register, segment register (except CS) or

memory location.
 For this instruction execution the content of SP is increment by ‘2’.

Ex: - POP CX
POP [2050H]

XCHG: - This instruction exchanges Source with Destination.

 It cannot exchange two memory locations directly.

 Exchange bytes or exchange words.

Ex: - XCHG DX, AX

XCHG DX, [5040H]

24-Aug-22 63
 1. Data Transfer Instructions cont’d…

1.1. General – Purpose Byte or Word Transfer Instructions

XLAT:-Translate a byte using table in the Memory

 Replaces a byte AL with a byte in a memory look up table.

 BX register stores the starting address of lookup table and

AL register stores OFFSET address

 This instruction copies the byte from address pointed by [BX+AL], to AL

24-Aug-22 64
 1. Data Transfer Instructions cont’d…

1.2. Input and Output Port Transfer Instructions

IN: - Copy a byte or word from specific Input Port to Accumulator.

Ex: - IN AX, 0050H IN Accumulator, I/P Port address

IN AL

OUT: - Copy a byte or word from accumulator to specific Output Port.

Ex: - OUT 0050H, AX OUT O/P Port address, Accumulator

OUT AL

24-Aug-22 65
 1. Data Transfer Instructions cont’d…
1.3. Address Transfer Instructions
i) LEA: - Load Effective Address of operand into specified register (16-bit)

LEA Register, source LOCATION

Ex: - LEA BX, [SI]

ii) LDS: - It loads destination register and DS, from memory source.

LDS Register, memory address of first word

 The offset is placed in the destination register and the segment base is placed in
DS.
 To use this instruction the word at the lower order memory address must contain
the offset and the word at the higher order address must contain the segment
base address.

Ex: - LDS BX, [0302 H]

24-Aug-22 66
 1. Data Transfer Instructions cont’d…
1.3. Address Transfer Instructions

LES: - It loads destination register and ES, from memory source.

LES Register, memory address of first word

 The offset is placed in the destination register and the segment base is placed in ES.

 This instruction is very similar to LDS except that it initializes ES instead of DS.

Ex: - LES DX, [1030 H]

24-Aug-22 67
 1. Data Transfer Instructions cont’d…

1.4. Flag Transfer Instructions

LAHF: - Load AH with the low byte of flag register.

SAHF: - Store AH register to low byte of flag register.

PUSHF: - Copy flag register to top of stack.

POPF: - Copy word to top of stack to flag register.

24-Aug-22 68
 1. Data Transfer Instructions cont’d…

1.4. Flag Transfer Instructions

• LAHF:
– It copies the lower byte of flag register to AH.

• SAHF:
– It copies the contents of AH to lower byte of flag register.

• PUSHF:
– Pushes flag register to top of stack.

• POPF:
– Pops the stack top to flag register.

21-Nov-2010 69
 2. Arithmetic Instructions

 To perform Arithmetic calculations

They are classified into four groups.

Addition Subtraction Multiplication, Division

Instructions Instructions Increment, & Instructions
Decrement Instructions
ADD SUB MUL DIV
ADC SBB IMUL IDIV
INC DEC AAM AAD
AAA NEG CBW
INC
DAA CMP CWD
AAS DEC
DAS

24-Aug-22 70
 Arithmetic Instructions
• ADD Des, Src:
– It adds a byte to byte or a word to word.
– It effects AF, CF, OF, PF, SF, ZF flags.
– i.e., All conditional flags will be effected.
– E.g.:
• ADD AL, 74H
• ADD DX, AX
• ADD AX, [BX]

24-Aug-22 71
 Arithmetic Instructions
• ADC Des, Src:
– It adds the two operands with CF.
– It effects AF, CF, OF, PF, SF, ZF flags.
– i.e., All conditional flags will be effected.
– E.g.:
• ADC AL, 74H
• ADC DX, AX
• ADC AX, [BX]

24-Aug-22 72
 Arithmetic Instructions

• SUB Des, Src:

– It subtracts a byte from byte or a word from word.
– It effects AF, CF, OF, PF, SF, ZF flags.
– i.e., All conditional flags will be effected.
– For subtraction, CF acts as borrow flag.
– E.g.:
• SUB AL, 74H
• SUB DX, AX
• SUB AX, [BX]

24-Aug-22 73
 Arithmetic Instructions

• SBB Des, Src:

– It subtracts the two operands and also the borrow
from the result.
– It effects AF, CF, OF, PF, SF, ZF flags.
– i.e., All conditional flags will be effected.
– E.g.:
• SBB AL, 74H
• SBB DX, AX
• SBB AX, [BX]

24-Aug-22 74
 Arithmetic Instructions
• INC Src:
– It increments the byte or word by one.
– The operand can be a register or memory location.
– It effects AF, OF, PF, SF, ZF flags.
– CF is not effected.
– i.e., All conditional flags except CF will be effected.
– Destination operand must not be an immediate
number.
– E.g.: INC AX
» INC [BX]
» INC [2050H]
24-Aug-22 75
 Arithmetic Instructions
• DEC Src:
– It decrements the byte or word by one.
– The operand can be a register or memory location.
– It effects AF, OF, PF, SF, ZF flags.
– CF is not effected.
– i.e., All conditional flags except CF will be effected.
– E.g.: DEC AX
» DEC [BX]
» DEC [2050H]

24-Aug-22 76
 Arithmetic Instructions
• AAA (ASCII Adjust after Addition):
– The data entered from the terminal is in ASCII format.
– In ASCII, 0 – 9 are represented by 30H – 39H.
– This instruction allows us to add the ASCII codes.
– This instruction does not have any operand.
• Other ASCII Instructions:
– AAS (ASCII Adjust after Subtraction)
– AAM (ASCII Adjust after Multiplication)
– AAD (ASCII Adjust Before Division)

24-Aug-22 77
 Arithmetic Instructions
• DAA (Decimal Adjust after Addition)
– It is used to make sure that the result of adding two
BCD numbers is adjusted to be a correct BCD number.
– It only works on AL register.
• DAS (Decimal Adjust after Subtraction)
– It is used to make sure that the result of subtracting
two BCD numbers is adjusted to be a correct BCD
number.
– It only works on AL register.

24-Aug-22 78
 Arithmetic Instructions

• NEG Src:
– It creates 2’s complement of a given number.
– That means, it changes the sign of a number.
– Ex:
» NEG AX

» NEG [1250H]

» NEG [BX]

24-Aug-22 79
 Arithmetic Instructions
• CMP Des, Src:
– It compares two specified bytes or words.
– The Src and Des can be a constant, register or memory location.
– Both operands cannot be a memory location at the same time.
– The comparison is done simply by internally subtracting the source from
destination.
– The value of source and destination does not change, but the flags are
modified to indicate the result.
– Ex:
» CMP AX, BX
» CMP AX, [2050H]
» CMP BX,, 3050H
24-Aug-22 80
 Arithmetic Instructions
• MUL Src:
– It is an unsigned multiplication instruction.
– It multiplies two bytes to produce a word or two words to produce a double word.
– AX = AL * Src
– DX : AX = AX * Src
– This instruction assumes one of the operand in AL or AX.
– Src can be a register or memory location.
– Ex: MUL BL; MUL [2050H]; MUL CX

• IMUL Src:
– It is a signed multiplication instruction.

24-Aug-22 81
 Arithmetic Instructions

• DIV Src:
– It is an unsigned division instruction.
– It divides word by byte or double word by word.
– The operand is stored in AX, divisor is Src and the result is stored
as:
• AH = remainder AL = quotient

• Ex: DIV BL; DIV [2050H]; DIV CX

• IDIV Src:
– It is a signed division instruction.
24-Aug-22 82
 Arithmetic Instructions
• CBW (Convert Byte to Word):
– This instruction converts byte in AL to word in AX.
– The conversion is done by extending the sign bit of AL throughout AH.

– AX = 0000 0000 1001 1000 Convert signed byte in AL signed word in AX

Result in AX = 1111 1111 1001 1000

• CWD (Convert Word to Double Word):

– This instruction converts word in AX to double word in DX : AX.
– The conversion is done by extending the sign bit of AX throughout DX.
– DX = 1111 1111 1111 1111
Result in AX = 1111 0000 1100 0001

24-Aug-22 83
3. Logical or Bit Manipulation Instructions

Logical Instructions

NOT
AND
OR
XOR
TEST

24-Aug-22 84
 Bit Manipulation Instructions
• These instructions are used at the bit level.
• These instructions can be used for:
– Testing a zero bit
– Set or reset a bit
– Shift bits across registers

24-Aug-22 85
 Logical or Bit Manipulation Instructions
• NOT Src:
– It complements each bit of Src to produce 1’s
complement of the specified operand.
– The operand can be a register or memory
location.
Ex: - NOT AX
NOT [2050H]

24-Aug-22 86
 Bit Manipulation Instructions
• AND Des, Src:
– It performs AND operation of Des and Src.
– Src can be immediate number, register or memory location.
– Des can be register or memory location.
– Both operands cannot be memory locations at the same time.
– CF and OF become zero after the operation.
– PF, SF and ZF are updated.

• Ex: - AND AX, BX

AND AX, [3050H]
AND AX, 1200H
AND [3040H], 1250H

24-Aug-22 87
 Bit Manipulation Instructions
• OR Des, Src:
– It performs OR operation of Des and Src.
– Src can be immediate number, register or memory location.
– Des can be register or memory location.
– Both operands cannot be memory locations at the same time.
– CF and OF become zero after the operation.
– PF, SF and ZF are updated.

• Ex: - OR AX, BX
OR AX, [3050H]
OR AX, 1200H
OR [3040H], 1250H

24-Aug-22 88
 Bit Manipulation Instructions
• XOR Des, Src:
– It performs XOR operation of Des and Src.
– Src can be immediate number, register or memory location.
– Des can be register or memory location.
– Both operands cannot be memory locations at the same time.
– CF and OF become zero after the operation.
– PF, SF and ZF are updated.

• Ex: - XOR AX, BX

XOR AX, [3050H]
XOR AX, 1200H
XOR [3040H], 1250H

24-Aug-22 89
 Bit Manipulation Instructions
• TEST Des, Src:
• This instruction ANDs the contents of a source byte or word
with the contents of specified destination byte or word.
• Flags are updated but neither operand is changed .
• TEST instruction is often used to set flags before a condition
jump instruction.

• Ex: - TEST AL, BH; AND BH with AL, updates flags but result not
stored.

TEST CX, 0001H

24-Aug-22 90
 4. Shift and Rotate Instruction
Shift Rotate
Instructions Instructions
SHL / SAL ROL
SHR ROR
SAR RCL
RCR
SAL : Shift Arithmetic Left ROL : Rotate Left
SHL: Shift Logical Left RCL: Rotate Left through carry
SAR : Shift Arithmetic Right ROR : Rotate Right
SHR: Shift Logical Right RCR: Rotate Right through carry
24-Aug-22 91
 Bit Manipulation Instructions : Shift Instructions

• SAL/ SHL Des, Count:

– It shift bits of byte or word to left, by count.

– It puts zero(s) in LSBs. LSB= 0

– MSB is shifted into carry flag. CN=MSB

– If the number of bits desired to be shifted is 1, then the immediate number 1 can
be written in Count.

– However, if the number of bits to be shifted is more than 1, then the count is put in
CL register. SAL AX,1; MOV CL, 05H; SAL AX, CL

Cy= 0 1 0 1 1 0 1 1 1 0

Cy= 1 0 1 1 0 1 1 1 0
24-Aug-22 92
Bit Manipulation Instructions : Shift Instructions
• SHR Des, Count:
– It shift bits of byte or word right, by count.

– It puts zero(s) in MSBs. MSB = 0

– LSB is shifted into carry flag. CN= LSB

– If the number of bits desired to be shifted is 1, then the immediate number 1

can be written in Count.

– However, if the number of bits to be shifted is more than 1, then the count is
put in CL register.

0 1 0 1 0 1 0 0 1 Cy= 0

0 1 0 1 0 1 0 0 Cy= 1

24-Aug-22 93
Bit Manipulation Instructions : Shift Instructions
• SAR Des, Count:
– It shift bits of byte or word right, by count.

– It puts OLD MSB in the new MSB. MSB = OLD MSB

– LSB is shifted into carry flag. CN= LSB

– If the number of bits desired to be shifted is 1, then the immediate number 1

can be written in Count.

– However, if the number of bits to be shifted is more than 1, then the count is
put in CL register.

1 0 1 0 1 0 0 1 Cy= 0

1 1 0 1 0 1 0 0 Cy= 1

24-Aug-22 94
Bit Manipulation Instructions : Rotate Instructions
• ROL Des, Count:
– It rotates bits of byte or word left, by count.

– MSB is transferred to LSB and also to CF. LSB = OLD MSB

CN= OLD MSB

– If the number of bits desired to be shifted is 1, then the immediate

number 1 can be written in Count.

– However, if the number of bits to be shifted is more than 1, then the

count is put in CL register.

Cy= 1 0 0 1 1 0 1 1 1

Cy= 0 0 1 1 0 1 1 1 0
24-Aug-22 95
Bit Manipulation Instructions : Rotate Instructions
• ROR Des, Count:
– It rotates bits of byte or word right, by count.

– LSB is transferred to MSB and also to CF.

– MSB= CN= OLD LSB

– If the number of bits desired to be shifted is 1, then the immediate number 1

can be written in Count.

– However, if the number of bits to be shifted is more than 1, then the count is
put in CL register.

1 0 1 0 1 0 0 1 Cy= 0

1 1 0 1 0 1 0 0 Cy= 1
24-Aug-22
96
Bit Manipulation Instructions : Rotate Instructions
• RCL Des, Count:

– RCL instruction : RCL destination, count

– This instruction rotates all the bits in a specified byte or word some number of
bits position to the left along with the carry flags.

– MSB is placed as a new carry and previous carry in place as new LSB.

Eg.

RCL CX, 1
MOV CL, 04H
RCL AL, CL

Cy= 1 0 0 1 1 0 1 1 1

Cy= 0 0 1 1 0 1 1 1 1
24-Aug-22 97
Bit Manipulation Instructions : Rotate Instructions
• RCR Des, Count:
– RCR instruction : RCR destination , count

– This instruction rotates all bits in a specified byte or word some number of bit
positions to the right along with the carry flag.

– LSB is placed as a new carry and previous carry is in place as a new MSB.

Eg. RCR CX, 1

MOV CL, 04H
RCR AL, CL

1 0 1 0 1 0 0 1 Cy= 0

0 1 0 1 0 1 0 0 Cy= 1
24-Aug-22
98
 5. Program Flow control Instructions

• These instructions cause change in the sequence of the execution of

instruction.

• This change can be through a condition or sometimes unconditional.

• The conditions are represented by flags.

• These are also called as Branching Instructions or Transfer of control

Instructions.

• 2 types.
– i. Uncondtional Branching Instructions : CALL RET JMP

– ii. Condtional Branching Instructions : Set of J Cond

24-Aug-22 99
 5.1: Unconditional Branching Instructions
• CALL Des: Main  ISR
– This instruction is used to call a subroutine or function or procedure,
from a main program.
– Ex: CALL [CX] ; CALL DWORD PTR [BX]
– The address of next instruction after CALL is saved onto stack.
– 1. NEAR CALL : is used when the subprogram and main program both
appears in same segment
– 2. FAR CALL: is used when the subprogram and main program appears
in different segments.

– RET: Return from the procedure ISR  Main

– It returns the control from subroutine procedure to calling main
program.
– Every CALL instruction should have a RET. It affects no flag.
24-Aug-22 100
 5.1: Unconditional Branching Instructions cont’d.. .
• JMP Des:
– This instruction is used for unconditional jump from
one place to another. i.e., without taking any
condition from conditional flags of 8086.
• Ex: - JMP 2000H
• JMP [SI]

• Jxx Des (Conditional Jump):

– All the conditional jumps follow some conditional
statements or any instruction that affects the flag.

24-Aug-22 101
 5.2: Conditional Branching Instructions
Conditional Jump Table
Mnemonic Meaning Jump Condition
JA Jump if Above CF = 0 and ZF = 0
JAE Jump if Above or Equal CF = 0
JB Jump if Below CF = 1
JBE Jump if Below or Equal CF = 1 or ZF = 1
JC Jump if Carry CF = 1
JE Jump if Equal ZF = 1
JNC Jump if No Carry CF = 0
JNE Jump if Not Equal ZF = 0
JNZ Jump if Not Zero ZF = 0
JPE Jump if Parity is Even PF = 1
JPO Jump if Parity is Odd PF = 0
JZ Jump if Zero ZF = 1
24-Aug-22 102
 6. Loop related Instructions

• Loop Des:
– This is a looping instruction.

– The number of times looping is required is placed in the CX register.

– With each iteration, the contents of CX are decremented.

– ZF is checked whether to loop again or not.

– Ex: Loop Unconditional Loop.

– LoopZ / LOOPE Loop through sequence while ZF=1 & CX=0

– LoopNZ / LOOPNE Loop through sequence while ZF=0 & CX=0

24-Aug-22 103
 7. Machine control / Processor Control Instructions
• These instructions are used to control the machine operation.
• These instructions are also called ‘Processor Control Instructions’.
• These instructions control the processor itself.
• 8086 allows to control certain control flags that:
– causes the processing in a certain direction
– processor synchronization if more than one microprocessor
attached.

24-Aug-22 104
7. Machine control / Processor Control Instructions cont’d…

• HLT: - To stop the execution of any ongoing program.

• Wait: - To Enter the processor in wait state.

Wait for TEST i/p to go LOW

• ESC: Escape

• NOP : No Operation

– LOCK : Bus lock prefix

24-Aug-22 105
 8. Flag Manipulation Instructions

• STC:
– It Sets the carry flag to 1.

• CLC:
– It clears the carry flag to 0.

• CMC:
– It complements the carry flag.

24-Aug-22 106
 8. Flag Manipulation Instructions cont’d…

• STD:
– It sets the direction flag to 1.
– If it is set, string bytes are accessed from higher memory
address to lower memory address. Auto Decrement

• CLD:
– It clears the direction flag to 0.
– If it is reset, the string bytes are accessed from lower memory
address to higher memory address. Auto Increment
– STI : Set the Interrupt Flag
– CLI : Clear the Interrupt Flag
24-Aug-22 107
 9. String Instructions
• String in assembly language is just a sequentially stored bytes
or words.
• There are very strong set of string instructions in 8086.
• By using these string instructions, the size of the program is
considerably reduced.
– The length of the string byte must be stored in CX.

• The direction flag controls the string instruction execution.

• 1. If DF=0, execution follows auto increment. (1. CLD)
• 2. If DF=1, execution follows auto decrement. (2.STD)
24-Aug-22 108
 9. String Instructions cont’d…

• 3. CMPS Des, Src:

– It compares the string bytes or words.
– The length of the string byte must be stored in CX.
– If both byte or word strings are equal; ZF will SET.

• 4. SCAS String:
– It scans a string.
– It compares the String with byte in AL or with word in AX.
– Whenever a match to the specified operand, is found in the
string, Execution stops and ZF will SET.
– If no match, ZF is RESET.
24-Aug-22 109
 9. String Instructions cont’d…

• 5. MOVS / MOVSB / MOVSW:

– It causes moving of byte or word from one string to another.
– The length of the string byte must be stored in CX.
– In this instruction, the source string is in Data Segment and
destination string is in Extra Segment.
– SI and DI store the offset values for source and destination
index.
– String copies as following.
DS : SI  ES : DI
24-Aug-22 110
 9. String Instructions cont’d…

• 6. REP (Repeat):
– This is an instruction prefix.
– It causes the repetition of the instruction until CX
becomes zero.
– E.g.: REP MOVSB STR1, STR2
• It copies byte by byte contents.
• REP repeats the operation MOVSB until CX becomes
zero.

24-Aug-22 111
 9. String Instructions cont’d…

7. LODS : Load String byte or word:

• It loads AL/ AX register by a string pointed by DS:

SI
• DS  AL

8. STOS: Store string byte or word:

• It stores AL/ AX register content to a string
pointed by ES: DI
• AL  DS
24-Aug-22 112
 Interrupts of 8086
 The meaning of ‘interrupts’ is to break the sequence of operation.

 While the CPU is executing a program, on ‘interrupt’ , breaks the normal

sequence of execution of instructions, diverts its execution to some other
program called Interrupt Service Routine (ISR).

 After executing ISR , the control is transferred back again to the main program.

 An 8086 interrupt can come from any of the 3 sources.

1. External signal applied from INTR / NMI
2. Interrupt Instruction ( INT N)
3. Some error condition produced in 8086 by the execution of an instruction.
( Divide an operand by 0)

 In 8086 system, the 1st 1KB of memory 00000H to 003FC H is set as table
for storing the starting address of ISR.

 Starting address of ISR, is called as Interrupt vector or interrupt pointer. Hence the
table is called as Interrupt vector table or interrupt pointer table .
Interrupt vector table
 Interrupts of 8086 cont’d…

Types of Interrupts: There are two types of Interrupts in 8086.

(i) Hardware Interrupts (ii) Software Interrupts

i. Hardware Interrupts ( External Interrupts ).

 The Intel microprocessors support hardware interrupts through:

two pins that allow interrupt requests, INTR (pin 18) and
NMI (pin 17) .

 One pin that acknowledges, INTA (pin 24), the interrupt requested
on INTR.
 Hardware and Software Interrupts
The nonmaskable interrupt is Cannot be ignored by the microprocessor.
generated by en external device, Generates a Type 2 interrupt (address
trough a rising edge on the NMI pin. 0008H in the Interrupt vector table)
The maskable interrupts (00…FFH) can • an external device, trough a high logic
Hardware be generated by: level on the INTR pin (the external
interrupts (IF (interrupt flag) in FLAGS register device has to specify the interrupt
enables or disables (masks) the P to number).
accept maskable interrupts.) • microprocessor itself (i.e. when trying
to divide by 0), (the interrupt number is
hardware defined).
Software interrupts (exceptions) using the INT instruction
(followed by the interrupt number (type)).

Interrupt priority
Divide-error Highest
INT, INTO
NMI
INTR
Single-step Lowest
 Hardware Interrupts of 8086 cont’d…

INTR
 INTR is a maskable hardware interrupt.
 The interrupt can be enabled/disabled using STI/CLI instructions
(or)
 using more complicated method of updating the FLAGS register with the
help of the POPF instruction.

 When an interrupt occurs, the processor

 stores FLAGS register into stack,
 disables further interrupts,
fetches one byte (00 H to FF H) representing interrupt type,
and jumps to interrupt processing routine address of which is stored in
location 4 * <interrupt type>.
 Interrupt processing routine should return with the IRET instruction.
 Hardware Interrupts of 8086 cont’d…

NMI

 NMI is a non-maskable interrupt.

 This interrupt has higher priority than the maskable interrupt.
 Interrupt is processed in the same way as the INTR interrupt.
 Interrupt type of the NMI is 2,
 i.e. the address of the NMI processing routine is stored in
location 0008 H Type N* 4.
 Interrupts of 8086 cont’d…

(ii) Software Interrupts (Internal Interrupts and Instructions) .

Software interrupts can be caused by:

1. INT 3 instruction - breakpoint interrupt. This is a type 3 interrupt.

2. INT <interrupt Type N > instruction : -

any one interrupt from available 256 interrupts. ( 00 H to FF H).

 When an INT N instruction is executed, Type byte N is multiplied with 4;

 The content of IP & CS of ISR will be taken from the N*4 as OFFSET address
and 0000 as segment address.

Ex: INT 20H;

Type N * 4 = 20H*4= 80H

So, ISR address is specified by 0000: 0080 H

 Interrupts of 8086 cont’d…

(ii) Software Interrupts (Internal Interrupts and Instructions) .

3. INTO instruction - interrupt on overflow

4. Single-step interrupt – ( It executes one instruction & stop)

 generated if the TF flag is set.
 This is a type 1 interrupt.
 When the CPU processes this interrupt it clears TF flag , before calling
the interrupt processing routine.

5. Processor exceptions: Divide Error (Type 0),

Unused Opcode (type 6) and
Escape Opcode (type 7).

Software interrupt processing is the same as for the hardware interrupts.

Ex: INT n (Software Instructions)

 (ii) Software Interrupts

INT 00 (divide by zero error): -

 INT 00 is invoked by the microprocessor whenever there is an attempt to

divide a number by zero.
 ISR is responsible for displaying the message “Divide Error” on the screen

INT 01 (Single-step Interrupt): -

 For single stepping the trap flag must be 1

 After execution of each instruction, 8086 automatically jumps to 00004H to fetch
4 bytes for CS: IP of the ISR.

INT 02 (Non-Maskable Interrupt): -

 Whenever NMI pin of the 8086 is activated by a high signal (5v),

 The CPU Jumps to physical memory location 00008 to fetch CS: IP of the
ISR associated with NMI.
 (ii) Software Interrupts
INT 03 (break point Interrupt): -

 A break point is used to examine the CPU and memory after the execution
of a group of Instructions.

 It is one byte instruction

whereas other instructions of the form “INT nn” are 2 byte instructions.

INT 04 (Signed number overflow Interrupt): -

 There is an instruction associated with this INT 04 (interrupt on overflow).

 If INT 04 is placed after a signed number arithmetic as IMUL or ADD

the CPU will activate INT 04 if 0F = 1.

 In case where 0F = 0, the INT 04 is not executed but is bypassed and

acts as a NOP.
Performance of Hardware Interrupts: -
 8086 - Pins and Signals

8/24/2022 6:27 AM 124

 8086 - Pins and Signals
 8086 is available in 40 pin DIP.
 It operates in single processor (MIN) mode and
multi processor (MAX) mode configurations.
 8086 signals can be categorized into 3 groups.
 Signals with common functions in MIN & MAX modes
 Signals which have special functions for MIN mode.
 Signals which have special functions for MAX mode.

8/24/2022 6:27 AM 125

8086 Microprocessor
Common signals
Pins and Signals
AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

Address remains on the lines during T1

state. Data is available during T2, T3, TW
& T4 CLOCK States.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals

8/24/2022 6:27 AM 126

 8086 Microprocessor
Pins and Signals Common signals

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals.

The address bits are separated from the

status bits using Latches controlled by
ALE signal.

During T1 , these are the Address lines.

During T2, T3, TW & T4 CLOCK States

status information is available on these
lines.

S6 is always LOW (Logical).

S5 displays the status of IF (Interrupt S4 S3 Segment Reg

enable flag bit), at the beginning of each Indication
clock cycle. 0 0 Extra (ES)

S4 & S3 combindely indicates, which 0 1 Stack (SS)

segment register is being used presently,
1 0 Code (CS) or None
for memory access.
1 1 Data (DS)
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8086 Microprocessor
Pins and Signals Common signals

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the data
bus use BHE (Active Low) signal. It is
multiplexed with status signal S7.

Bus High Enable/Status Signal BHE / S7

1024KB [1MB] addressable memory of 8086
is divided into two 512KB even and odd
memory banks.

Even memory bank has addresses from

00000H to 0FFFFEH it contains only Even
Addresses.

Odd memory bank has addresses from

00001H to 0FFFFFH it contains only Odd
Addresses.

BHE is active low signal which is used as

enable signal of Odd memory bank. (D8-D15)

The address line A0 is used as Enable signal

8/24/2022 6:27 AM for the Even Memory Bank. (D0-D7) 128
8086 Microprocessor
Pins and Signals Common signals

BHE (Active Low)/S7 (Output)

A0 Indication
0 0 Whole word is received/transmitted [D15-D0 data lines are active]

0 1 Byte from Odd memory bank [D15-D8 data lines are active]
1 0 Byte from Even memory bank [D7-D0 data lines are active]

1 1 Passive

MN/ MX*

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD* (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low.
8/24/2022 6:27 AM 129
8086 Microprocessor
Pins and Signals Common signals

RESET (Input)

Causes the processor to immediately

terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

CLK

The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a level triggered input. This is

sampled during the last clock cycles of
each instruction to determine the
availability of the request. If any
interrupt request is pending, the
processor enters the interrupt
acknowledge cycle.

This signal is active high and internally

8/24/2022 6:27 AM 130
synchronized.
READY :

• It is the acknowledgement from the addressed memory or I/O device .

• If READY=0 then the processor will insert WAIT states between T3 and T4.

• If READY=1, the external device is ready to communicate with the processor.

TEST*

It is the input signal which is examined by the "wait" instruction.

If TEST* is LOW, execution continues, otherwise the processor waits in an "idle"

state.

8/24/2022 6:27 AM 131

8086 Microprocessor
Min/ Max Pins
Pins and Signals
The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

8/24/2022 6:27 AM 132

8086 Microprocessor
Pins and Signals Minimum mode signals

Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied

to VCC (logic high)

8086 itself generates all the bus control signals

(Data Transmit/ Receive) Output signal from the

processor to control the direction of data flow
through the data transceivers

(Data Enable) Output signal from the processor

used to enable the transceivers. It indicates the
availability of data over address / data lines.

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

M/𝐈𝐎 Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.

𝐖𝐑 Write control signal; asserted low Whenever

processor writes data to memory or I/O port

𝐈𝐍𝐓𝐀 (Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
8/24/2022 6:27 AM 133
8086 Microprocessor
Pins and Signals Minimum mode signals

Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied

to VCC (logic high)

8086 itself generates all the bus control signals

HOLD Input signal to the processor from the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.

8/24/2022 6:27 AM 134

8086 Microprocessor
Pins and Signals Maximum mode signals

During maximum mode operation, the MN/ 𝐌𝐗 is

grounded (logic low)

Pins 24 -31 are reassigned

𝑺𝟎 , 𝑺𝟏 , 𝑺𝟐 Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.

8/24/2022 6:27 AM 135

8086 Microprocessor
Pins and Signals Maximum mode signals

During maximum mode operation, the MN/ 𝐌𝐗 is

grounded (logic low)

Pins 24 -31 are reassigned

𝑸𝑺𝟎 , 𝑸𝑺𝟏 (Queue Status) The processor provides the status

of queue in these lines.

The queue status can be used by external device to

track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as

shown in the table.

8/24/2022 6:27 AM 136

8086 Microprocessor
Pins and Signals Maximum mode signals

During maximum mode operation, the MN/ 𝐌𝐗 is

grounded (logic low)

Pins 24 -31 are reassigned

𝐑𝐐/𝐆𝐓𝟎 , (Bus Request/ Bus Grant) These requests are used

𝐑𝐐/𝐆𝐓𝟏 by other local bus masters to force the processor
to release the local bus at the end of the
processor’s current bus cycle.

These pins are bidirectional.

The request on𝐆𝐓𝟎 will have higher priority than𝐆𝐓𝟏

𝐋𝐎𝐂𝐊 An output signal activated by the LOCK prefix

instruction.

Remains active until the completion of the

instruction prefixed by LOCK.

The 8086 output low on the 𝐋𝐎𝐂𝐊 pin while

executing an instruction prefixed by LOCK to
prevent other bus masters from gaining control of
the system bus.

8/24/2022 6:27 AM 137

 A0 Indication

0 0 Whole word is received/transmitted [D15-D0 data lines are active]

0 1 Byte from Odd memory bank [D15-D8 data lines are active]
1 0 Byte from Even memory bank [D7-D0 data lines are active]

1 1 Passive

M/ Transfer Type
0 0 1 I/O read
0 1 0 I/O write
1 0 1 Memory read
1 1 0 Memory write

8/24/2022 6:27 AM 138

 S4 S3 Segment Reg Indication

0 0 Extra (ES)

0 1 Stack (SS)

1 0 Code (CS) or None

1 1 Data (DS)

8/24/2022 6:27 AM 139

TRY IT…
1) What are Minimum mode pins?
2) What are maximum mode pins?
3) What is INTR?
4) What is the importance of ALE?
5) Why two ground pins for 8086?
6) Why address and data pins are multiplexed?
7) How many address pins in total?
8) List out all active low signals of 8086.

8/24/2022 6:27 AM 140

 PHYSICAL MEMORY ORGANIZATION in 8086-BASED SYSTEM

8/24/2022 6:27 AM 141

 PHYSICAL MEMORY ORGANIZATION cont’d...

8/24/2022 6:27 AM 142

 PHYSICAL MEMORY ORGANIZATION cont’d...

 The 8086 microprocessor provides a 20-bit address to memory.

 The memory is organized as a linear array of up to 1 MB, addressed from

00000H to FFFFFH.

 The 1MB of 8086 addressable memory space is divided into 2 banks :

Even memory bank and Odd memory bank.

 Each bank will have an addressable space of 512 kB.

 In 8086-based system the lower 8 lines of data bus, Do- D7, are connected
to even bank memory ICs and

 The upper 8 lines of data bus, D8- D15 are connected to odd bank memory .

8/24/2022 6:27 AM 143

 PHYSICAL MEMORY ORGANIZATION cont’d...

 The processor provides two enable signals and A0.

 These two signals selectively allow reading from or writing into either
an odd byte location, even byte location, or both.

 is used to enable the odd bank and

 The A0 address line is used to enable the even bank.

A0 Indication

0 0 Whole word is received/transmitted [D15-D0 data lines are active]

0 1 Byte from Odd memory bank [D15-D8 data lines are active]
1 0 Byte from Even memory bank [D7-D0 data lines are active]

1 1 Passive

8/24/2022 6:27 AM 144

 PHYSICAL MEMORY ORGANIZATION cont’d...

 A microprocessor-based system requires both EPROM and RAM.

 Hence, the available memory space has to be divided between EPROM

and RAM.

 This choice depends on the system designer as well as on the application

for which the system is designed.

 The system designer should allot equal address space in odd and even
bank for both EPROM and RAM.

 The required EPROM memory capacity can be implemented in two Ics

(one for even and the other for odd bank) or in multiple ICs.

 Similarly, the RAM capacity of the system can be implemented in two ICs
or in multiple ICs.
 This choice depends on the availability of memory IC and the system designer.
8/24/2022 6:27 AM 145
 PHYSICAL MEMORY ORGANIZATION cont’d...

8/24/2022 6:27 AM 146

 Simple Programs using 8086 Microprocessor

16 Bit Addition 16 Bit Multiplication Multi Byte ADDITION

MOV AX,[2100] MOV AX,[0500] MOV CX,000A

MOV BX,[2102] MOV BX,[0502] MOV BX,0500
ADD AX,BX MUL BX MOV SI,0600
MOV [2140],AX INT 03 MOV DI,0700
INT 03 HLT
HLT L1: MOV AX,[BX]
16BIT DIVISION ADC AX,[SI]
16 Bit Subtraction MOV [DI],AX
MOV AX,000CH INC BX
MOV AX,[2100] MOV BL,04H INC SI
MOV BX,[2102] DIV BL INC DI
SUB AX,BX INT 03 LOOP L1
MOV [2140],AX HLT INT 03
INT 03 HLT
HLT
LARGEST NO IN AN ARRAY AL CL= CL= CL= CL= CL= CL= CL=
06 05 04 03 02 01 00
MOV SI,0300 E9 13 13 13 13 13 13 13
MOV CL, 06
E9 13 13 13 13 13 13 13
MOV AL,00
L1: CMP AL,[SI] E9 68 68 68 68 68 68 68
JAE L2 B4 E9 E9 E9 E9 E9 E9 E9
MOV AL,[SI]
L2: INC SI B4 4A 4A 4A 4A 4A 4A 4A

LOOP L1 35 B4 B4 B4 B4 B4 B4 B4
MOV [SI],AX SI 0300 00 35 35 35 35 35 35 35
INT 03
HLT
LARGEST NO IN AN ARRAY AL CX=06

MOV SI,0300 13 13 13 13 13 13 13
MOV CX,0006 68 68 68 68 68 68 68
MOV AX,0000
E9 E9 E9 E9 E9 E9 E9
L1: CMP AX,[SI]
JAE L2 4A 4A 4A 4A 4A 4A 4A
MOV AX,[SI] SI 0301 B4 B4 B4 B4 B4 B4 B4
L2: INC SI
SI 0300 35 35 35 35 35 35 35
INC SI
LOOP NE L1
MOV [SI],AX
INT 03
HLT
SMALLEST NUMBER IN AN ARRAY

MOV SI,0300
MOV CX,0003
MOV AX,FFFF
L1 : CMP AX,[SI]
JB L2
MOV AX,[SI]
L2 : INC SI
INC SI
LOOP NE L1
MOV [SI],AX
INT 03
HLT
AM OF N NO’S

MOV BX,0500
MOV CL,[BX]
MOV DI,0000
INC BX
L1: MOV AL,[BX]
MOV AH,00
ADD DI, AX
INC BX
LOOP L1
MOV DL,[0500]
MOV AX,DI
DIV DL
INT 03
HLT
SUM OF N NATURAL NO’S SUM OF SQUARES OF ‘N’ SUM OF CUBES OF N
MOV AX,0005 NATURAL NUMBERS NATURAL NO’S
MOV BX,AX
INC BX MOV CX,[3000] MOV CX,[3000]
MUL BX MOV BX,0001 MOV BX,0001
MOV CL,02 L1: MOV AX,BX L1: MOV AX,BX
DIV CL MUL AX MUL AX
INT 03 ADD [3002],AX MUL BX
HLT INC BX ADD [3002],AX
DEC CX INC BX
Hint: n(n+1)/2 JNZ L1 DEC CX
INT 03 JNZ L1
HLT INT 03
HLT
ASCENDING ORDER DESCENDING ORDER

MOV CX,0000 MOV CX,0000

MOV DL,04 MOV DL,04
L3: MOV DI,0500 L3: MOV DI,0500
MOV CL,DL MOV CL,DL
MOV BX,0500 MOV BX.0500
MOV AL,[BX] MOV AL,[BX]
L2: INC BX L2: INC BX
CMP AL,[BX] CMP AL,[BX]
JNC L1 JC L1
MOV AL,[BX] MOV AL,[BX]
MOV DI,BX MOV DI,BX
L1: DEC CX L1: DEC CX
JNZ L2 JNZ L2
MOV AH,[BX] MOV AH,[BX]
MOV [BX],AL MOV [BX],AL
MOV [DI],AH MOV [DI],AH
DEC DL DEC DL
JNZ L3 JNZ L3
INT 03 INT 03
HLT HLT
Multi Byte Addition

Assume CS:CODE,DS:DATA
DATA SEGMENT
CODE SEGMENT
NUM1 DB 04H DUP(0)
MOV AX,DATA
NUM2 DB 04H DUP(0)
MOV DS,AX
RESULT DB 04H DUP(0)
DATA ENDS
LEA SI,NUM1
LEA DI,NUM2
END
LEA BX,RESULT
MOV CX,0004 H

L1: MOV AL,[SI]

ADC AL,[DI]
MOV [BX],AL
INC SI
INC DI
INC BX
LOOP L1
INT 03
CODE ENDS
24-Aug-22 155