electronics

Editorial
Design of Ultra-Low Voltage/Power Circuits and Systems
Marco Lanuzza 1, * , Raffaele De Rose 1, * and Sebastiano Strangio 2, *

1 Department of Computer Engineering, Modeling, Electronics and Systems, University of Calabria,

87036 Rende, Italy
2 Dipartimento di Ingegneria dell’Informazione (DII), University of Pisa, 56122 Toscana, Italy
* Correspondence: [email protected] (M.L.); [email protected] (R.D.);
[email protected] (S.S.)

Over the last years, the Internet of Things (IoT), wireless sensor networks and the
emergence of other energy-constrained applications have pushed the demand for low-cost
systems-on-chip solutions, entailing tight area and small power/voltage budgets [1,2]. In
response to such requests, considerable effort has been spent in defining novel ultra-low
voltage/power analog (e.g., [3–6]), mixed-signal (e.g., [7–9]), digital circuits (e.g., [10–12]),
as well as energy-efficient and high-density memory solutions [13–16].
In the above context, this Special Issue features five research papers [17–21] that
present original contributions for a wide range of applications, including image sensors,
sensor interfaces, cryogenic computing, deep neural networks, and memory design. These
five papers are briefly summarized as follows. A. M. Brunetti et al. [17] presented a
logarithmic six-transistor pixel circuit for CMOS image sensors, which exploits low-voltage
photodiode biasing to enable low dark current. The proposal was experimentally validated
in 110 nm CIS process technology and compared against the typical logarithmic three-
transistor pixel circuit. Experimental results prove that, when compared to the standard





 design, the proposed implementation achieves a dark current reduction by 34.5 dB at the
Citation: Lanuzza, M.; De Rose, R.; expense of three additional transistors. This improvement in dark current also translates
Strangio, S. Design of Ultra-Low into increased dynamic range, reaching a value larger than 160 dB, which is a record for
Voltage/Power Circuits and Systems. logarithmic pixels.
Electronics 2022, 11, 607. A. Ria et al. [18] proposed a low-power CMOS bandgap voltage reference for sensor
https://doi.org/10.3390/ interfaces, which is able to work with supply voltages down to 0.5 V. The proposal is based
electronics11040607 on a classic CMOS bandgap core, whose design was properly modified to be compatible
Received: 11 February 2022
with low-threshold or zero-threshold MOSFETs. The core was combined with a recently
Accepted: 12 February 2022
proposed switched capacitor, inverter-like integrator implementing offset cancellation
Published: 16 February 2022
and low-frequency noise reduction techniques. Both theoretical analysis and numerical
simulations were presented to describe circuit operation. A prototype was also fabricated in
Publisher’s Note: MDPI stays neutral
a commercial 180 nm CMOS technology. The experimental results show that the proposed
with regard to jurisdictional claims in
circuit provides a reference voltage of 220 mV at 0.5 V supply with a power consumption of
published maps and institutional affil-
315 nW and a temperature sensitivity of 45 ppm/°C across a 10–50 °C temperature range.
iations.
E. Garzón et al. [19] investigated three appealing embedded memory technologies such
as six-transistor static random-access memory (6T-SRAM), gain-cell embedded DRAM
(GC-eDRAM) and non-volatile spin-transfer torque magnetic random access memory
Copyright: © 2022 by the authors.
(STT-MRAM) under cryogenic (77 K) operation. The study was carried out using a com-
Licensee MDPI, Basel, Switzerland. mercial 65 nm 1.2 V CMOS technology fully calibrated under silicon measurements at
This article is an open access article cryogenic temperatures. The obtained results demonstrate that as the temperature goes
distributed under the terms and down to 77 K, 6T-SRAM exhibits slight improvements in static noise margin (SNM) during
conditions of the Creative Commons hold and read operations, while suffering from lower (−16%) write SNM. GC-eDRAM
Attribution (CC BY) license (https:// shows significant benefits under cryogenic operation with read voltage margins and data
creativecommons.org/licenses/by/ retention time improved by about 2× and 900×, respectively. STT-MRAM based on single-
4.0/). or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing

Electronics 2022, 11, 607. https://doi.org/10.3390/electronics11040607 https://www.mdpi.com/journal/electronics

Electronics 2022, 11, 607 2 of 3

margins (36% and 48%, respectively) at the cost of longer write access time (1.45× and 2.1×,
respectively). Overall, the performed analysis points out that embedded memory technolo-
gies can be attractive candidates for cryogenic applications not only for high-performance
computing but also for bridging the gap from room temperature to the realm of cryogenic
applications that operate down to liquid helium temperatures and below.
M. Vatalaro et al. [20] presented a novel low-power, low-voltage analog implementa-
tion of the softmax function to be used in deep neural network (DNN) applications. The
proposal is based on a modular and scalable PMOS-only design, which enables electrically
adjustable amplitude and slope parameters. More specifically, the architecture is composed
of input current–voltage linear converter stages, MOSFETs operating in a subthreshold
regime implementing the exponential functions, and analog divider stages. The softmax
circuit was designed in 180-nm CMOS technology and validated through circuit simula-
tions. The obtained results show that the circuit is able to operate at supply voltages down
to 0.5 V. A 10-input/10-output implementation occupies a chip area of 2570 µm2 with a
power consumption of only 3 µW, thus resulting in a very compact and energy-efficient
solution as compared to digital implementations.
K. Vicuña et al. [21] presented a 1024 bit self-adaptive memory address decoder
based on the Dual Mode Logic (DML) design style to allow working in two modes of
operation, i.e., dynamic for high-performance and static for energy-saving. The main
novelty of the proposal concerns the design of a controlling mechanism that mixes both of
these modes of operation to simultaneously benefit from their inherent advantages. When
performance is the primary target, the mixed operating mode is enabled. As a consequence,
the self-adjustment mechanism identifies at run time the logic gates that have to work in the
energy-efficient mode (i.e., static mode), while those belonging to the critical path operate
in the faster dynamic mode. In addition, the decoder can operate in the fully static mode to
achieve the lowest energy consumption when speed is not a primary concern. The memory
address decoder design was implemented in 65-nm CMOS technology and simulated to be
compared against other logically equivalent dynamic and static solutions. When operating
in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in
comparison with a dynamic logic-based design, while presenting significantly reduced
energy consumption (28%). On the contrary, further energy is saved (29%) with respect to
conventional logic styles when the circuit works in the fully static mode.
Finally, we would like to thank all the authors for their appreciable contributions
and all the reviewers for their fruitful comments and feedback. Special thanks are also
addressed to the Editorial Board of MDPI’s Electronics journal for the opportunity to manage
this Special Issue, and to the Editorial Office staff for their valuable and timely support.

Funding: This research received no external funding.

Conflicts of Interest: The authors declare no conflict of interest.

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