ISSCC 2021 / SESSION 10 / CONTINUOUS-TIME ADCs AND DACs / 10.

10.1 A 116μW 104.4dB-DR 100.6dB-SNDR CT ΔΣ Audio ADC Using We also improve the energy efficiency of the amplifier (OTA) of the first integrator (INT1)
Tri-Level Current-Steering DAC with Gate-Leakage as shown in Fig. 10.1.3. Thanks to the CIFF-B structure with multi-level DAC
implementation, the INT1 output swing is minimized and the driving requirement is
Compensated Off-Transistor-Based Bias Noise Filter greatly relaxed. The current reused first stage chopped at fs/2 [7] is adopted to tackle
the flicker noise and achieve the required thermal noise level with minimum current
Chilun Lo, Jongmi Lee, Yong Lim, Younghyun Yoon, Hyunseok Hwang, consumption. To further improve the energy efficiency of INT1, a power-domain shifting
Jaehoon Lee, MooYeol Choi, Myungjin Lee, Seunghyun Oh, Jongwoo Lee from 1.8V to 1V at the second stage of the OTA is introduced. In order to achieve this
level shifting, two voltage references are used in a common-mode feedback loop to
Samsung Electronics, Hwaseong, Korea guarantee the desired output common-mode voltage. An input feedforward to the second
stage of the OTA without miller compensation maintains unit gain bandwidth (UGBW)
as 4.5× fs. The OTA of the SAB is a simple two-stage topology with UGBW as 1.2× fs at
2021 IEEE International Solid- State Circuits Conference (ISSCC) | 978-1-7281-9549-0/20/$31.00 ©2021 IEEE | DOI: 10.1109/ISSCC42613.2021.9365807

A continuous-time delta-sigma modulator (CT-DSM) ADC is commonly used in audio

applications because of its high energy efficiency and driving-friendly front-end the 1V domain without chopping scheme since the noise of the SAB is strongly shaped
compared with its discrete time counterpart. A resistive DAC (R-DAC) is widely used for by the INT1 and is thus not a concern. As results, the loop filter consumes only 42μW
its intrinsic low flicker noise. However, the design of a high PSRR and low flicker noise to provide low input-referred noise, third-order noise-shaping, and satisfies the driving
reference generator for R-DAC not only consumes extra power and area with an external requirement for linearity.
RC filter [1] but also limits the peak SNDR performance [2]. In contrast, a current-
steering DAC (I-DAC) has intrinsic PSRR. In addition, the use of a tri-level This work is fabricated in a 28nm CMOS process and occupies an active area of 0.07mm2
implementation with a dumped buffer reduces noise with a small input signal, which (Fig. 10.1.7). The measured spectrums (Fig. 10.1.4) with different noise filter
improves dynamic range (DR), but flicker noise from the bias circuit still limits the peak configurations prove the effectiveness of the proposed GLCOT filters (the chopping and
SNR of the ADC. Instead of using large-sized transistors or an off-chip RC filter for TDWA are turned on to mitigate non-ideality contributions from other blocks). “No filter”
required low flicker noise, the sample-and-hold noise filter [3] is proposed for a low suffers from the reference and DAC bias circuit noise and SNDR is limited to 86dB by
noise I-DAC by filtering the bias noise with an off-transistor-based filter, which requires the noise floor. “Off-transistor filter only” suffers from the unbalanced IP/IN current of
periodic refreshing to compensate the bias voltage drift due to the gate-leakage current the DAC cells due to gate-leakage current and SNDR is limited to 91dB by THD
of the DAC cells. However, a trade-off between bias voltage drift and folded sampling degradation while the noise floor is greatly reduced. “GLCOT filter type I” improves the
noise of this technique limits its usage in more advanced technology because larger noise floor by 6dB achieving 92dB SNDR while “GLCOT filter type II” further improves
gate-leakage current is expected. In order to solve aforementioned problems, we the noise floor by 14.7dB achieving 100.6dB SNDR. Figure 10.1.5 shows the measured
introduce a CT-DSM ADC with a gate-leakage compensated off-transistor (GLCOT) based SNDR versus the input amplitude for a 1kHz input, SNDR of ten corner samples, and
I-DAC bias noise filter without extra off-chip components which is suitable for true power breakdown of the ADC. It achieves 100.6dB SNDR, 100.7dB SNR, 104.4dB DR,
wireless stereo (TWS) applications. The ADC achieves 104.4dB DR and 100.6dB SNDR and 118dB SFDR while consuming a total of 116μW dominated by DAC and INT1. Figure
in 24kHz bandwidth while consuming 116μW. This corresponds to a Schreier FoMDR of 10.1.6 summarizes the performance of the ADC and compares with recent audio ADCs.
187.5dB and FoMSNDR of 183.7dB, respectively. This work achieves a Schreier FoMDR of 187.5dB and an FoMSNDR of 183.7dB, both of
which are state-of-the-art, and occupies competitively small area without extra external
The architecture of the CT-DSM ADC (Fig. 10.1.1) is derived from a third-order cascade components, making it suitable for TWS applications.
of integrators feedforward feedback (CIFF-B) structure with a 4b quantizer operating at
6.144MHz to achieve 136dB SQNR at an OSR of 128×. The out-of-band gain is set as References:
low as 2 for less clock jitter sensitivity, and lower toggling activity with a small input [1] R. Veldhoven et al., “A Low-Cost 4-Channel Reconfigurable Audio Interface for Car
signal for better noise performance by adopting a tri-level I-DAC. A single amplifier Entertainment System,” ISSCC, pp. 168–170, Feb. 2020.
biquad (SAB) [4,5] combined with the first integrator output feedforward and passive [2] S. H. Wu et al., “A Current-Sensing Front-End Realized by A Continuous-Time
summation reduces the number of amplifiers while maintaining the third-order CIFF-B Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving
coefficients. The excess loop delay compensation (ELDC) embedded charge redistributed 140dB DR and 8ppm INL at 4kS/s,” ISSCC, pp. 154–156, Feb. 2020.
SAR quantizer further avoids the static current consumption compared with an I-DAC- [3] S. H. Wen et al., “A -105dBc THD+N (-114dBc HD2) at 2.8VPP Swing and 120dB
based ELDC. The tri-level DAC current cell with resistive source degeneration with a 1.8V DR Audio Decoder with Sample-and-Hold Noise Filtering and Poly Resistor Linearization
supply is designed to achieve the target noise floor with a 40kΩ input resistor for small Schemes,” ISSCC, pp. 294–296, Feb. 2019.
input signal condition. The linearity of the multi-level DAC is handled by a tri-level data- [4] H. Chae et al., “A 12mW low-power continuous-time bandpass Δ∑ modulator with
weighted average technique (TDWA) [6]. 58dB SNDR and 24MHz bandwidth at 200MHz IF,” ISSCC, pp. 148–150, Feb. 2012.
[5] C.-Y. Ho et al., “A 4.5mW CT self-coupled Delta-Sigma modulator with 2.2 MHz BW
We improve the off-transistor-based filter by compensating the gate-leakage current of and 90.4 dB SNDR using residual ELD compensation,” IEEE JSSC, vol. 50, no. 12, pp.
the DAC cells as shown in Fig. 10.1.2. In order to filter out the reference noise with 2870–2879, Dec. 2015.
reasonable on-chip capacitance, tens or even hundreds of GΩ resistance is required. [6] I.-H. Jang et al., “A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-
An off-transistor is a good candidate to provide such a high impedance but the gate- Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling,” IEEE JSSC, vol.
leakage current (IGL) of the DAC cells would cause un-ignorable IR drop which makes 53, no. 4, pp. 1139–1148, April 2018.
unbalanced IP/IN current even with thick-oxide device implementation in an advanced [7] S. Billa et al., “Analysis and design of continuous-time delta–sigma converters
process technology. This current unbalance should be minimized to relax the dumped incorporating chopping,” IEEE JSSC, vol. 52, no. 9, pp. 2350–2361, Sept. 2017.
buffer design of the multi-bit tri-level DACs, otherwise THD degradation would be
expected from the signal-dependent disturbance. The proposed GLCOT filter
compensates IGL using an analog loop (type I in Fig. 10.1.2) which locks the filter output
voltage (VB’’) with the input bias voltage (VB) by adjusting the amplifier output voltage
(VO) to supply the required current (IGLC); this is possible because the order of IGL is
generally much smaller than the drain-to-source leakage of an off-transistor. However,
the bandwidth of the type I filter is extended by a factor of (1+A) where A represents the
gain of the amplifier. It is not preferred, since the gain needs to be high enough to
minimize the extra error from the analog loop, but this reduces the noise filter ability.
To break this trade-off, one more capacitor (CC) is added to configure the amplifier as a
unit gain buffer at relatively high frequency and one more off-transistor (M2) is added to
filter out the low-frequency noise as shown in Fig. 10.1.2 GLCOT filter type II. The
bandwidth of the filter is now only extended by a factor of 2 and not related to amplifier
gain. The noise of the amplifier is also filtered out by the off-transistor-based filter and
the offset of the amplifier is designed to be low enough so that it only causes negligible
IP/IN current unbalance.

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10

Figure 10.1.1: The proposed 128× OSR 4b third-order CT-DSM ADC architecture Figure 10.1.2: Comparison of different noise filter implementations based on off-
(actual implementation is fully differential). transistors.

Figure 10.1.4: Measured spectrums with different off-transistor based filter

Figure 10.1.3: Amplifier topology of the first integrator. configurations.

Figure 10.1.5: Measured SNDR versus input amplitude (top), performance of corner Figure 10.1.6: Performance summary and comparison with state-of-the-art audio
samples (bottom left), and power breakdown (bottom right). ADCs.

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Figure 10.1.7: Die photo.

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