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CHAPTER 7 INPUT/OUTPUT
ANSWERS TO QUESTIONS
7.1 Human readable: Suitable for communicating with the computer user.
Machine readable: Suitable for communicating with equipment.
Communication: Suitable for communicating with remote devices
7.2 The most commonly used text code is the International Reference
Alphabet (IRA), in which each character is represented by a unique 7-bit
binary code; thus, 128 different characters can be represented.
7.3 Control and timing. Processor communication. Device communication.
Data buffering. Error detection.
7.4 Programmed I/O: The processor issues an I/O command, on behalf of
a process, to an I/O module; that process then busy-waits for the
operation to be completed before proceeding. Interrupt-driven I/O:
The processor issues an I/O command on behalf of a process, continues
to execute subsequent instructions, and is interrupted by the I/O
module when the latter has completed its work. The subsequent
instructions may be in the same process, if it is not necessary for that
process to wait for the completion of the I/O. Otherwise, the process is
suspended pending the interrupt and other work is performed. Direct
memory access (DMA): A DMA module controls the exchange of data
between main memory and an I/O module. The processor sends a
request for the transfer of a block of data to the DMA module and is
interrupted only after the entire block has been transferred.
7.5 With memory-mapped I/O, there is a single address space for
memory locations and I/O devices. The processor treats the status and
data registers of I/O modules as memory locations and uses the same
machine instructions to access both memory and I/O devices. With
isolated I/O, a command specifies whether the address refers to a
memory location or an I/O device. The full range of addresses may be
available for both.
7.6 Four general categories of techniques are in common use: multiple
interrupt lines; software poll; daisy chain (hardware poll, vectored); bus
arbitration (vectored).
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7.7 The processor pauses for each bus cycle stolen by the DMA module.
ANSWERS TO PROBLEMS
7.1 In the first addressing mode, 28 = 256 ports can be addressed.
Typically, this would allow 128 devices to be addressed. However, an
opcode specifies either an input or output operation, so it is possible to
reuse the addresses, so that there are 256 input port addresses and 256
output port addresses. In the second addressing mode, 216 = 64K port
addresses are possible.
7.2 In direct addressing mode, an instruction can address up to 216 = 64K
ports. In indirect addressing mode, the port address resides in a 16-bit
registers, so again, the instruction can address up to 216 = 64K ports.
7.3 64 kB
7.4 Using non-block I/O instructions, the transfer takes 20 × 128 = 2560
clock cycles. With block I/O, the transfer takes 5 × 128 = 640 clock
cycles (ignoring the one-time fetching of the iterative instruction and its
operands). The speedup is
(2560 Ð 640)/2560 = 0.75, or 75%.
7.5 a. Each I/O device requires one output (from the point of view of the
processor) port for commands and one input port for status.
b. The first device requires only one port for data, while the second
devices requires and input data port and an output data port.
Because each device requires one command and one status port, the
total number of ports is seven.
c. seven.
7.6 a. The printing rate is slowed to 5 cps.
b. The situation must be treated differently with input devices such as
the keyboard. It is necessary to scan the buffer at a rate of at least
once per 60 ms. Otherwise, there is the risk of overwriting characters
in the buffer.
7.7 At 8 MHz, the processor has a clock period of 0.125 µs, so that an
instruction cycle takes 12 × 0.125 = 1.5 µs. To check status requires
one input-type instruction to read the device status register, plus at
least one other instruction to examine the register contents. If the
device is ready, one output-type instruction is needed to present data to
the device handler. The total is 3 instructions, requiring 4.5 µs.
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7.8 Advantages of memory mapped I/O:
1. No additional control lines are needed on the bus to distinguish
memory commands from I/O commands.
2. Addressing is more flexible. Examples: The various addressing
modes of the instruction set can be used, and various registers
can be used to exchange data with I/O modules.
Disadvantages of memory-mapped I/O:
1. Memory-mapped I/O uses memory-reference instructions, which
in most machines are longer than I/O instructions. The length of
the program therefore is longer.
2. The hardware addressing logic to the I/O module is more
complex, because the device address is longer.
7.9 a. The processor scans the keyboard 10 times per second. In 8 hours,
the number of times the keyboard is scanned is 10 × 60 × 60 × 8 =
288,000.
b. Only 60 visits would be required. The reduction is 1 Ð (60/288000) =
0.999, or 99.9%
7.10 1001 0000
7.11 a. The device generates 8000 interrupts per second or a rate of one
every 125 µs. If each interrupt consumes 100 µs, then the fraction
of processor time consumed is 100/125 = 0.8
b. In this case, the time interval between interrupts is 16 × 125 =
2000 µs. Each interrupt now requires 100 µs for the first character
plus the time for transferring each remaining character, which adds
up to 8 × 15 = 120 µs, for a total of 220 µs. The fraction of
processor time consumed is 220/2000 = 0.11
c. The time per byte has been reduced by 6 µs, so the total time
reduction is 16 × 6 = 96 µs. The fraction of processor time
consumed is therefore (220 Ð 96)/2000 = 0.062. This is an
improvement of almost a factor of 2 over the result from part (b).
7.12 If a processor is held up in attempting to read or write memory,
usually no damage occurs except a slight loss of time. However, a
DMA transfer may be to or from a device that is receiving or sending
data in a stream (e.g., disk or tape), and cannot be stopped. Thus, if
the DMA module is held up (denied continuing access to main
memory), data will be lost.
7.13 Let us ignore data read/write operations and assume the processor
only fetches instructions. Then the processor needs access to main
memory once every microsecond. The DMA module is transferring
characters at a rate of 1200 characters per second, or one every 833
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µs. The DMA therefore "steals" every 833rd cycle. This slows down the
1
processor approximately × 100% = 0.12%
833
7.14 a. For the actual transfer, the time needed is (128 bytes)/(50 kBps) =
2.56 ms. Added to this is the time to transfer bus control at the
beginning and end of the transfer, which is 250 + 250 = 500 ns.
This additional time is negligible, so that the transfer time can be
considered as 2.56 ms.
b. The time to transfer one byte in cycle stealing mode is 250 + 500 +
250 = 1000 ns = 1 µs. Total amount of time the bus is occupied for
the transfer is 128 µs. This is less than the result from part (a) by a
factor of 20.
7.15 a. At 5 MHz, on clock cycle takes 0.2 µs. A transfer of one byte
therefore takes 0.6 µs.
b. The data rate is 1/(0.6 × 10Ð6) = 1.67 MB/s
c. Two wait states add an addition 0.4 µs, so that a transfer of one
byte takes 1 µs. The resulting data rate is 1 MB/s.
7.16 A DMA cycle could take as long as 0.75 µs without the need for wait
states. This corresponds to a clock period of 0.75/3 = 0.25 µs, which
in turn corresponds to a clock rate of 4 MHz. This approach would
eliminate the circuitry associated with wait state insertion and also
reduce power dissipation.
7.17 a. Telecommunications links can operate continuously, so burst mode
cannot be used, as this would tie up the bus continuously. Cycle-
stealing is needed.
b. Because all 4 links have the same data rate, they should be given
the same priority.
7.18 Only one device at a time can be serviced on a selector channel. Thus,
Maximum rate = 800 + 800 + 2 × 6.6 + 2 × 1.2 + 10 × 1 = 1625.6
kB/sec
7.19 a. The processor can only devote 5% of its time to I/O. Thus the
maximum I/O instruction execution rate is 106 × 0.05 = 50,000
instructions per second. The I/O transfer rate is therefore 25,000
words/second.
b. The number of machine cycles available for DMA control is
106(0.05 × 5 + 0.95 × 2) = 2.15 × 106
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If we assume that the DMA module can use all of these cycles, and
ignore any setup or status-checking time, then this value is the
maximum I/O transfer rate.
7.20 For each case, compute the fraction g of transmitted bits that are data
bits. Then the maximum effective data rate ER is
ER = gR
a. There are 7 data bits, 1 start bit, 1.5 stop bits, and 1 parity bit.
7
g = = 7/10.5
1 + 7 + 1 + 1.5
ER = 0.67 × R
b. Each frame contains 48 + 128 = 176 bits. The number of
characters is 128/8 = 16, and the number of data bits is 16 × 7 =
112.
112
ER= × R = 0.64 × R
176
c. Each frame contains 48 = 1024 bits. The number of characters is
1024/8 = 128, and the number of data bits is 128 × 7 = 896.
896
ER= × R = 0.84 × R
1072
d. With 9 control characters and 16 information characters, each
frame contains (9 + 16) × 8 = 200 bits. The number of data bits is
16 × 7 = 112 bits.
112
ER= × R = 0.56 × R
200
e. With 9 control characters and 128 information characters, each
frame contains
(9 + 128) × 8 = 1096 bits. The number of data bits is 128 × 7 =
896 bits.
896
ER= × R = 0.82 × R
1096
7.21 a. Assume that the women are working, or sleeping, or otherwise
engaged. The first time the alarm goes off, it alerts both that it is
time to work on apples. The next alarm signal causes apple-server
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to pick up an apple an throw it over the fence. The third alarm is a
signal to Apple-eater that he can pick up and eat the apple. The
transfer of apples is in strict synchronization with the alarm clock,
which should be set to exactly match Apple-eater's needs. This
procedure is analogous to standard synchronous transfer of data
between a device and a computer. It can be compared to an I/O
read operation on a typical bus-based system. The timing diagram
is as follows:
On the first clock signal, the port address is output to the address
bus. On the second signal, the I/O Read line is activated, causing
the selected port to place its data on the data bus. On the third
clock signal, the CPU reads the data.
A potential problem with synchronous I/O will occur if Apple-
eater's needs change. If he must eat at a slower or faster rate than
the clock rate, he will either have too many apples or too few.
b. The women agree that Apple-server will pick and throw over an
apple whenever he sees Apple-eater's flag waving. One problem
with this approach is that if Apple-eater leaves his flag up, Apple-
server will see it all the time and will inundate her friend with
apples. This problem can be avoided by giving Apple-server a flag
and providing for the following sequence:
1. Apple-eater raises her "hungry" flag when ready for an apple.
2. Apple-server sees the flag and tosses over an apple.
3. Apple-server briefly waves her "apple-sent" flag
4. Apple-eater sees the "apple-sent" flag, takes down her "hungry"
flag, and grabs the apple.
5. Apple-eater keeps her "hungry" flag stays down until she needs
another apple.
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This procedure is analogous to asynchronous I/O. Unfortunately,
Apple-server may be doing something other than watching for her
friend's flag (like sleeping!). In that case, she will not see the flag,
and Apple-eater will go hungry. One solution is to not permit apple-
server to do anything but look for her friend's flag. This is a polling,
or wait-loop, approach, which is clearly inefficient.
c. Assume that the string that goes over the fence and is tied to
Apple-server's wrist. Apple-eater can pull the string when she needs
an apple. When Apple-server feels a tug on the string, she stops
what she is doing and throws over an apple. The string corresponds
to an interrupt signal and allows Apple-server to use her time more
efficiently. Moreover, if Apple-server is doing something really
important, she can temporarily untie the string, disabling the
interrupt.
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