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Department of ECE
IV B.Tech I Semester
VLSI DESIGN
 1
UNIT IV
Subsystem Design: Architectural issues, switch logic, Gate logic, examples of
structured design, clocked sequential circuits, system considerations, general
considerations of subsystem design processes, an illustration of design
processes.
Day 30
Topics to be covered: Architectural issues, Switch logic, Gate logic
Q1. Explain the architectural issues of VLSI system design and also give
measures to solve them.
Architectural issues in VLSI system design:
In all design processes, it is very essential to follows a logical and systematic
approach, without which the whole system would become obsolete.
For instance, the designing time required by engineers to develop an MSI
logic circuit consisting of 500 transistors is two months. But when the
numbers of transistors are extended to 500,000 the designing time would be
approximately equal to 2000 engineer months or 170 engineer years, which
increases the complexity to a much a higher level. Therefore, effective
methods must be adopted which can handle these kind of architectural
complexities in reasonable period of time and minimum labor.
Measures to minimize the architecture issues:
Some of the effective measures which help in minimizing the architectural
issues are,
1) The requirements must be outlined in a proper manner.
2) The overall architectural systems should be divided into subsystems for
ease in designing.
3) The between the subsystem must be taken into considered with atmost
care such that sensible inter relationships are established.
4) A floor plan must be designed first, which enables proper mapping of
mapping of system on the silicon.
5) The focus should be on regular structures for which imprint of design
are available in advance.
6) For simplicity the leaf-cells of the subsystems must be represented as
stick or symbolic diagrams.
7) Every cell should be transformed as a layout.
8) Every cell should be vigilantly and efficiently checked for the designed
rules.
9) The performance of each and every cell/system is required to be
simulated.

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The whole procedure is required to be followed while designing a system it
can be summarized as, to obtain and clean and effective subsystems having
least interdependence and interconnection complexity, careful partitioning is
desired. For further simplification of design of a subsystem, architectures
capable of exploiting cellular design concept must be employed.
Consequently system gets composed of relativity few standard cells which on
replication produced highly regular structures.
Homework:
1) Discuss the architectural issues to the followed in the design of a VLSI
subsystems
Day 31
Topics to be covered: Switch logic, Gate logic
Q1. Explain Switch Logic?

Switch logic is based on the 'pass transistor' or on transmission gates. This

approach is fast for small arrays and takes no static current from the supply

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rails. Thus, power dissipation of such arrays is small since current only flows
on switching.
Switch (pass transistor) logic is similar to logic arrays based on relay contacts
in that the path through each switch is isolated from the signal activating the
switch. In such consequence, the designer has a considerable amount of
freedom in implementing architectural features compared with bipolar logic-
based designs.
A number of texts on switching theory, some dating from the 1950s and
1960s, have sections on relay/switch logic and the reader is referred to such
material for generating ideas for implementation in MOS switch logic. Basic
AND and OR connections are set out in Figure 6.1, but many combinations of
switches are possible.
Q2. Explain about Pass Transistors and Transmission Gates
Switches and switch logic may be formed from simple n- or p-pass transistors
or from transmission gates (complementary switches) comprising an n-pass
and a p-pass transistor in parallel as shown in Figure 6.2. The reason for
adopting the apparent complexity of the transmission gate, rather than using
a simple n-switch or p-switch in most CMOS applications, is to eliminate the
undesirable threshold voltage effects which give rise to the loss of logic levels
in pass transistors as indicated in Figure 6.2. No such degradation occurs with
the transmission gate, but more area is occupied and complementary signals
are needed to drive it. 'On' resistance, however, is lower than that of the
simple pass transistor switches.

Fig. Some properties of Pass transistors and Transmission Transistor

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When using nMOS switch logic, there is one restriction which must always be
observed: no pass transistor gate input may be driven through one or more
pass transistors. As shown, logic levels propagated through pass transistors
are degraded threshold voltage effects. Since the signal out of pass transistor
T1 does not reach a full logic 1, but rather a voltage one transistor threshold
below a true logic 1, this degraded voltage would not permit the output of T2
to reach an acceptable logic 1 level.
Important Questions:
1) Explain about Pass transistors and Transmission gate
2) Design logic diagram for 2input AND gate using Pass transistor.
Day 32
Topics to be covered: Switch logic:-Pseudo NMOS Logic, Alternate forms of
CMOS Logic
Q1. Explain Pseudo-nMOS logic
Clearly, if we replace the depletion mode pull-up transistor of the standard
nMOS circuits with a p-transistor with gate connected to Vss, we have a
structure similar to the nMOS equivalent. This approach to logic design is
illustrated by the three-input Nand gate in Figure 6.9. The circuit
arrangements look and behave much like nMOS circuits and appropriate ratio
rules must be applied.

Fig: Pseudo-nMOS Nand gate

In order to determine the required ratio, we consider the arrangement of
Figure 6.10 in which a pseudo-nMOS inverter is being driven by another
similar inverter, and we consider the conditions necessary to produce an
output voltage of Vinv for an identical input voltage. As for the nMOS analysis,
we consider the conditions for which Vinv = VDD/2.
At this point the n-device is in saturation (i.e. 0 < Vgsn - Vtn < Vdsn) and the p-
device is operating in the resistive region (i.e. 0 < Vdsp < Vgsp – Vtp). Equating

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currents of the n transistor and the p-transistor, and by suitable
rearrangement of the resultant expression,
we obtain

Where Z p . u .= Lp /w p and Z p . d .=Ln /W n

Fig: Pseudo-nMOS Inverter when driven from a similar Inverter

A transfer characteristic, Vout vs Vin can be drawn and, as for the nMOS case,
the characteristic will shift with changes of Zp.u./Zp.d. ratio.
Two points require comment:
1) Since the channel sheet resistance of the p-pull-up is about 2.5 times
that of the n-pull down, and allowing for the ratio of 3:1, the pseudo-
nMOS inverter presents a resistance between VDD and Vss which is, say,
85 kW compared with 50 kW for a comparable 4: 1 nMOS device. Thus,
power dissipation is reduced to about 60% of that associated with the
comparable nMOS device.
2) Owing to the higher pull-up resistance, the inverter pair delay is larger
by a factor of 8.5:5 than the 4:1 minimum size nMOS inverter.
Important Questions:
1) Explain about Pseudo NMOS Logic
Day 33
Topics to be covered: Switch logic:-Dynamic CMOS Logic, Alternate forms of
CMOS Logic
Q1. Explain Dynamic CMOS logic
The actual logic is implemented in the inherently faster nMOS logic (the n-
block); a p-transistor is used for the non-time-critical precharging of the
output line 'Z' so that the output capacitance is charged to VDD during the off
period of the clock signal f .

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During this same period the inputs are applied to the n-block and the state of
the logic is then evaluated during the on period of the clock when the bottom
n-transistor is turned on. Note the following:
1. Charge sharing may be problem unless the inputs are constrained not to
change during the on period of the clock.

Fig: Dynamic CMOS Logic 3 input Nand gate

2. Single phase dynamic logic structures cannot be cascaded since, owing to
circuit delays, an incorrect input to the next stage may be present when
evaluation begins, so that its output is inadvertently discharged and the
wrong output results. One remedy is to employ a four-phase clock in which
the actual signals used are the derived clocks , , , , 12 23 34 41 f f f and f as
illustrated in Figure 6.1l(b) The basic circuit of Figure 6.11(a) is modified by
the inclusion of a transmission gate as in Figure 6.11(c), the function of which

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is to sample the output during the 'evaluate' period and to hold the output
state while the next stage logic evaluates. For this strategy to work, the next
stage must operate on overlapping but later clock signals. Clearly, since there
are four different derived clock signals which are used in sequential pairs (e.g.
12 23 f and f in Figure(c), there are four different gate clocking configurations.
These configurations are usually identified by a type number which reflects
the last of the clock periods activating the gate. For example, the gate shown
would be identified as 'type 3' since the output Z is pre-charged during 2 f and
is evaluated during 3 f (the transmission gate is clocked by 23 f ). In order to
avoid erroneous evaluations.
In static circuits at every point in time (except when switching) the output is
Connected to either GND or VDD via a low resistance path. Fan-in of n
requires 2n transistors (n N-type and n P-type)
 Dynamic circuits rely on the temporary storage of signal values on the
capacitance of high impedance nodes. Requires only n+2 (n+1 N-type
and 1 P-type) transistors (can be further reduced to n+1)
nMOS logic structure with pre-charged pull up

 Pre-charge to VDD when clock is low

 Evaluate when clock is high
Dynamic Gate

Q2. What are the Conditions of Output

Once the output of a dynamic gate is discharged, it cannot be charged again
until the next pre-charge operation.
 Inputs to the gate can make at most one transition during evaluation.
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 Output can be in the high impedance state during and after evaluation
(PDN off), state is stored on CL
Q3. List Properties of Dynamic Logic
Logic function is implemented by the PDN only
Number of transistors is N + 2 (versus 2N for static complementary CMOS)
• Full swing outputs (VOL = GND and VOH =VDD)
• Sizing of the devices does not affect the logic levels (ratioless)
 Faster switching speeds
 reduced load capacitance due to smaller input capacitance (Cin)
 reduced load capacitance due to smaller output loading (Cout)
 Ideally, no Isc, so all the current provided by PDN goes into
discharging CL
 Overall power dissipation usually higher than static CMOS (mainly due
to clock)
 no static current path exists between VDD and GND
 no glitching (static CMOS has many glitches)
 higher transition probabilities
 extra load on Clk
 PDN starts to work as soon as the input signals exceed VTn,
 low noise margin (NML)
 Needs a pre-charge/evaluate clock
1. What are the advantages and disadvantages of Dynamic Logic
• Advantages
i. Fewer transistors than CMOS
ii. Smaller load capacitance – faster speed
• Disadvantages
i. Leakage
ii. Charge sharing
iii. Cannot be cascaded directly
iv. Only 0_1 transitions allowed at inputs, thus cannot be connected
to static gate directly
Important Questions:
1) Explain about dynamic Logic Gate
2) Design 3input Nand gate using dynamic CMOS logic
3) List out the Properties of Dynamic Logic gates
4) Write Advantages and Disadvantages of Dynamic CMOS logic gates
Day 34
Topics to be covered: Switch logic:-Issues in Dynamic CMOS Logic, Alternate
forms of CMOS Logic
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Q1. What are the Issues in Dynamic Logic

Issues in Dynamic Logic

Dominant component is sub threshold current

Solution:

Increase size of inverter to increase capacitance

Issues in Dynamic Design 2: Charge Sharing
Charge stored originally on CL is redistributed (shared) over CL and CA
leading to reduced robustness

Solution: Charge sharing

 Assume that the internal capacitances have been discharged
 In the pre-charge phase, the output capacitance gets charged
 During evaluation, if all the inputs are high except the bottom one, the
output capacitance gets distributed to the internal capacitance
Co
 The output voltage will drop to V DD
C o +2 C1
 This could be low enough to trigger the inverter, causing a wrong value
on the output
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Pre-charge internal nodes using a clock driven transistor (at the cost of
increased area and power)

CASCADE Problem
Since the evaluation from the first stage takes some time, the second stage
will start evaluating with the pre-charged internal value rather than the inputs

Cascading dynamic logic

Important Questions:
1. What are the Issues in Dynamic CMOS logic? How do you overcome?
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Day 35
Topics to be covered: Domino Logic, Clocked CMOS Logic
Q1. Explain Domino Logic
Cascading solution

Since the pre-charged output from the first stage is 0, it will never activate the
pull-down network in the second stage until the first stage evaluation has
completed.
CMOS domino logic
An extension to the dynamic CMOS logic discussed earlier is set out in Figure.
This modified arrangement allows for the cascading of logic structures using
only a single phase clock. This requires a static CMOS buffer in each logic gate.
The following remarks will help to place this type of logic in the scheme of
things:

1) Such logic structures can have smaller areas than conventional CMOS
logic.
2) Parasitic capacitances are smaller so that higher operating speeds are
possible.
3) Operation is free of glitches since each gate can make only one '1' to '0'
transition.
4) Only non-inverting structures are possible because of the presence of
the inverting buffer.
5) Charge distribution may be a problem and must be considered.
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Q2. Explain Clocked CMOS (C2MOS) logic
The general arrangement may be made clearer by Figure 6.12. The logic is
implemented in both n- and p-transistors in the form of a pull-up p-block and
a complementary n-block pull down structure (Figure 6.12(a)), as for the
inverter-based CMOS logic discussed earlier. However, the logic in this case is
evaluated (connected to the output) only during the on period of the clock. As
might be expected, a clocked inverter circuit forms part of this family of logic
as shown in Figure 6.12(b). Owing to the extra transistors in series with the
output, slower rise-times and fall-times can be expected.

Q3. Explain n-p CMOS logic

This is another variation of basic dynamic logic arrangement, in which the
actual logic blocks are alternately 'n' and 'p' in a cascaded structure as in
Figure 6.14. The precharge and evaluate transistors are fed from the clock f
and clockbar f alternately, and clearly the functions of the top and bottom
transistors also alternate, between precharge and evaluate.

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Other forms of CMOS logic are also possible, but this text does not attempt to
give an exhaustive treatment.
Important Questions:
1) Explain about Domino CMOS Logic
2) Explain about n-p CMOS logic
Day 36
Topics to be covered: Design Examples
Q1. Design Examples on Pass Transistors and Transmission Gates
Pass Transistors and Transmission Gates:
 Switches and switch logic realized either using simple n or p pass
transistors or from transmission gates (complementary switches)
 The transmission gates are complementary switches made up of a p-pass
transistors may suffer from parallel as shown in figure.
 Simple pass transistors may suffer from undesirable threshold voltage
effects which give rise to the loss of logic levels as indicated in Figure
below.
 For this reason, for apparently complex transmission gate is preferred to
the simple n-switch or p-switch in most CMOS applications.
 No such degradation occurs with the transmission gate, but more area is
occupied and complementary signals are needed to drive it.
 'On' resistance, however, is lower than that of the simple pass transistor
switches.
Q2. Design 2:1 MUX using transmission gates
A multiplexer or mux is a combinational circuits that selects several analog or
digital input signals and forwards the selected input into a single output line.
A multiplexer of 2n inputs has n selected lines, are used to select which input
line to send to the output.

Fig: The schematic diagram, Boolean equation and the truth table of a 2:1
multiplexer with inputs A and B, select input S and the output Z.

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Figure shows how a 4:1 MUX can be constructed out of two 2:1 MUXs.
Q3. Design a 2:1 mux using pass-transistor logic
A multiplexer can be designed using various logics. Fig.3 shows how a 2:1
MUX is implemented using a pass-transistor logic.

Fig. Design of a 2:1 MUX using pass-transistor logic

The pass-transistor logic attempts to reduce the number of transistors to
implement a logic by allowing the primary inputs to drive gate terminals as
well as source-drain terminals. The implementation of a 2:1 MUX requires 4
transistors (including the inverter required to invert S), while a
complementary CMOS implementation would require 6 transistors. The
reduced number of devices has the additional advantage of lower
capacitance.
Design a 2:1 mux using transmission gate logic
A transmission gate is an electronic element and good non mechanical relay
built with CMOS technology. It is made by parallel combination of nMOS and
pMOS transistors with the input at the gate of one transistor (C) being
complementary to the input at the gate () of the other. The symbol of a
transmission gate is shown below in fig.4.

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Fig: Symbol for transmission gate

The transmission gate acts as a bidirectional switch controlled by the gate
signal C. When C=1, both MOSFETs are on, allowing the signal to pass through
the gate. In short, A=B, if C=1. On the other hand, C=0, places both transistors
in cut-off, creating an open circuit between nodes A and B. Fig. shows the
implementation of a 2:1 MUX using transmission gate logic.

Fig: Circuit diagram of a 2:1 MUX using transmission gate logic

Here, the transmission gates select input A or B on the basis of the value of
the control signal S. When S=0, Z=A and when S=1, Z=B.
Important Questions:
1) Design 2:1 MUX using Pass transistor
2) Design 2:1 MUX using Transmission gate logic
Day 37
Topics to be covered: Examples of structured design, Clocked sequential
circuits
Q1. What are the alternate gate circuits available? (April/may-11,set-3)
There are six alternating CMOS gate circuits. They are
i. CMOS static logic iv. Pass transistor logic
ii. CMOs transmission gate v. Dynamic CMOS logic
iii. Tri-state gates vi. Domino CMOS logic
Q2. What are the drawback in CMOS logic gate
CMOS logic gates have following drawbacks
a. Increased area c. Greater delay
b. Increased capacitance d. Complexity
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Q3. Explain clocked CMOS logic, domino logic and n-p CMOS logic.
(April/may-08,set-1 Q4(a), April/may-09,set-1 Q4(a))
Clocked CMOS Logic:
 Clocked CMOS Logic is also referred as C2MOS logic.
 A pull-up p-block and complementary n-block pull-down structure
represent in n and p-transistors respectively and are used as implement
clocked CMOS logic as shown in figure (a).
 However, the logic in this case is connected to the output only during
the ON period of the clock.
 In figure(b) shows a clocked inverter circuit which also belongs to
clocked CMOS logic family
 The slower rise times and fall times can be expected due to owing of
extra transistors in series with the output.

Domino logic:
An extension to the dynamic CMOS logic referred as CMOS domino logic.
This modified arrangement allows for the cascading of logic structures using
only a single phase clock. This requires. a static CMOS buffer in each logic
gate.

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The following remarks will help to place this type of logic in the scheme of
things:
1) Such logic structures can have smaller areas than conventional CMOS
logic.
2) Parasitic capacitances are smaller so that higher operating speeds are
possible.
3) Operation is free of glitches since each gate can make only one '1' to '0'
transition.
4) Only non-inverting structures are possible because of the presence of
the inverting buffer.
5. Charge distribution may be a problem and must be considered.
n-p CMOS Logic:
 This is another variation of basic dynamic logic arrangement is called as
n- CMOS logic.
 In this, the actual logic blocks are alternately 'n' and 'p' in a cascaded
structure.
 The clock φ and clock φ’ are used alternately to fed the precharge and
evaluate transistors.
 However, the functions of top and bottom transistors also alternate
between precharge and evaluate.

Q4. In gate logic, compare the geometry aspects between two-input nMOS
NAND and CMOS NAND gates
 In NMOS NAND gate the desired overall Z P.U carefully observing the L:W
ratios of NMOS circuits.
 It is also necessary to consider the very simple circuit model of the gate
in the condition when all n pull-down transistors are the gate in the
condition when all n pull-down transistors are conducting to arrive at
the required L: W ratios for an nMOS NAND gate with n inputs.

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the output voltage Vout is the critical factor which must be near to ground to
turn off any inverter stage i.e.,
V OUT ≤ V T =0.2V DD
V DD × n Z P . D
≤ 0.2V DD
n Z P . D + Z P .U
n Z P. D
=0.2
n Z P . D +n Z P .U
Z P. D 4
Thus, nMOS NAND ratio¿ n Z =
1
P .U

Therefore, the ratio between ZP.U and the sum of all the pull-down ZP.D ‘s must
be 4:1 for an nMOS inverter case. If the above ratio must be adjusted. The
following two significant factors are revealed by the further consideration of
the NMOS NAND gate.
i. The required of NMOS NAND gate are considerably large.
ii. NMOS NAND gate delays increases with the number of added inputs.
The delayed associated with the NMOS NAND are,
τ NAND =τ INV
Where, n-number of inputs
τINV –The corresponding NMOS inverter delay.
Furthermore, the actual input(s) on which the transition takes place are
responsible for the rise time of the NMOS NAND output.
Thus, the usage of NMOS NAND gate is only where absolutely necessary and
its number of inputs is restricted.
Unlike NMOS NAND gate, CMOS NAND gate has no restrictions in the number
of inputs. It is necessary to allow of n-transistors in series forming the pull-
down, but the CMOS NAND gate has an asymmetric structure. Thus, we need
to make some adjustment of transistor geometry for obtaining the symmetry
V DD
structure and to keep the transfer characteristics symmetrical about 2

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Q5. Describe constructional features and performance characteristics of

pseudo-nMOS logic
CMOS suffers from increased area and corresponding increased capacitance
and delay, as the logic gates become more complex. For this reason, designers
developed circuits (alternate gate circuits) that can be used to supplement
the complementary type circuits. These forms are not intended to replace
CMOS but rather to be used in special purposes.
Pseudo nMOS logic is one type of alternate gate circuit that is used as a
supplement for the complementary MOS circuits.
Modified form of CMOS inverter is shown below. Here, only Q N is driven by
the input voltage while the gate of Q p is grounded and Qp acts as an active
load for QN. an advantage of pseudo NMOS over CMOS is, each must be
connected to the gate of only one transistor or alternatively, only one
additional transistor (an NMOS) will be needed for each additional gate input.
Thus the area and delay penalties arising from increased fan-in a
complementary CMOS gate will be reduced.

The inverter circuit of figure resembles other forms of nMOS logic that
consist of a driver, transistor (Q N) and a load transistor( in this case (Q P).

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hence, the pseudo nMOS
Expect for the load device, the pseudo nMOS gate circuit is identical to
the PDN of the complementary CMOS gate. For input pseudo nMOS NOR and
NAND gates shown. Observe that each requires five transistors compared to
the eight used in complementary CMOS. For N inputs, pseudo nMOS logic
gate requires (N+1) FETs. Standard n-input CMOS gates use 2N transistors.

Pseudo NMOS NOR Gate Pseudo NMOS NAND gate

Y=(A+B+C+D)’ Y=(ABCD)’
Pseudo NMOS is particularly suited for application in which the output
remains high most of the time. In such applications the static power
dissipation can be reasonably low (since the gate dissipates static power only
in the low-output state). Further, the output transistor that matter would
presumably be high-to–low ones where the propagation delay can be made
as short as necessary. A particular application of this type can be found in the
design of address decoders for memory chips and in read only memories.
Important and Previous University Questions:
1) What are the alternate gate circuits available?(April/may-11,set-3)
2) Explain clocked CMOS logic, domino logic and n-p CMOS
logic.(April/may-08,set-1 Q4(a), April/may-09,set-1 Q4(a))
3) What are the drawbacks in CMOS Logic
Day 38
Topic to be covered: Clocked sequential circuits, System considerations
Q1. Discuss the term two phase clocking?
 A two phase clock offers a great deal of freedom in sequential circuit
design if the clock period and the duration of the signals φ 1 and φ2
are correctly chosen.
 If this is the case, data is allowed to become stable before any further
transfer taken place and there is no chance of race conditions
occurring.
 Clocked circuitry is considerably easier to design than the
corresponding asynchronous sequential circuitry.
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 It is necessary to recognize the fact that φ 1 and φ2 do not be
symmetrical as shown

 for a given clock period, each clock period and its associated underlap
period can be varied if the need arises in optimizing a design
Day 39
Topic to be covered: Some general considerations, An illustration of design
processes
Q1. Some general considerations related to subsystem design process
 Lower unit cast
 Higher reliability
 Lower power dissipation
 Lower weight
 Lower volume
 Enhanced repeatability
 Possibility of reduced design/development periods
Q2. What are problems associated with VLSI design
1) How to design complex systems in a reasonable time & with reasonable
effort.
2) The nature of architectures best suited to take full advantage of VLSI
and the technology.
3) The testability of large/complex systems once implemented on silicon.
 Problem 1 & 3 are greatly reduced if two aspects of standard practices
are accepted:
a) Top-down design approach with adequate CAD tools to do the job
b) Partitioning the system sensibly
c) Aiming for simple interconnections
d) High regularity within subsystem
e) Generate and then verify each section of the design.
Devote significant portion of total chip area to test and diagnostic
facility Select architectures that allow design objectives and high regularity
in realization
Homework:
1) Mention the salient feature for subsystem design process
2) What are problems associated with VLSI design

Raghu Engineering College Dept. of ECE VLSI DESIGN Unit-IV