SRI RAMAKRISHNA ENGINEERING COLLEGE

COIMBATORE – 641 022.

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

20EC2E13 - EMBEDDED NETWORKS

: PRESENTED BY:

Dr. S. Jayanthy,
Professor, Department of ECE
 Module 1
EMBEDDED COMMUNICATION PROTOCOLS
• Embedded Networking: Introduction -
Serial/Parallel Communication - Serial
Communication Protocols - RS232 Standard -
RS 422- RS 485 - Synchronous Serial Protocols
-Serial Peripheral Interface (SPI) - Inter
Integrated Circuits (I2C) - PC Parallel Port
Programming - ISA/PCI Bus Protocols. - IrDA
protocol

8/11/2023 SREC/ECE/SJ 2
 COURSE OUTCOMES

• CO1: Explain the parallel and serial embedded

networking protocols--- PO1

TEXT BOOKS
John Catsoulis "Designing Embedded
Hardware", O'Reilly Media, Inc. Publication,
2013.
.
8/11/2023 SREC/ECE/SJ 3
 Serial/Parallel Communication
• Serial communication is common method of
transmitting data between a computer and a
peripheral device
• Serial communication transmits data one bit at a
time, sequentially, over a single communication
line to a receiver.
• Serial is also a most popular communication
protocol that is used by many devices for
instrumentation; numerous GPIB-compatible
devices also come with an RS-232 based port
8/11/2023 unit 1-S.Jayanthy 4
 Contd.
. Serial communication is used when data transfer
rates are very low or the data must be transferred
over long distances and also where the cost of
cable and synchronization difficulties make
parallel communication impractical.
• Serial communication is popular because most
computers have one or more serial ports, so no
extra hardware is needed other than a cable to
connect the instrument to the computer or two
computers together.

8/11/2023 unit 1-S.Jayanthy 5

 Serial Vs Parallel

8/11/2023 unit 1-S.Jayanthy 6

 Serial Vs Parallel
Parallel
• A parallel port sends and receives data eight bits at a time over
eight separate wires or lines. This allows data to be transferred very
quickly.
• However, the setup looks more bulky
• IEEE 488 specifications -cabling between equipment can be no
more than 20 meters total, with no more than 2 meters between
any two devices
• No need of (serializer and deserializer).

Serial
Few wires are required
A serial port sends and receives data one bit at a time, sequentially

8/11/2023 unit 1-S.Jayanthy 7

 Contd.
• Slower but it is simpler and can be used over
longer distances-as 1200 meters.
• In modern technology-achieve a higher data rate
• Serial communications have many advantages
over parallel one like:
a) Requires fewer interconnecting cables and hence
occupies less space.
b) "Cross talk" is less of an issue, because there are
fewer conductors compared to that of parallel
communication cables.
8/11/2023 unit 1-S.Jayanthy 8
 Contd.
c) Many IC s and peripheral devices have serial
interfaces.
d) Clock skew between different channels is not
an issue.
e) Cheaper to implement

8/11/2023 unit 1-S.Jayanthy 9

 Clock skew
Clock skew is a phenomenon in synchronous
circuits in which the clock signal sent from the
clock circuit arrives at different components at
different times, which can be caused by many
things, like: -
a) Wire-interconnect length,
b) Temperature variations,
c) Variation in intermediate devices,
d) Capacitive coupling,
e) Material imperfections
8/11/2023 unit 1-S.Jayanthy 10
 Asynchronous Vs Synchronous data
transmission
• Serial Communication also requires coordination
between the sender and receiver(when to start
the transmission and when to end it, when one
particular bit or byte ends and another begins,
when the receiver's capacity has been exceeded,
and so on)
• A protocol defines the specific methods of
coordinating transmission between a sender and
receiver

8/11/2023 unit 1-S.Jayanthy 11

 Contd.
• There are two ways to synchronize the two ends of the
communication namely synchronous and asynchronous
• Synchronous transmissions use an external clock, while
asynchronous transmissions are use special signals
along the transmission medium
• Asynchronous communication is the commonly
prevailing communication method in the personal
computer industry, due to the reason that it is easier to
implement and has the unique advantage that bytes
can be sent whenever they are ready, an no need to
wait for blocks of data to accumulate.

8/11/2023 unit 1-S.Jayanthy 12

 Synchronous transmission
• In synchronous transmission, the stream of data
to be transferred is encoded and sent on one line,
and a periodic pulse of voltage which is often
called the "clock" or "strobe" is put on another
line, that tells the receiver about the beginning
and the ending of each bit (or byte)
• Synchronization can also be embedded into a
signal on a single wire. In differential Manchester
encoding, each transition from a low to high or
high to low represents a logical zero

8/11/2023 unit 1-S.Jayanthy 13

 Contd.

8/11/2023 unit 1-S.Jayanthy 14

 Contd.
• The only advantage of synchronous data
transfer is the Lower overhead and thus,
greater throughput, compared to
asynchronous one.
• Disadvantages such as,
1) Slightly more complex and
2) Hardware is more expensive

8/11/2023 unit 1-S.Jayanthy 15

 Async
Disadvantage
• Is the large relative overhead, where a high proportion of
the transmitted bits are uniquely for control purposes and
thus carry no useful information.
• Adv:
• 1) Simple and doesn't require much synchronization on
both communication sides
2) The timing is not as critical as for synchronous
transmission; therefore hardware can be made cheaper.
3) Set-up is very fast, so well suited for applications where
messages are generated at irregular intervals, for example
data entry from the keyboard

8/11/2023 unit 1-S.Jayanthy 16

 Asynchronous transmission

8/11/2023 unit 1-S.Jayanthy 17

 Asynchronous serial communication

8/11/2023 unit 1-S.Jayanthy 18

 Contd.
• Each transmitted character is packaged in a
character frame that consists of a single start bit
followed by the data bits, the optional parity bit,
and the stop bit or bits
• After the stop bit, the line may remain idle
indefinitely, or another character may
immediately be started.
• The minimum stop bit length required by the
system can be larger than a "bit". In fact it can be
1.5 stop bits, or 2 stop bits
8/11/2023 unit 1-S.Jayanthy 19
 Serial Communication Protocols
• Various types of serial communication Standards:
1. RS-232
• -RS 422
2. RS-423
3. RS-485
4. USB
5. Fire Wire
6. Ethernet
7. MIDI
8. PCI Express
9. SPI & SCI
10. IIC
11. IrDA
8/11/2023 unit 1-S.Jayanthy 20
 RS-232 interface
• RS-232C is a serial communication interface
standard
• RS-232C is used for interfacing serial devices over
cable lengths of up to 25 meters and at data rates
of up to 38.4 kbps.
• You can use it to connect to other computers,
modems, and even old terminals
• With the need to transfer large amounts of data
rapidly, RS-232C is being supplanted as a
connection standard by high-speed networks,
such as Ethernet.

8/11/2023 unit 1-S.Jayanthy 21

 Contd.
• RS-232C is unbalanced, meaning that the voltage
level of a data bit being transmitted is referenced
to local ground.
• A logic high for RS-232C is a signal voltage in the
range of -5 to -15 V (typically - 12 V), and a logic
low is between +5 and +15 V (typically +12 V).
• So, just to make that clear, an RS-232C high is a
negative voltage, and a low is a positive voltage,
unlike the rest of your computer's logic
8/11/2023 SREC/ECE/SJ 22
 Contd.

8/11/2023 SREC/ECE/SJ 23
 Contd.

8/11/2023 SREC/ECE/SJ 24
 Contd.
• An RS-232C link consists of a driver and a
comparator, as shown in Fig 1

8/11/2023 SREC/ECE/SJ 25
 Contd.
• RS-232C also defines connectors and pin
assignments
• RS-232C was originally intended for
connecting Data Terminal Equipment (DTE) to
Data Communication Equipment (DCE)

Fig 2: Original use of RS232: connecting teletypes to modems

8/11/2023 SREC/ECE/SJ 26
 Contd.

DTE device connected to a computer

DCE device connected to a computer

8/11/2023 SREC/ECE/SJ 27
 Contd.
• To connect a PC to a modem, you need a DTE-DCE cable.
• To connect a PC to a terminal, you need a DTE-DTE cable.
• To connect a Sun workstation to a terminal, you need a
DCEDTE cable.
• To connect a Sun to a modem you need a DCE-DCE cable.
• To connect a Sun to another Sun, you need a DCE-DCE null
modem cable (where Rx and Tx cross over),
• To connect a Sun to a PC, you need a DCE-DTE null modem
cable.
• To connect two PCs together, you need a DTE-DTE null
modem cable

8/11/2023 SREC/ECE/SJ 28
 Contd.
• Table shows the "standard" connections for RS-
232C, for both 25-pin and 9-pin connectors.

9-pin connector

8/11/2023 SREC/ECE/SJ 29
 RS-232C signals
The RS-232C connector may be either a 25-pin or a 9-pin DB connector.

Tx refers to data being transmitted from the DTE but received by a DCE.
8/11/2023 SREC/ECE/SJ 30
 Contd.
• Data is transmitted and received on pins 2 and 3 respectively.
• Data Set Ready (DSR) is an indication from the Data Set (i.e.,
the modem) that it is on.
• Similarly, DTR indicates to the Data Set that the DTE is on.
• Data Carrier Detect (DCD) indicates that a good carrier is
being received from the remote modem.
• Pins 4 RTS (Request To Send - from the transmitting computer)
and 5 CTS (Clear To Send - from the Data set) are used to
control.
• When a station wants to transmit, it raises RTS. The modem
turns on carrier, typically waits a few milliseconds for carrier
to stabilize, and then raises CTS.
• The DTE transmits when it sees CTS up. If the CTS line is low, it
means that the receiver (DCE) is busy and not yet ready to receive
data.

8/11/2023 SREC/ECE/SJ 31
 Contd.
• To form a very simple link between a
computer and a terminal, the only signals
required are Tx, Rx, and SG.

8/11/2023 SREC/ECE/SJ 32
 Handshaking
• When two remote systems are communicating
serially, there needs to be some way to prevent
the transmitter from sending new data before the
receiver has had a chance to process the old data.
• This process is known as handshaking, or flow
control. The way it works is simple.
• After transmitting a byte (or data packet), the
transmitter will not send again until it has been
given confirmation that the receiver is ready.
• There are three forms of handshaking: hardware,
software, and none.
8/11/2023 SREC/ECE/SJ 33
 Contd.
• The no-handshaking option is obviously the simplest and is
used in situations where the transmitting system is much
slower in preparing and sending data than the receiver is in
processing.
• For example, if you had a small, embedded computer
running at 1 MHz that was feeding data into a high-speed
computer system running at 4 GHz, it would not be
unreasonable to assume that the faster machine would be
able to keep up.
• However, if the faster machine is running a certain popular
operating system (renowned for poor responsiveness to
real-time events), it may very well be the case that it may
not be able to keep up.

8/11/2023 SREC/ECE/SJ 34
 Contd.
• Hardware handshaking in RS-232C uses two
signals, RTS (Request To Send) and CTS (Clear To
Send).
• When the transmitter wishes to send, it asserts
RTS, indicating to the receiver that there is
pending data.
• The receiver asserts CTS when it is ready,
indicating to the transmitter that it may send.
• In this way, the flow of data is limited to the rate
at which it may be processed
8/11/2023 SREC/ECE/SJ 35
 Contd.
Software handshaking, also known as XON/XOFF, is
used where it is not possible to have hardware and
shaking between the transmitter and receiver, such as
when the transmission occurs over a phone line.

8/11/2023 SREC/ECE/SJ 36
 Implementing an RS-232C Interface

RS-232C interface using a MAX3222

8/11/2023 SREC/ECE/SJ 37
 Contd.
• Adding an RS-232C interface to a system is easy. Most
microcontrollers incorporate a UART within the chip, so all
that is required is an external level shifter to convert the serial
transmissions to and from RS-232C levels.
• Maxim makes a huge range of RS-232C interface chips (level
shifters). A good generic choice is the MAX3222 transceiver.
• Unlike many other level shifters, the Maxim parts can operate
from a low supply voltage, in the range of 3.0 V to 5.5 V.
• The MAX3222 consumes minimal power (1 mA in normal
operation and as low as 1 uA in shutdown mode), making it
ideal for portable and battery-powered applications.

8/11/2023 SREC/ECE/SJ 38
 Contd.
• The only external support components required in
MAX3222 are capacitors for the chip's internal charge
pumps.
• These pumps generate the +12 V and -12 V voltages
required for RS-232C transmission, and they do so
without requiring additional external voltage
regulators.
• The only remaining connections are the serial data
lines from the UART and the signals to the RS- 232C
connector. If you are implementing a minimal serial
interface, only Rx, Tx, and ground are required. RTS
and CTS are optional.

8/11/2023 SREC/ECE/SJ 39
 Contd.
• The capacitor C1 must be a minimum of 0.1 uF.
• If operating the chip at less than 3.6 V, C2, C3, and C4
can also be 0.1 uF.
• If the supply voltage is to be as high as 5.5 V, then C2,
C3, and C4 must be a minimum of 0.47 uF.
• Since these are minimum values, larger capacitors may
be used.
• However, if C1 is increased, then the remaining
capacitors must also be increased accordingly.
• C5, the decoupling capacitor for VCC, is nominally 0.1
uF. All capacitors should be as close to the appropriate
pins of the chip as possible.
8/11/2023 SREC/ECE/SJ 40
 Contd.
• The MAX3222 has two control inputs,
(shutdown) and (enable). Shutdown places
the RS-232C transmitters in high impedance,
thereby disabling them.
• This reduces the chip's current consumption
to less than 1 uA. When in shutdown mode,
the receivers are still active.
• Thus, the UART is still able to receive data
even if the MAX3222 is in low-power mode. If
is not required, just connect it directly to VCC.

8/11/2023 SREC/ECE/SJ 41
 Contd.
• Similarly, enable is used to control the receiver outputs.
• Placing enable high puts the receiver outputs into high
impedance, while the transmitter outputs are unaffected. To
enable the receivers, is asserted (pulled low).
• If disabling the receivers is not required, then tie enable to
ground to permanently activate them.
• If needed, shutdown and enable may be controlled by a
.

microcontroller's I/O lines, or by simple digital outputs using a

latch.
• The MAX3222 is sufficient to implement a minimal RS-232C
interface, using just Rx, Tx, and ground.
• It also has additional drivers to support RTS and CTS, allowing
for basic flow control.
• DCD, and RI for modem control.

SREC/ECE/SJ
8/11/2023 42
 RS-422
• RS-422 uses the difference between two lines, known
as a twisted pair or a differential pair, to represent the
logic level.
• Thus, RS-422 is a balanced transmission, or, in other
words, it is not referenced to local ground.
• Any noise or interference will affect both wires of the
twisted pair, but the difference between them will be
less affected.
• This is known as common-mode rejection. RS-422 can
therefore carry data over longer distances and at
higher rates with greater noise immunity than RS-232C.
• RS-422 can support data transmission over cable
lengths of up to 1,200 meters

8/11/2023 SREC/ECE/SJ 43
 Contd.
• Figure shows a basic RS-422 link, where a driver
(D) of one embedded system is connected to a
receiver (R) of another embedded system via a
twisted pair.
• The resistor, Rt, at receiving end of the twisted
pair is a termination resistor.
• It acts to remove signal reflections that may occur
during transmission over long distances, and it is
required.
• Rt is nominally 100-120 W..

8/11/2023 SREC/ECE/SJ 44
 Contd.

Figure shows a basic RS-422 link

RS-422 voltage levels

8/11/2023 SREC/ECE/SJ 45
 Contd.
• The voltage difference between an RS-422
twisted pair is between ±4 V and ±12 V between
the transmission lines.
• RS-422 is, to a degree, compatible with RS-232C.
• By connecting the negative side of the twisted
pair to ground, RS-422 effectively becomes an
unbalanced transmission.
• RS-422 was the serial interface found on early
Apple Macintosh computers, quietly dropped
with the coming of the iMacs.
8/11/2023 SREC/ECE/SJ 46
 Contd.
• There is a wide variety of RS-422 interface
chips available.
• Figure shows a simple RS-422 bidirectional
interface implemented using two Maxim
MAX3488s.
• The Tx and Rx pairs of each MAX3488 are
connected to UARTs within each embedded
system, just as we did with RS-232C.

8/11/2023 SREC/ECE/SJ 47
 Contd.

Bidirectional RS-422 interface

8/11/2023 SREC/ECE/SJ 48
 Contd.
• It's important to note that RS-422 specifies
only the voltages for the standard, not the
physical implementation (pinouts or
connectors).
• People using RS-422 pick whatever cable and
connectors (and pinouts!) they feel are
appropriate for their application.

8/11/2023 SREC/ECE/SJ 49
 Contd.
• Some RS-422 interface chips have an optional enable input.
• When enabled, the chip outputs and drives a transmission
onto the twisted pair.
• When disabled, the chip's output is high-impedance, and
the chip appears "invisible."
• Because of the ability of the interface chip to "disappear"
from the connection, it is possible to have multiple
interface chips (and therefore more than two embedded
systems) connected to the twisted pair.
• In this way, it is possible to extend RS-422 into a low-cost,
robust, simple network. When implemented in this fashion,
it becomes RS-485.

8/11/2023 SREC/ECE/SJ 50
 RS-485
• RS-485 is a variation on RS-422 that is
commonly used for low-cost networking and
in many industrial applications.
• It is one of the simplest and easiest networks
to implement.
• It allows multiple systems (nodes) to exchange
data over a single twisted pair

8/11/2023 SREC/ECE/SJ 51
 Contd.

RS-485 network

8/11/2023 SREC/ECE/SJ 52
 RS232 VS RS485
RS232 Communication Protocol RS-485 Communication Protocol

It is used for shorter distance and a It is used for longer distance with a higher
lesser data rate data rate

It has a maximum cable length of 50

It has a maximum cable length of 4000 feet
feet and a maximum data rate of
and a maximum data rate of 100 Kbps
20 Kbps

It lowers the noise immunity It offers higher noise immunity

It uses single-ended lines or It uses a balanced differential signalling

unbalanced signalling technique

RS-232 is used for connecting only

RS-485 is designed for multi-point systems
two devices.

8/11/2023 SREC/ECE/SJ 53
 Contd.
• RS-485 is based on a master-slave architecture.
• All transactions are initiated by the master, and a
slave will transmit only when specifically
instructed to do so.
• There are many different protocols that run over
RS-485, and often people will do their own thing
and create a protocol specific to the application
at hand.
• The interface to the RS-485 network is provided
by a transceiver, such as a Maxim MAX3483
8/11/2023 SREC/ECE/SJ 54
 Contd.

RS-485 transceiver

8/11/2023 SREC/ECE/SJ 55
 Contd.
• The MAX3483 is just an RS-422 transceiver with
enable inputs,
• On the network side, the MAX3483 has two
signal lines, A and B.
• This is the twisted pair (network cable)
attachment point.
• The MAX3483 also has Data In (DI) and Receiver
Out (RO).
• These are connected to the Tx and Rx signals of
the UART (or microcontroller), respectively.

8/11/2023 SREC/ECE/SJ 56
 Contd.
• Since it is connected to a common network on which
it must both listen and transmit, it has two control
inputs, Data Enable (DE) and Receiver Enable ( ).
• A high input to DE allows the DI input to be
transmitted on the network.
• A low input to DE disables the output of the
transmitter.
• Similarly, a low input to enables the receiver, and
network traffic is passed through to RO.
• DE and RO are normally controlled by an I/O line of
the processor.
8/11/2023 SREC/ECE/SJ 57
 Contd.
• Only one of the two—the transmitter or the
receiver—should be active at any one time. If the
transmitter is on, the receiver should be off, and
vice versa.
• The control for the transmitter is therefore the
logical opposite of the control for the receiver.
• By having DE active high and active low, a single
control line may be used for both. When it wishes
to transmit, it sends DE/ high. Upon completion
of transmission, it returns DE/ low and resumes
listening.

8/11/2023 SREC/ECE/SJ 58
 Contd.
Figure 14 shows a MAX3483 interfaced to a microcontroller in this way. The
microcontroller normally has DE/ low so that it is listening to network traffic.

Connecting a MAX3483 to a microcontroller

8/11/2023 SREC/ECE/SJ 59
 Contd.
• RS-485 may be implemented as half duplex,
where a single twisted pair is used for both
transmission and reception or full duplex, where
separate twisted pairs are used for each
direction.
• Full-duplex RS-485 is sometimes known as four-
wire mode.
• Note that for full-duplex operation, the
MAX3483s are replaced with MAX3491s that
have dual network interfaces.
8/11/2023 SREC/ECE/SJ 60
 Contd.

Half-duplex RS-485

8/11/2023 SREC/ECE/SJ 61
 Contd.

Full-duplex RS-485

8/11/2023 SREC/ECE/SJ 62
 Contd.
• These examples show four computers (nodes) connected to
an RS-485 network.
• Each RS-485 interface chip (MAX3483 or MAX3491) exists
in a separate embedded computer.
• The UART transmitter output, Tx, in each embedded system
is connected to the respective DI of each of the RS-485
interface chips.
• Similarly, RO connects to the Rx input of each UART.
• The driver of each RS-485 interface chip is enabled by
asserting DE, and, similarly,/RE reception is enabled by
asserting.
• Normally, all systems connected to the RS-485 network
have their receivers enabled and listen to the traffic.

8/11/2023 SREC/ECE/SJ 63
 Contd.
• Only when a system wishes to transmit does it enable its
driver. There are a number of formal protocols that use RS-
485 as a transmission medium, and twice as many homespun
protocols as well.
• The main problem to avoid is the possibility of two nodes of
the network transmitting at the same time.
• The simplest technique is to designate one node as a master
node and the others as slaves.
• Only the master may initiate a transmission on the network,
and a slave may only respond directly to the master, once that
master has finished.
• The number of nodes possible on the network is limited by
the driving capability of the interface chips. Normally, this
limit is 32 nodes per network,
8/11/2023
but some chips can support up
SREC/ECE/SJ 64
to 512 nodes
 Contd.
• - Synchronous Serial Protocols
• -Serial Peripheral Interface (SPI)
• - Inter Integrated Circuits (I2C)

8/11/2023 SREC/ECE/SJ 65
 Serial peripheral interface
• The Serial Peripheral Interface (SPI or 4 wire I/F)
was developed by Motorola to provide a low-cost
and simple interface between microcontrollers
and peripheral chips.
• It can be used to interface to memory, analog-
digital converters, digital-analog converters, real-
time clock calendars, LCD drivers, sensors, audio
chips, SD Cards and even other processors.
• Typical bus speeds are in the 50 MHz range. For a
50 MHz SPI line, the throughput is 50 Mbps.
• 10-100 Mbps is common
8/11/2023 SREC/ECE/SJ 66
 Contd.
Only limited by number of pins available for SS lines on master

8/11/2023 SREC/ECE/SJ 67
 Contd.
• SPI is a synchronous protocol in which all
transmissions are referenced to a common
clock, generated by the master.
• The receiving peripheral (slave) uses the clock
to synchronize its acquisition of the serial bit
stream.
• A master selects a slave to receive by asserting
the slave's chip select input.

8/11/2023 SREC/ECE/SJ 68
 Contd.
• SPI uses four main signals: Master Out Slave In
(MOSI), Master In Slave Out (MISO), Serial Clock
(SCLK or SCK) and Chip Select ( ) for the peripheral.
• MOSI is generated by the master and is received by
the slave. MOSI can also labeled simply as Serial In
(SI) or Serial Data In (SDI).
• MISO is produced by the slave, but its generation is
controlled by the master. MISO is sometimes known
as Serial Out (SO) or Serial Data Out (SDO).

8/11/2023 SREC/ECE/SJ 69
 Contd.

A microprocessor interfaced to a peripheral using SPI.

8/11/2023 SREC/ECE/SJ 70
 Contd.
• Both masters and slaves contain a serial shift
register.
• The master starts a transfer of a byte by
writing it to its SPI shift register.
• As the register transmits the byte to the slave
on the MOSI signal line, the slave transfers the
contents of its shift register back to the master
on the MISO signal line---Figure 2

8/11/2023 SREC/ECE/SJ 71
 Contd.

Figure 2

8/11/2023 SREC/ECE/SJ 72
 Contd.
• The contents of the two shift registers are
exchanged.
• Both a write and a read operation are
performed with the slave simultaneously.

8/11/2023 SREC/ECE/SJ 73
 Contd.
• Some peripherals can handle multiple byte
transfers, where a continuous stream of data is
shifted from the master.
• With this type of transfer, the chip select for the
SPI slave must remain low for the entire duration
of the transmission.
• For example, a memory chip might expect a
"write" command to be followed by four address
bytes (starting address), then the data bytes to be
stored.
8/11/2023 SREC/ECE/SJ 74
 Contd.
• SPI can be daisy chained as shown BELOW

8/11/2023 SREC/ECE/SJ 75
 Contd.
• SPI has four modes of operation, depending
on clock polarity and clock phase
• The two clock phases are known as clock
phase zero(first edge) and clock phase
one(second edge).
• For clock phase zero, MOSI and MISO outputs
are valid on the rising edge of the clock (SCK)
if the clock polarity is low.

8/11/2023 SREC/ECE/SJ 76
 Contd.

8/11/2023 SREC/ECE/SJ 77
 Contd.
• If the clock polarity is high, these outputs are
valid on the falling edge of SCK, for clock
phase zero.

8/11/2023 SREC/ECE/SJ 78
 Contd.
• For clock phase one, the opposite is true.
MOSI and MISO are valid on the falling edge
of the clock if clock polarity is low (Figure 6).
They are valid on the rising edge of the clock if
the clock polarity is high(Figure 7)

8/11/2023 SREC/ECE/SJ 79
 Contd.

8/11/2023 SREC/ECE/SJ 80
 Contd.

8/11/2023 SREC/ECE/SJ 81
 SPI-Based Clock/Calendar
• In this, processor is I/F with a clock/calendar chip.
• Such chips contain an oscillator module driven by
a crystal.
• The oscillator module ticks over internal counters
that track milliseconds, seconds, minutes, hours,
days, months, and years.
• They are specifically designed to provide accurate
timekeeping, and many have additional functions
such as an "alarm“ and a watchdog.
8/11/2023 SREC/ECE/SJ 82
 Contd.
• The Maxim DS1305 Real-Time Clock (RTC) provides
timekeeping services and tracks seconds, minutes,
hours, day of the month, month, day of the week, and
year.
• It knows which months have 30 days and which have
31.
• It even automatically adjusts for leap years, up to the
year 2100.
• It can generate two interrupts to the microcontroller
for time-of-day alarms.
• These alarms can be used to trigger a regular system
event, such as a backup or user notification.

8/11/2023 SREC/ECE/SJ 83
 Contd.
• The DS1305 can run off two separate power
sources and supports battery backup of its
internal state.
• The chip can use a power supply in the range
of 2 V to 5.5 V.
• It also has 96 bytes of static RAM, used for
parameter storage

8/11/2023 SREC/ECE/SJ 84
 Contd.
• The RAM, like the timekeeping function, is battery-backed,
and so its contents will be retained for the life of the battery.
• It has three power-supply inputs--VCC1, VCC2, and VBAT--
from which it can choose to draw power.
• VCC1 is the primary supply input and is connected directly to
the system's power supply.
• When the computer is up and running, the DS1305 draws its
current from this source.
• VCC2 is the secondary power source, and this can be a
rechargeable battery.
• VBAT is the third power source and is for non-rechargeable
batteries.
8/11/2023 SREC/ECE/SJ 85
 Contd.
• Figure 8 shows the DS1305 powered by a primary
DC supply connected to VCC1 and a secondary,
nonrechargeable battery connected to VBAT.

8/11/2023 SREC/ECE/SJ 86
 Contd.
If the secondary power source is a rechargeable battery,
then the DS1305 may be wired as shown in Figure 9. When
using a rechargeable battery on VCC2, VBAT must be
connected to GND

8/11/2023 SREC/ECE/SJ 87
 Contd.
• The DS1305 may be used with only a battery as its primary
power source and no backup power supply. This is shown in
Figure 10. For this configuration, both VCC1 and VBAT are
connected to ground, while the battery is connected to VCC2.

8/11/2023 SREC/ECE/SJ 88
 DS1305 RTC I/F to a microcontroller

8/11/2023 SREC/ECE/SJ 89
 Contd.
• The serial interface of the DS1305 can operate as either a
SPI port or a three-wire port.
• The input SERMODE (SERial MODE) selects which serial
mode to use.
• Connecting SERMODE to the power supply selects SPI
operation. Connecting SERMODE to GND selects three-
wire operation.
• CE (Chip Enable) is active-high.
• Therefore, the processor's I/O line driving CE must be low
when the device is not selected and high when the device is
selected.
8/11/2023 SREC/ECE/SJ 90
 Contd.
• The DS1305 has a special Power Fail ( ) output that is
asserted low when the primary power source VCC1
falls below the secondary power source (VCC2 or
VBAT). This can be used to alert the processor of the
power fail.
• The input VCCif (VCC for the interface logic) selects
the output voltage levels of SDO and PF.
• Since the DS1305 can be used in both 5 V and 3.3 V
systems, this input allows the output levels of these
pins to be set to the appropriate high voltage.

8/11/2023 SREC/ECE/SJ 91
 Contd.
• VCCif is just connected to the system's power supply.
Thus, for a 5 V system, VCCif is 5 V, and the outputs of the
DS1305 are also 5 V.
• Similarly, for a 3.3 V system, VCCif is 3.3 V and so are the
outputs.
• DS1305 has two interrupt outputs: INTO &INT1. These
may be used to interrupt the processor when a DS1305
alarm function triggers.
• The DS1305 has two crystal inputs, X1 and X2. A 32.768
kHz watch crystal is connected across these pins, providing
the timing source for the internal clock.

8/11/2023 SREC/ECE/SJ 92
 SPI-Based Digital Potentiometer
• Digital Potentiometer-Microprocessor is made
to adjust the pots.
• Examples: Televisions, computer monitors,
and stereos with internal embedded
controllers use digital pots to adjust settings
such as volume.

8/11/2023 SREC/ECE/SJ 93
 Contd.

8/11/2023 SREC/ECE/SJ 94
 Contd.
• Figure shows an Analog Devices AD5203 digital
potentiometer with a SPI interface.
• This chip has four potentiometers, all of which
may be adjusted under software control.
• Each pot has 64 possible positions, and versions
of the chip are available with either 10 k or 100 k
impedances.
• For higher resolution, the pin-compatible AD8403
has a possible 256 settings, also configurable
through a SPI interface.
8/11/2023 SREC/ECE/SJ 95
 Contd.
• The AD5203 has a Serial Data Input (SDI), which is
connected to the processor's MOSI output.
• Similarly, the device's Serial Data Output (SDO) is
connected to MISO.
• The AD5203's clock input (CLK) is positive-edge
triggered midway through each SPI cycle, which
means that any processor communicating with it
must use high clock polarity and clock phase one on
SCLK.
• The Chip Select () of the AD5203 may be driven by a
processor digital I/O line.

8/11/2023 SREC/ECE/SJ 96
 Contd.
• The AD5203 has two other inputs, Shutdown (
) and Reset ( ).SHDN places the device in low-
power mode, and RS resets the potentiometer
wipers to their midpoint.
• Both of these inputs may also be driven by a
processor I/O line, or, if their functionality is
not needed, they may be simply tied high
using 10 kW pull-up resistors.

8/11/2023 SREC/ECE/SJ 97
 Contd.
• The A and B terminals connect to either end of the
internal resistors, and the position of the wiper (W) is
adjusted under software control.
• The AD5203 has several ground connections. DGND
is the digital ground for the SPI interface and control
logic of the chip.
• The AGNDs are the analog grounds of the internal
potentiometers, and they should all be connected to
DGND at a single point.

8/11/2023 SREC/ECE/SJ 98
 Adding Nonvolatile Data Memory
with SPI
• Increase the storage capacity of embedded
system by adding an Atmel AT45DB161 2M
serial DataFlash using SPI.
• These chips are commonly used in low-cost
digital cameras and answering machines.
• Can also be used as a virtual disk drive in your
embedded system.

8/11/2023 SREC/ECE/SJ 99
 Contd.
• AT45DB161 has a serial interface, making it well
suited for use with small microcontrollers.
• The chip consists of an array of flash memory,
organized as individual pages of 528 bytes each,
and two RAM buffers, also 528 bytes each.
• To write data into the main flash array, the
processor must first write data into one of the
buffers and then issue a command to write that
buffer into the array.
8/11/2023 SREC/ECE/SJ 100
 Contd.
• A processor can read the contents of either of the
buffers, transfer a flash page to the buffers, or read
from the flash array directly.
• The operation of the buffers is independent, and one
buffer may be accessed by the processor (via SPI)
while the contents of the other buffer are being
written into the flash array.
• The flash supports numerous commands for writing
to and reading from the buffers, writing the buffers
to the main array, and transferring an array page
back to a buffer
8/11/2023 SREC/ECE/SJ 101
 Contd.

8/11/2023 SREC/ECE/SJ 102

 Contd.
• From fig 13,it is noted that 528-byte page of
the flash array is not contiguous with the next.
It is pages of 528 bytes with big gaps and it
has a lifetime of only 1,000 write cycles per
page.
• The chip will read existing data back correctly,
but new pages will not write successfully once
exceeded.

8/11/2023 SREC/ECE/SJ 103

 Contd.

8/11/2023 SREC/ECE/SJ 104

 Contd.
• In fig 14,On the left of the chip are the SPI interface connections,
MOSI, MISO, SCK, and a chip select (FLASH).
• The chip will support SPI transfers at up to 20 MHz, so the SPI
interface can be run very fast indeed.
• On the right of the chip is the power supply, VDD, which is
decoupled to ground using a 100 nF capacitor.
• The AT45DB161 requires a power supply in the range 2.5 V to 3.6
V. However, its logic inputs are 5 V tolerant, meaning this chip
can be used in systems with mixed power supplies.
• The AT45DB161 has a write-protect pin ( ), which, when driven
low, prevents the contents of the flash from being modified.
• The flash also has a RESET input so that the chip can be
manually reset under software control.
8/11/2023 SREC/ECE/SJ 105
 Contd.
• Pin 1 is a status output (RDY/BUSY) indicating
whether the device is ready or if it is still
completing an internal operation
• Figure 15 shows the interfacing data flash with
microcontroller through SPI.
• Fig shows decoupling capacitors for the power
supplies, the crystal oscillator for the
processor, and a pull-up resistor for RESET.

8/11/2023 SREC/ECE/SJ 106

 A 2M DataFlash I/F to an AT90S4434

8/11/2023 SREC/ECE/SJ 107

 Adding a Parameter Memory Using
SPI
• Use SPI to add a small parameter memory (in
the form on an EEPROM) to embedded
system.
• One million write cycles.
• Hold data for at least 100 years without
power.
• AT25640 has 8K of memory.

8/11/2023 SREC/ECE/SJ 108

 Contd.

8/11/2023 SREC/ECE/SJ 109

 Contd.
• The interface is standard SPI, and the chip also has a
write-protect input and a hold input. Asserting HOLD
allows the processor to temporarily stall a serial transfer
without terminating the access to the AT25640.
• Write-protect, when asserted, turns the chip into a read-
only device.
• These control inputs may be driven by programmable I/O
lines of the processor.
• 2.7 V to 5.5 V,
• 1.8 to 3.6V

8/11/2023 SREC/ECE/SJ 110

 Overview of I2C
• I2C (Inter-Integrated Circuit) bus is a very
cheap yet effective network used to
interconnect peripheral devices within small-
scale embedded systems.
• It is sometimes also known as IIC and has
been in existence for more than 20 years.
• Philips Semiconductors (now known as NXP
Semiconductors) created the I2C specification.

8/11/2023 SREC/ECE/SJ 111

 Contd.
112 devices can be connected with 7-bit addressing. Of 128
addresses -16 addresses are reserved.

8/11/2023 SREC/ECE/SJ 112

 Contd.
• I2C uses two wires to connect multiple devices in a
multi-drop bus.
• The bus is bidirectional, low speed, and synchronous to
a common clock.
• Devices may be attached or detached from the I2C bus
without affecting other devices.
• Several manufacturers, such as Microchip, Philips,
Intel, and others produce small microcontrollers with
I2C built in.
• The data rate of I2C is somewhat slower than SPI, at
100 kbps in standard mode, and 400 kbps in fast
mode(3.4 Mbps is possible with high-speed mode).

8/11/2023 SREC/ECE/SJ 113

 Contd.
• The two wires used to interconnect with I2C are SDA
(serial data) and SCL (serial clock).
• Both lines are open-drain.
• They are connected to a positive supply via a pull-up
resistor and therefore remain high when not in use.
• A device using the I2C bus to communicate drives the
lines low or leaves them pulled high as appropriate.
• Each device connected to the I2C bus has a unique
address and can operate as either a transmitter (a bus
master), a receiver (a bus slave), or both.
• I2C is a multi-master bus, meaning that more than one
device may assume the role of bus master.
8/11/2023 SREC/ECE/SJ 114
 Contd.

8/11/2023 SREC/ECE/SJ 115

 Contd.
• Both SDA and SCL are bidirectional.
• I2C shares the same signal line for master transmission and
slave response.
• I2C does not have several modes of operation.
• When idle, both SDA and SCL are high.
• An I2C transaction begins with SDA going low, followed by SCL
(Figure 2). This indicates to all receivers on the bus that a
packet transmission is commencing.
• While SCL is low, SDA transitions (high or low) for the first
valid data bit. This is known as a "START condition

8/11/2023 SREC/ECE/SJ 116

 Contd.

8/11/2023 SREC/ECE/SJ 117

 Contd.
• For each bit that is transmitted, the bit must become
valid on SDA while SCL is low.
• The bit is sampled on the rising edge of SCL and must
remain valid until SCL goes low once more.(Fig 3)
• Then SDA transitions to the next bit before SCL goes
high once more
• Finally, the transaction completes by SCL returning
high (inactive) followed by SDA (Figure 4).
• This is known as a "STOP condition.

8/11/2023 SREC/ECE/SJ 118

 Contd.

8/11/2023 SREC/ECE/SJ 119

 Contd.
• Any number of bytes may be transmitted in an I2C packet.
• If the receiver is unable to accept any more bytes, it can abort
the transmission by holding SCL low. This forces the
transmitter to wait until SCL is released again.
• Each byte transmitted must be acknowledged by the receiver.
Upon the transmission of the eighth data bit, the master
releases the data line SDA. The master then generates an
additional clock pulse on SCL. This triggers the receiver to
acknowledge the byte by pulling SDA low (Figure 5).

8/11/2023 SREC/ECE/SJ 120

 Contd.

8/11/2023 SREC/ECE/SJ 121

 Contd.
• I2C is a multi-master bus. So, more than one master
may attempt to start transmission at the same time.
• Since the bus's default state is high, a master
transmitting a 0 bit will pull SDA low but will leave the
bus in its default state if the bit is to be a 1.
• Thus, if two masters begin simultaneous transmission,
a master leaving the bus in its default state for a 1 bit,
but detecting the bus pulled low by another master
(for a 0 bit), will register an error condition and abort
the transmission.

8/11/2023 SREC/ECE/SJ 122

 Contd.
• Each device on the bus has a unique address, and the
packet transmission begins with address bits, followed
by the data.
• An address byte consists of seven address bits,
followed by a direction bit.
• If the direction bit is a 0, the transmission is a write
cycle and the selected slave will accept the data as
input.
• If the direction bit is a 1, then the request is for the
slave to transfer data back to the master.
• A sample packet, transferring one byte of data, is
shown in Figure 6.

8/11/2023 SREC/ECE/SJ 123

 Contd.

8/11/2023 SREC/ECE/SJ 124

 Contd.
• There is a special address, known as the general call
address, which broadcasts to all I2C devices.
• This address is %0000000 with a direction bit of 0.(% a
prefix indicating binary format; also known as Motorola
convention)
• The general call is the mechanism by which the master
determines what slaves are available, and there are several
types of general call.
• The second byte of a general call indicates the purpose of
the general call to the slaves.
• Upon receiving the second byte, individual slaves will
determine whether the command is applicable to them,
and, if so, they will acknowledge

8/11/2023 SREC/ECE/SJ 125

 Contd.
• If the command is not applicable to a given slave,
then the slave simply ignores the general call and
does not acknowledge.
• If the second byte is 0x06 (%00000110), then this
indicates that appropriate slaves should reset and
respond with their addresses.
• If the second byte is 0x04 (%00000100), slaves
respond with their addresses but do not reset.
• Any other second byte of a general call, where the
least significant bit is a 0, should be ignored

8/11/2023 SREC/ECE/SJ 126

 Contd.
• If the least significant bit of the second byte is a 1,
then the general call is by a master device identifying
itself to other masters in the system by transmitting
its own address.
• The other bits of the second byte contain the
master's address.

8/11/2023 SREC/ECE/SJ 127

 Contd.
• I2C also supports an extended 10-bit addressing mode,
allowing up to 1,024 peripherals.
• Devices that use 7-bit addressing may be mixed with
10-bit addressing devices in a single system.
• In 10-bit addressing, two bytes are used to hold the
address.
• If the (first) address byte begins with %11110XX, then a
10-bit address is being generated.
• The two least significant bits of the first byte,
combined with the eight bits of the second byte, form
the 10-bit address (Figure 7).
• 7-bit devices will ignore the transaction.
8/11/2023 SREC/ECE/SJ 128
 Contd.

8/11/2023 SREC/ECE/SJ 129

 Adding a Real-Time Clock with I2C
• Philips PCF8583.
• It also has 240 bytes of RAM, may be used for
parameter storage.
• It does not have an integrated battery-backup
system.
• An external battery-backup circuit is needed.

8/11/2023 SREC/ECE/SJ 130

 Contd.
• The PCF8583 has two pins (OSCI and OSCO) for
connecting a 32.768 kHz watch crystal.
• This crystal pulses an internal circuit that performs the
timekeeping functions.
• The address pin, A0, determines the address of the
device on the I2C bus.
• The PCF8583 has only one address pin, to reduce the
pin count of the chip.
• Six of its address bits are hardwired internally. Only the
least significant, A0, is available to the system designer.
The address configuration of the PCF8583 is shown in
Figure8.

8/11/2023 SREC/ECE/SJ 131

 Contd.

If A0=0,1010000 =50H;A0=1,1010001=51H;

8/11/2023 SREC/ECE/SJ 132

 Contd.
• Connecting A0 directly to ground sets that
address bit to 0 and therefore maps the
PCF8583 to I2C address 0x50.
• Alternatively, if A0 is tied to VDD, then the
address of the device is 0x51.
• The schematic for interfacing the PCF8583 to a
microcontroller is shown in Figure 9.

8/11/2023 SREC/ECE/SJ 133

 Contd.

8/11/2023 SREC/ECE/SJ 134

 Contd.
• SDA and SCL both require pull-up resistors to
VDD.
• The PCF8583 also has an internal alarm
function and asserts an output (INT) for
interrupting the processor.
• Since this output is open-drain, a pull-up
resistor is also required.

8/11/2023 SREC/ECE/SJ 135

 Adding a Small Display with I2C
• VFD2041. This display module is 80 characters
wide by 4 lines deep.
• The interface circuit is shown in Figure 10.
• The types of LCDs found in laptops are
considerably more complicated, and
interfacing them to small processors is just not
an option.
• But for simple message displays a circuit like
this is ideal.
8/11/2023 SREC/ECE/SJ 136
 Contd.

8/11/2023 SREC/ECE/SJ 137

ISA bus
 Introduction
• Since about 1984, standard bus for PC I/O
functions has been named ISA (Industry
Standard Architecture).
• Designed to connect peripheral cards to
the motherboard.
• It is still used in all PCs to maintain backwards
compatibility.
• In that way modern PCs can accept expansion
cards of the old ISA type.
8/11/2023 isa 139
 Contd.

8/11/2023 isa 140

 Contd.
• IBM's trademark is AT bus. Usually, it is just
referred to as ISA bus.
• ISA is 16 bit wide and runs at a maximum of 8
MHz.
• However, it requires 2-3 clock ticks to move 16
bits of data.
• The ISA bus works synchronous with the CPU

8/11/2023 isa 141

8/11/2023 SREC/ECE/SJ 142
8/11/2023 SREC/ECE/SJ 143
 Contd.
• SA19 to SA0 (SA for System Address) System Address bits 19:0
are used to address memory and I/O devices within the
system.
• These signals may be used along with LA23 to LA17 to address
up to 16 megabytes of memory.
• Only the lower 16 bits are used during I/O operations to
address up to 64K I/O locations. SA19 is the most significant
bit. SA0 is the least significant bit.
• These signals are gated on the system bus when BALE is high
and are latched on the falling edge of BALE. They remain valid
throughout a read or write command.

8/11/2023 isa 144

 Contd.

• LA23 to LA17- Unlatched Address bits 23:17

are used to address memory within the
system. They are used along with SA19 to SA0
to address up to 16 megabytes of memory.
• These signals are valid when BALE is high.

8/11/2023 isa 145

 Contd.
• AEN Address Enable is used to degate the
system microprocessor and other devices
from the bus during DMA transfers.
• When this signal is active the system DMA
controller has control of the address, data,
and read/write signals

8/11/2023 isa 146

 Contd.
• BALE Buffered Address Latch Enable is used to
latch the LA23 to LA17 signals or decodes of
these signals.
• Addresses are latched on the falling edge of
BALE.
• It is forced high during DMA cycles. When
used with AEN, it indicates a valid
microprocessor or DMA address.

8/11/2023 isa 147

 Contd.
• CLK System Clock is a free running clock
typically in the 8MHz to 10MHz range,
although its exact frequency is not
guaranteed.
• It is used in some ISA board applications to
allow synchronization with the system
microprocessor.

8/11/2023 isa 148

 Contd.
• SD15 to SD0 System Data serves as the data bus
bits for devices on the ISA bus.
• SD15 is the most significant bit. SD0 is the least
significant bits. SD7 to SD0 are used for transfer
of data with 8-bit devices.
• SD15 to SD0 are used for transfer of data with 16-
bit devices.
• 16-bit devices transferring data with 8-bit devices
shall convert the transfer into two 8-bit cycles
using SD7 to SD0.
8/11/2023 isa 149
 Contd.
• DACK0 to DACK3 and DACK5 to DACK7 DMA
Acknowledge 0 to 3 and 5 to 7 are used to
acknowledge DMA requests on DRQ0 to DRQ3 and
DRQ5 to DRQ7.
• DRQ0 to DRQ3 and DRQ5 to DRQ7 DMA Requests are
used by ISA boards to request service from the system
DMA controller or to request ownership of the bus as a
bus master device.
• These signals may be asserted asynchronously.
• The requesting device must hold the request signal
active until the system board asserts the corresponding
DACK signal.

8/11/2023 isa 150

 Contd.
• I/O CH CK I/O Channel Check signal may be activated
by ISA boards to request an non-maskable interrupt
(NMI) be generated to the system microprocessor.
• It is driven active to indicate a uncorrectable error has
been detected.
• I/O CH RDY I/O Channel Ready allow slower ISA boards
to lengthen I/O or memory cycles by inserting wait
states.
• This signals normal state is active high (ready). ISA
boards drive the signal inactive low (not ready) to
insert wait states.

8/11/2023 isa 151

 Contd.
• IOR I/O Read is driven by the owner of the bus
and instructs the selected I/O device to drive
read data onto the data bus.
• IOW I/O Write is driven by the owner of the
bus and instructs the selected I/O device to
capture the write data on the data bus.

8/11/2023 isa 152

 Contd.
• IRQ3 to IRQ7 and IRQ9 to IRQ12 and IRQ14 to
IRQ15 Interrupt Requests are used to signal
the system microprocessor that an ISA board
requires attention.
• An interrupt request is generated when an IRQ
line is raised from low to high.
• The line must be held high until the
microprocessor acknowledges the request
through its interrupt service routine

8/11/2023 isa 153

 Contd.
• SMEMW, SMEMR System Memory Write/Read
instructs a selected memory device to
store/LOAD the data currently on the data bus.(1
Mbyte of memory)
• MEMR Memory Read instructs a selected
memory device to drive data onto the data bus. It
is active on all memory read cycles.( 16MB)
• MEMW Memory Write instructs a selected
memory device to store the data currently on the
data bus. It is active on all memory write cycles.
8/11/2023 isa 154
 Contd.
• REFRESH Memory Refresh is driven low to
indicate a memory refresh operation is in
progress.
• OSC Oscillator is a clock with a 70ns period
(14.31818 MHz).
• This signal is not synchronous with the system
clock (CLK).
• RESET DRV Reset Drive is driven high to reset or
initialize system logic upon power up or
subsequent system reset.
8/11/2023 isa 155
 Contd.
• TC Terminal Count provides a pulse to signal a terminal
count has been reached on a DMA channel operation.
• MASTER Master is used by an ISA board along with a
DRQ line to gain ownership of the ISA bus. Upon
receiving a -DACK a device can pull -MASTER low which
will allow it to control the system address, data, and
control lines.
• After MASTER is low, the device should wait one CLK
period before driving the address and data lines, and
two clock periods before issuing a read or write
command.

8/11/2023 isa 156

 Contd.
• MEM CS16 Memory Chip Select 16 is driven
low by a memory slave device to indicate it is
capable of performing a 16-bit memory data
transfer.
• I/O CS16 I/O Chip Select 16 is driven low by a
I/O slave device to indicate it is capable of
performing a 16-bit I/O data transfer.

8/11/2023 isa 157

 Contd.
• 0WS Zero Wait State is driven low by a bus
slave device to indicate it is capable of
performing a bus cycle without inserting any
additional wait states.
• SBHE System Byte High Enable is driven low to
indicate a transfer of data on the high half of
the data bus (D15 to D8).

8/11/2023 isa 158

 Contd.
• If the system bus is faster than 10 MHz, many
expansion boards become flaky and the ISA
clock frequency is reduced to a fraction of the
system bus clock frequency.
• The ISA bus has an theoretical transmission
capacity of about 8 MBps.
• However, the actual speed does not exceed 1-
2 MBps, and it soon became too slow.

8/11/2023 isa 159

 Contd.
• The ISA bus has two "faces" in the modern PC:
 The internal ISA bus, which is used on the
simple ports, like keyboard, diskette drive,
serial and parallel ports.
 As external expansion bus, which can be
connected with 16 bit ISA adapters.

8/11/2023 isa 160

 Contd.
• ISA slots are today mostly used for the
common 16 bit SoundBlaster compatible
sound cards.

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 Contd.

8/11/2023 isa 162

 Contd.
• Problems
• The problem with the ISA bus is twofold:
• It is narrow and slow.
• It has no intelligence.

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 Contd.
• The ISA bus cannot transfer enough bits at a
time. It has a very limited bandwidth

Bus Transmission time Data volume per transmission

ISA 375 ns 16 bit

PCI 30 ns 32 bit

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 Contd.
• The ISA bus uses a lot of time for every data transfer,
and it only moves 16 bits in one operation.
• The other problem with the ISA bus is the lack of
intelligence. This means that the CPU has to control the
data transfer across the bus. The CPU cannot start a
new assignment, until the transfer is completed.
• You can observe that, when your PC communicates
with the floppy drive, while the rest of the PC is
waiting.
• Quite often the whole PC seems to be sleeping.
• That is the result of a slow and unintelligent ISA bus.
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 Contd.
• The ISA bus can be a tease, when you install
new expansion cards (for example a sound
card). Many of these problems derive from
the tuning of IRQ and DMA, which must be
done manually on the old ISA bus.
• Every component occupies a specific IRQ and
possibly a DMA channel. That can create
conflict with existing components

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 Contd.
• As described, the ISA bus is quite outdated
and should not be used in modern PCs. There
is a good chance, that this "outdated legacy
technology" (quoting Intel) will disappear
completely

8/11/2023 isa 167

PCI
 Introduction
• A set of parallel conductors, which allow
devices attached to it to communicate with
the CPU.
• The bus consists of three main parts: Control
lines, Address lines , Data lines

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 Peripheral Component Interconnect

8/11/2023 pci 170

 PCI General Block Diagram

8/11/2023 pci 171

 Contd.

8/11/2023 pci 172

 Contd.
Conventional PCI
• Plug-and-Play Functionality
• Standard PCI is 32 bit and operates at 33 MHz
• Throughput 133 MB/sec
PCI 2.1 introduced
• Universal PCI cards supporting both 3.3V and 5V
• 64 Bit slots and 66 MHz capability
• 32-Bit throughput @ 66 MHz: 266 MB/sec
• 64-Bit throughput @ 66 MHz: 532 MB/sec

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 Contd.
PCI-X 1.0
• Based on existing PCI architecture
• 64-Bit slots with support for 3.3V
• No support for 5V-only boards!
• Fully backwards-compatible

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 Contd.
PCI-X 2.0
• Based on PCI-X 1.0
• Still fully backwards-compatible
• Introduces ECC (Error Correction Codes
mechanism to improve robustness and data
integrity)
Provides two additional speed grades
• PCI-X 266: 266 MHz (2.13 GB/sec)
• PCI-X 533: 533 MHz (4.26 GB/sec)
• 10 Gigabit Ethernet / Fiber Channel
8/11/2023 pci 175
 Contd.
PCI Express
• High-speed point-to-point architecture that is essentially a
serialized, packetized version of PCI
• General purpose serial I/O bus for chip-to-chip
communication, USB 2.0 / IEEE 1349b interconnects, and
high-end graphics
• With PCIe, data is transferred over two signal pairs: two wires
for transmitting and two wires for receiving. Each set of signal
pairs is called a "lane," and each lane is capable of sending
and receiving eight-bit data packets simultaneously between
two points.
• Bandwidth 4 Gigabit/second full duplex per lane
• Up to 32 separate lanes ,Total:128 Gigabit/second
• Software-compatible with PCI device driver model
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 PCI Interface Signals

8/11/2023 pci 177

 Contd.
PCI System Signals
• CLK : clean signal derived from the clock
generator (33MHz , 66MHz)
• RST : Active Low Asynchronous reset
• PAR : Parity Signal to ensure the parity across
the AD bus and C/BE.

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 Contd.
PCI Bus Protocol - Signal Definition
• AD- Multiplexed address and data lines
• C/BE - Command and Byte Enables
• FRAME - Master indicating start/end of transfer
• IRDY - Master (initiator) ready
• TRDY - Target ready
• DEVSEL - Target device selected
• REQ - Request indicates to the arbiter that this agent
desires use ofthe bus
• GNT - Bus Grant-indicates to the agent that access to
the bus has been granted.

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 Contd.
• STOP [I/0]: Stop indicates the current target is
requesting the master to stop the current
transaction.
• IDSEL [I]: Initialization Device Select is used as a
chip select during configuration read and write
transactions.
• LOCK [I/0] : During semaphore currently accessed
target locked by initiator
• DEVSEL [I/0] :Asserted by target when the target
asserts has decoded its address.
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 Contd.
PCI Configuration Register
• Device ID: This field identifies the particular
device
• Vendor ID: This field identifies the manufacturer
of the device
• Status / Command regs.
• Base Address Registers [0,1,2,3,4,5]
• Maximum Latency
• Minimum GNT
• Subsystem ID, Subsystem Vendor ID
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 PCI Configuration Register

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 Contd.
PCI Command Types
C/BE[3::0]#
0000 INTR ACK
• 0010 I/O Read
• 0011 I/O Write
• 0110 Memory Read
• 0111 Memory Write
• 1010 Configuration read
• 1011 Configuration write

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 Contd.
JTAG boundary scan
Test Access Port: It consists of four pins:
• Test Clock: Test Clock is used to clock state information and test
data into and out of the device during operation of the TAP.
• Test Data in: Test Data Input is used to serially shift test data and
test instructions into the device during TAP operation
• Test Data out: Test Output is used to serially shift test data and test
instructions out of the device during TAP operation
• Test Mode select:Test Mode Select is used to control the state of
the TAP controller in the device.
• Test Reset:Test Reset provides an asynchronous initialization of the
TAP controller
• IEEE standard 1149.1 compliant

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 Contd.
Interrupts
• Asynchronous events
• 4 interrupt lines for multi-functional devices.
• Interrupt lines goes to the interrupt controller
to execute the ISR

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 Contd.
PCI Bus Protocol-Transfer mechanism
• Configuration read/write
• IO read/write
• The basic transfer mechanism is a burst,
composed of an address phase and one or
more data phase.

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 Contd.
Burst Transfer Mechanism
• Assert REQ
• GNT granted
• Wait for current transaction to end
• Assert FRAME
• Transfer data when both TRDY and IRDY are
asserted
• De-assert FRAME during last data phase

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 Timing Diagram for a basic Read
operation

8/11/2023 pci 188

 Basic Write Operation

8/11/2023 pci 189

 Contd.
Transaction termination: Bus masters can terminate
transactions on completion or time-out; targets can also
terminate transactions
Last data phase completes when
• !FRAME and TRDY (normal - master)
• !FRAME and STOP (target termination)
• !FRAME and Device Select Timer expires (Master abort)
• !DEVSEL and STOP (Target abort)
[The target signals Target-Abort by deasserting DEVSEL#
and asserting STOP# at the same time.]

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 IrDA
• Serial interface that uses pulses of infrared light to
transmit data across short distances, without the need
for interconnecting cables.
• Infrared (IR) transmission of data is becoming
commonplace, and IR transceivers are appearing in
laptop computers, PDAs, and cell phones.
• They are also appearing in peripherals such as printers
and network interfaces, allowing no-fuss/no-cable
connection for people on the move.
• IR communication is also used by remote controls to
talk to their appliances. Your TV, VCR, and DVD remotes
all have an IR LED to beam commands across the room.

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 Contd.
• IrDA, which stands for "Infrared Data Association," is a
consortium of over 150 companies that maintain and
develop the standard.
• IrDA owes it origins to the infrared communication
links used in Hewlett-Packard calculators, known as HP-
SIR (Hewlett-Packard Serial Infra Red).
• The IrDA standard has expanded on HP-SIR significantly
and provides a range of protocols that application
software may use in communication.

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 Contd.
• The basic purpose of IrDA is to provide device-to-device
communication over short distances.
• Mobile devices, such as laptops, present a problem when
they must be connected to other machines or networks.
• Chances are the correct cable is not at hand, or one of the
machines is not configured correctly to allow networking to
take place.
• When the users are nontechnical types, this can be a real
problem. IrDA was developed as the solution to this
problem.
• With IrDA, no cables are required, and standard protocols
ensure that devices can exchange information seamlessly.

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 Contd.
• The expectation is that the IrDA user will be a mobile
professional using a laptop to communicate with other
computers, PDAs, or peripherals nearby.
• This concept has a number of important consequences.
• The devices communicating will be physically close, so
relatively low power transmissions are all that is required. This
is important because there are regulations guarding the
maximum level of IR radiation that can be emitted.
• Also, it is reasonable to assume that the two devices that are
to communicate will be physically pointed toward each other
prior to use.

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 Contd.
• It can also be assumed that only two devices will be communicating
and that their proximity will exclude interference from other IrDA
devices.
• Thus, IrDA does not have to deal with transmission collision and
detection issues that standards such as 802.11 (wireless Ethernet)
do.
• Two IrDA devices may be communicating at one end of a desk,
while another two devices are communicating at the other, with no
problems at all.
• Further, a transmission will be initiated by the user, which simplifies
the software protocols
• An overall guiding principle is that IrDA should be cheap to
implement, since it must find its way into low-cost consumer
devices.

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 Contd.
• IrDA is a point-to-point protocol that uses
asynchronous serial transmission over short distances.
• The initial IrDA specification (1.0) supported data rates
of between 2,400 bps and 115.2 kbps over distances of
one meter, although some IrDA transceivers can
achieve greater distances than this.
• Initial IR communication takes place at 9,600 bps, and
devices negotiate the data rate up or down, depending
on their capabilities and needs.
• Unlike RS-232C, the user does not need to set, know
about, or even care what bit rate is being used in
communication.

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 Contd.
• An IrDA transmitter will beam out its
transmission at an angle of 15 degrees to 30
degrees on either side of the line of sight.
• The receiver has a "viewing angle" of 15 degrees
on either side of its line of sight (Figure 10).
• So, if two IrDA devices are placed a meter or less
apart and generally aimed in each other's
direction, communication will not be a problem.
• Since its original specification, the standard has
been expanded to support higher data rates of
1.152 Mbps and 4 Mbps.
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 Contd.

IrDA transmission and viewing angles

Figure 10

8/11/2023 SREC/ECE/SJ 198

 Contd.
• The IrDA standard specifies a number of protocol layers
for communication.
• The IrPHY (IR Physical Layer) specification details the
hardware layer, including requirements for modulating
the outputs of UARTs prior to transmission.
• The control protocol is known as High-level Data Link
Control, or HDLC. IrLAP (Infrared Link Access Protocol)
uses a HDLC for controlling access to the communication
medium. One IrLAP exists per device.
• An IrLAP connection is essentially a master-slave
configuration, or, as they are known in IrDA parlance,
primary and secondary devices.

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 Contd.
• The primary device starts communication, sends
commands, and handles data-flow control
(handshaking).
• It is rare for a primary device to be anything other than
a computer.
• Secondary's (such as printers) simply respond to
requests from primaries.
• Two primary devices can communicate by one primary
assuming the role of a secondary device.
• Typically, the device that initiates the transfer remains
the primary, while the other device becomes a
secondary for the duration of the transaction.

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 Contd.
• IrLMP (Infrared Link Management Protocol) provides the device's
software with a means of sharing the single IrLAP between multiple
tasks that wish to communicate using IrDA.
• IrLMP also provides a query protocol by which one device may
interrogate another to determine what services are available on the
remote system.
• This query protocol is known as LM-IAS, or Link Management
Information Access Service.
• These are the basic IrDA protocols that all devices must support.
• Beyond these, IrDA also provides a number of optional services.
IrCOMM provides emulation of standard serial-port and parallel-
port devices.
• For application software, the IR port can then be used as if it were
just another serial or parallel port.

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 Contd.
• Using IrCOMM, a laptop or PDA can communicate with
an IR-enabled printer just as though that printer were
physically plugged into the mobile computer.
• IrLAN allows access to local area networks via the IR
interface.
• IrOBEX provides a mechanism for object exchange
between devices, in software that supports object-
oriented programming.
• Finally, Tiny TP is a lightweight protocol allowing
applications to perform flowcontrol (handshaking)
when transferring data from one device to another.
• Figure shows how these protocol layers fit together.

8/11/2023 SREC/ECE/SJ 202

 Contd.

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 Contd.
• At the lower data rates, all protocol handling,
packet forming, and error checking is done in
software by the processor within an IrDA-
compliant device.
• At higher data rates, dedicated hardware
performs these functions, since low-cost
embedded processors may not have the
computing horsepower to complete these
tasks in the time available.

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 Contd.
• Since IrDA communicates using light, there must
be some way to distinguish between a logic 0 and
a logic 1 during transmission.
• To solve this problem, IrDA uses a bit-encoding
scheme known as Return-to-Zero, or RZ.
• With RZ, a frame consists of a transmission
interval that is divided into subintervals
representing individual bits.
• A logic zero is represented by a pulse that is 3/16
the width of a bit subinterval, while a logic 1 is
represented by the absence of a pulse (
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 Contd.
• At data rates of 4 Mbps, PPM, or Pulse Position
Modulation, is used to distinguish different bits.
• With PPM, the position of the pulse is varied. Its
location within the subinterval determines the
transmitted bit pattern.
• The PPM used in IrDA is known as 4PPM and uses
one of four positions to provide the transmission
of two data bits.
• In PPM terminology, these are known as cells.
8/11/2023 SREC/ECE/SJ 206
 Contd.

4PPM cell encoding

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 Contd.
• A sample data packet (for a 4 Mbps
transmission) is shown in Figure.
• It consists of a 64-cell (128-bit) preamble
packet, a start packet, the frame body
containing the data to be transmitted, a 32-
bit Cyclic Redundancy Check (CRC) code, and a
packet stop marker.
• The data frame can be as little as 2 bytes or as
large as 2050 bytes.

8/11/2023 SREC/ECE/SJ 208

 Contd.

A 4 Mbps data packet

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 Contd.
• Now, most UARTs are not capable of performing
transmissions in RZ or PPM encoding.
• Therefore, a special device, known as an EnDec
(Encoder Decoder), converts the standard UART
output to RZ, and vice versa.
• A good EnDec to choose is the HSDL-7001 from
Agilent or the MCP2120 from Microchip.
• Some UARTs, such as the MAX3100, incorporate
an EnDec on chip and thus may be used to
directly interface to an IR transceiver
8/11/2023 SREC/ECE/SJ 210
 Thank you

8/11/2023 SREC/ECE/SJ 211