Chandan Singh
Takula, Bageshwar, Uttarakhand (263628) [email protected] | Ó +91-7300920471
¯ linkedin.com/in/chandan-singh-ba080b262 |
Academic Qualifications
Year Degree/Certificate Institute CGPA/%
2023–2025 M.Tech in VLSI Indian Institute of Technology, Mandi 7.73/10
2016–2020 B.Tech in Electrical Engineering G.B. Pant Engineering College, Uttarakhand 70.8%
Work Experience
• Intel, Bangalore — Design Verification Intern June 2024 - April 2025
– Conducted functional verification for the Host Backed Caching (HBC) flow of the Network Sub-System (NSS) IP used in
high-performance NICs for data centers.
– Updated test plan vManager, enabling traceable and systematic verification tracking aligned with project goals.
– Executed regressions to validate functionality, identify issues, and improve RTL quality.
– Utilized Verdi to debug waveform mismatches and analyze signal transitions to ensure correct system behavior.
– Collaborated with RTL and DV teams in meetings and contributed toward closure of critical issues under project deadlines.
Technical Skills
• Hardware Description Languages: Verilog
• Hardware Verification Languages: System Verilog, System Verilog Assertions
• Methodologies: UVM
• Programming Language: C
• Scripting Language: Perl
• Synthesis Tools: EDA Playground, Xilinx Vivado
• EDA Tools: Cadence Virtuoso
Projects
• Implementation of CORDIC Algorithm using Verilog HDL in Vivado
– Designed a CORDIC-based sine/cosine computation unit with configurable iterations.
– Verified functionality by comparing simulated waveforms with theoretical outputs across multiple precision levels.
• Synchronous FIFO Verification using System Verilog
– Designed a synchronous FIFO using System Verilog with parameterized depth and width.
– Verified using testbenches with corner cases like simultaneous read/write, full/empty conditions, and reset scenarios.
• Asynchronous FIFO Verification using UVM
– Developed an asynchronous FIFO with independent read/write clocks and Gray code pointer logic.
– Created UVM-based testbench to validate metastability handling, pointer synchronization, and data integrity under asyn-
chronous operations.
• UVM-Based AXI Protocol Verification Environment
– Built complete UVM verification environment for AXI protocol including agents, monitors, and scoreboard.
– Applied constrained-random tests for burst, size, alignment, ensuring protocol robustness.
– Validated data integrity using a custom UVM scoreboard for end-to-end AXI transactions.
• UVM-Based APB Protocol Verification Environment
– Developed complete UVM verification environment for APB protocol including agents, monitor, and scoreboard.
– Implemented constrained-random test cases for read/write operations, address decoding, and response verification.
– Ensured protocol compliance by validating setup/hold timing and APB transfer sequences.
Certifications
• System Verilog Fundamentals and System Verilog Projects — Udemy
• System Verilog assertions and System Verilog functional coverage — Udemy
• UVM Fundamentals, UVM Register Abstraction Layer (RAL), and UVM Projects — Udemy
