DAY-51
SYSTEM VERILOG: REFERENCE GUIDE
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What is System Verilog:-
• System Verilog is a combined hardware description language
and Hardware verification language
• System Verilog is an extensive set of enhancements to the
IEEE
• 1364 Verilog-2001 standards
• It has features inherited from Verilog HDL, VHDL, C, C++
History and Evolution of System Verilog:-
• Verilog (IEEE standard 1364)
✓ Began in 1983 as a proprietary language
✓ Opened to the public in 1992
✓ Became an IEEE standard in 1995 (updated in 2001 and
2005)
✓ Between 1983 and 2005 design sizes increased
dramatically
• System Verilog (IEEE standard 1800)
✓ Originally intended to be the 2005 update to Verilog
✓ Contains hundreds of enhancements and extensions to
Verilog
✓ Published in 2005 as a separate document
✓ Officially superseded Verilog in 2009
✓ Updated with more features in 2012 (IEE 1800 2012
standard)
Why is System Verilog:-
System Verilog-User View:-
System Verilog has 5 major parts
1. SVD – System Verilog for Design:-Features supporting
Design
2. SVTB – System Verilog for Test benches:- Test bench specific
Features
3. SVA – System Verilog Assertions:- Features for temporal and
concurrent assertions
4. SVDPI – SV Direct Programming Interface:- For better
C/C++ Integration
5. SVAPI – SV Application Programming Interface:-For better
Coverage/Assertion integration
