CHAPTER 3 Combinatorial and Sequential Circuits

Combinatorial Circuits Sequential Circuits

• Only logic gates, no • Logic gates with
feedback, no memory feedback and memory
• No states • States
• Equivalent to • Equivalent to
mathematical function computer program

Which one would you need for implementing:

• Game show buzzer ?
• Traffic Light ?
• Washing machine ?
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Building Blocks
• Combinational Circuits
• Flip-Flops
• Register
• Decoder
• Multiplexer / Demultiplexer
• Adder
• Comparator

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1. Combinational Circuits
• Everything is a combination of AND, OR, NOT gates
(or just NAND gates, or just NOR gates)
• There are no feedback loops!
• There is no memory,
every output line is a simple function of its inputs

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Gates

a AND ab a AND b a OR b NOT a

00 0 0 1
b
OR 01 0 1 1

10 0 1 0

NOT 11 1 1 0

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Gates

a NAND
ab a NAND b a NOR b a XOR b
b 00 1 1 0

NOR 01 1 0 1

10 1 0 1
XOR
11 0 0 0

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De Morgan’s Law
a Are these a
b identical ? b

Check with
truth table
De Morgan’s Law
ab a NOR b a’ AND b’
00
A OR B = A AND B
01
A AND B = A OR B
10

11

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Combinatorial Circuits
• Arbitrarily complex circuits can be built from
AND/OR/NOT gates
• The output will only depend on the input lines
(after some propagation delay)
• There is no memory.

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2. Decoder
X1
D Y3 Y3
3 1 Y
X1 1
2 2
X0
X0 0 1 Y1 Y2
0
Y0

Y1

“set corresponding Yi to ‘1’, Y0

all others to ‘0’ “

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Encoder

X3 E X3 Y1
3
X2 2 Y1 X2
X1 1 X1 Y0
0
Y0
X0 X0

Note: X0 is not used!

“set Y to the binary equivalent

to the Xi input line “

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Encoder and Decoder

X0 E D X0
0 Y1 0
X1 1 1 X1
X2 2 Y0 2 X2
X3 3 3 X3

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3. Multiplexer
A
0 A
Z
S
B
1
B Z

S 0/ 1

Z : = (A AND S’) OR (B AND S)

= A · S’ + B · S
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 Multiplexer (4-way)
A
A 0
B
B 1 Z Z
C 2 C
D 3 D

D0
1
2
3
S1 S0

S1 S0
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 Multiplexer with multiple lines
A3 0
4 B3 1 Z3
A 0 C3 2
4 3
B 1 4 Z D3
A2 0
4
C 2 B2 1 Z2
C2 2
4
D 3 D2 3
A1 0
B1 1 Z1
2
S1 S0 C1
3 A0 0
D1
B0 1 Z0
C0 2
D0 3
0 1
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S1 S0
Demultiplexer
A
0
X X A
B
1 S
B
S 0/ 1

“if S = 1 then B := X
else A := X “
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Demultiplexer (4 way)
X A
0 A
X 1 B B
2 C
C
3 D
D
S1 S0
D0
1
2
3
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S1 S0 15
 4. Half Adder
Y XY carry sum
00 0 0
carry H X 01 0 1

10 0 1
sum 11 1 0
Adding 2 input bits (X, Y)
resulting in 2 output bits (sum, carry)
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 XY carry sum

Half Adder Implementation 00 0 0

01 0 1

Y 10 0 1

carry 11 1 0
X

XOR
Y

sum carry X
H

sum
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Full-Adder (1 stage)
X Y Cin Cout sum
X Y
000 0 0
001 0 1
010 0 1
Cout A Cin 011 1 0
100 0 1
101 1 0
sum 110 1 0
111 1 1
Adding 3 input bits (X, Y, Cin)
resulting in 2 output bits (sum, Cout)
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Full-Adder Implementation (1 stage)
X

H Y
X Y
Cout Cin
A
H Cin
sum

Cout sum

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 Full Adder (n stages)
4-bit adder

X3 Y3 X2 Y2 X1 Y1 X0 Y0

C3 C2 C1 C0 C-1
A A A A 0

S3 S2 S1 S0

This is called a ripple carry adder – note propagation delay.

Faster: “carry look-ahead“ adder.
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 5. Tri-State
En X Y
enable 0 0 *

0 1 *

X Y 1 0 0

1 1 1
If enable is 0, output is “high-ohm” (not connected)
If enable is 1, output equals input
Extension of
binary logic

Bräunl 2023 Diagram: electronics-tutorials.ws 21

Tri-State Implementation
Note: Never link two outputs together without tri-state !!

enable
Vcc En X Y
0 0 *
X 0 1 *

Y 1 0 0

1 1 1

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Gnd 22
6. Latches, Flip-Flops, Memory
• We now introduce a feedback loop
• This will allow to “trap” a single bit of information
• It is the smallest instance of a memory cell
• Required functions:
– Change the bit (set to 1 or reset to 0)
– Read the current bit value

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Memory

0 0 If the first input is 0, a 0 gets

1
fed back into it

If the first input is 1, a 1 gets

1 0 1 fed back into it

This circuit will hold its state forever - stable

Bräunl 2023 Source: Boussaid 24

Memory

Bräunl 2023 Source: Boussaid 25

 Memory

Qnext = NOR(R, NOR(Qold, S))

Consider all cases: S S

R S Qnext R R
0 0 __unchanged
Q Q
0 1 __1
1 0 __0 Q’ Q’

1 1 not allowed t t
Bräunl 2023 Source: Boussaid, Bräunl 26
Memory
What happens if R,S are both set to 1, then reset to 0?
•Uncontrolled oscillation
•That’s is why this state is illegal

S
Q
Q’

Bräunl 2023 Graph: Boussaid 27

Memory
Note:
• This circuit’s output Qnext (aka Q+) does depend not only
on its inputs R, S – but also on its previous state Q.
• This means we have built a sequential circuit. This is no
longer a combinatorial circuit.
• We achieved this by using a feedback connection.
• We built the smallest instance of a memory cell (1 bit).
• The desired initial state (after power-on) is Q=0.
However, depending on used chip, initial state may be
random.
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Memory

Bräunl 2023 Source: Fairchild 29

7. Level-Triggered Latches (RS)
RS Latch
How to use: How to build:
R Q
S Q

R Q' Q'
S

Can also be built with 2 NAND gates.

S and R must not be 1 at the same time!

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Level-Triggered Latches (D-input)
D-Latch with Enable
How to use: How to build:

D Q R Q
En
S Q
En D

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8. Edge-Triggered Flip-Flops
D–Flip-Flop

D Q Q+ = D

clk

trigger on rising edge

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 D Q
Edge-Triggered Flip-Flops clk

Trigger on rising clock edge

Clock

Bräunl 2023 Graph: Boussaid 33

 D Q
Level Latch
En

Trigger on positive clock level

Clock

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Edge-Triggered Flip-Flops
D–Flip-Flop

D Q Q+ = D

clk

trigger on falling edge

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 D Q
Edge-Triggered Flip-Flops clk

Trigger on falling clock edge

Clock

Bräunl 2023 Graph: Boussaid 36

 Implement Edge-Triggering Flip-Flop

D D Q D Q Q Master-Slave Method:
Master Slave • clk 0: Master changes
• clk 1: Slave changes
En En
Overall:
• Rising edge triggered
clk

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JK-Flip-Flop
Edge triggered, similar to RS-FF, but it flips its
state when both J=K=1
Q+ = J · Q’ + K’ · Q
J Q
K J K Q(t+1) Operation
0 0 Q(t) No change
0 1 0 Reset
clk 1 0 1 Set
1 1 Q’(t) Complement

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JK-Flip-Flop
How to build Q+ = J · Q’ + K’ · Q

R Q Q
K
J S Q Q
clk

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 9. Registers
• Several flip-flops can be combined into one register.
• An n-bit register is a group of n binary storage cells (flip-flops).

• Registers are classified according to the number of bits of storage and

operating mode:
– parallel in – parallel out (PIPO) ç standard, this is what we’ll use
– parallel in – serial out (PISO)
– serial in – parallel out (SIPO)
– serial in – serial out (SISO)
– universal (control signals for either serial or parallel op.)
• Registers are commonly used as temporary storage in a processor.
– They are faster and more convenient than main memory.
– More registers can help speed up complex calculations.

Bräunl 2023 Source: Boussaid 40

Register Example
• Basic registers are easy to build. We can store multiple bits just
by putting a bunch of flip-flops together!
• 4-bit register is (right), and its internal implementation (below).
– All the flip-flops share a common CLK (clock) and CLR
(clear) signal.

Bräunl 2023 Source: Boussaid 41

 Shift Registers
Q0(t+1) = SI
Q1(t+1) = Q0(t)
Q2(t+1) = Q1(t)
Q3(t+1) = Q2(t)

• A shift register “shifts” its output once every clock cycle.

• SI is an input that supplies a new bit to shift “into” the register.
• E.g., on some positive clock edge we have: SI = 1
Q0-Q3 = 0110

then the next state will be: Q0-Q3 = 1011

• The current Q3 (0 in this example) will be lost on the next cycle.
• The circuit and example make it look like the register shifts “right”,
but it depends on your interpretation of the bits. If you consider Q3 to be the
most significant bit instead, then the register is shifting in the “left”!
Bräunl 2023 Source: Boussaid 42
Registers
Trigger e.g. rising edge Equivalent to:
Bank of D Flip-Flops
A
A

Register clock D Q D Q D Q D Q
00
clock

Z
Z
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10. Clock

Symbol

Bräunl 2023 Source: electronics-tutorials.ws 44

11. Real Hardware
For experimenting use a breadboard (proto-board)
Connections

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 LEDs and Resistors

Note: LEDs have

polarity. The longer
pin is “+”

+ – Black
Brown
Red
Orange
Yellow
Green
Blue
Purple
Gray
White
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Data-
sheets

Bräunl 2023 Source: National Semiconductor 47

NOR Chip CD4001
See http://robotics.ee.uwa.edu.au/courses/des/labs/datasheets/

Bräunl 2023 Source: National Semiconductor 48

NOR Chip CD4001
• Place chip over middle row on proto-board
(so no pins are connected with each other)
• Make sure to connect power and ground!

+ –

+ 3.3V
or 5V
–
330 Ohm

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NAND Chip CD4011
See http://robotics.ee.uwa.edu.au/courses/des/labs/datasheets/

Bräunl 2023 Source: National Semiconductor 50

Flip-Flop Chip CD4013
Note: Some FF have a random initial state.
These FF require a power-up reset circuit
using a capacitor to Vcc and a resistor to Gnd.

Bräunl 2023 Source: National Semiconductor 51

 Hardware Simulators for Testing
• Fritzing
http://fritzing.org/home/
• Retro
http://robotics.ee.uwa.edu.au/
retro/

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 QUIZ

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A
B
C

A. A·B·C

B. A·B + C

C. A·B + C’

D. A+B · C’

Bräunl 2023 http://roblab.org/quiz/ 54

 X3 Y3 X2 Y2 X1 Y1 X0 Y0

Delay C3
A
C2
A
C1
A
C0
A
C-1
0
steps
S3 S2 S1 S0
A. 8

B. 12

C. 16

D. 20

Bräunl 2023 http://roblab.org/quiz/ 55

 X3 Y3 X2 Y2 X1 Y1 X0 Y0

Delay C3
A
C2
A
C1
A
C0
H
steps
S3 S2 S1 S0
A. 9

B. 10

C. 11

D. 12

Bräunl 2023 http://roblab.org/quiz/ 56

 D Q clock

clk D

Q ??
A. 0, 1, 0, 1, 0, 1

B. 1, 0, 0, 0, 1

C. 1, 0, 1

D. 0, 0

Bräunl 2023 http://roblab.org/quiz/ 57

 D Q clock

clk D
Q ??
A. 0, 1, 0, 1, 0, 1

B. 1, 0, 0, 0, 1

C. 1, 0, 1

D. 0, 0

Bräunl 2023 http://roblab.org/quiz/ 58