PRAKASH BABU GAJULA
Design and Verification Engineer
[email protected] | +91 9346225240 | Rajamahendravaram ,Andhra Pradesh
www.linkedin.com/in/prakash-babu-gajula
CAREER OBJECTIVE
Aspiring VLSI Design and Verification Engineer with a strong foundation in digital design, RTL coding, and
verification using Verilog, SystemVerilog, and UVM. Eager to contribute to innovative ASIC/FPGA projects
by applying practical experience gained through professional training and internship. Seeking a challenging
role in a dynamic organization where I can grow as a skilled engineer while delivering value through quality-
driven design and verification solutions.
PROFESSIONAL TRAINING
Maven Silicon Softech Pvt Ltd, Bangalore Jan 2025 - Present
Trained in RTL design using Verilog, functional verification using SystemVerilog, Assertions (SVA), and
UVM methodology.
Hands-on experience with industry tools like Synopsys VCS, QuestaSim, and SpyGlass through lab
sessions and real-time project work
EDUCATION
Bachelor of Technology(B.Tech) -79% June 2020- Apr 2024
Vishnu Institute Of Technology , Bhimavaram
Electronics and Communication Engineering
Intermediate (BIEAP) -95.5% Jun 2018 - May 2020
Tirumala junior Kalasala , Katheru
MPC
Secondary School Certificate(SSC) -95% Jun 2017 - May 2018
Swarna Bharathi High School ,Dharmavaram
SKILLS
VLSI DOMAIN SKILLS
HDL :Verilog
HVL :System Verilog
Verification methodologies :Constraint Random Coverage Driven Verification ,SVA
TB methodology :UVM
EDA Tool :Synopsys - VCS, Mentor Graphics - QuestaSim, Xilinx- ISE,
Synopsys Design Compiler, VC SpyGlass Lint
Domain :ASIC/FPGA front-end Design and Verification
PROJECTS
ROUTER 1X3
April 2025 - May 2025
HDL :Verilog | HVL: SystemVerilog | TB Methodology: UVM
EDA Tools :Vivado & QuestaSim , Synopsys - VCS
Contribution :Developed the block-level architecture and implemented RTL design in Verilog HDL,
ensuring quality through code coverage and assertions. Enhanced a class-base Verification
environment in SystemVerilog, achieved functional coverage, and performed RTL synthesis
for subsequent design stages.
4-BIT MOD-12 UP-DOWN COUNTER DESIGN & VERIFICATION Jun 2025 - Jun 2025
HDL : Verilog | HVL: System Verilog
EDATools : Vivado & QuestaSim, Synopsys-VCS
Contribution : Designed a 4-bit Synchronous up-down counter with MOD-14 behavior , featuring active-
low load and direction control. Implemented a layered System Verilog testbench architecture
with components like driver, monitor, and scoreboard.Verified all functional scenarios using
Synopsys VCS ,performed wave form analysis ,and achieved 100% functional coverage.
FIFO MEMORY DESIGNIN VERILOG Jun 2025- Jun 2025
EDATools : Xilinx
Contribution :Designed asynchronous FIFO memory module using Verilog HDL.Implemented control
logic for read/write operations with full and empty flag generation.Simulated and verified
the design to ensure correct data flow and timing behavior.
ASSERTION -BASED VERIFICATION OF DIGITAL ALARM CLOCK USING SYSTEM -VERILOG
EDATools : Questa Sim
Contribution Wrote SystemVerilog Assertions (SVA) to validate counter rollover and reset behavior.
Verified correct alarm trigger when programmed time matched counter values.
Implemented assertions to ensure clock enable/disable signals maintained protocol integrity.
Used simulation waveforms and assertion coverage to confirm functional correctness.
WORKEXPERIENCE
Design Intern (Verilog ) at Hexa Semi Solutions pvt ltd Aug 2023 – Sep 2023
Designed SPI master-slave module in Verilog with configurable CPOL/CPHA.
Verified protocol functionality through testbenches and waveform analysis.
Ensured reliable full-duplex data transfer with proper synchronization.
Implemented parameterized design for flexible data width and clock frequency.
VOLUNTEERING
Active member of the National Service Scheme (NSS) at college. Participated in various social service
initiatives, including blood donation drives, “Feed the Need” programs, and a special rural outreach
camp. Contributed to community welfare, team coordination, and awareness activities through
dedicated volunteering efforts.
SOFT SKILLS
Team Collaboration Leadership
Responsibility and Accountability Quick Learner
DECLARATION
I hereby declare that the information provided above is true to the best of my knowledge and belief.
Date :
Place : Bangalore PRAKASH BABU GAJULA
