Journal of Computational Electronics

https://doi.org/10.1007/s10825-019-01318-2

A comparative study of a deep‑trench superjunction SiC VDMOS

device
Shengdong Hu1 · Ye Huang1 · Tao Liu1 · Jingwei Guo1 · Jian’an Wang2 · Jun Luo2

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Abstract
A superjunction (SJ) SiC VDMOS device with a deep trench (DT-SJ SiC) is investigated and compared with conventional
SiC VDMOS (C SiC) and SJ SiC VDMOS (C-SJ SiC) devices using numerical simulations. The DT-SJ SiC VDMOS device
has an SJ drift region and a deep trench (DT) extending from the gate to the drain. The SJ provides a better trade-off between
the breakdown voltage (BV) and specific on-resistance (Ron,sp), resulting in a high figure of merit (FOM = BV2/Ron,sp). The
DT leads to a lower maximum gate oxide field (Eox,max) by breaking the restriction of Gauss’s law on the vertical electric
field at the gate oxide interface. Moreover, the gate charge (Qg) and the gate–drain charge (Qgd) are dramatically reduced. The
electrical characteristics of the DT-SJ SiC are studied and compared with the other two devices with the same dimensions.
Compared with the C SiC, the BV and the maximum FOM are increased by 308 V and 3028 MW cm−2, respectively, while
Ron,sp, Eox,max, Qg, and Qgd are decreased by 47.97 %, 26.98 %, 35.59 %, and 58.73 %, respectively. Compared with the C-SJ
SiC, the BV and the maximum FOM are increased by 18 V and 116 MW cm−2, respectively, while Ron,sp, Eox,max, Qg, and
Qgd are decreased by 1.04 %, 21.48 %, 40.63 %, and 61.91 %, respectively.

Keywords Superjunction · SiC VDMOS · Breakdown voltage · Specific on-resistance · Gate oxide field · Gate charge

1 Introduction Compared with the trench technology, SiC devices based on

the superjunction (SJ) principle have not been sufficiently
Because of its superior electrical properties, silicon car- studied. In 2003, fabrication of a 400-V SiC lateral SJ diode
bide (SiC) is attracting increasing attention for use in power was reported for the first time [12]. Yu and Sheng [13] devel-
devices for high-power applications [1, 2]. Recently, many oped models for the electric field distribution in such SiC SJ
studies have been conducted on SiC devices with different devices. In 2012, simulations of 5–20-kV SiC SJ diodes were
structures, to examine their performance in terms of the reported, revealing the structural parameters that yielded the
breakdown voltage (BV), specific on-resistance (R on,sp), best trade-off between the BV and Ron,sp [14]. Kosugi et al.
maximum gate oxide field (Eox,max), gate charge (Qg), etc. [15] presented the first experimental demonstration of an SiC
[3–9]. Some technologies that are widely used in silicon SJ structure obtained by multiepitaxial growth, measuring
power devices, such as the trench structure, have also been a BV of 1545 V and an Ron,sp of 1.06 mΩ cm2. In 2016, an
introduced into SiC devices and rapidly developed [10, 11]. SiC Schottky diode with a partial SJ region was developed
based on a process including two groups of implantations,
achieving a BV of 1350 V and an Ron,sp of 0.92 mΩ cm2 [16].
* Shengdong Hu Masuda et al. [17] reported the fabrication of an 820-V SiC
[email protected] SJ V-groove trench metal–oxide–semiconductor field-effect
1
transistor (MOSFET) with 0.97 mΩ cm2. Since the use of
Key Laboratory of Dependable Service Computing in Cyber
Physical Society, Ministry of Education, and Chongqing the SJ principle can improve the trade-off between the BV
Engineering Laboratory of High Performance Integrated and Ron,sp [18–20], further studies on such structures for SiC
Circuits, College of Communication Engineering, SJ devices are expected.
Chongqing University, Chongqing 400044, China To date, most investigations on SiC VDMOS devices with
2
The National Laboratory of Analogue Integrated Circuits, SJ structures have only studied the trade-off between the BV
No. 24 Research Institute of China Electronics Technology and Ron,sp, as in silicon power devices, while the influence
Group Corporation, Chongqing 400060, China

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of such SJ structures on new problems faced by SiC power DT-SJ VDMOS device offers a good trade-off between
devices, such as the high gate oxide field, has rarely been the BV and Ron,sp as well.
studied. In addition, SJ SiC VDMOS devices with a dielec- B. The maximum gate oxide field Eox,max results from the
tric layer have not been reported so far. An SiC VDMOS application of Gauss’s law, εoxEi,ox = εSiCEi,SiC, on the
device with a deep trench (DT) and an SJ structure (DT-SJ interface of the gate oxide and the curvature effect (CE)
SiC) is studied herein. The electrical characteristics, such at the corner of the gate. Here, Ei,ox and Ei,SiC, and εox
as the BV, Ron,sp, figure of merit (FOM = BV2/Ron,sp) [9], and εSiC are the interface electric field and permittivity
Eox,max, and Qg, of the device are analyzed using simulations. of ­SiO2 and SiC, respectively. Eox,max can be resolved
For comparison, simulations are also performed for conven- into lateral and vertical components for analysis. Fig-
tional SiC VDMOS (C SiC) and SJ SiC VDMOS (C-SJ SiC) ure 2 shows schematic distributions of the lateral (Ex)
devices with the same dimension. and vertical electric field components (Ey) for the three

2 Device structure and mechanism

Figure 1 shows the structures of the C SiC VDMOS, C-SJ

SiC VDMOS, and DT-SJ SiC VDMOS devices. Compared
with the C SiC VDMOS device, the C-SJ SiC VDMOS and
DT-SJ VDMOS devices have an SJ structure in the drift
region, formed of P-pillars and N-pillars. The major distin-
guishing feature of the DT-SJ SiC VDMOS structure is the
DT, which extends from the gate to the drain N+ substrate.

A. The lateral depletion effect between the P and N pil-

lars of the SJ structure leads to a heavier doping for
full depletion, thus a lower Ron,sp is obtained. The opti-
mized field distribution resulting from the SJ structure
increases the BV. Therefore, the C-SJ SiC VDMOS and
DT-SJ SiC VDMOS devices have higher BV and lower
Fig. 2  Schematic distributions of the lateral (Ex) and vertical electric
Ron,sp values in comparison with the C SiC VDMOS field components (Ey) along point M for the three devices. Ei,SiC and
device. Although the P and N pillars of the DT-SJ Ei,ox are the electric fields in the SiC and ­SiO2 at the interface of the
VDMOS structure are narrower than those of the C-SJ gate oxide, respectively. Region A is formed of SiC material for all
three devices. Region B is formed of SiC material for the C-SJ SiC
SiC VDMOS structure owing to the presence of the DT,
VDMOS and C SiC VDMOS devices, but is ­SiO2 material for the
the high optimized doping concentration ensures that the DT-SJ SiC VDMOS device. EM,L and EM,V are the lateral and vertical
components of the electric field at point M, respectively

Fig. 1  The structures of the

studied SiC MOSFET devices:
a C SiC VDMOS, b C-SJ SiC
VDMOS, and c DT-SJ SiC
VDMOS

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devices. The electric field at point M (EM) is Eox,max, 3 Results and discussion
and Ex and Ey are both along the point M. EM is equal to
2
(EM,L + E2M,V)1/2, where EM,L and EM,V are the lateral and Figure 3 shows the I–V curves obtained for the DT-SJ SiC
vertical components of EM, respectively. For Ex, EM,L is VDMOS, C-SJ SiC VDMOS, and C SiC VDMOS devices.
always affected by Gauss’s law and the CE, for all three The doping concentrations for the three devices are opti-
devices. Due to the charge imbalance at the border of mized based on the maximum FOM (­FOM max). N sj is
the N-pillar in the SJ structure [19], Ei,SiC is highest for 6 × 1016 cm−3 for the DT-SJ SiC VDMOS structure, Nsj is
the DT-SJ SiC VDMOS structure. However, the lower 3.3 × 1016 ­cm−3 for the C-SJ SiC VDMOS structure, and Ndrf
CE at the gate corner means that the EM,L value of the is 5.3 × 1015 cm−3 for the C SiC VDMOS structure. Figure 3a
DT-SJ SiC VDMOS structure does no show an obvious shows the I–V characteristics in the off-state (Vgs = 0 V). The
distinction for the other two devices. For Ey, there is BV is determined when the drain–source current Ids reaches
no SiC/SiO2 interface under the gate for the DT-SJ SiC 1 × 10−9 A/μm. It can be seen that the optimized electric
VDMOS device, and Ei,ox is obviously reduced because field distributions in the drift regions lead to a higher BV of
of the absence of the restriction based on Gauss’s law above 2800 V for the two SJ devices, compared with 2577 V
compared with the other two devices. Actually, E i,ox for the C SiC VDMOS device. Because a higher Nsj results
is linearly enhanced in the situation in the DT-SJ SiC in a higher critical electric field, the BV of the DT-SJ SiC
VDMOS device, whereas Ei,ox is enhanced according to VDMOS device (2885 V) is slightly larger than that of the
Gauss’s law for the other two devices. Therefore, EM,V C-SJ SiC VDMOS device (2867 V). Figure 3b shows the
is lower for the DT-SJ SiC VDMOS device, as shown in
Fig. 2. Thus, the DT-SJ SiC VDMOS device has a lower
Eox,max value compared with the C SiC VDMOS or C-SJ
SiC VDMOS device, based on the analysis above.
C. Inclusion of a thick oxide layer between the gate and
the drain of a MOSFET device is favorable to achieve
a lower gate–drain charge Qgd and a lower gate charge
Qg. Therefore, the DT-SJ SiC VDMOS device has much
lower Qg and Qgd values because of the DT, in com-
parison with the other two devices, which contributes to
reducing the switching loss and increasing the switching
speed for such power MOSFETs.

The key parameters of the devices are defined and given

in Table 1. Device simulations using Sentaurus TCAD [21]
are employed to reveal the electrical performance of the
three devices. In the simulations, the SRH, AUGER, and
OkutoCrowell recombination models are used, as well as
the DopingDependence, HighFieldSaturation, and Enormal Fig. 3  The I–V characteristics of the DT-SJ SiC VDMOS, C-SJ SiC
mobility models. The mobility in the channel inversion layer VDMOS, and C SiC VDMOS devices. The breakdown criterion is
that the drain–source current Ids equals 1 × 10−9 A/μm. The chan-
is set to a constant value of 50 cm2/(V s) [7, 22]. nel mobility is assumed to be 50 cm2/(V s). Wt is 1 μm for all three
devices. a Off-state (Vgs = 0 V); b on-state (Vgs = 20 V)

Table 1  The key parameters in Parameter DT-SJ SiC (μm) C-SJ SiC (μm) C SiC (μm)
the analysis
Half-cell width 3 3 3
Thickness of gate (Tg) 1.55 1.55 1.55
Thickness of gate oxide (Tox) 0.05 0.05 0.05
Thickness of epi-layer (Tepi) 18 18 18
Thickness of N+ substrate (Tsub) 1 1 1
Width of N/P-pillars (Wsj) 0.9–1.1 1.5 –
Width of gate oxide (Wt) 0.8-1.2 1 1
N/P-pillar concentration (Nsj) Optimized Optimized –
Drift-region concentration (Ndrf) – – Optimized

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I–V characteristics in the on-state (Vgs = 20 V). Although the

Nsj value is much higher, the Ron,sp value of the DT-SJ SiC
VDMOS device (1.625 mΩ cm2) is slightly lower than that
of the C-SJ SiC VDMOS device (1.642 mΩ cm2), because
of the narrower Wsj. In addition, because of the higher Nsj
caused by the advantage of the SJ structure, the specific on-
resistance of both SJ devices is much lower than that of the
C SiC VDMOS device (Ron,sp = 3.123 mΩ cm2). Here, the
Ron,sp is calculated from the expression WVds/Ids. Figure 4
illustrates the dependences of the BV, Ron,sp, and FOM on
the doping concentrations for the three devices. The BV and
Ron,sp both decrease with increasing doping concentration,
and there will be an F ­ OMmax on the condition of a certain
doping concentration, which is termed the optimized con-
centration for each device (Nsj,op for the SJ SiC VDMOS
and Ndrf,op for the C SiC VDMOS). Nsj,op is much higher
than Ndrf,op (Ndrf,op = 5.3 × 1015 ­cm−3) because of the lateral
depletion effect between the P and N pillars. The Nsj,op value
of the DT-SJ SiC VDMOS (Ndrf,op = 6×1016 ­cm−3) is higher
than that of the C-SJ SiC VDMOS device (Ndrf,op = 3.3 × 1016
­cm−3), because the former’s N/P pillars are narrower. Based
on the analysis of the BV and Ron,sp, the DT-SJ SiC VDMOS
device shows the highest F ­ OM max of 5122 MW cm−2,
slightly larger than the value of 5006 MW cm−2 found for
the C-SJ SiC VDMOS. The C SiC VDMOS device shows
the lowest F­ OMmax of 2094 MW cm−2. Overall, these results
show that the BV of the DT-SJ SiC VDMOS device is higher
by 18 V and 308 V compared with the C-SJ SiC VDMOS
and C SiC VDMOS device, respectively, the Ron,sp of the
DT-SJ SiC VDMOS device is lower by 0.017 mΩ cm2 and
1.498 mΩ cm2 compared with the C-SJ SiC VDMOS and C
SiC VDMOS device, respectively, and the ­FOMmax of the
DT-SJ SiC VDMOS device is larger by 116 MW cm−2 and

Fig. 4  The dependences of the BV and Ron,sp on the doping con- Fig. 5  The distribution of the electric field in the off-state around the
centration (Nsj for the DT-SJ SiC VDMOS and C-SJ SiC VDMOS gate corner in the three devices with Vds = 1700 V: a C SiC VDMOS,
devices, or Ndrf for the C SiC VDMOS device). The inset shows the b C-SJ SiC VDMOS, and c DT-SJ SiC VDMOS
dependence of the FOM on the doping concentration. Wt is 1 μm for
all three devices

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Fig. 7  The dependence of Eox,max on Vds with Vgs = 0 V for all three
devices. Wt is 1 μm for all three devices

MV/cm for the C-SJ SiC VDMOS device, respectively.

Figure 6 shows the distributions of the lateral and vertical
electric fields along the point of Eox,max for the three devices.
Eox,max is the equivalent of EM in Fig. 2, thus EM,L and EM,V
are used to refer to the lateral and vertical components of
Eox,max as well, respectively. Considering the lateral electric
field (Fig. 6a), the C-SJ SiC VDMOS device has the lowest
interface field Ei,SiC of 0.75MV/cm, because the gate corner
is within an N-pillar of an SJ structure. Meanwhile, Ei,SiC
is 0.81 MV/cm for the C SiC VDMOS device. The Ei,SiC
value of the DT-SJ SiC VDMOS device is 0.96 MV/cm,
the highest among the three devices, because of the charge
Fig. 6  The distribution of the electric field along the point of imbalance at the border of the SJ structure. However, the
Eox,max (point M in Fig. 2) for the three devices with Vgs = 0 V and DT of the DT-SJ SiC VDMOS decreases the CE, so EM,L
Vds = 1700 V. Wt is 1 μm for all three devices. a Lateral electric field takes the same value of 3.44 MV/cm as for the C-SJ SiC
component. b Vertical electric field component
VDMOS device, being slightly lower than the value of
3.69 MV/cm found for the C SiC VDMOS device. Consid-
ering the vertical electric field (Fig. 6b), the Gauss relation
3028 MW cm−2 compared with the C-SJ SiC VDMOS and Ei,ox = εSiCEi,SiC/εox causes the interface electric field on the
C SiC VDMOS device, respectively. Therefore, the trade-off ­SiO2 side to be about 2.5 times higher than on the SiC side
between the BV and Ron,sp is slightly better for the DT-SJ for the C SiC VDMOS device (Ei,SiC = 1.9 MV/cm) and the
SiC VDMOS device compared with the C-SJ SiC VDMOS C-SJ VDMOS device (Ei,SiC = 1.77 MV/cm), which accounts
device, and much better compared with the C SiC VDMOS for the vast majority of the electric field EM,V. Ei,SiC and
device, as shown in Figs. 3 and 4. EM,V are 1.77 MV/cm and 6.26 MV/cm or 1.77 MV/cm and
Figure 5 shows the electric field distribution near the 5.82 MV/cm for the C SiC VDMOS or C-SJ SiC VDMOS
gate region with Vgs = 0 V and Vds = 1700 V. It is clear that device, respectively. What is more noteworthy is that, in
the high-field region of the DT-SJ SiC VDMOS device is spite of the higher interface electric field (Ei,ox = 2.46 MV/
much smaller than for the other two devices, which is due cm), the EM,V value of the DT-SJ SiC VDMOS device is
to the absence of the SiC–SiO2 interface and the restriction much lower, due to the linear relation between the electric
of Gauss’s law under the gate. At the same time, the DT-SJ fields at the interface. Overall, both the lateral and vertical
SiC VDMOS device shows the lowest Eox,max of 4.79 MV/ electric field components of Eox,max are effectively reduced
cm, lower by 27 % and 21.48 % compared with the val- for the DT-SJ SiC VDMOS device. Figure 7 shows the
ues of 6.56MV/cm for the C SiC VDMOS device and 6.1 dependence of Eox,max on Vds in the off-state for all three

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Table 2  The performance of the three devices

Parameter DT-SJ SiC C-SJ SiC C SiC

BV (V) 2885 2867 2577

Ron,sp (mΩ cm2) at Vgs = 20 V 1.625 1.642 3.123
FOMmax (MW cm−2) 5122 5006 2094
Eox,max (MV/cm) at Vds = 1700 V 4.79 6.10 6.56
Qg (nC) at Vgs = 20 V 38 64 59
Qgd (nC) 8.75 22.97 21.2

Fig. 8  The circuit used in the gate charge testing for the three devices

Fig. 9  The Vgs–Qg characteristics for the three devices. Wt is 1 μm for

all three devices

devices. It is obvious that the increase of Eox,max with Vds

is much slower than the situations in the other two devices.
Figures 5, 6, and 7 indicate that the DT-SJ SiC VDMOS
device has the lowest Eox,max, which is beneficial for the Fig. 10  The influence of the structural parameters on the perfor-
application reliability of the device. mance of the DT-SJ SiC VDMOS. a Nsj versus the FOM for differ-
Since the gate charge (Qg) plays a significant role in the ent values of Wt; the inset table presents the F ­ OMmax, Nsj,op, BV, and
Ron,sp values in detail. b Wt versus Eox,max and Qg under the condition
switching loss and speed of power MOSFETs, Qg is tested of Nsj = Nsj,op. Eox,max is obtained at a Vds of 1700 V. Qg is calculated
for the C SiC VDMOS, C-SJ SiC VDMOS, and DT-SJ SiC using the same circuit and condition as shown in Figs. 8 and 9
VDMOS devices. The circuit used in this test is shown
in Fig. 8. The device area is set to 5 mm2. The supply
voltage is set to 200 V. The load current is set to 50 A. A DT-SJ SiC VDMOS device exhibits the lowest Qg value of
freewheeling diode (FWD) is used to give a freewheeling 38 nC. For comparison, the Qg value of the C SiC VDMOS
path. A gate current of 50 mA is added to the gate of the and C-SJ SiC VDMOS device is 59 nC and 64 nC, respec-
tested device. Figure 9 illustrates the Vgs–Qg characteris- tively. Because of the DT between the gate and the drain,
tics for the three devices. When tested at V gs = 20 V, the the gate–drain charge (Q gd) is reduced by 58.73 % and

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