UNIT-1

Introduction:

 A microprocessor is the Central Processing Unit (CPU) of a computer, fabricated on a single

silicon chip (Integrated Circuit – IC).

 It is a programmable controlled device capable of processing data.

 A Microprocessor (MP) is the brain of a computer, implemented on a semiconductor silicon
chip.
 The term comes from the combination of two words:
o Micro → extremely small

o Processor → a device that processes (manipulates) binary numbers (0’s and 1’s).

Basic Units of a Microprocessor:

 ALU (Arithmetic Logic Unit)
 Array of registers
 Control Unit
 Flip-Flops
Other Key Points:
 All microprocessors work using Von Neumann architecture.
 Microprocessor operations: fetch, decode, and execute instructions.
 A microprocessor is identified by the size of data it processes at a time.
Bit Size Classification:
 If the ALU performs 8-bit operations → called an 8-bit microprocessor.
 Example: 8085 is an 8-bit microprocessor.
 If the ALU performs 16-bit operations → it’s a 16-bit microprocessor
Bit Size Classification of Microprocessors
 If the ALU performs 8-bit data operations at a time → it is an 8-bit microprocessor.
o Example: 8085 is an 8-bit microprocessor.

 If the ALU performs 16-bit data operations at a time → it is a 16-bit microprocessor.

o Example: 8086 is a 16-bit microprocessor.

Functional Units of a Microprocessor

A microprocessor is connected with three main functional units:
1. Central Processing Unit (CPU)
o ALU (Arithmetic Logic Unit)
 o Registers

o Timing & Control Unit

2. Input and Output Units

3. Memory Unit

Functional Units of a Microprocessor

1. Input Unit
 Used to give input data to the microprocessor.
 Examples: Keyboard, mouse, scanner, etc.
2. Output Unit
 Used to provide the result of calculation/processing.
 Examples: Monitor, printer, etc.
3. Memory Unit
 Used to store data.
 It is bidirectional — can read data from memory and write data into memory.
 Before execution starts, the complete program must be stored in memory.
4. CPU (Central Processing Unit)
 Fetches instructions from memory and decodes them.
 Interprets the instruction/command and generates clock-synchronized control signals for
execution.
 Executes the instructions and repeats the cycle for all instructions until execution is
terminated by hardware or software.
 Data required for execution may come from memory or from input ports.
Clock
 A clock is a square wave signal used to synchronize various devices in the microprocessor
and the overall system.
  Every microprocessor system requires a clock for its functioning.
Bus
 A bus is a group of conducting lines that carries data, address, and control signals.
 Types of buses:
1. Data Bus – Lines that carry data.
2. Address Bus – Lines that carry addresses.
3. Control Bus – Lines that carry control signals.
Features of 8085 Microprocessor
 Introduced in 1976.
 8-bit microprocessor.
 Designed using NMOS technology and manufactured using HMOS technology.
 Contains approximately 6,500 transistors.
 Comes in a 40-pin DIP (Dual-In-Line Package).
 Requires +5V DC supply for operation.
 Clock frequency is about 3 MHz.
  Requires +5V DC supply for operation.
  Clock frequency is about 3 MHz.
  Has an 8-bit data bus (D0–D7) and a 16-bit address bus (A0–A15).
  The lower-order address bus (A0–A7) is multiplexed with D0–D7 data bus, so it requires
external hardware to separate address and data lines.
  Uses a 16-bit address to access memory:
 65,536=64×1024=64K65,536 = 64 \times 1024 = 64K65,536=64×1024=64K memory
locations.
 Since one byte of information can be stored in one memory location, the maximum memory
capacity is 64 KB.
 Can give 8-bit I/O address, i.e., 28=2562^8 = 25628=256.
 Can access 256 input/output ports.
 Provides 5 hardware interrupts:
 TRAP,RST 5.5,RST 6.5,RST 7.5,INTR

Architecture of 8085 microprocessor :

A microprocessor is a small electronic chip (IC) that works as the brain of a computer. It acts as
the Central Processing Unit (CPU) and controls all operations.
The 8085 microprocessor is an 8-bit processor made by Intel in the mid-1970s. It was very
popular in early personal computers because it was simple, easy to use, and low-cost.
The 8085 architecture has important parts like:
 Accumulator
 Registers
 Program Counter
 Stack Pointer
 Instruction Register
 Flags Register
 Data Bus
 Address Bus
 Control Bus
Accumulator –
 An 8-bit register inside the CPU.
 Stores results of arithmetic operations (like addition, subtraction) and logical operations (like
AND, OR, XOR).
 It is the most used register in the 8085 because almost every calculation uses it.
Features of 8085 Microprocessor :

 General Purpose Registers –

 Six registers: B, C, D, E, H, L.
 Can be combined as BC, DE, HL for 16-bit operations.
 Program Counter (PC) –
 16-bit register.
 Stores the address of the next instruction to run.
 Automatically increases after each instruction.
 Stack Pointer (SP) –
 16-bit register.
 Points to the top of the stack (temporary storage in memory).
 Used for storing return addresses and temporary data.
 Instruction Register –
 8-bit register.
 Holds the instruction that is currently being executed.
 Flags Register –
 8-bit register that stores results of operations in the form of flags:
o Carry (CY) – set if a carry is generated.
o Zero (Z) – set if result is zero.
o Sign (S) – set if result is negative.
o Parity (P) – set if result has an even number of 1s.
 Data Bus –
 8-bit, two-way path.
 Transfers data between microprocessor, memory, and devices.
 Address Bus –
  16-bit, one-way path.
 Carries addresses of memory locations and devices.
 Control Bus –
 Carries control signals for processor operations, such as:
o Read (RD) – to get data.
o Write (WR) – to store data.
o Interrupt (INT) – to respond to external events.
o Reset – to restart the processor

8085 is an 8-bit, general-purpose microprocessor. It consists of the following functional units:

Arithmetic and Logic Unit (ALU)

 ALU is the part of the microprocessor that does all the calculations and decision-making.

 It performs:

o Arithmetic operations – addition, subtraction, multiplication, division, increment,

decrement, etc.

o Logical operations – AND, OR, NOT, XOR, etc.

o Bit-shifting operations – shifting bits left or right.

Flag Register

 The Flag Register is an 8-bit register that shows the status of the result after an operation.

 It stores 0 or 1 (OFF or ON) based on the value in the accumulator after the operation.
  Out of 8 bits:

o 5 bits are important for status.

o 3 bits are not used (don’t care).

 It is called a dynamic register because its value changes after every operation.

 It helps to check:

o If the result is zero.

o If the result is positive or negative.

o If there is a carry or overflow.

o For comparisons between numbers.

 It is also called a status register because it shows the condition of the last operation done by
the ALU.

Different Fields in Flag Register

1. Carry Flag (CY) – Set if there is a carry from the most significant bit.

2. Parity Flag (P) – Set if the result has an even number of 1s.

3. Auxiliary Carry Flag (AC) – Set if there is a carry from bit 3 to bit 4 (used in BCD
operations).

4. Zero Flag (Z) – Set if the result is zero.

5. Sign Flag (S) – Set if the result is negative (MSB = 1).

Accumulator

 The accumulator is an 8-bit register used for all arithmetic (add, subtract), logic (AND,
OR, XOR), and I/O operations.

 It is directly connected to the ALU (Arithmetic and Logic Unit) and the internal data bus.

 After most operations, the result is stored in the accumulator.

 It’s often called the heart of the microprocessor because almost every calculation passes
through it.

General Purpose Registers

 There are six general-purpose registers: B, C, D, E, H, L.

 Each holds an 8-bit value.

 They can work in pairs as BC, DE, HL to store 16-bit data.

 Two registers (W and Z) are reserved for internal use (e.g., swapping two 16-bit numbers)
and cannot be directly used for arithmetic.

Program Counter (PC)

 A 16-bit register that holds the address of the next instruction to be executed.
  After fetching an instruction, it automatically increases by 1 to point to the next instruction.

 Example: If PC = 4000H, the next instruction is stored at memory location 4000H.

Stack Pointer (SP)

 A 16-bit register that points to the top of the stack in memory.

 The stack is a special area where data is stored temporarily (for example, during PUSH, POP,
and function calls).

 Unlike the PC, which jumps randomly to instructions, the SP works in a continuous block of
memory.

Temporary Register

 An 8-bit register used only inside the microprocessor.

 It temporarily holds data when performing arithmetic or logic operations.

 Not accessible to the programmer.

Instruction Register and Decoder

 Instruction Register stores the current instruction fetched from memory.

 Decoder interprets the instruction so the microprocessor knows what action to perform.

Timing and Control Unit

 Controls the flow of data between the CPU and other devices.

 Generates control signals like:

o Control signals (Read, Write)

o DMA signals (Direct Memory Access)

o Reset signals (Restart the microprocessor)

o Status signals (Show the current state of the processor)

Interrupt Control

 Interrupts pause the main program to execute a high-priority task.

 After completing the task, control returns to the main program.

 8085 has 5 interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5, INTR.

 Priority order (highest to lowest):

TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR.

1. Address Bus

 Definition: The Address Bus carries the address (location) of memory or I/O device that the
microprocessor wants to access.

 Direction: Unidirectional → Data flows only from the microprocessor to memory or I/O
(because you only send an address, never receive it back).
  Size in 8085: 16-bit

 Capacity: Can address 2^16 = 65,536 memory locations (i.e., 64 KB).

 Example: If the microprocessor wants to store data at memory location 2050H, the Address
Bus will carry 2050H to the memory.

2. Data Bus

 Definition: The Data Bus carries the actual data between the microprocessor, memory, and
I/O devices.

 Direction: Bidirectional → Can send data to memory (Write) and receive data from memory
(Read).

 Size in 8085: 8-bit

 Function: Transfers one byte of data at a time.

 Extra Use: Also used for fetching instructions from memory.

Serial Input/Output Control

 Definition: Serial communication means transferring data one bit at a time instead of one
byte at a time.

 Why Needed: Useful for long-distance or low-pin communication.

In 8085:

 SID (Serial Input Data): Pin used to receive serial data into the microprocessor.

 SOD (Serial Output Data): Pin used to send serial data out of the microprocessor.

 Control Registers:

o Serial Control Register (SC) → Controls how serial communication works.

o Serial Shift Register (SS) → Shifts bits in/out during communication.

 Example: If you connect the 8085 to another microprocessor via SOD, it will send 1 bit at a
time until the full byte is transmitted.

Pin Diagram Of 8085 MicroProcessor:

 The 8085 microprocessor is an 8-bit microprocessor developed by Intel in 1976.

 It has 40 pins, each assigned a specific function for communication with memory,
input/output (I/O) devices, and other system components.

 The 8085 is widely used in microprocessor-based systems for control, computation, and
interfacing applications.

Pin diagram of 8085 microprocessor is shown below:

1. Address Bus and Data Bus

 Address Bus (A8–A15)

o Carries the address of memory or I/O location where data is stored.

o Works in one direction – from microprocessor to memory/I/O.

o Has 8 higher-order lines (A8 to A15).

 Address/Data Bus (AD0–AD7)

o Works in both directions.

o Carries lower-order address in the first clock cycle, then carries data in the next
cycles.

o 8 lines are shared for address and data.

2. Control and Status Signals

 ALE (Address Latch Enable) – Tells when AD0–AD7 are carrying the address (used to
separate address and data).

 IO/M’ – Tells whether the address is for I/O device (1) or memory (0).

 S0, S1 – Show the type of operation (fetch, read, write, halt, etc.).
  RD’ (Read) – Low signal means microprocessor is reading from memory/I/O.

 WR’ (Write) – Low signal means microprocessor is writing data to memory/I/O.

 READY – Checks if device is ready for data transfer. If low, the CPU waits.

IO/M′ S1 S0 Operation / Data Bus Status

0 1 1 Opcode Fetch

0 1 0 Memory Read

0 0 1 Memory Write

1 1 0 I/O Read

1 0 1 I/O Write

1 1 1 Interrupt Acknowledge

0 0 0 Halt

3.Power Supply and Clock

 Vcc – +5V supply.

 Vss – Ground.

 X1, X2 – For connecting crystal oscillator (6 MHz crystal gives 3 MHz CPU speed).

 CLK (OUT) – Gives clock signal to other devices.

7. Serial I/O Ports in 8085

The 8085 microprocessor can send and receive data one bit at a time (serial communication) using
two pins:

 SID (Serial Input Data) → Used to receive data from an external device.

 SOD (Serial Output Data) → Used to send data to an external device.

Features of 8085 Microprocessor

1. 8-bit Processor → Can work with 8 bits of data at a time.

2. 16-bit Address Bus → Can access up to 64 KB memory.

3. 5 MHz Clock Speed → Enough for small/basic operations.

4. Low Power Use → Good for battery-powered devices.

5. Interrupt System → Has 5 pins to respond to outside signals quickly.

Limitations of 8085 Microprocessor

1. Memory Limit → Can only use 64 KB memory (because of 16-bit address bus).

2. No Multiprocessing → Cannot use more than one processor together.

3. Limited Instructions → Only 50 instructions, so not good for complex work.

 4. No DMA Support → Cannot directly move data between memory and devices; this makes it
slower.

5. Low Speed → Only 5 MHz, much slower than modern processors.

4. Interrupts and Peripheral Signals

 INTR – General interrupt request from external device.

 RST 7.5, RST 6.5, RST 5.5 – Vectored interrupts (fixed service locations) with priority.

 TRAP – Highest priority, non-maskable interrupt.

 INTA’ – CPU sends this signal to acknowledge an interrupt.

Other control signals:

 RESET – Restarts CPU, program counter set to 0.

 HOLD – Another device requests control of bus.

 HLDA – CPU says “OK” and gives control of bus.

5. DMA (Direct Memory Access) Signals

 HOLD – Request from device to use buses.

 HLDA – Acknowledgement from CPU that buses are free.

Serial I/O Ports in 8085

The 8085 microprocessor can send and receive data one bit at a time (serial communication) using
two pins:

 SID (Serial Input Data) → Used to receive data from an external device.

 SOD (Serial Output Data) → Used to send data to an external device.

Features of 8085 Microprocessor

1. 8-bit Processor → Can work with 8 bits of data at a time.

2. 16-bit Address Bus → Can access up to 64 KB memory.

3. 5 MHz Clock Speed → Enough for small/basic operations.

4. Low Power Use → Good for battery-powered devices.

5. Interrupt System → Has 5 pins to respond to outside signals quickly.

Limitations of 8085 Microprocessor

1. Memory Limit → Can only use 64 KB memory (because of 16-bit address bus).

2. No Multiprocessing → Cannot use more than one processor together.

3. Limited Instructions → Only 50 instructions, so not good for complex work.

4. No DMA Support → Cannot directly move data between memory and devices; this makes it
slower.
 5. Low Speed → Only 5 MHz, much slower than modern processors.

Memory Organization :
The 8085 microprocessor has 16 address lines, so it can access up to 64 KB of memory.
This 64 KB can be provided by one large memory chip or several smaller memory chips combined.

The main operations with memory are:

 Memory Read – reading data from memory

 Memory Write – writing data to memory

To perform these operations, we connect the RD′ (Read) and WR′ (Write) signals from the
microprocessor to the matching RD′ and WR′ pins on the memory chip.
These signals can also be produced by external logic circuits if needed.

The figure shows the signals and pins of a typical 64-byte memory chip. These signals include:

 6 address lines – because 26=642^6 = 6426=64, these lines select the memory location.

 8 data lines – used to transfer 8-bit data between the microprocessor and memory.

 Control lines – RD′ (Read), WR′ (Write), and CS (Chip Select).

Types of Memory Addressing

The way address lines are used in chip selection and memory access can be of two types:

1. Full (Absolute) Addressing

2. Partial Addressing

1.Absolute or Full Address Decoding

In this method, all address lines from the microprocessor are used for interfacing with the
memory chip.
This allows the maximum possible memory (64 KB) to be connected to the 8085.
 Example:
If we want to connect a 16 KB memory chip using absolute addressing, all address lines will be
connected so that the processor can uniquely identify every location in that 16 KB memory.

2. Partial Address Decoding

This method is used when we connect a memory chip smaller than 64 KB.

In this case, not all address lines of the microprocessor are connected to the memory chip.
Some address lines are left unconnected (not used) for chip selection — that’s why it is called
partial decoding.

Partial decoding is simpler and needs fewer hardware components, but it may cause the same
memory chip to appear at multiple address ranges (called memory mirroring).

Address Mapping in 8085

Address mapping means finding the starting and ending addresses of memory chips in a system.
We do this using:
 Chip Select (CS) lines – to choose which memory chip will be active.
  Address lines – connected directly to the memory chip to access locations inside it.
Example:
If we have four memory chips, each 16 KB in size, we can connect them to make a 64 KB total
memory system.
 The chip select pins of the memory chips are connected to the output of a 2×4 decoder.
 The decoder takes A15 and A14 (two higher address lines from the microprocessor) as input.
 Based on these two bits, the decoder activates one chip at a time.
 Inside each chip, the remaining address lines are used to access data.
I/O Ports & Interfacing:

 Interface: A communication path between two components (e.g., a microprocessor and an

I/O device).

 Interfacing: The method of connecting these two components so they can exchange data.
 In the example, we are interfacing an I/O device with the 8085 microprocessor.
o One component = Microprocessor (µP)

o Other component = I/O device

 Ports are connection points through which this communication happens.

2. Two Ways to Interface I/O with a Microprocessor
 1. Peripheral Mapped I/O
2. Memory Mapped I/O
Peripheral Mapped I/O
 In Peripheral Mapped I/O, the I/O devices are treated only as I/O devices, not as part of
memory.
 They are considered as ordinary I/O ports.
 Data transfer:
o Read data from I/O device to microprocessor.

o Write data from microprocessor to I/O device.

 Control Signals are needed for read/write operations:

o IO/M (I/O or Memory select)

o RD (Read)

o WR (Write)

 These signals are combined to create two main control signals:

o IOR (I/O Read) → Used to read data from I/O device.

o IOW (I/O Write) → Used to write data to I/O device.

4. Signal Combination
 IOR = Combination of IO/M and RD
(Tells µP to read from an I/O port)
 IOW = Combination of IO/M and WR
(Tells µP to write to an I/O port)
Control Signal Formation
 IO/M and RD combine to make IOR
→ Used for Read Operation from an I/O device.
 IO/M and WR combine to make IOW
→ Used for Write Operation to an I/O device.
2. Status of Control Signals
There’s a truth table showing the combination of signals:

IO/M RD WR IOR IOW Operation

0 0 1 0 1 Memory Read

1 0 1 1 0 I/O Read

1 1 0 0 1 I/O Write

(Note: The handwritten table shows specifically the combinations for I/O Read and I/O
Write.)
  For I/O Read, IO/M = 1, RD = 0, WR = 1 → IOR activated.
 For I/O Write, IO/M = 1, RD = 1, WR = 0 → IOW activated.
3. Instructions to Access I/O Ports
The 8085 uses two instructions for I/O operations:
1. IN – Used to access an input port
o Syntax: IN port_address

o Example: IN 01H → Reads data from input port 01H into the accumulator.

2. OUT – Used to access an output port

o Syntax: OUT port_address

o Example: OUT 02H → Sends data from the accumulator to output port 02H.

4. Addressing in Peripheral Mapped I/O

 In Peripheral Mapped I/O, only 8-bit addresses are used for ports.
 That means:
o 2⁸ = 256 input devices can be connected.

o 256 output devices can be connected.

 Both input and output devices can be interfaced simultaneously with the microprocessor.
2. Memory Mapped I/O
 In this method, each I/O device is treated like a memory location.
 Just like memory locations are accessed with a 16-bit address, I/O devices in this method are
also given 16-bit addresses.
 This means an I/O device is addressed just like memory, using the same instructions and
addressing mode.

2. Control Signals
 Instead of IOR and IOW (Peripheral Mapped I/O), here the signals are:
o MEMR → Memory Read

o MEMW → Memory Write

 How they are formed:

o IO/M = 0 and RD = 0 → MEMR (Read operation)

o IO/M = 0 and WR = 0 → MEMW (Write operation)

3. Truth Table for Signals

IO/M RD WR MEMR MEMW Operation

0 0 1 1 0 Read

0 1 0 0 1 Write

(In this method, IO/M = 0 means it’s treated like a memory operation.)

4. Instructions Used
 Since the I/O devices are treated like memory:
o You use memory-related instructions (e.g., LDA, STA, MOV M,A, etc.) to access
them.
 No special IN or OUT instructions are required.

5. Memory Sharing
 In Memory Mapped I/O, the total memory space of the microprocessor (e.g., 64 KB in the
8085) is shared between:
o Regular memory

o I/O devices

 This means I/O devices reduce the available memory for program/data storage.
 In Peripheral Mapped I/O, the full memory (64 KB) is available for memory use because
I/O devices are in a separate address space.
Data Transfer concepts:

In a computer system, data transfer means moving data between different

components like:

 Microprocessor (CPU)
 Memory (RAM/ROM)
 I/O Devices (input/output like keyboard, printer, etc.)
From the diagram:
 The microprocessor can communicate with both memory and I/O devices to transfer data.
 Data can move between any two of these units.

Factors Affecting Data Transfer

The method of data transfer depends on:
1. Character of data – Is it text, binary numbers, or signals?
2. Addressing of the device – Which device is being accessed?
3. Amount of data – Small chunks (bytes/words) or large blocks?
4. Method of transfer – Parallel or serial transfer.
5. Interaction among devices – Whether the devices can directly communicate or need CPU
involvement.

Types of Data Transfer Methods

Based on addressing modes and device characteristics, data transfer can be divided mainly into:
1. Parallel Data Transfer
o Multiple bits are sent simultaneously over multiple lines.

o Example: In 8085 microprocessor, 8 bits are transferred together using 8 separate

data lines.
o Advantage: Fast transfer.

o Disadvantage: Expensive (more wires needed) and not suitable for long-distance
communication.
2. Serial Data Transfer
o Bits are transferred one after another over a single line.

o Advantage: Cheaper, suitable for long distances.

o Disadvantage: Slower than parallel transfer.

1. Parallel Data Transfer

 In this method, multiple bits are transmitted at the same time using multiple parallel lines.
 Example: In 8085 microprocessor, 8 bits (1 byte) are transferred together using 8 parallel
data lines.
 Advantage → Fast transfer rate (all bits move at once).
 Disadvantage → Requires more lines (costly), not good for long distances (signal distortion).

Types of Parallel Data Transfer

There are 3 types:
a) Programmed I/O Parallel Data Transfer
 The processor continuously checks if the I/O device is ready by looking at the READY
signal.
 If READY = HIGH, the processor sends data to the device.
 If not, the processor keeps checking again and again.
 Drawback → Wastage of processor time (busy waiting or “polling”).
 b) Interrupt I/O Parallel Data Transfer
 Here, the I/O device itself informs (interrupts) the processor when it is ready for data using
an INTR (Interrupt Request) signal.
 Processor temporarily pauses its normal work, transfers data to the I/O device, and then
resumes its task.
 Advantage → Processor is free to do other work instead of constantly checking device status.

c) DMA (Direct Memory Access) Parallel Data Transfer

 DMA = Direct Memory Access.
 In this method, the I/O device directly transfers data to memory without involving the
processor for each byte/word.
 Processor only gives initial permission to DMA controller and then is free for other tasks.
 Advantage → Very fast and efficient for large data transfer (like disk to RAM).
c) DMA (Direct Memory Access)
 DMA = Direct Memory Access.
 Using DMA, I/O devices can transfer data directly to memory without needing the
processor for each step.
 The DMA controller uses the address and data buses of the processor to complete the
transfer.
 This makes bulk data transfer (like from hard disk to RAM) much faster and frees the
CPU to do other tasks.

2. Serial Data Transfer

 Definition: In serial data transfer, data is transmitted one bit at a time (bit-by-bit) through a
single communication line.
 Opposite of parallel transfer (where all bits are sent together).
 Advantages:
o Requires fewer lines (cheaper).

o Suitable for long-distance communication (less interference).

 Disadvantages:
o Slower compared to parallel transfer (since only one bit goes at a time).

Examples:
 USB, UART (used in microcontrollers), RS-232, etc.

Interrupts in 8085 Microprocessor :

  In the 8085 microprocessor, an interrupt is a signal that temporarily stops the main program.

 Control is transferred to a special routine called the Interrupt Service Routine (ISR).
 Interrupts are generated by external devices or peripherals, such as keyboards, timers, or
sensors.
 They request immediate attention from the processor.
 When an interrupt occurs, the microprocessor acknowledges the request.
 The processor executes the ISR to handle the event.
 After execution, control returns to the main program from where it was interrupted.
 Interrupts allow the system to respond promptly to external events without constantly
checking devices.
 This improves efficiency and ensures timely handling of critical tasks.
Types of Interrupt Signals in 8085 Microprocessor
1. TRAP
o Non-maskable interrupt (cannot be disabled).

o Highest priority.

o Generated by critical external events, e.g., power failure or hardware malfunction.

2. RST 7.5
o Maskable interrupt (can be disabled).

o Second highest priority.

o Can be triggered by software or peripherals.

3. RST 6.5
o Maskable interrupt.

o Third highest priority.

o Generated by software or peripherals.

4. RST 5.5
o Maskable interrupt.

o Fourth highest priority.

o Generated by software or peripherals.

5. INTR
o Maskable interrupt.

o Lowest priority.

o Generated by external devices like keyboard or mouse.

How Interrupts Work
1. When an interrupt signal is received, the microprocessor stops the current program.
2. It transfers control to a subroutine (Interrupt Service Routine) using the CALL instruction.
3. After executing the ISR, control returns to the main program using the RET instruction.
4. The microprocessor sends an acknowledgment signal (INTA) to the requesting peripheral.
Classification of Interrupts
1. Hardware vs Software Interrupts
o Hardware Interrupts: Received via microprocessor pins. Examples: INTR, RST
7.5, RST 6.5, RST 5.5, TRAP.
o Software Interrupts: Inserted in the program as instructions. Examples: RST 0, RST
1, … RST 7.
2. Vectored vs Non-Vectored Interrupts
Vectored Interrupts: Have a fixed starting address (vector address) for ISR. Examples: TRAP,
RST 7.5, RST 6.5, RST 5.5.
 Vector Address Formula:
Vector Address=8×TYPE\text{Vector Address}
(TYPE = RST number)
o Non-Vectored Interrupts: Do not have a fixed address. Example: INTR. External
hardware provides ISR address.

INTERRUPT VECTOR ADDRESS

TRAP (RST 4.5) 24 H

RST 5.5 2C H

RST 6.5 34 H

RST 7.5 3C H

For Software interrupts vector addresses are given by:

INTERRUPT VECTOR ADDRESS

RST 0 00 H

RST 1 08 H

RST 2 10 H

RST 3 18 H

RST 4 20 H

RST 5 28 H

RST 6 30 H

RST 7 38 H

Maskable and Non-Maskable Interrupts in 8085

1. Maskable Interrupts
o Can be disabled or ignored by the microprocessor.

o May be edge-triggered or level-triggered.

o Examples in 8085: INTR, RST 7.5, RST 6.5, RST 5.5.

2. Non-Maskable Interrupts
o Cannot be disabled or ignored by the microprocessor.

o Consists of both level and edge triggering.

o Example in 8085: TRAP.

o Used for critical events, e.g., power failure.

Priority of Interrupts
 When multiple interrupts occur simultaneously, the microprocessor executes the Interrupt
Service Routine (ISR) based on priority.
  Highest Priority → Lowest Priority:
1. TRAP (Non-maskable)
2. RST 7.5
3. RST 6.5
4. RST 5.5
5. INTR

Instructions for Interrupts in 8085

1. Enable Interrupt (EI)
o Sets the interrupt enable flip-flop, allowing all interrupts to be enabled.

o Takes effect after the next instruction executes.

o No flags are affected.

o After a system reset, interrupts are disabled, so EI is needed to enable them (except
TRAP).
2. Disable Interrupt (DI)
o Resets the interrupt enable flip-flop, disabling all interrupts.

o No flags are affected.

o Useful to temporarily prevent interrupts during critical sections of a program.

3. Set Interrupt Mask (SIM)

o Used to control hardware interrupts: RST 7.5, RST 6.5, RST 5.5.

o Allows setting masks to enable/disable specific interrupts.

o Can also generate output data through the Serial Output Data (SOD) line.

o Process: Load the required bit pattern into the accumulator, then execute SIM to
apply it.
  Reads interrupt mask status: Loads an 8-bit value into the accumulator showing the mask
status and pending requests for RST 7.5, RST 6.5, and RST 5.5. Monitors SID line: Reads the
condition of the Serial Input Data (SID) bit of the microprocessor. No flags affected:
Executing RIM does not change any processor flags.

Uses of Interrupts in 8085

1. Real-time processing:
o Allows quick response to external events like user input or hardware signals.

o Useful in time-critical applications such as control systems and data acquisition.

2. Multi-tasking:
 o Enables switching between tasks by temporarily suspending the current task to
execute the ISR.
o Maximizes system resource utilization.

3. Input/Output operations:
o Handles data transfer between the microprocessor and external devices.
o Lets the processor do other tasks while waiting for I/O operations to finish.
4. Error handling:
o Detects and recovers from hardware or software errors through interrupts.
5. Power management:
o Can put the processor into low-power mode when idle and wake it up on an interrupt.

8086 Architecture
Main Features:

 Introduced by Intel in 1978 – marked a milestone in computing history.

 First x86 architecture microprocessor, forming the base for modern CPUs.
 16-bit processor – can process 16 bits of data in a single cycle.
 Played a crucial role in the evolution of personal computers.
 16-bit Architecture – Can process 16 bits of data at a time; improved performance over
8085.
 16-bit Data Bus – Transfers 8 or 16 bits of data between processor, memory, and I/O.
 20-bit Address Bus – Can directly access 220=12^{20} = 1220=1 MB of memory; each
address stores 1 byte.
 16-bit I/O Addresses – Supports up to 216=65,5362^{16} = 65,536216=65,536 I/O ports for
peripheral communication.
 Registers – Fourteen 16-bit registers:
 General Purpose: AX, BX, CX, DX
 Segment: CS, DS, SS, ES
 Special Purpose: SP, BP, SI, DI, IP
 Flag Register – Contains conditional & control flags.
 Multiplexed Address/Data Bus (AD0–AD15) – Reduces pin count; slightly slows data
transfer.
 Clock Speed – Requires single-phase clock (33% duty cycle). Variants: 8086 (5 MHz), 8086-
2 (8 MHz), 8086-1 (10 MHz).
 Operating Modes –
 Minimum Mode: Single processor (MN/MX = 1)
 Maximum Mode: Multiprocessor systems (MN/MX = 0)
 Instruction Prefetching – Can prefetch up to 6 bytes of instructions to speed execution.
 Multiprogramming – Stores and executes multiple processes in a time-shared manner.
 Powerful Instruction Set – Supports multiple addressing modes: register, immediate, direct,
indirect, relative, implied.
 Arithmetic & Logical Operations – Performs add, subtract, multiply, divide, AND, OR,
NOT, XOR on bits, bytes, words, and blocks.
 Packaging – Available in a 40-pin ceramic or plastic DIP package.
 Power Supply – Operates on a +5V power supply.
 Memory Addressing – Byte-addressable memory for efficient storage and access.
Architecture of 8086 :
The 8086 microprocessor, developed by Intel in the late 1970s, is the first member of the
x86 family and is based on CISC architecture. It has a 20-bit address bus capable of addressing 1 MB
of memory and a 16-bit data bus for data transfer. It uses segmented memory architecture, dividing
memory into segments addressed by a segment register and an offset. The 8086 consists of two main
units: the Bus Interface Unit (BIU) for fetching and decoding instructions, and the Execution Unit
(EU) for executing them. It contains 14 internal registers, including general-purpose, segment, and
special registers, each 16 bits wide. Packaged in a 40-pin DIP, it requires external RAM/ROM and
supports pipelining for faster processing.

 Internal architecture is divided into two main units:

1. Bus Interface Unit (BIU)
2. Execution Unit (EU)

1. Bus Interface Unit (BIU)

Purpose: Connects 8086 to memory and I/O devices; handles instruction fetching and data transfers.
Main Functions:
1. Generates physical addresses using:
Physical Address=(Segment Address×10H)+Offset\text{Physical Address} = (\text{Segment
Address} \times 10H) + \text{Offset}Physical Address=(Segment Address×10H)+Offset
2. Fetches instructions from memory into the 6-byte prefetch queue (supports pipelining).
3. Transfers data to/from memory and I/O.
Key Components:
 Segment Registers (16-bit):
o CS (Code Segment) – base address of program instructions.

o DS (Data Segment) – base address of program data.

o SS (Stack Segment) – base address of stack.

o ES (Extra Segment) – base address for additional data.

  Instruction Pointer (IP) – holds offset of the next instruction in CS.
 Address Generation Circuit – calculates 20-bit addresses.
 6-byte Prefetch Queue – stores fetched instructions ahead of execution.

2. Prefetch Unit
 Fetches several instructions ahead of execution and stores them in the queue.
 Improves speed by allowing execution while the next instruction is already being fetched.
 Queue is flushed when a branch/jump occurs.
 Works in parallel with the Execution Unit.

3. Execution Unit (EU)

Purpose: Executes instructions fetched by the BIU.
Main Functions:
 Takes instructions from the prefetch queue.
 Decodes them and executes using the ALU (Arithmetic Logic Unit).
 Sends control signals for data transfer.
Components:
 General Purpose Registers (16-bit): AX, BX, CX, DX (each split into high and low bytes,
e.g., AH/AL).
 Special Purpose Registers: Stack Pointer (SP), Base Pointer (BP), Source Index (SI),
Destination Index (DI).
 Instruction Register – holds current instruction.
 Instruction Decoder – decodes opcodes for execution.
 Flag Register (16-bit):
o Status Flags – CF, PF, AF, ZF, SF, OF.

o Control Flags – TF, IF, DF.

4. Decode Unit
 Translates machine code into micro-operations.
 Handles complex instructions like jumps, loops, calls, returns.

5. Control Unit
 Coordinates all operations inside the CPU.
  Controls fetching, decoding, executing, and managing interrupts.
 Ensures correct sequence of operations.

6. Buses in 8086
 Address Bus – 20 bits (addresses memory locations).
 Data Bus – 16 bits (transfers data).
 Control Bus – sends control signals (Read, Write, Interrupt, etc.).
Instruction Fetch & Execution in 8086 (Pipelining Concept)
 Physical Address Calculation
 Instructions are stored in memory.
 To fetch an instruction, the Bus Interface Unit (BIU) uses Segment Registers + Instruction
Pointer (IP) to calculate the physical address.
 Instruction Fetch
 BIU fetches the instruction from memory using the calculated address.
 Instruction is stored in the Instruction Pre-fetch Queue (FIFO method).
 Example:
 MOV AX, BX → 1-byte instruction → occupies 1 block in queue.
 MOV BX, 4050H → 3-byte instruction → occupies 3 blocks in queue.
 Instruction Decode
 When it’s the turn of an instruction, it is sent to the Execution Unit (EU).
 The Control Unit decodes it into opcode and decides the operation.
 Execution
 EU fetches data from General Purpose Registers (GPRs).
 ALU performs operations like ADD, SUB, MUL, DIV.
 Flags in the Flag Register change accordingly.
 Parallel Processing (Pipelining)
 While EU is decoding/executing one instruction, BIU is already fetching the next.
 This parallelism improves speed compared to 8085 (where fetch–decode–execute happens
sequentially).

 Advantages of 8086 Architecture

 Wide Range of Instructions → Can perform various complex operations.
  Segmented Memory Architecture → Can address up to 1 MB memory using 16-bit bus.
 Powerful Instruction Set → Reduces number of instructions needed.
 Two Units (BIU + EU) → Improves speed with pipelining.
 Rich Set of Registers → Faster data manipulation.
 Backward Compatibility → Can run programs of older 8-bit processors.

 Disadvantages of 8086 Architecture

 Complex Programming → Requires assembly language knowledge.
 Difficult Memory Management → Segmented memory requires segment + offset
addressing.
 Limited Performance → Slower clock speed compared to modern CPUs.
 Limited Instruction Set → Lacks some advanced features.
 Limited Memory Addressing → Only up to 1 MB.
 No Built-in Modern Features → No hardware floating-point or virtual memory.
Pin Diagram:

The Intel 8086 is a 16-bit HMOS microprocessor packaged in a 40-pin DIP and operates on a 5V DC
supply. It has a 20-line address bus (allowing it to address up to 1 MB memory) and a 16-line data
bus. The address bus operates in multiplexed mode, meaning some lines are shared between address
and other signals.
 AD0–AD15 (Address/Data Bus): Low-order address lines multiplexed with data lines. When
carrying addresses, they are labeled A0–A15; when carrying data, they are labeled D0–D15.
 A16–A19: High-order address lines multiplexed with status signals.
 S2, S1, S0 (Status Pins): Indicate the type of operation (memory or I/O). These are used by
the 8288 bus controller to generate control signals for read/write operations. Changes in these
signals mark the start of a bus cycle.

S
S2 S1 0 Characteristics

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive state

A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with corresponding
status signals.

A17/S4 A16/S3 Function

0 0 Extra segment access

A17/S4 A16/S3 Function

Stack segment
0 1
access

1 0 Code segment access

1 1 Data segment access

 BHE’/S7 (Bus High Enable / Status)

 During T1, BHE’ is low to enable data transfer on the upper half of the data bus (D8–D15).
 Used for 8-bit devices connected to upper half of data bus.
 Multiplexed with status signal S7 (available during T2, T3, T4).
 RD’ (Read)
 Output signal, active low.
 Indicates read operation from memory or I/O.
 READY
 Input signal, active high.
 Sent by memory/slow device to indicate data transfer completion.
 Synchronized by 8284A clock generator.
 INTR (Interrupt Request)
 Input signal, active high.
 Checked at the end of each instruction.
 If enabled and request is pending, processor executes interrupt acknowledge cycle.
 Can be masked by software.
 NMI (Non-Maskable Interrupt)
 Edge-triggered input, active on low-to-high transition.
 Cannot be masked by software.
 Causes a Type II interrupt.
 INTA’ (Interrupt Acknowledge)
 Output signal, active low during T2, T3, Tw of interrupt acknowledge cycle.
 MN/MX’ (Minimum/Maximum Mode)
  Indicates mode of operation: Minimum mode (single processor) or Maximum mode
(multiprocessor).
 RQ’/GT1’, RQ’/GT0’ (Request/Grant)
 Bi-directional pins used by bus masters to request control of the local bus.
 RQ’/GT0’ has higher priority than RQ’/GT1’.
 LOCK’
 Active low output.
 Prevents other bus masters from taking control of system bus until next instruction completes.
 TEST’
 Used with WAIT instruction.
 If TEST’ is low, execution continues; otherwise, processor stays idle.
 CLK (Clock Input)
 Basic timing signal for processing and bus control.
 Asymmetric square wave, 33% duty cycle.
 RESET
 Active high for at least 4 clock cycles.
 Forces processor to stop current task and restart.
 Vcc – +5V DC power supply.
 GND – Ground.

QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction queue
according to the table shown below:

QS
QS1 0 Status

0 0 No operation

0 1 First byte of op code from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

M/IO′ (Memory/Input-Output Select)

  Distinguishes between memory and I/O operations.
 High → Memory operation; Low → I/O operation.
DT/R (Data Transmit/Receive)
 Used with data bus transceivers (e.g., 8286/8287).
 Controls direction of data flow.
DEN (Data Enable)
 Output enable signal for transceivers (8286/8287).
 Active low during memory, I/O, and INTA cycles.
HOLD / HLDA (Hold / Hold Acknowledge)
 HOLD: Indicates another device is requesting control of the bus.
 HLDA: Sent by CPU to acknowledge and release the bus.
ALE (Address Latch Enable)
 Latches the address into an external latch (8282/8283).
 Active high pulse during T1 of any bus cycle.
Interrupts and Interrupt response:
 Definition:
An interrupt is a signal that temporarily stops the execution of the current program so the
microprocessor can handle a different task.
When an interrupt occurs, the CPU executes an ISR (Interrupt Service Routine) — a small
program that tells the CPU how to handle the event.

1. Purpose of interrupts
 o Sometimes the microprocessor needs to automatically execute special routines
when certain conditions occur.
o Example: Responding to a keyboard press or a sensor signal.

o These routines are stored in the microprocessor system and run whenever the device
requests service.
2. Two main ways to service devices
o Polling Method

o Interrupt Method

Polling Method
 The processor checks each device one by one to see if it needs attention.
 This checking is repeated continuously (polling cycle).
 Disadvantage: Wastes time and reduces system performance because the CPU is busy
checking instead of doing useful work.

Interrupt Method
 The processor runs its main program normally and only stops when a device signals it needs
service.
 The device sends an interrupt signal to the processor.
 The CPU temporarily stops the current program, runs a special routine (ISR – Interrupt
Service Routine), then returns to where it left off.
 Advantages:
o More efficient than polling.

o Increases system throughput (less wasted CPU time).

Sources of Interrupts
An 8086 can be interrupted in three main ways:
1. By External Signal
o An outside device sends a signal to the NMI (Non-Maskable Interrupt) pin or the
INTR (Maskable Interrupt) pin.
o Example: Keyboard or other hardware sending a request.

2. By Special Instruction
o The program itself contains an INT instruction to trigger an interrupt.

o This is called a software interrupt.

3. By Condition in the Program

 o An interrupt happens automatically when a certain condition occurs.

o Example: Division by zero causes the CPU to interrupt the program.

Hardware vs. Software Interrupts

 Hardware Interrupt: Triggered by an external signal.
 Software Interrupt: Triggered by instructions or specific conditions in the code.

Other Classifications
1. Vectored and Non-Vectored Interrupts
o Vectored: The ISR (Interrupt Service Routine) address is fixed in memory.

o Non-Vectored: The ISR address is not fixed; it must be supplied externally or

determined at runtime.
2. Maskable and Non-Maskable Interrupts
o Maskable: Can be ignored (disabled) by the CPU.

o Non-Maskable: Cannot be ignored and must be serviced immediately.

8086 Interrupt Handling Steps

When an interrupt occurs, the CPU:
1. Pushes the flag register onto the stack (after decrementing stack pointer by 2).
2. Disables further maskable interrupts by clearing the Interrupt Flag (IF).
3. Resets the Trap Flag (TF) to prevent single-stepping.
4. Pushes the Code Segment (CS) register onto the stack.
5. Pushes the Instruction Pointer (IP) register onto the stack.
6. Jumps to the ISR by loading CS and IP with the address of the interrupt routine.
Returning from an Interrupt
 At the end of an ISR, the IRET (Interrupt Return) instruction is used.
 IRET restores:
1. IP (Instruction Pointer)
2. CS (Code Segment)
3. Flags register
 This returns control back to the exact point in the main program where the interrupt occurred.

2. 8086 Interrupt Response Process

When an interrupt occurs:
Step-by-step (based on the diagram)
1. Mainline Program:
o Normal program execution is happening.

2. Interrupt Service Procedure Begins:

o Push Flags onto the stack.

o Clear IF (Interrupt Flag) — disables further maskable interrupts.

o Clear TF (Trap Flag) — stops single-step mode.

o Push CS onto the stack.

o Push IP onto the stack.

o Fetch the ISR address from memory.

 3. Interrupt Service Routine Executes.
4. Returning to Main Program (IRET):
o Pop IP from stack.

o Pop CS from stack.

o Pop Flags from stack.

o Resume execution from where the interrupt happened.

3. Interrupt Vector Table (IVT)

 The 8086 stores ISR starting addresses in a fixed memory area called the Interrupt Vector
Table (also called Interrupt Pointer Table).
 Location: First 1 KB of memory (addresses 00000H to 003FFH).
 Each entry = 4 bytes:
o 2 bytes for IP (offset address)

o 2 bytes for CS (segment address)

4. Capacity of the IVT

 Since each interrupt requires 4 bytes,
1024 bytes/4 bytes=256 possible interrupts1024\ \text{bytes} / 4\ \text{bytes} = 256\ \text{possible
interrupts}1024 bytes/4 bytes=256 possible interrupts
 This means 8086 supports up to 256 interrupts (numbered 0 to 255, or "Type 0" to "Type
255").
Memory Layout Example
 Type 0 interrupt → Address stored at 00000H to 00003H
 Type 1 interrupt → Address stored at 00004H to 00007H
 …and so on, up to Type 255 at 003FCH–003FFH.
. Interrupt Numbering and Addressing
 Every interrupt is assigned a number 0 to 255.
 The address of the interrupt’s ISR is found by:
Address=Interrupt Type×4\text{Address} = \text{Interrupt Type} \times 4Address=Interrupt Type×4
Example: Type 11 → 11×4=4410=2CH11 \times 4 = 44_{10} = 2C_{H}11×4=4410=2CH → Address
= 0002CH.
 Only the first five types (0–4) have predefined purposes.
 Types 5–31 are reserved by Intel for future use.
 Types 32–255 are available for user-defined hardware or software interrupts.
 On an interrupt, the 8086 goes to the Interrupt Vector Table, fetches the CS:IP, and starts the
ISR.

2. Predefined 8086 Interrupt Types

1. Type 0 – Divide by Zero
Triggered when a DIV or IDIV result doesn’t fit in the destination register.
2. Type 1 – Single Step
Used in single-step mode for debugging. Executes one instruction, then stops so the user can
inspect system state.
3. Type 2 – Non-Maskable Interrupt (NMI)
Cannot be disabled by software. Triggered by a low-to-high signal on the NMI pin.
 4. Type 3 – Breakpoint
Triggered by the INT 3 instruction, used for debugging and breakpoints.
5. Type 4 – Overflow
Triggered after signed arithmetic overflow when the OF (overflow flag) is set.

3. Software Interrupts (Type 0–255)

 Generated using the INT n instruction (where n is the interrupt type number).
 Example: INT 2 → Calls the Type 2 ISR.
 Can also be used to test the NMI routine without hardware.

4. Maskable Interrupt (INTR)

 Generated by external hardware devices.
 Can be enabled or disabled by the Interrupt Flag (IF).
 Used for general-purpose interrupting of program execution.
System Bus Timing in 8086 Microprocessor :

The 8086 microprocessor uses a system bus timing method to communicate with memory and
I/O devices in an organized way. This timing is controlled by a clock signal and divided into small time
intervals called T-states.

1. Clock Signal
 A single-phase clock signal (CLK) controls all operations.
 Common speeds: 5 MHz, 8 MHz, and 10 MHz.
 The clock speed decides how fast the processor works.

2. Bus Cycle (Machine Cycle)

 A bus cycle is the time taken to access memory or I/O devices.
 One bus cycle = 4 clock periods: T1, T2, T3, T4.
 In a 5 MHz 8086:
o One clock period = 200 ns

o One bus cycle = 800 ns (200 ns × 4)

3. T-State Functions
T1
  Address is placed on the address bus.
 ALE (Address Latch Enable) signal is activated to store the address.
T2
 Address bus goes into high-impedance state.
 For write → Data appears on data bus.
For read → Read signal is activated.
 READY signal checked at end of T2. If low → Wait state added.
T3
 Read cycle → Data is ready to be read.
Write cycle → Data stays on the bus.
T4
 Read cycle → Data is taken into CPU.
Write cycle → Data is sent to memory/I/O.

4. Wait States (Tw)

 Extra time given if memory or I/O devices are slow.
 Inserted between T2 and T3 when READY = Low.

5. Timing Diagram
 Shows signals and timings during bus cycles.
 Used for designing and debugging 8086 systems.
Minimum mode configuration of 8086 microprocessor:

 The 8086 works in minimum mode when MN/MX' = 1. In this mode, 8086 is the only
processor in the system and generates all the control signals needed for memory operations
and I/O interfacing.
 The circuit design is simple but does not support multiprocessing.
 Other components in the system include transceivers, latches, 8284 clock generator, 74138
decoder, memory, and I/O devices.
 The address bus is 20 bits long, allowing access to 2²⁰ bytes = 1 MB memory.
 Multiplexing is used:
 A0–A15 are multiplexed with the data bus (address in T1, data in remaining T-states).
 A16–A19 are multiplexed with status lines S3–S6.
 BHE' is multiplexed with S7.
 Control signals from 8086 determine:
 Whether the bus carries a valid address.
 Direction of data transfer.
 When write data is valid.
 When to place read data on the system bus.
 The correct sequence of these signals ensures all operations occur successfully within a
machine cycle.
8282 (8-bit Latch)
 The 8282 latch is a buffered D-type flip-flop.
 Purpose: To separate the valid address from the multiplexed Address/Data bus (AD0–
AD15).
 Control Signal:
o ALE (Address Latch Enable) → Connected to STB (Strobe) of 8282.

o ALE is an active-high signal.

o When ALE = 1 → Address is latched and stored in 8282.

 Since the 8086 address bus is 20 bits (A0–A19), we need 3 latches (8282 × 3 = 24 bits
capacity, but only 20 used).

8286 (8-bit Transceiver)

 The 8286 transceiver is a bidirectional buffer (also called data amplifier).
 Purpose: To separate valid data from the multiplexed Address/Data bus (AD0–AD15).
 Since the data bus in 8086 is 16 bits, we require 2 transceivers (8286 × 2 = 16 bits).
 Control Signals:
o DEN' (Data Enable, active low): Enables the transceiver.

o DT/R' (Data Transmit/Receive, active low): Controls direction of data.

  DT/R' = 1 → Data flows from processor → external bus (Transmit).
 DT/R' = 0 → Data flows from external bus → processor (Receive).
o Connections: DT/R' → T and DEN' → OE'.

Direction of data flow

284 Clock Generator
 The 8284 provides the clock signal required for the 8086 microprocessor.
 It ensures that all operations (fetch, read, write, I/O transfer) are synchronized.

M/IO’ Signal
 Used to decide whether the operation is Memory or I/O.
o M/IO’ = 1 → Memory operation (transfer with memory).

o M/IO’ = 0 → I/O operation (transfer with input/output devices).

RD’ (Read) & WR’ (Write) Signals

 RD’ (Read, active low): Indicates that 8086 is performing a read cycle (fetching data or
instruction).
 WR’ (Write, active low): Indicates that valid output data is placed on the data bus by the
processor.

DEN (Data Enable) Signal

 DEN tells the external devices (memory or I/O) when to put data on the bus.
 Works together with RD’ during read operations.

74138 (3-to-8 Decoder)

 The control signals (M/IO’, RD’, WR’) are given as inputs to the 74138 decoder.
 It decodes these signals and generates specific control signals for:
o Memory Read

o Memory Write

o I/O Read

o I/O Write

INTR (Interrupt Request) & INTA’ (Interrupt Acknowledge)

 INTR (active high):

o Sent by an external device to request the processor’s attention.

o When INTR = 1, it means some peripheral wants service.

 INTA’ (active low):

o Sent by 8086 to acknowledge the interrupt.

o When INTA’ = 0, it means the processor is ready to service the device.

HOLD & HLDA (Hold Request & Hold Acknowledge)

 HOLD:

o Signal sent by another device to request control of the system bus.

 HLDA (Hold Acknowledge):

o Signal from 8086 to indicate that it has granted the bus to the requesting device.

Bus Cycle and Timing (Minimum Mode)

A bus cycle = 4 clock states (T1, T2, T3, T4)

1. T1:

o Address is placed on the address bus by the processor.

 o Valid only for one T-state.

2. T2:

o Bus is tristated (high-impedance).

o This allows changing the bus direction (important in read cycles).

3. T3:

o Data transfer begins (from memory/I/O device to CPU in read cycle, or CPU to
device in write cycle).

4. T4:

o Data transfer completes.

👉 If the device is slow and cannot complete transfer in T3–T4, then:

 Wait states (Tw) are inserted between T3 and T4 until the device is ready.

Opcode fetch or read timing diagram

T1 (Address Latch Enable)

 ALE = 1 → A valid address is placed on the address bus.

 The address is latched using 8282 latch.

 M/IO’ = 1 → Indicates it is a memory operation (not I/O).

T2 (Bus Direction & Control Signals)

 Address is removed from the bus and sent to the memory/I/O device.

 The local bus becomes tristated.

 RD’ = 0 → Indicates a read operation.

 DEN’ = 0 → Enables transceivers (data drivers).

 DT/R’ = 0 → Data direction = receive (CPU will read data).

T3 (Data Transfer Begins)

 The addressed device places valid data on the data bus.

 The processor reads this data.

T4 (Data Transfer Ends)

 READY = 1 → Indicates the device has completed data transfer.

 Processor sets RD’ = 1 → Read cycle ends.

 Device tristates its bus drivers (data bus free).

Extra Case (Slow Device)

 If the device is slow → WAIT states (Tw) are inserted between T3 and T4 until data is ready.
Write memory cycle

T1 (Address Setup)

 ALE = 1 → A valid address is placed on the address bus and latched using 8282 latch.

 M/IO’ = 1 → Indicates a memory operation (if 0 → I/O operation).

 BHE’ and A0 → Indicate whether lower byte / upper byte / both bytes of the data bus are
active.

T2 (Data Out + Control Signals)

 Processor places the data to be written onto the data bus.

 WR’ = 0 → Indicates a valid write operation.

 DEN’ = 0 → Enables transceivers (so bus drivers are active).

 DT/R’ = 1 → Data direction = from CPU → memory/I/O (write).

T3 (Data Hold)

 The data remains stable on the data bus.

 The addressed device samples (captures) this data.

T4 (End of Write Cycle)

 Data is held on the bus until the middle of T4, then removed.

 WR’ = 1 → Write cycle completed.

 The bus becomes tristated (free for next operation).

Extra Case (Slow Device)

 If the addressed memory/I/O is slow, extra WAIT states (Tw) may be inserted between T3
and T4 until the device is ready.

Maximum Mode Configuration:

The Intel 8086 microprocessor (introduced in 1978) is the first member of the x86 family.
It is a CISC (Complex Instruction Set Computer) processor, supporting a wide range of powerful
instructions.

Key Characteristics of 8086

1. Word Size

o 8086 is a 16-bit microprocessor.

o It can handle 16-bit data at a time.

2. Addressing Capacity

o It has a 20-bit address bus.

o Can directly address 2^20 = 1 MB memory.

3. Data Bus

o It has a 16-bit data bus, so it can transfer 16 bits (2 bytes) at a time.

4. Pipelining

o It is a 2-stage pipelined processor:

 Fetch stage: Prefetches up to 6 bytes of instructions into a queue.

 Execution stage: Executes instructions while the next ones are fetched.

o This improves execution speed.

5. Memory Organization

o Total memory is 1 MB, divided into two 512 KB banks:

 Lower bank (Even) → accessed when A0 = 0

 Higher bank (Odd) → accessed when A0 = 1

 o Supports byte and word operations.

6. Segmentation

o Memory is divided into four segments of up to 64 KB each:

 Code Segment (CS) → Stores program instructions

 Data Segment (DS) → Stores program data

 Stack Segment (SS) → Stores stack (temporary data, return addresses)

 Extra Segment (ES) → Additional data storage

7. I/O Addressing

o Supports 16-bit I/O addressing.

o Can access up to 2^16 = 64 KB I/O ports.

8. Interrupts

o Supports 256 interrupts (0–255).

o Provides hardware and software interrupts for handling external/internal events.

9. Control Bus

o Includes signals for Read (RD’), Write (WR’), Interrupt, Hold, HLDA, etc.

Operating Modes of 8086

The 8086 microprocessor can work in two modes depending on the logic level applied to the
MN/MX' (Minimum/Maximum) pin:

1. Minimum Mode (Single Processor Mode)

 Selected when MN/MX' = 1.

 Used when 8086 is the only processor in the system.

 In this mode, 8086 itself generates all the control signals needed for memory and I/O
operations.

 No need for an external bus controller.

 Simpler system design, cheaper, used in small computers.

✅ Key Points:

 Only one CPU in the system.

 All control signals generated by 8086.

 Example signals: RD’, WR’, INTA’, ALE, DEN’, DT/R’.

 Used in small, low-cost systems.

2. Maximum Mode (Multiprocessor Mode)

 Selected when MN/MX' = 0.

 Used when multiple processors (e.g., 8086 + 8087 coprocessor or 8089 I/O processor) are
present.

 In this mode, 8086 gives out status signals, and an external bus controller (Intel 8288)
generates the actual control signals.

 Supports resource sharing between processors.

✅ Key Points:

 More than one processor can exist in the system.

 8086 shares global resources (e.g., system bus, memory).

 Private resources (e.g., local memory, registers) are specific to each processor.

 Useful in powerful, high-speed systems.

Circuit Explanation of 8086 in Maximum Mode

When the MN/MX' pin = 0, the 8086 microprocessor works in Maximum Mode.
In this mode, several support chips are required to manage memory, I/O, and bus control.

1. Clock Generator (8284)

 The 8284 clock generator provides the system clock for the 8086 and other components.

 It also provides the RESET and READY synchronization signals.

2. Bus Controller (8288)

 The 8086 does not generate control signals directly in maximum mode.

 Instead, it provides status signals (S0, S1, S2).

 The 8288 bus controller takes these status signals and generates the required control
signals:

o ALE (Address Latch Enable)

o RD’ (Read)

o WR’ (Write)

o DEN’ (Data Enable)

o DT/R’ (Data Transmit/Receive)

o Control for memory and I/O operations

3. Address Latching (8282 Latch)

 The address bus of 8086 is 20-bit (A0–A19).

 Since the lower 16 lines (AD0–AD15) are multiplexed with data, latches are required to hold
the address.

 8282 (8-bit latch) is used.

o **3 latches (3 × 8 = 24 > 20 bits).

o ALE (from 8288) is connected to STB (Strobe) of the latches to store the address.

o  Data Bus Transceivers (8286):

o The 8086 data bus is 16-bit, so two 8286 transceivers (8-bit each) are used.

o DEN (Data Enable) from 8288 enables the transceivers.

o DT/R (Data Transmit/Receive) controls the direction (processor to device or device

to processor).

o Connections:

o DEN → OE’ of transceiver

o DT/R → T (direction pin)

  Control signals for all operations are generated by decoding S'2, S'1 and S'0 using 8288 bus
controller.

 Bus Request / Grant (RQ’/GT’ lines):

 The 8086 in maximum mode has two Bus Request/Grant pairs:
o RQ0’ / GT0’ (higher priority)

o RQ1’ / GT1’ (lower priority)

 External devices use these lines to request control of the system bus.
 The processor responds with Grant (GT), giving bus control to the requesting device.
 Since RQ0 has higher priority than RQ1, devices connected to RQ0 can override those
connected to RQ1.
 Interrupt Acknowledge (INTA’):
 When the INTR (Interrupt Request) pin of 8086 is activated, the 8288 bus controller
generates INTA’.
 INTA’ tells the external device that its interrupt has been recognized, and the CPU is ready to
receive the interrupt vector.
 Advanced Write Signals:
 In maximum mode, the 8086 enables advanced write signals.
 These signals become active one T-state earlier than normal write signals.
 Advantage:
o Gives slower devices (like memory or I/O) extra time to prepare for data transfer.
o Reduces the total number of cycles needed → improves efficiency.