Three different implementation:
Data path looks at the block of words while control signal tells when to implement at right time.
Single cycle processor datapath: LW
R type:
Hardware does not execute instruction step by step but once at all.
Add instructions:
Step:1:
Load the instructions from the memory of PC.
OP CODE.
000000 goes from Instruction memory to Controller.
RegDst:
High signal
Tells multiplexer three register are being used.
ALUop
Addition, so HIGH signal, tells ALU control unit what data needs to be pass on.
RegWrite:
High signal,
Notify register file, resulting data will be written.
Jump and branch:
Both low singal no need.
MemRead, MemtoReg, MemWrite.
All low, as no memory manipulation.
ALUSrc:
Low signal,
JUMP AND LABEL:
R type uses most registers, while Jump uses non.
Jump uses a label, which hardware does not understand.
Jump label must be converted to memory address.
Problem
32 bits length required but only 26 bits available.
Assembler, removed truncate the 4 most sign bits.
Like we used to add +4 and give to controller and it would simply jump 4 now it has calculated
custom address to jump;
BRANCH:
Similar to jump;
Branch to jump to label, if conditions is met.
Controller:
Pipelined Processor
In this, in single cycle, one whole instructions gets complete and then the 2 nd starts on while in
pipelined one, fetch of 1st instructions ends and fetch of 2nd cycle starts with decoding of 1st one at
same time and so on.
Each pipeline stage is
represented with its major component—instruction memory (IM), register file (RF) read,
ALU execution, data memory (DM), and register
file writeback—to illustrate the flow of instructions through the pipeline.
Pipeline Datapath:
The pipelined datapath is formed by chopping the single-cycle datapath
into five stages separated by pipeline register
One of the subtle but critical issues in pipelining is that all signals
associated with a particular instruction must advance through the pipeline
in unison
The error is in the register file write logic, which should operate in
the Writeback stage. The data value comes from ResultW, a Writeback
stage signal. But the destination register comes from RdD (InstrD11:7),
which is a Decode stage signal.
Here the thing is that this blue lines runs through all pipelines stages, so once we reach at last part
we have updated value for Rd and that goes into the register file.
Pipelined Control
Same control unit as of Pipelines control.
The control unit
examines the op, funct3, and funct75 fields of the instruction in the Decode
stage to produce the control signals,
These control signals must be pipelined along
with the data so that they remain synchronized with the instruction.
RegWrite must be pipelined into the Writeback stage before it feeds back
to the register file, just as Rd was pipelined in Figure 7.50. In addition to
R-type ALU instructions, lw, sw, and beq, this pipelined processor also
supports jal and I-type ALU instructions
Pipelined Processor Data Hazards
S8 was first computed at cycle 5th but second instruction needs s8 in 3 cycle and I t is not available.
How to handle it?
- NOP
-Rearrange code at compile
-Forward data at run time
-Stall at runtime.
he statement you mentioned describes a specific check that the processor
performs to determine if data forwarding is necessary. It states that the
processor checks whether the source register of an instruction currently in
the execute stage (EX) matches the destination register of an instruction
that is either in the memory stage (MEM) or the writeback stage (WB).
If there is a match, it means that the instruction in the EX stage requires
the result of the instruction in the MEM or WB stage, and that result is not
yet available. In this case, the processor forwards the result from the MEM
or WB stage to the EX stage to avoid a pipeline stall.
Not even available so how to forward?
so make it stall:
Control hazards:
The label part as well as the sub/or part calculated however, the bew
determines to go for the label part hence, the sub/or part will be flushed.\
In a typical computer architecture, the process of executing an
instruction involves several stages, including fetching the
instruction from memory, decoding it to determine its operation,
and executing the instruction to produce a result.
If a branch instruction is taken during the execution stage, it
means that the next instruction to be executed is not the one
immediately following the current instruction. Instead, the
processor needs to jump to a different location in the program,
based on the condition specified by the branch instruction.
However, the instructions that were already fetched and decoded
in the pipeline, prior to the branch instruction being taken, may
no longer be relevant. This is because the processor needs to
start fetching and decoding a new set of instructions from the
new program location indicated by the branch instruction.
To avoid executing the wrong instructions, the pipeline needs to
be flushed, which means discarding the instructions that were
already fetched and decoded, and starting again from the
beginning of the pipeline with the correct instructions.
Therefore, when a branch instruction is taken in the execution
stage, the processor needs to signal the fetch and decode stages
to discard the current instruction and any subsequent instructions
in the pipeline, and begin fetching and decoding new instructions
from the correct program location indicated by the branch
instruction.
Regenerate response
The execution time of an instruction depends on both the number of cycles it uses and the
cycle time.
The multicycle processor requires three cycles for branches, four for R-type, I-type ALU,
jump, and store instructions, and five for loads. The number of clock cycles per instruction
(CPI) depends on the relative likelihood that each instruction is used.
In summary, RAW data hazards occur when an instruction depends on a result (from another
instruction) that has not yet been written into the register file. Data hazards can be resolved
by forwarding if the result is computed soon enough; otherwise, they require stalling the
pipeline until the result is available. Control hazards occur when the decision of what
instruction to fetch has not been made by the time the next instruction must be fetched.
Control hazards are solved by stalling the pipeline until the decision is made or by predicting
which instruction should be fetched and flushing the pipeline if the prediction is later
determined to be wrong. Moving the decision as early as possible minimizes the number of
instructions that are flushed on a misprediction. You may have observed by now that one of
the challenges of designing a pipelined processor is to understand all possible interactions
between instructions and to discover all of the hazards that may exist. Figure 7.61 shows the
complete pipelined processor handling all of the hazards. The hazard logic is summarized on
the next page
