The 12F508 Architecture

Dr. Gheith Abandah 57

 Summary
• An embedded system is a product that has one or more computers
embedded within it, which exercise primarily a control function.
• The embedded computer is usually a microcontroller: a microprocessor
adapted for embedded control applications.
• Microcontrollers are designed according to accepted electronic and
computer principles, and are fundamentally made up of microprocessor
core, memory and peripherals.
• Microchip offers a wide range of microcontrollers, divided into a number
of different families. Each family has identical central architecture and
instruction set. However, common features also appear across all their
microcontrollers.
• The Microchip 12F508 is a good microcontroller to introduce a range of
features of microcontrollers in general and of PIC microcontrollers in
particular.
Dr. Gheith Abandah 58
 Chapter 1
The 80x86 Microprocessors

Processor Architecture Impacting Factors

Markets

Processor
Architecture

Technology Applications

The 80x86 Microprocessors 1.2 Assembly Language

1
 Evolution of Intel’s Processors

Moore’s law: The number of transistors per integrated

circuit would double every 18 months
Pentium 4, 2001
55 Million Transistors
1.5 GHz
~ 30 years

4004, 1971
2300 Transistors
108 kHz

http://www.intel.com/research/silicon/mooreslaw.htm
The 80x86 Microprocessors 1.3 Assembly Language

By End of the Decade…

10,,000
10
~2B Transistors 100,,000
100
~30 GHz 30GHz
30GHz
1.8B
1,000 10,,000
10 14GHz
14GHz
6.5GHz
100 Itanium® 3 GHz
Transistors

1,000
Itanium® proc
(MT)

10
Pentium® Pro
100 Pentium® Pro
1 Pentium proc
486Pentium
486 Pentium® proc
486
386 10 8085
0.1 286 Frequency 286 386
8085 8086
8086
(MHz) 1 8080
0.01 8080
8008 8008
4004
0.001 0.1 4004
’70 ’80 ’90 ’00 ’10
’70 ’80 ’90 ’00 ’10

30 gigahertz devices, 10 nanometer or less

“…30
“…
delivering a tera instruction of performance by 2010”(”(11)
1) Pat Gelsinger, Intel CTO, Spring 2002 IDF

The 80x86 Microprocessors 1.4 Assembly Language

2
 Evolution of Intel’s Processors
Product 4004 8008 8080 8085 8086 8088 80286 80386 80486 Pentium P. Pro

Year 1971 1972 1974 1976 1978 1979 1982 1985 1989 1992 1995

MHz .108 .5-.8 2 -3 3-8 5-10 5 -8 6-16 16--33

16 25--50
25 60,, 66
60 150

# Pins 18 18 40 40 40 40 68 132 168 273 387

# Tran K 2 .3 3 4 .5 6 .5 29 29 130 275 1,200 3,100 5,500

Memory 4K 16K 64K 64K 1M 1M 16M 4G 4G 4G 64G

Data bus

Int. 4 8 8 8 16 16 16 32 32 32 32

Ext. 4 8 8 8 16 8 16 32 32 64 64

Add bus 4 8 16 16 20 20 24 32 32 32 36

Data type 4 8 8 8 8, 16 8, 16 8, 16 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32

The 80x86 Microprocessors 1.5 Assembly Language

Evolution from 8080

8080//8085 to 8086
 In 1978, Intel Corp. introduced a 16--bit microprocessor called the 8086.
16
 8086 was a major improvement over 8080/8085 in several ways:
1. The 8086's capacity of 1 megabyte of memory exceeded the
8080/8085's capability of handling a maximum of 64K bytes.
2. The 8080/8085 was an 8-bit system (work on only 8 bits of data at a
time). Data larger than 8 bits had to be broken into 8-bit pieces to be
processed by the CPU.
3. The 8086 was a pipelined processor, as opposed to the non
pipelined 8080/8085.
 In a system with pipelining, the data and address buses are busy
transferring data while the CPU is processing information, thereby
increasing the effective processing power of the microprocessor.

The 80x86 Microprocessors 1.6 Assembly Language

3
 Evolution from 8086 to 8088
 The 8086 is a microprocessor with a 16-bit data bus internally and
externally
 All registers are 16 bits wide and there is a 16-bit data bus to transfer
data in and out of the CPU.
 At that time all peripherals were designed around an 8-bit microprocessor
instead of 16-bit external data bus .
 A printed circuit board with a 16-bit data bus was much more expensive.
 Therefore, Intel came out with the 8088 version.
 8088 is identical to the 8086 as far as programming is concerned, but
externally it has an 8-bit data bus instead of a 16-bit bus.
 8088 has the same memory capacity, 1 megabyte.
 In 1981, Intel's fortunes changed forever when IBM picked up the 8088
as their microprocessor of choice in designing the IBM PC.

The 80x86 Microprocessors 1.7 Assembly Language

Other Microprocessors: 80286

80286,, 80386
80386,, 80486
 Intel introduced the 80286 in 1982.
 Its features included
 16--bit internal and external data buses
16
 24 address lines, which give 16 megabytes of memory (224 = 16
megabytes); and most significantly,
 Virtual memory
 The 80286 can operate in one of two modes: real mode or protected
mode.
 Real mode is simply a faster 8088/8086 with the same maximum of
1 megabyte of memory. Protected mode allows for 16M of memory
but is also capable of protecting the operating system and programs
from accidental or deliberate destruction by a user
 Virtual memory is a way of fooling the microprocessor into thinking
that it has access to an almost unlimited amount of memory by
swapping data between disk storage and RAM.

The 80x86 Microprocessors 1.8 Assembly Language

4
 32--bit Microprocessor
32
 In 1985 Intel introduced the 80386 (sometimes called 80386DX), internally
and externally a 32
32--bit microprocessor with a 32-bit address bus.
 It is capable of handling physical memory of up to 4 gigabytes (232).
 Virtual memory was increased to 64 terabytes (246).
 Intel introduced numeric data processing chips, called math coprocessors,
such as the 8087, 80287, and 80387.
 Later Intel introduced the 386SX, which is internally identical to the 80386
but has a 16-bit external data bus and a 24-bit address bus which gives a
capacity of 16 megabytes (224) of memory.
 This makes the 386SX system much cheaper.
 With the introduction of the 486 in 1989, Intel put a greatly enhanced
version of the 386 and the math coprocessor on a single chip plus
additional features such as cache memory.
 Cache memory is static RAM with a very fast access time.

The 80x86 Microprocessors 1.9 Assembly Language

Pentium
 In 1992 Intel introduced the Pentium.
 The Pentium had speeds of 60 and 66 MHz, but new design features
made its processing speed twice that of the 66-MHz 80486.
 Although the Pentium has a 64--bit data bus, its registers are 32-bit and
64
it has a 32
32--bit address bus capable of addressing 4 gigabyes of
memory.
 In 1995 Intel introduced the Pentium Pro, the sixth generation of the x86
family.
 Pentium Pro is an enhanced version of the Pentium.

The 80x86 Microprocessors 1.10 Assembly Language

5
 Internal Block Diagram of the 8088
8088//86 CPU
EXECUTION UNIT (EU) BUS INTERFACE UNIT (BIU)

address
generation and
bus control

The 80x86 Microprocessors 1.11 Assembly Language

Pipelining
 There are two ways to make the CPU process information faster:
1. Increase the working frequency or
2. Change the internal architecture of the CPU
 The first option is technology dependent, meaning that the designer must
use whatever technology is available at the time, with consideration for
cost.
 The technology determines the working frequency, power consumption,
and the number of transistors packed into a single-chip microprocessor.
 The second option for improving the processing power of the CPU has to
do with the internal working of the CPU.
 In the 8085 microprocessor, the CPU could either fetch or execute at a
given time.

Fetch Execute Fetch Execute

The 80x86 Microprocessors 1.12 Assembly Language

6
 Pipelining (Cont.)
 The idea of pipelining in its simplest form is to allow the CPU to fetch and
execute at the same time.

Fetch Execute Fetch Execute Non pipelined

Fetch Execute
Fetch Execute
2-stage pipeline
Fetch Execute

Fetch Decode Execute

3-stage pipeline
Fetch Decode Execute
Fetch Decode Execute

The 80x86 Microprocessors 1.13 Assembly Language

Pipelining in the 8088

8088//86
 Intel implemented the concept of pipelining in the 8088/86 by splitting the
internal structure of the microprocessor into two sections:
 the execution unit (EU) and
 the bus interface unit (BIU).
 These two sections work simultaneously. The BIU accesses memory and
peripherals while the EU executes instructions previously fetched.
 This works only if the BIU keeps ahead of the EU; thus the BIU of the
8088/86 has a buffer, or queue.
 The buffer is 4 bytes long in the 8088 and 6 bytes in the 8086.
 If any instruction takes too long to execute, the queue is filled to its
maximum capacity and the buses will sit idle.
 The BIU fetches a new instruction whenever the queue has room for 2
bytes in the 6-byte 8086 queue, and for 1 byte in the 4-byte 8088 queue.
 In some circumstances, the microprocessor must flush out the queue.

The 80x86 Microprocessors 1.14 Assembly Language

7
 8088//86 Registers
8088
 Registers: used to store information temporarily.
 Information: data (8/16-bit) to be processed or the address of data.

Category Bits Register Names

AX (accumulator), BX (base addressing),
General 16
CX (counter), DX (point to data in I/O operations)
registers, 16-bit each

8 AH, AL, BH, BL, CH, CL, DH, DL

categories

Pointer 16 SP (stack pointer), BP (base pointer)

Index 16 SI (source index), DI (destination index)
Six

CS (code segment), DS (data segment),

Segment 16
SS (stack segment), ES (extra segment)
14

Instruction 16 IP (instruction pointer)

Flag 16 FR (flag register)

The 80x86 Microprocessors 1.15 Assembly Language

8-bit/
bit/16
16--bit Registers

8-bit registers

16-bit registers

The 80x86 Microprocessors 1.16 Assembly Language

8
 Introduction to Assembly Programming

 A program that consists of 0s and 1s is called machine language.

 In the early days of the computer, programmers actually coded programs
in machine language.
 Assembly languages were developed, which provided mnemonics for
the machine code instructions, plus other features that made
programming faster and less prone to error.
 Mnemonic  codes and abbreviations that are relatively easy to
remember.
 Assembler  Translator program from assembly code to machine code
 Assembly language is referred to as a low-level language because it
deals directly with the internal structure of the CPU.
 To program in Assembly language, the programmer must know the
number of registers and their size, as well as other details of the CPU.
 Pascal, BASIC, C, ... are called high
high--level languages because the
programmer does not have to be concerned with the internal details of the
CPU.
The 80x86 Microprocessors 1.17 Assembly Language

Assembly Language Programming

 Assembly language program consists of a series of lines of Assembly
language instructions.
 Each instruction consists of a mnemonic, optionally followed by one or two
operands.
 The operands are the data items being manipulated, and the mnemonics
are the commands to the CPU, telling it what to do with those items.


The 80x86 Microprocessors 1.18 Assembly Language

9
 MOV Instruction
 The MOV instruction copies data from one location to another.
 MOV destination, source ;copy source operand to destination

Destination  Source
 The MOV instruction does not affect the source operand.
 MOV AX, 35A0H
AH AL High byte Low byte
35 A0
AX 00110101 10100000
00110101 10100000

 MOV DX, AX ; copies the contents of register AX to register DX

DH DL AH AL
DX 00110101 10100000 AX 00110101 10100000

The 80x86 Microprocessors 1.19 Assembly Language

Data can be moved among all registers

including the segment registers
 MOV AL, DX ; cause an error
 The source and destination registers must be matched in size
 MOV FR, AX ; cause an error
 Loading the flag register is done through other means
 MOV CX, 468FH ;move 468FH into CX (now CH=46,CL=8F)
 MOV AX, CX ;copy contents of CX to AX (now AX=CX=468FH)
 MOV DX,AX ;copy contents of AX to DX (now DX=AX=468FH)
 MOV BX,DX
 MOV DI,BX
 MOV SI,DI
 MOV DS,SI
 MOV BP,DI
 MOV CS, AX
 MOV DS, BX

The 80x86 Microprocessors 1.20 Assembly Language

10
 Immediate MOV
 Data can be moved directly into nonsegment registers only, using the
MOV instruction

 MOV AX,58FCH ;move 58FCH into AX (LEGAL)

 MOV DX,6678H ;move 6678H into DX (LEGAL)

 MOV SI,924BH ;move 924B into Sl (LEGAL)

 MOV BP,2459H ;move 2459H into BP (LEGAL)

 MOV DS,2341H ;move2341H into DS (ILLEGAL)

 MOV CX,8876H ;move 8876H into CX (LEGAL)

 MOV CS,3F47H ;move 3F47H into CS (ILLEGAL)

 MOV BH,99H ;move 99H into BH (LEGAL)

The 80x86 Microprocessors 1.21 Assembly Language

Loading Segment Registers

 Values cannot be loaded directly into any segment register
(CS, DS, ES, or SS).
 To load a value into a segment register, first load it to a nonsegment register
and then move it to the segment register
 MOV AX,2345H ;load 2345H into AX
 MOV DS,AX ;then load the value of AX into DS
 MOV DI,1400H ;load 1400H into Dl
 MOV ES,DI ;then move it into ES, now ES=DI=1400
 If a value less than FFH is moved into a 16-bit register, the rest of the bits
are assumed to be all zeros.
 MOV BX,5 ;BX = 0005 (BH = 00 and BL = 05)
 Moving a value that is too large into a register will cause an error.
 MOV BL,7F2H ;ILLEGAL: BL is 8-bit register and 7F2H > 8 bits
 MOV AX,2FE456H ;ILLEGAL: the value is larger than AX

The 80x86 Microprocessors 1.22 Assembly Language

11
 ADD instruction
ADD destination, source ;ADD the source operand to the destination

Destination  Destination + Source

 The ADD instruction tells the CPU to add the source and the destination
operands and put the result in the destination.
 To add two numbers such as 25H and 34H:
 MOV AL,25H ;move (25)16 = (00100101)2 into AL
 MOV BL,34H ;move (34)16 = (00110100)2 into BL
 ADD AL,BL ;AL = AL + BL, AL = (01011001)2 , BL = 34)16
 Another way:
 MOV DH,25H ;move 25 into DH
 MOV CL,34H ;move 34 into CL
 ADD DH,CL ;add CL to DH: DH = DH + CL
 Using immediate operand:
 MOV DH,25H ;load one operand into DH
 ADD DH,34H ;add the second operand to DH

The 80x86 Microprocessors 1.23 Assembly Language

16--bit Addition
16
 To add two numbers such as 34EH and 6A5H:

 MOV AX,34EH ; AX  001101001110

 MOV DX,6A5H ; DX  011010100101

 ADD DX,AX ; DX = DX + AX, DX = 100111110011

The 80x86 Microprocessors 1.24 Assembly Language

12
 Introduction to Program Segments
 A typical Assembly language program consists of at least three segments:

 Code segment (CS contains the program instructions ),

 Data segment (DS store data that needs to be processed by the

instructions in CS), and

 Stack segment (The stack is used to store information temporarily).

The 80x86 Microprocessors 1.25 Assembly Language

8085//8086 Segments
8085
 A segment is an area of memory
 includes up to 64K bytes and
 begins on an address evenly divisible by 16 (address ends in 0H).
 8085 microprocessor had only 16 pins for the address lines (216 = 64K).
 8085 microprocessor could address a maximum of 64K bytes of physical
memory for code, data, and stack.
 For compatibility
compatibility, 64K bytes segment was carried into the design of the
8088/86.
 Three segments can be used: code, data, and stack segments.
 8088/86 can only handle a maximum of 64K bytes of code and 64K bytes
of data and 64K bytes of stack at any given time, although it has a range
of 1 megabyte of memory (20 address pins  220  1 megabyte).

The 80x86 Microprocessors 1.26 Assembly Language

13
 Logical address and physical address
 In Intel literature, there are three types of addresses mentioned frequently:
 Physical address
 20-bit address that is actually put on the address pins of the 8086
microprocessor and decoded by the memory interfacing circuitry.
 This address can have a range of 00000H to FFFFFH.
 Offset address
 a location within a 64K-byte segment range.
 An offset address can range from 0000H to FFFFH.
 Logical address
 The logical address consists of a segment value and an offset
address

 Segment value : Offset address

The 80x86 Microprocessors 1.27 Assembly Language

Code segment
 To execute a program, the 8086 fetches the instructions (opcodes and operands)
from the code segment.
 The logical address of an instruction, CS:IP
 The physical address for the location of the instruction is
 CS10H + IP Shifting the CS left one hex digit and then adding it to the IP
 CS or IP is 16-bit register, the physical address (CS10H + IP) is 20-bit.
 Example: assume CS = 2500H and IP = 95F3H.
 The offset address: 95F3H (the content of IP)
 The logical address: 2500:95F3H (CS:IP)
 The physical address: 250010 + 95F3 = 2E5F3H
 The logical address range: 2500:0000 to 2500:FFFF
 The lowest memory location of the code segment: 25000H (25000+0000)
 The highest memory location of the code segment: 34FFFH (25000+FFFF)
 8086 will read the instruction from memory locations starting at 2E5F3H

The 80x86 Microprocessors 1.28 Assembly Language

14
 Example
 If CS = 24F6H and IP = 634AH

Show: (a) The logical address (b) The offset address

Calculate: (c) The physical address (d) The lower range of the code segment
(e) The upper range of the code segment

 Solution:
(a) The logical address  24F6:634A

(b) The offset address  634A

(c) The physical address  2B2AA (24F610 + 634A)

(d) The lower range of the code segment  24F60 (24F610 + 0000)

(e) The upper range of the code segment  34F5F (24F610 + FFFF)

The 80x86 Microprocessors 1.29 Assembly Language

80x
80 x86 ADDRESSING MODES
 The CPU can access operands (data) in various ways, called addressing
modes.

 The 80x86 provides a total of seven distinct addressing modes:

1. Register
2. Immediate
3. Direct
4. register indirect
5. Based relative
6. Indexed relative
7. Based indexed relative

The 80x86 Microprocessors 1.30 Assembly Language

15
 Register addressing mode
 The operands are inside the microprocessor.
 The register addressing mode involves the use of registers to hold the
data to be manipulated.
 Memory is not accessed when this addressing mode is executed;
 It is relatively fast
 Examples:
MOV BX,DX ; copy the contents of DX into BX
MOV ES,AX ; copy the contents of AX into ES
ADD AL,BH ; add the contents of BH to contents of AL

 The source and destination registers must match in size.

MOV CL,AX ; this instruction will give an error

The 80x86 Microprocessors 1.31 Assembly Language

Immediate addressing mode

 In the immediate addressing mode, the source operand is a constant.
 In immediate addressing mode, as the name implies, when the instruction
is assembled, the operand comes immediately after the opcode.
 For this reason, this addressing mode executes quickly.
 However, in programming it has limited use.
 Immediate addressing mode can be used to load information into any of
the registers except the segment registers and flag registers.
 Examples:
MOV AX,2550H ; move 2550H into AX
MOV CX,625 ; load the decimal value 625 into CX
MOV BL,40H ; load 40H into BL
MOV DS,0123H ; illegal

The 80x86 Microprocessors 1.32 Assembly Language

16
 Direct addressing mode
 In the direct addressing mode the data is in some memory location(s) and
the address of the data in memory comes immediately after the
instruction.
 Note that in immediate addressing, the operand itself is provided with the
instruction, whereas in direct addressing mode, the address of the
operand is provided with the instruction.
 This address is the offset address and one can calculate the physical
address by shifting left the DS register and adding it to the offset as
follows:
MOV DL,[2400] ;move contents of DS:2400H into DL
 Notice the bracket [ ] around the address.
 In the absence of this bracket it will give an error since it is interpreted to
move the value 2400 (16-bit data) into register DL, an 8-bit register.
MOV DL,2400 ; move 2400 into DL illegal

The 80x86 Microprocessors 1.33 Assembly Language

Example
 Find the physical address of the memory location and its contents after
the execution of the following instructions
assuming that DS = 1512H.
MOV AL,99H ; AL is initialized to 99H
MOV [3518],AL

 Solution:
 The contents of AL are moved to logical address DS:3518 which is
1512:3518.
 The physical address: 18638H (151210H + 3518H = 18638H).
 That means after the execution of the second instruction, the memory
location with address 18638H will contain the value 99H.

The 80x86 Microprocessors 1.34 Assembly Language

17
 Register indirect addressing mode
 In the register indirect addressing mode, the address of the memory location
where the operand resides is held by a register.
 The registers used for this purpose are SI, DI, and BX.
 If these three registers are used as pointers, they must be combined with DS
in order to generate the 20-bit physical address.
Example:
MOV AL,[BX] ; AL contents of the memory location pointed to by DS:BX
 Notice that BX is in brackets.
 In the absence of brackets: MOV AL,BX  illegal
 Physical address: DS10H+ BX
 The same rules apply when using register SI or DI.
MOV CL,[SI] ; move contents of DS:SI into CL (move a byte)
MOV [DI],AH ; move contents of AH into DS:DI (move a byte)

The 80x86 Microprocessors 1.35 Assembly Language

Example
 Assume that DS = 1120, SI = 2498, and AX = 17FE. Show the contents of
memory locations after the execution of
MOV [SI],AX

 Solution:
 The contents of AX are moved into memory locations with logical
address DS:SI and DS:SI + 1
 The physical address: DS10H + SI = 13698.
 According to the little endian convention
 low address 13698H contains FE, the low byte, and
 high address 13699H will contain 17, the high byte.

The 80x86 Microprocessors 1.36 Assembly Language

18