hange E hange E

XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

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ac ac
k e r- s o ft w a k e r- s o ft w a

School of Electrical and Computer Engineering

Digital Logic Design

Unit 6
COMBINATIONAL CIRCUITS-1
(Adder, Subtractor)
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
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ac ac
k e r- s o ft w a k e r- s o ft w a
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

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ac ac
k e r- s o ft w a k e r- s o ft w a
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
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ac ac

Adder
k e r- s o ft w a k e r- s o ft w a

 Design an Adder for 1-bit numbers?

 1. Specification:
2 inputs (X,Y)
2 outputs (C,S)
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

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ac ac

Adder
k e r- s o ft w a k e r- s o ft w a

 Design an Adder for 1-bit numbers?

 1. Specification:
2 inputs (X,Y)
2 outputs (C,S)
 2. Formulation:

X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

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ac ac

Adder
k e r- s o ft w a k e r- s o ft w a

 Design an Adder for 1-bit numbers?

 1. Specification: 3. Optimization/Circuit
2 inputs (X,Y)
2 outputs (C,S)
 2. Formulation:

X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

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w

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tr re tr re
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ac ac

Half Adder
k e r- s o ft w a k e r- s o ft w a

 This adder is called a Half Adder

 Q: Why?

X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

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C

C
.c

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tr re tr re
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ac ac

Full Adder
k e r- s o ft w a k e r- s o ft w a

 A combinational circuit that adds 3 input bits to generate a Sum

bit and a Carry bit
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

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C

C
.c

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Full Adder
k e r- s o ft w a k e r- s o ft w a

 A combinational circuit that adds 3 input bits to generate a Sum

bit and a Carry bit

Sum YZ
X Y Z C S
X 00 01 11 10
0 0 0 0 0 0 0 1 0 1 S = X’Y’Z + X’YZ’
0 0 1 0 1 + XY’Z’ +XYZ
1 1 0 1 0
0 1 0 0 1 = X ⊕Y ⊕ Z
0 1 1 1 0 Carry
YZ
1 0 0 0 1 X 00 01 11 10
1 0 1 1 0 0 0 0 1 0

1 1 0 1 0 1 0 1 1 1
1 1 1 1 1 C = XY + YZ + XZ
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

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tr re tr re
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ac ac

Full Adder = 2 Half Adders

k e r- s o ft w a k e r- s o ft w a

Manipulating the Equations:

S = X ⊕Y ⊕ Z
C = XY + XZ + YZ
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

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C

C
.c

.c
w

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tr re tr re
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ac ac

Full Adder = 2 Half Adders

k e r- s o ft w a k e r- s o ft w a

Manipulating the Equations:

S = ( X ⊕Y ) ⊕ Z
C = XY + XZ + YZ
= XY + XYZ + XY’Z + X’YZ + XYZ
= XY( 1 + Z) + Z(XY’ + X’Y)
= XY + Z(X ⊕ Y )
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

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ac ac

Full Adder = 2 Half Adders

k e r- s o ft w a k e r- s o ft w a

Manipulating the Equations:

S = ( X ⊕Y ) ⊕ Z
C = XY + XZ + YZ = XY + Z(X ⊕ Y )

Think of
Z as a
carry in

Src: Mano’s Book

 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

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ac ac

Bigger Adders
k e r- s o ft w a k e r- s o ft w a

• How to build an adder for n-bit numbers?

• Example: 4-Bit Adder
• Inputs ?
• Outputs ?
• What is the size of the truth table?
• How many functions to optimize?
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

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w

w
tr re tr re
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ac ac

Bigger Adders
k e r- s o ft w a k e r- s o ft w a

• How to build an adder for n-bit numbers?

• Example: 4-Bit Adder
• Inputs ? 9 inputs
• Outputs ? 5 outputs
• What is the size of the truth table? 512 rows!
• How many functions to optimize? 5 functions
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

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C

C
.c

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w

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tr re tr re
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ac ac

Binary Parallel Adder

k e r- s o ft w a k e r- s o ft w a

 To add n-bit numbers:

• Use n Full-Adders in parallel
• The carries propagates as in addition by hand
• Use Z in the circuit as a Cin

 1 0 0 0
 0101
 0110
 1011
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

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w

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tr re tr re
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ac ac

Binary Parallel Adder

k e r- s o ft w a k e r- s o ft w a

 To add n-bit numbers:

• Use n Full-Adders in parallel
• The carries propagates as in addition by hand

Src: Mano’s Book

This adder is called ripple carry adder

 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

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w

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tr re tr re
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ac ac

Subtraction (2’s Complement)

k e r- s o ft w a k e r- s o ft w a

 How to build a subtractor using 2’s complement?

 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

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ac ac

Subtraction (2’s Complement)

k e r- s o ft w a k e r- s o ft w a

 How to build a subtractor using 2’s complement?

Src: Mano’s Book

S = A + ( -B)
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
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C

C
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tr re tr re
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ac ac

Adder/Subtractor
k e r- s o ft w a k e r- s o ft w a

 How to build a circuit that performs both addition and

subtraction?
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

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ac ac

Adder/Subtractor
k e r- s o ft w a k e r- s o ft w a

0 : Add
1: subtract

Src: Mano’s Book

Using full adders and XOR we can build an Adder/Subtractor!

Ahmad Almulhem, KFUPM 2009

 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

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C

C
.c

.c
w

w
tr re tr re
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ac ac

Binary Parallel Adder (Again)

k e r- s o ft w a k e r- s o ft w a

 To add n-bit numbers:

• Use n Full-Adders in parallel
• The carries propagates as in addition by hand

Src: Mano’s Book

This adder is called ripple carry adder

 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
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ww
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C

C
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ac ac

Carry Look Ahead Adder

k e r- s o ft w a k e r- s o ft w a

• How to reduce propagation delay of ripple carry adders?

• Carry look ahead adder: All carries are computed as a function of C0
(independent of n !)
• It works on the following standard principles:
• A carry bit is generated when both input bits Ai and Bi are 1, or
• When one of input bits is 1, and a carry in bit exists

Carry bits Cn Cn-1…….Ci……….C2C1C0

An-1…….Ai……….A2A1A0
Bn-1…….Bi……….B2B1B0
Carry Out
Sn Sn-1…….Si……….S2S1S0