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MOSFET

Presentation · February 2016

DOI: 10.13140/RG.2.1.2021.9760

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MOSFET

B Y – D H WA N I S A M E T R I YA
OUTLINE
• Introduction to Electronics
• MOSFET
• SPICE Model for MOSFET
• CMOS Technology Scaling
• FinFET
• References
INT RODUC TION
TO
E LEC TRONIC S
 ELECTRONICS
• The Science and Technology which deals with emission, behaviour and
effects of electrons in a medium like vacuum, Gas or semiconductor in
electronics devices.
• In early 19th century, Electronics was treated separately from electrical
branch and “ electron” was identified and measurement of its electric
charge took place.
• Then, vacuum tubes and conducting wires were used in order to achieve
amplification of radio signals but they were expensive, bulky and heat up
when performing at higher operating range.
 INTRODUCTION OF TRANSISTOR
• In 1947, Bell Laboratory invented a series of new devices known as
Transistor with remarkable potential for expanding the utility of
electronic equipment.
• Transistors are made up of crystalline solid materials known as
Semiconductors which have electrical properties that can be varied over
extremely wide range by addition of minuscule properties of other
elements.
• Electrons (-Ve Charge) and Holes (+Ve Charge) carries valuable properties
in semiconductors which can be exploited in many electronics devices.
• Si and Ge are primary material used in Semiconductors but today III-V
(group of elements in periodic table) semiconductors are also used.
CONT..
• In order to achieve a compact, lightweight, cost effective and with less
power dissipation, concept of Integrated circuit was introduced by Texas
Instruments.
• Millions of transistors can be integrated on a single Si substrate (Si Chip)
can be known as Integrated Circuit (IC).

IC Technology Transistor Count

SSI < 100
MSI 101 – 1000
LSI 1001 – 10,000
VLSI > 100,000
ULSI > 100,000,000
MOSFET
COMPARISON OF BJT AND MOSFET
 MOSFET
• Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is
fundamental building block for CMOS and Digital circuits.
• Compare to BJT, MOSFET has less Silicon area, less fabrication processing
steps and small physical geometry can help to enhance overall
performance of Large scale ICs.
• MOSFET can work as a switch which can be controlled by Voltage applied
at Gate (G) terminal.
MOSFET SYMBOLS
STRUCTURE OF MOSFET
 THRESHOLD OF MOSFET
• Value of VG for which
transistor is Turned ON
will be known as “
Threshold Voltage “.

• Threshold voltage can

be adjusted with
implementation of
dopants into channel
area during fabrication.
MOSFET I/V CHARACTERISTICS
 Linear Region

Saturation Region

Over dry Voltage

 SECOND ORDER EFFECTS
• Body Effect
• Channel Length Modulation
SPIC E MODEL
FOR MOSFET
 SPICE
• The simulation program with an integrated circuit emphasis (SPICE) is a
software tool for the simulation of circuits.
• Extension of SPICE Files are: *.cir, *.sp, or *.spi
• SPICE has built-in models for the semiconductor devices, and the user
needs to specify only the pertinent model parameter values.

PMOS and NMOS in LTSPICE Software

 TYPES OF ANALYSIS
Type Analysis
dc operating point of the circuit with
DC Analysis
inductors shorted and capacitors opened.
ac output variables as a function of
AC Small-Signal Analysis
frequency.
transient output variables as a function of
Transient Analysis
time over a user-specified time interval
the poles and/or zeroes in the small-signal
Pole-Zero Analysis
ac transfer function.
steady-state harmonic and intermodulation
Small-Signal Distortion Analysis
products for small input signal magnitudes.
device-generated noise for the given circuit
& noise contributions of each device (and
Noise Analysis
each noise generator within the device) to
the output port voltage.
MOSFET LAYOUT
C MOS
T EC HNOLOGY
SC ALING
 SCALING
• MOS technology scaling has been a primary driver of the electronics
industry and has provided a path toward both denser and faster
integration.
• The need for more performance and integration has accelerated the scaling
trends in almost every device parameter, such as lithography, effective channel
length, gate dielectric thickness, supply voltage, device leakage, etc.
 TYPES OF SCALING
1) Constant Field Scaling
2) Constant Voltage Scaling
3) General Scaling
CONT.
1) Constant Field Scaling/Full Scaling
all the dimensions of MOS device scaled down by same factor S.
Keeping all electric field patterns constant avoid breakdown and other
secondary effects
Primary Scaling Factors Scalded by

Tox, L, W, Xj (all in linear dimension) 1/K

Na , Nd (doping concentration) αK

VDD (Supply Voltage) α/K

CONT.
1) Constant Voltage Scaling
Supply voltage scaling is not feasible option in terms of
compatibility with earlier chips voltage. Thus, Supply voltage is kept
constant while scaling all other MOS device parameters.

Primary Scaling Factors Scalded by

Tox, L, W, Xj (all in linear dimension) 1/K

Na , Nd (doping concentration) K2
VDD (Supply Voltage) 1
CONT.
1) General Scaling
Voltage scaling makes difficult to turn off device which in turn
increase rate of leakage current. Thus a more general scaling model
needed which scales device dimensions and voltage proportionally with
α and K scaling factors respectively.

Primary Scaling Factors Scalded by

Tox, L, W, Xj (all in linear dimension) 1/K

Na , Nd (doping concentration) αK
VDD (Supply Voltage) α/K
we will compare experimental results of 3 different nm technologies that
are :

1. 90nm.
2. 65nm.
3. 45nm.
 90 NM & 65 NM CMOS TECHNOLOGY
• As the gate oxide was scaled the gate leakage increased; this increase in gate
leakage was insignificant until the 90nm technology node.
• At the 90nm and 65nm nodes, the scaling of the gate oxide slowed as a
result of the power limitations from the increase in gate leakage.
 NEED OF 45 NM CMOS TECHNOLOGY
• In order to overcome the limitation in 90 nm and 65 nm CMOS technologies,
a gate dielectric with a higher dielectric constant (high-k) has been
introduced in 45 nm CMOS technology.
• This enabled a >25x gate leakage reduction while scaling the Tox by 0.7x.
• The effective gate length required for 45 nm technology is 25nm.
• The high-k +metal gate transistors exhibit excellent short channel
characteristics due to the combination of Tox scaling.
• MOS performance is improved by using the high - k+metal gate as well as by
the enhancements to the embedded SiGe processing.
FINFE T
 CHALLENGES OF MOSFET
• drastic increase in the sub threshold leakage current in nm regime due to
aggressive scaling.
• Loss of gate control on channel due to Narrow channel length results
inability to turn off device.
• The use of thinner gate oxides and high-k dielectric materials helps alleviate
this problem by increasing the gate-channel capacitance.
• All these challenges raise a need to introduced an alternative for MOSFETS
and FinFET comes into picture.
 FINFET
• the transistor channel is a thin
vertical fin with the gate fully
“wrapped” around the channel
formed between the source and the
drain.
• The gate of the FinFET can be
thought of as a “multiple” gate
surrounding the thin channel. Such a
multiple gate can fully deplete the
channel of carriers resulting in much
better electrostatic control of the
channel and thus better electrical
characteristics.
THE GEOMETRIC KEY PARAMETERS OF
FINFETS
• Lg – Length of the gate,
• h – Height of the FIN,
• tox – Thickness of gate oxide,
• tox-top - Oxide thickness of top gate and fin,
• Tsi- Thickness of the fin
• Channel Doping
 ADVANTAGES OF FINFET
• Very good electrostatic control of the channel.
• Greatly reduced short channel effects.
• High integration density, 3D, vertical channel orientation delivers more
performance per linear “w” than planar.
• Smaller variability, especially variability resulting from random dopant
fluctuation primarily due to doping-free or low doping channels.
RE FE RENCES
 REFERENCES
1) http://www.intel.com/content/www/us/en/silicon-innovations/intel-22nm-technology.html
2) http://www.hindawi.com/journals/aelc/2014/365689/
3) http://www.eecs.berkeley.edu/~tking/presentations/KingLiu_2012VLSI-Tshortcourse
4) S. Jim Hawkinson, “Analysis and Performance Comparison of CMOS and FinFET for VLSI
Applications”, International Journal of Emerging Technology and Advanced Engineering, Volume 3,
Issue 2, February 2013.
5) Adel S. Sedra, Kenneth Carless Smith, “Microelectronic Circuits”, ISBN 0-19-514252-7, Oxford
University Press NY, 2004.
6) Sung-mo (steve) kang and Yusuf Leblebigi, “CMOS Digital Integrated Circuits”, ISBN 0-07-246053-9,
McGrow-Hill Publication, 2003.
7) Robert Boylestad and Louis Nashelsky, “ELECTRONIC DEVICES AND CIRCUIT THEORY”, ISBN:
9780133757347, Prentice Hall International editions, 1996.

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