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• Processors support number of registers, therefore,
register file size is large
• ALU operands are performed on a registers data that
means both of the ALU operands are required in the
register or in memory
• Separate register is used to store the result
• Processors support less number of registers, therefore,
register file size is small.
• First ALU operand is always required in the register
• Same register is used as the destination or to store the result
• Second ALU operand is present either in a register or in
memory
• One of the ALU operands is always present in the accumulator.
• Same accumulator is also used as the destination.
• Another ALU operand is present either in the register or in
memory
• Accumulator becomes the default location
• There is no need of address because in
this TOS becomes the default location
• ALU operands are performed only on a stack data
• Both of the ALU operands are always required in the stack
• The same stack is also used as the destination
• ALU operands are zero address operation whereas data transfer
instructions are not a zero address instruction
 Machine Cycle
•Machine Cycle- The time required to complete an operation of
accessing memory or I/O devices is called machine cycle.
•t- state- One time period of the clock signal is called t-state.
•Instruction Cycle: The time a microprocessor needs to fetch and
execute one entire instruction is known as an instruction cycle
 Interrupt Cycle
The interrupt cycle is added to the instruction cycle.
Processor checks for interrupt indicated by an interrupt flag.
If there is NO interrupt Fetch next instruction
If there is an interrupt:
Suspend operation of the program
Save its context
Set PC to start address of the interrupt handler
Process the interrupt
Restore the context of the original program and continue its
execution.
 Instruction Cycle with Interrupts

Following each execute cycle:

•Check for interrupts
•Handle active interrupts
Control Unit
 Some Important Terms
Control Word : A control word is a word whose individual bits
represent various control signals.
Micro-routine : A sequence of control words corresponding
to the control sequence of a machine instruction constitutes
the micro-routine for that instruction.
Micro-instruction : Individual control words in this micro-
routine are referred to as microinstructions.
Micro-program : A sequence of micro-instructions is called a
micro-program, which is stored in a ROM or RAM called a
Control Memory (CM).
Control Store : The micro-routines for all instructions in the
instruction set of a computer are stored in a special memory
called the Control Store.
 Micro-programmed Control Unit

• The control signals associated with operations are stored

in special memory units inaccessible by the programmer as
Control Words.
• Control signals are generated by a program are similar to
machine language programs.
• Micro-programmed control unit is slower in speed
because of the time it takes to fetch microinstructions from
the control memory.
 Instruction stream: It is the sequence of instructions as executed by the machine
Data Stream is a sequence of data including input, or partial or temporary result,
called by the instruction Stream.
Classical von Neumann architecture

Most common and general parallel machine Non existent, just listed for completeness
• Instructions are executed sequentially
It represents an organization that includes multiple processing units under the
control of a common control unit. All processors receive the same instruction from
control unit but operate on different parts of the data.
They are basically used for numerical problems that are expressed in the form of vector or
matrix. But they are not suitable for other types of computations
It consists of a single computer containing multiple processors
connected with multiple control units and a common memory unit.
It is capable of processing several instructions over single data
stream simultaneously.
MISD structure is only of theoretical interest since no practical system
has been constructed using this organization.
• Represents the organization which is capable of
processing several programs at same time
• It is the organization of a single computer containing
multiple processors connected with multiple control
units and a shared memory unit
• The shared memory unit contains multiple modules
to communicate with all processors simultaneously
• Multiprocessors and multicomputer are the
examples of MIMD
• It fulfils the demand of large scale computations.
Overview of Pipelining
Pipeline Case- Laundry
Pipeline Case- Laundry
Designer divides the processor’s data path into sections called
stages and place pipeline latches between each section
Advantages
 • Arises due to the resource conflict in the pipeline
• A resource conflict is a situation when more than one instruction tries to access the
same resource in the same cycle.

INSTRUCTIO
1 2 3 4 5
N / CYCLE
I1 IF(Mem) ID EX Mem
I2 IF(Mem) ID EX
I3 IF(Mem) ID EX
I4 IF(Mem) ID

In cycle 4, instructions I1 and I4 are trying to access same resource (Memory) which
introduces a resource conflict.
To avoid this problem, we have to keep the instruction on wait until the required
resource (memory in our case) becomes available.

• Divide the memory into two independent modules used to store the instruction and
data separately called renaming
 Output Sequence: I1 -> I2 -> I3 -> BI1

INSTRUCTI
1 2 3 4 5 6
ON/ CYCLE
I1 IF ID EX MEM WB
ID
I2 IF EX Mem WB
(PC:250)
I3 IF ID EX Mem
BI1 IF ID EX

Target address of the JMP instruction is known after ID stage only 100: I1
To correct the above problem we need to stop the Instruction 101: I2 (JMP 250)
fetch until we get target address of branch instruction. This can be 102: I3
implemented by introducing delay slot until we get the target .
address. .
Output Sequence: I1 -> I2 -> Delay (Stall) -> BI1 250: BI1
Branch penalty: The number of stalls introduced during
the branch operations in the pipelined processor is
known as branch penalty.
For branch prediction logic Branch penalty is zero.
Total number of stalls introduced in the pipeline due to
branch instructions = Branch frequency * Branch Penalty
 I1 : ADD R1, R2, R3
I2 : SUB R4, R1, R2 I2 tries to read the data before I1 writes it
INSTRUCTION /
1 2 3 4
CYCLE
I1 IF ID EX DM
I2 IF ID(Old value) EX

There are mainly three types of data hazards:

1) RAW (Read after Write) [Flow/True data dependency]
2) WAR (Write after Read) [Anti-Data dependency]
3) WAW (Write after Write) [Output data dependency]
 Types of data dependent hazards
RAW hazard occurs when instruction J tries to read data before
instruction I writes it. Eg:
I: R2 <- R1 + R3
J: R4 <- R2 + R3
WAR hazard occurs when instruction J tries to write data before
instruction I reads it. Eg:
I: R2 <- R1 + R3
J: R3 <- R4 + R5
WAW hazard occurs when instruction J tries to write output
before instruction I writes it. Eg:
I: R2 <- R1 + R3
J: R2 <- R4 + R5
WAR and WAW hazards occur during the out-of-order execution
of the instructions.