ABES ENGINEERING COLLEGE, GHAZIABAD

DEPATMENT OF ELECTRONICS &

COMMUNICATION ENGINEERING

COURSE MATERIAL
Subject Name: VLSI Technology
Subject Code: [KEC -053]
Branch/Semester: ECE / 5th
Session: 2024-25 (Odd Semester)
 DEPATMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Curriculum (Vth semester)
BEC-054 VLSI TECHNOLOGY (3L: 0T: 0P, 3 Credits)

Unit Topics Lectures

I Introduction To IC Technology: SSI, MSI, LSI, VLSI Integrated 8
Circuits. Crystal Growth and Wafer Preparation: Electronic Grade Silicon,
Czochralski Crystal Growth, Silicon Shaping, Processing Considerations.
Wafer Cleaning Technology - Basic Concepts, Wet cleaning, Dry cleaning
II Epitaxy: Vapor-Phase Epitaxy, Molecular Beam Epitaxy, Silicon on 8
Insulators, Epitaxial Evaluation.
Oxidation: Growth Kinetics, Thin Oxides, Oxidation Techniques and
Systems, Oxides Properties.
III Lithography: Optical Lithography, Electron beam lithography, Photo 8
masks, Wet Chemical Etching.
Dielectric and Polysilicon Film Deposition: Deposition Processes of
Polysilicon, Silicon Dioxide, Silicon Nitride.
IV Diffusion: Models of diffusion in solids, Fick’s 1-Dimensional diffusion 8
equation, Diffusion of Impurities in Silicon and Silicon Dioxide, Diffusion
Equations, Diffusion Profiles, Diffusion Furnace, Solid, Liquid and
Gaseous Sources,
Ion-Implantation: Ion-Implantation Technique, Range Theory,
Implantation Equipment.
V Metallization: Metallization Application, Metallization Choices, Physical 8
Vapor Deposition, Vacuum Deposition, Sputtering Apparatus.
Packaging of VLSI devices: Package Types, Packaging Design
Consideration, VLSI Assembly Technologies, Package Fabrication
Technologies, CMOS fabrication steps.

Text Books:
1. S. M. Sze, "VLSI Technology", McGraw Hill Publication, 2nd Edition 2017
2. S.K. Ghandhi, "VLSI Fabrication Principles", Willy-India Pvt. Ltd, 2008

Reference Books:
1. J. D. Plummer, M. D. Deal and Peter B. Griffin, “Silicon VLSI Technology:
Fundamentals, Practice and Modeling", Pearson Education Publication, 2009
2. Stephen A. Campbell, "Fabrication Engineering at the Micro and Nano scale",
Oxford University Press, 2013

Course Outcomes: At the end of this course students will demonstrate the ability to:
1. Interpret the basics of crystal growth, wafer preparation and wafer cleaning.
2. Evaluate the process of Epitaxy and oxidation.
3. Differentiate the lithography, etching and deposition process.
4. Analyze the process of diffusion and ion implantation
5. Express the basic process involved in metallization and packaging.
 [Unit-1]

(Introduction to IC Technology)
 CONTENTS
(Syllabus as per university curriculum: - Introduction to IC Technology: SSI, MSI, LSI, VLSI Integrated
Circuits. Crystal Growth and Wafer Preparation: Electronic Grade Silicon, Czochralski Crystal Growth,
Silicon Shaping, Processing Considerations. Wafer Cleaning Technology - Basic Concepts, Wet
cleaning, Dry cleaning)
Modified Syllabus: Contents by faculty
1.1 Introduction to IC Technology
1.1.1 What is VLSI?
1.1.2 Why VLSI? What is the need of studying this subject VLSI Technology?
1.1.3 History of VLSI
1.1.4 VLSI Applications

1.2 SSI, MSI, LSI, VLSI Integrated Circuits

1.2.1 Classification
1.2.2 Moore’s Law
1.2.3 State of the art technology

1.3 Crystal Structure and Crystal Defects

1.4 Crystal Growth Process

1.5 Crystal Silicon Ingot Formation

1.5.1 Silicon Ingot Grown by CZ Method
1.5.2 Float Zone process

1.6 Wafer Preparation- Silicon Shaping

1.6.1 Cropping ingot
1.6.2 Grinding
1.6.3 Flats (primary and secondary)
1.6.4 Cutting wafers (Slicing)
1.6.5 Edge contouring
1.6.6 Etching
1.6.7 Lapping
1.6.8 Polishing
1.6.9 Chemical Cleaning
1.6.10 Inspection

1.7 Wafer Cleaning Technology

1.7.1 Basic Concepts
1.7.2 Wet cleaning
1.7.3 Dry cleaning

1.8 An example of circuit (IC) implementation in industries

1.9 University & Additional questions related to the topics

1.9.1 University Questions & answers related to the topic
1.9.2 Concept based questions & answers
1.9.3 Electronics Industry based questions & answers
1.9.4 Questions asked in competitive examinations with answers.
 [1.1 Introduction to IC Technology]
[VLSI Introduction]
The electronics industry has achieved a phenomenal growth over the last few decades, mainly
due to the rapid advances in large scale integration technologies and system design applications.
With the advent of very large scale integration (VLSI) designs, the number of applications of
integrated circuits (ICs) in high performance computing, controls, telecommunications, image
and video processing, and consumer electronics has been rising at a very fast pace. The current
cutting- edge technologies such as high resolution and low bit-rate video and cellular
communications provide the end-users a marvellous amount of applications, processing power
and portability. This trend is expected to grow rapidly, with very important implications on
VLSI design and systems design.

[1.1.1 What is VLSI?]

o VLSI is the field which involves packing more and more logic devices into smaller and
smaller areas.
o Very-large-scale integration is the process of creating integrated circuits by combining
thousands of transistor based circuits into a single chip.
o VLSI is an implementation technology for electronic circuitry - Concerned with forming
a pattern of interconnected switches and gates on the surface of a crystal of
semiconductor.
o Very Large Scale Integration can be defined as the process of designing, verifying,
fabricating and testing of a VLSI IC or CHIP.

A VLSI chip is an IC, which has transistors in excess of 10,000. At present CMOS technology
is widely used. The small piece of single crystal silicon that is used to build this IC is called a
‘DIE’. This die varies in different sizes. A typical value for a long die may be 1.5cms x 1.5cms.
This die is a part of a bigger circular silicon disc called as ‘WAFER’. Using batch process many
wafers are processed simultaneously to fabricate several ICs in one fabrication cycle. The initial
investment to set up a silicon fabrication unit runs into a few $Billion.

[1.1.2 Why VLSI? What is the need of studying this subject VLSI Technology?]-
1). Its use in our daily life-
Integration of number of components at a large scale gives us following benefits-
o Reduced size of the device
o Less Power consumption
o Lower parasitics, so high speed etc.
o reduces manufacturing cost - (almost) no manual assembly
These benefits are required in a number of devices used by human being on daily basis for
example-
o Mobile phones (almost everyone use it)
o Laptop/Desktop (Small size with good operating speed always required)
o Electronic Watches, calculators, washing machine and many more daily
used devices.
* We always prefer that mobile phone in our pocket must have long lasting battery and we can
use it as long as possible with fast speed and also our mobile should fit in our pocket easily but
we need a bigger screen too!
All these benefits are possible only because of VLSI technology because it provides us reduced
size with less power dissipation and higher speed which was not possible in any case without
using this technology!

[Figure1: Few daily used general devices]

2). For Electronics & Communication branch-

What is Electronics-?
Electronics is the branch of science that deals with the study of flow and control of electrons
(electricity) and the study of their behaviour and effects in vacuums, gases, and semiconductors,
and with devices using such electrons.
This control of electrons is accomplished by devices (electronic components) that resist, carry,
select, steer, switch, store, manipulate, and exploit the electron.

Understanding VLSI-?
As per the basic definition of VLSI defined just before it is obvious that – VLSI is nothing but
advance level Electronics which includes design of Electronic components at a large scale.

* So as an Electronics Engineer it is necessary to understand the concept of designing of

Electronics components at a large level.

3). Future scope and industry placement-

 As we are progressively increasing the implementation of a large no. of components in

a smaller area as much as possible as per the requirement of human being its future is
very wide and has tremendous scope.
 Electronics Engineers will get the opportunity to get placed in core companies with a
chance to work in same domain and of course a very good package. Some core
companies are - Cadence, Synopsys, Intel, Samsung, Texas Instruments (TI), Nvidia,
Mentor Graphics, Qualcomm, Broadcom, ST Micro, MediaTek, Microchip, AMD,
ARM, IBM, Cisco, Xlinix, Applied Materials, Cypress Semiconductor, NXP
Semiconductor, GE, Infinera, Maxim Integrated Circuits, HCL Technologies, Graphene
Semiconductors, L&T Infotech, TCS, Truechip etc.

[1.1.3 History of VLSI]

In 1947 and 1948, three researchers at Bell Laboratories- Brattin, Bardeen, and Schockley
introduced the bipolar junction transistor (BJT). This development marked the practical
beginning of the microelectronics industry. For the next 15 years, large numbers of different
BJTs were produced and applied in a wide range of instrumentation systems. The BJTs replaced
vacuum tubes in many applications and provided the impetus for a host of new electronic
systems.
In the summer of 1958 Jack Kilby, an engineer at Texas Instruments, invented the first
integrated circuit at Dallas of USA. Early the following year Robert Noyce of Fairchild
independently reported on a procedure that more closely resembles integrated circuits of today.
The specific details of Kilby's circuit are inconsequential, but the impact of his approach has
been phenomenal. The work of Kilby and Noyce marked the beginning of what has become the
field of VLSI design. The silicon IC industry has not looked back since then.

[Figure2: Jack Kilby's original integrated circuit (1958)]

(Source-https://en.wikipedia.org/wiki/Jack_Kilby#/media/File:Kilby_solid_circuit.jpg)

During 1950s computers that were made using vacuum tubes occupied an entire floor of a big
building. Vacuum tubes are even now used in high power applications such as radio
transmission and HAM radios. Gradually, attempts were made to integrate several circuits, be
it analog or digital, in a single package. These attempts succeeded in producing both analog and
digital ICs, as well as mixed signal ICs.
Analog ICs offered operational amplifiers, multipliers, modulators/demodulators, etc., while
digital ICs integrated AND, OR, XOR gates and so on.
Digital ICs are broadly classified according to their circuit complexity measured in terms of the
number of logic gates or transistors in a single package.
In summary we can note the following-
 Late 40s Transistor invented at Bell Labs
 Late 50s First IC (JK-FF by Jack Kilby at TI)
 Early 60s Small Scale Integration (SSI)
 10s of transistors on a chip
 Late 60s Medium Scale Integration (MSI)
 100s of transistors on a chip
 Early 70s Large Scale Integration (LSI)
 1000s of transistor on a chip
 Early 80s VLSI - 10,000s of transistors on a chip
 (Later 100,000s & now 1,000,000s)
 ULSI and GLSI or GSI
 [1.1.4 VLSI Applications]

VLSI technology has become the backbone of all other industries. We can see every other field
of science and technology getting benefit out of this. In fact the advancements that we see in
other fields like IT, AUTOMOBILE or MEDICAL, are because of VLSI. This being such
important discipline of engineering, there is so much interest to know more about this.
VLSI system applications includes communications including internet, image and video
processing, digital signal processing, instrumentation, power, automation, automobiles,
avionics, robotics, health and environment, agriculture, defence, games, etc.
There is hardly anyone who does not know what a cell phone is. From MP3 players, Camera
cell phones and GSM to Bluetooth and IPods, everyone wants all the features squeezed into a
single device as small as possible. Some of the ever-growing applications are as follows:
• Digital cameras
• Digital camcorders
• Digital camera interface
• Digital cinema
• Digital display
• Digital TV and digital cable TV
• Display interface
• Mobile phone
• FAX machine
• PDA
• Scanner
• LCD projector
• Low-cost computer
• Anti-lock brakes
• Automatic transmission
• Cruise control
• Global positioning system for automobiles
• Electro cardiograph
• Life-support systems
• MRI/CT scan
• Traffic controller
• Washing machine
• Automated baggage clearance system in airports
• Avionic systems
• Flight simulator
• Ship controls
• Driverless shuttle
• Cruise controls
• Demodulator for satellite communication
• Encryption/decryption
• Network card
• Quadrature amplitude modulator (QAM) and demodulator
• Wireless LAN/WAN
Digital cameras Mobile phone FAX machine

Scanner Anti-lock brakes Electro cardiograph

PDA Avionic systems Cruise control

Gps for automobiles Traffic controller Digital display

[Figure3: Few application areas of VLSI]

 [1.2 SSI, MSI, LSI, VLSI Integrated Circuits]

[1.2.1 Classification]
Chips falling under the category of small scale integration (SSI) contain up to 10 independent
gates in a single package. The inputs and outputs of these gates are connected directly to the
pins in the package with provision for connections to a power supply.
With the advances in integration technology, more devices having a complexity of
approximately 10 to 100 gates were packed in a single package. They were called medium scale
integration (MSI) devices. Decoders, adders, multiplexers, de-multiplexers, encoders,
comparators are examples of MSIs.
Thereafter, large scale integration (LSI) devices emerged, which integrated between 100 and
1000 gates in a single package. Examples of this category include design such as processors,
memory chips, and programmable logic devices. Finally in late 1970s, very large scale
integration devices containing thousands of gates within a single package became a reality.
Personal computer chips such as 80186, 80286 of Intel are examples of this category.
Since then, integration has been growing by leaps and bounds crossing 10 million gates in a
single package, going into realms of ultra large scale integration (ULSI), grant large scale
integration (GLSI) or giant scale integration (GSI). This classification is summarized in the
following table-
Category Year Density (gates) Typical functions

Single transistor 1959 1 device -

Logic gate 1960 1 -
Small scale integration 1964 Up to 10 Gates, op amps, many linear applications
(SSI)
Medium scale 1967 10 – 100 Registers, filters
integration (MSI)
Large scale integration 1972 100 – 1000 Processors, A/D, etc.
(LSI)
Very large scale 1978 1000 – 10000 Memories, Microcontrollers etc.
integration (VLSI)
Ultra large scale 1989 10000 and Computers, Digital signal processors etc.
integration (ULSI) above
GLSI/GSI Late > 10 million System level integration, system on- chip
1990s

[1.2.2 Moore’s Law]

 Moore’s Law predicts the increase in number of transistors.
 In 1965, Gordon Moore stated that the number of transistors on an IC would double
every year.
 Ten years later, he revised his statement, asserting that doubling would occur every 18
months.
 Since then, this “rule” has been famously known as Moore’s Law. Figure shows
development of processors and increase in transistor counts which verifies Moore’s law.
 [Figure4: Moore’s law & Microprocessor transistor counts 1971-2011]

[1.2.3 State of the art technology]-

i.e. what is the latest technology available and which latest devices are available in the market?
14nm 10nm 7nm 5nm 3nm?
1948 to 1958 to 2021? Where we are?

What is technology node?

Technology nodes, also known as "process technologies" or “process node” or simply "nodes",
are typically indicated by the size in nanometers (previously micrometers) of the process's
transistor gate length. However this is not completely true now when the dimensions are reduced
upto 7nm or even less than that. So it is just an approximation at this level.
10 µm – 1971
6 µm – 1974
3 µm – 1977
1.5 µm – 1981
1 µm – 1984
800 nm – 1987
600 nm – 1990
350 nm – 1993
 250 nm – 1996
180 nm – 1999
130 nm – 2001
90 nm – 2003
65 nm – 2005
45 nm – 2007
32 nm – 2009
22 nm – 2012
14 nm – 2014
10 nm – 2016
7 nm – 2018
5 nm – 2020
Future
3 nm ~ 2022/2024
(Technology node development year wise)
(Source: https://en.wikipedia.org)

[Figure5: Technology node development 1971-2012]

(Source-https://anysilicon.com/semipedia/technology-node/)

[Latest developments - 2017 to 2024]-

(https://en.wikipedia.org/wiki/5_nm_process)

In 2020, Samsung and TSMC entered volume production of 5 nm chips, manufactured for
companies including Apple, Marvell, Huawei and Qualcomm.

In 2017, IBM revealed that they had created 5 nm silicon chips, using silicon nanosheets in a
gate-all-around configuration (GAAFET), a break from the usual FinFET design. The GAAFET
transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the
same gate, just like FinFETs usually have several physical fins side by side that are electrically
a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm 2
and had 600 million transistors per mm2, for a total of 50 billion transistors

In October 2019, TSMC started sampling 5nm A14 processors for Apple.
On October 13, 2020, Apple announced a new iPhone 12 lineup using the A14, together with
the Huawei Mate 40 lineup using the HiSilicon Kirin 9000, which were the first devices to be
commercialized on TSMC's 5nm node. Later, on November 10, 2020, Apple also revealed three
new Mac models using the Apple M1, another 5nm chip. According to Semianalysis, the A14
processor has a transistor density of 134 million transistors per mm2.

[Latest technology available in market]- (2022)

(Source: https://en.wikipedia.org/wiki/3_nm_process)

In semiconductor manufacturing, the 3 nm process is the next die shrink after the 5-nanometre
MOSFET (metal–oxide–semiconductor field-effect transistor) technology node. As of 2019,
TSMC and Samsung have announced plans to put a 3 nm semiconductor node into commercial
production for 2022 with Samsung delaying it to 2024 due to yield issues, followed by Intel for
2025.

Samsung's 3 nm process is based on GAAFET (gate-all-around field-effect transistor)

technology, a type of multi-gate MOSFET technology, while TSMC's 3nm process will still use
FinFET (fin field-effect transistor) technology, despite TSMC developing GAAFET transistors.
Specifically, Samsung plans to use its own variant of GAAFET called MBCFET (multi-bridge
channel field-effect transistor).

The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal
pitch or gate pitch) of the transistors. It is a commercial or marketing term used by the chip
fabrication industry to refer to a new, improved generation of silicon semiconductor chips in
terms of increased transistor density, increased speed and reduced power consumption. For
example, TSMC has stated that its 3nm FinFET chips will reduce power consumption by 25 to
30 percent at the same speed, increase speed by 10 to 15 percent at the same amount power and
increase transistor density by about 33 percent compared to its previous 5nm FinFET chips.
 [1.3 Crystal Structure and Crystal Defects]
[Crystal Structure]-

a). What is a crystal and what is crystal defect?

A crystal is a solid material in which the atoms are arranged in a definite pattern and whose
surface regularity reflects its internal symmetry. In other words, a crystal structure is a unique
arrangement of atoms in a crystal.

Crystal defects
A crystal is never perfect. A defect is a small imperfection affecting a few atoms. The simplest
type of defect is a missing atom and is called a vacancy.

b). What is the need of studying the crystal Structure and crystal Defects?
In IC fabrication generally single crystal Si is used for wafer manufacturing. Crystal structure
of Silicon must be known before proceeding further and which type of defects may appear must
also be known because even a single defect can damage a no. of IC’s on to the wafer.

Why defect are important?

There are a lot of properties that are controlled or affected by defects, for example:
Electric and thermal conductivity in metals (strongly reduced by point defects).
Electronic conductivity in semi-conductors (controlled by substitution defects).
Diffusion (controlled by vacancies).
Ionic conductivity (controlled by vacancies).
Plastic deformation in crystalline materials (controlled by dislocation).
Colours (affected by defects).
Mechanical strength (strongly depended on defects).

c). Construction details-

Crystal Structure is obtained by attaching atoms, groups of atoms or molecules. This structure
occurs from the intrinsic nature of the constituent particles to produce symmetric patterns. A
small group of a repeating pattern of the atomic structure is known as the unit cell of the
structure. A unit cell is the building block of the crystal structure and it also explains in detail
the entire crystal structure and symmetry with the atom positions along with its principal axes.
The length, edges of principal axes and the angle between the unit cells are called lattice
constants or lattice parameters.

There are four types of crystals: covalent, ionic, metallic, and molecular. Each type has a
different type of connection, or bond, between its atoms. The type of atoms and the arrangement
of bonds dictate what type of crystal is formed.

d). Types of crystal defects-

Lattice defects can be sorted into three-
1. Point defects (vacancies, interstitial defects, substitution defects)
2. Line defect (screw dislocation, edge dislocation)
3. Surface defects (material surface, grain boundaries)

Point defects: Missing atoms, atoms in positions where an atom would not normally be
(interstitials), and impurities. Point defects include the Frenkel type, the Schottky type, and the
impurity type.
 [Figure6: Point defects]
The Frenkel defect involves a single ion, which is displaced from its normal lattice point and
shifts to a nearby interstice, or space, between atoms in the lattice.

In the Schottky defect, two ions of opposite sign leave the lattice.

Dislocations: Line defects, or dislocations, are lines along which whole rows of atoms in a solid
are arranged anomalously. The resulting irregularity in spacing is most severe along a line called
the line of dislocation. Line defects can weaken or strengthen solids.

[Figure7: Line defects]

Planar defects: Surface defects may arise at the boundary between two grains, or small crystals,
within a larger crystal. The rows of atoms in two different grains may run in slightly different
directions, leading to a mismatch across the grain boundary. The actual external surface of a
crystal is also a surface defect because the atoms on the surface adjust their positions to
accommodate for the absence of neighbouring atoms outside the surface.
e). Characteristics related to the topic
The processing characteristics and some material properties of silicon wafers depend on its
orientation. Miller Indices are a method of describing the orientation of a plane or set
of planes within a lattice in relation to the unit cell.

[Figure8: Orientation of a plane or set of planes within a lattice]

The <111> planes have the highest density of atoms on the surface, so crystals grow most easily
on these planes and oxidation occurs at a higher pace when compared to other crystal planes.
Traditionally, bipolar devices are fabricated in <111> oriented crystals whereas <100> materials
are preferred for MOS devices. Real crystals are imperfect and contain point defects, line defects
or dislocations, area or plane defects, and volume defects.

Silicon which is widely used as a substrate material in IC fabrication has the basic diamond
crystal structure - two merged FCC cells offset by a/4 in x, y and z.

[Figure9: Silicon crystal structure]

 [1.4 Crystal Growth Process]

a). What is Crystal Growth Process?

In general, we define Crystal growth is the process of making a crystal grow by
continuing to remove a component from a solution. In integrated circuit (IC) fabrication, the
first step is preparing the high purity single crystal Si wafer. This is the starting input to the fab.

Typically, Si wafer refers to a single crystal of Si with a specific orientation, dopant

type, and resistivity (determined by dopant concentration). Typically, Si (100) or Si (111)
wafers are used. The numbers (100) and (111) refers to the orientation of the plane parallel to
the surface. The wafer should have structural defects, like dislocations, below a certain
permissible level and impurity (undesired) concentration of the order of ppb (parts per billion).

b). What is the need of studying the Crystal Growth Process?

Since highly purified single crystal Si is used for wafer manufacturing in semiconductor
industries, crystal growth process of Silicon must be known before proceeding further In IC
fabrication.

c). Steps of Crystal Growth Process -

Step 1 [Raw material to polysilicon]-

1). MGS production from Raw material
2). (i) Pulverization of solid Si material
(ii) Trichlorosilane (TCS) production
(iii) TCS purification using Fractional distillation
3). CVD process – Hydrogen reduction of TCS in CVD chamber

Step 2 [Polycrystalline to Single crystal Silicon]-

- Widely by using either Czochralaski method or Float zone process to obtain large single
crystal ingots.

Here we will cover step 1, step 2 will be covered in next topic.

d). Working/Operation of crystal grow process-

1). MGS production from Raw material

The typical source material for commercial production of elemental silicon is quartzite;
a relatively pure form of sand (SiO2). The first step in the synthesis of silicon is the melting and
reduction of the silica in a submerged-electrode arc furnace. An example of which is shown
schematically in Figure, along with the appropriate chemical reactions.
 [Figure10: MGS production from raw material

A mixture of quartzite and carbon are heated to high temperatures (1800 °C) in the
furnace. The carbon bed consists of a mixture of coal, coke, and wood chips. The latter providing
the necessary porosity such that the gases created during the reaction (SiO and CO) are able to
flow through the bed.

The overall reduction reaction of SiO2 is expressed in Equation, however, the reaction
sequence is more complex than this overall reaction implies, and involves the formation of SiC
and SiO intermediates.
SiC (s) + SiO2 (s) → Si (l) + SiO (g) + CO (g)

This MGS is approximately 98-99% pure, with the major impurities being aluminium
and iron, however, obtaining low levels of boron impurities is of particular importance, because
it is difficult to remove and serves as a dopant for silicon.

2). (i) Pulverization of solid Si material

“Pulverization” (comminution, crushing, grinding) is the process of applying an external
force to this solid MGS to destroy it and reduce it into pieces that are smaller than the original
size.

The formation of EGS from MGS is accomplished through chemical purification

processes. The basic concept of which involves the conversion of MGS to a volatile silicon
compound, which is purified by distillation, and subsequently decomposed to re-form elemental
silicon of higher purity (i.e., EGS).

A number of compounds, such as monosilane (SiH4), dichlorosilane (SiH2Cl2),

trichlorosilane (SiHCl3), and silicon tetrachloride (SiCl4), have been considered as chemical
intermediates. Among these, SiHCl3 has been used predominantly as the intermediate
compound for subsequent EGS formation, although SiH4 is used to a lesser extent. Silicon
tetrachloride and its lower chlorinated derivatives are used for the chemical vapour deposition
(CVD) growth of Si and SiO2.

[Figure11: Schematic of the process to purify MGS to obtain EGS. The process involves conversion of
silicon to trichlorosilane gas, which is purified, and then reduced to obtain silicon.]

(ii) Trichlorosilane (TCS) production

Trichlorosilane is synthesized by heating powdered MGS with anhydrous hydrogen

chloride (HCl) at around 300 °C in a fluidized-bed reactor,
Si (s) + 3HCl (g) → SiHCl3 (g) + H2 (g)
Since the reaction is actually an equilibrium and the formation of SiHCl3 highly
exothermic, efficient removal of generated heat is essential to assure a maximum yield of
SiHCl3

(iii) TCS purification using Fractional distillation

Fractional distillation is the process of separating a substance into its parts (or fractions),
taking advantage of different vapour pressure properties of those substances. Fractional
distillation works by using the fact that molecules of different sizes have different boiling points.
Generally, the smaller a molecule, the lower its boiling point. When heating up a mixture of
molecules, the lowest boiling compound will boil off first.

Fractional distillation of SiHCl3 from these impurity halides result in greatly increased
purity with a concentration of electrically active impurities of less than 1 ppb.

3). CVD process – Hydrogen reduction of TCS in CVD chamber

EGS is prepared from purified SiHCl3 in a chemical vapor deposition (CVD) process
similar to the epitaxial growth of Si. The high-purity SiHCl3 is vaporized, diluted with high-
purity hydrogen, and introduced into the Seimens deposition reactor, shown schematically in
Figure. Within the reactor, thin silicon rods called slim rods (4 mm diameter) are supported by
graphite electrodes. Resistance heating of the slim rods causes the decomposition of the SiHCl3
to yield silicon, as described by the reverse reaction of the above equation.

[Figure12: The Seimens deposition reactor where the purified Si is condensed. This is the electronic
grade Si, same purity level as Si wafers, but polycrystalline]

[Pyrolysis of Silane]-
An alternative process for the production of EGS that has begun to receive commercial
attention is the pyrolysis of silane (SiH4). The advantages of producing EGS from SiH4 instead
of SiHCl3 are potentially lower costs associated with lower reaction temperatures, and less
harmful byproducts. Silane decomposes < 900 °C to give silicon and hydrogen.
SiH4 (vapour) → Si (s) + 2 H2 (g)

Silane may be prepared by a number of routes, each having advantages with respect to
purity and production cost. The simplest process involves the direct reaction of MGS powders
with magnesium at 500 °C in a hydrogen atmosphere, to form magnesium silicide (Mg2Si). The
magnesium silicide is then reacted with ammonium chloride in liquid ammonia below 0 °C.
This process is ideally suited to the removal of boron impurities (a p-type dopant in Si), because
the diborane (B2H6) produced during the reaction forms the Lewis acid-base complex,
H3B(NH3), whose volatility is sufficiently lower than SiH4, allowing for the purification of the
latter. It is possible to prepare EGS with a boron content of ≤ 20 ppt using SiH4 synthesized in
this manner. However, phosphorus (another dopant) in the form of PH3 may be present as a
contaminant requiring subsequent purification of the SiH4.

Alternative routes to SiH4 involve the chemical reduction of SiCl4 by either lithium
hydride or lithium aluminum hydride, or via hydrogenation in the presence of elemental silicon.
The hydride reduction reactions may be carried-out on relatively large scales (ca. 50 kg), but
only batch processes. In contrast, Union Carbide has adapted the hydrogenation to a continuous
process, involving disproportionation reactions of chlorosilanes and the fractional distillation of
silane.
 Pyrolysis of silane on resistively heated polysilicon filaments at 700 - 800 °C yields
polycrystalline EGS. The EGS formed has remarkably low boron impurities compared with
material prepared from trichlorosilane. Moreover, the resulting EGS is less contaminated with
transition metals from the reactor container because SiH4 decomposition does not cause as
much of a corrosion problem as is observed with halide precursor compounds.

e). Advantages and Disadvantages-

The drawbacks of the above process are that it is energy and raw material intensive. It
is estimated that the production of one metric ton (1,000 kg) of MGS requires 2500 - 2700 kg
quartzite, 600 kg charcoal, 600 - 700 kg coal or coke, 300 - 500 kg wood chips, and 500,000
kWh of electric power. Currently, approximately 500,000 metric tons of MGS are produced per
year, worldwide. Most of the production (70%) is used for metallurgical applications (e.g.,
aluminium-silicon alloys are commonly used for automotive engine blocks) from where its
name is derived.

f). Applications-
Applications in a variety of chemical products such as silicone resins account for about
30%, and only 1% or less of the total production of MGS is used in the manufacturing of high-
purity EGS is widely used in the electronics industry. The current worldwide consumption of
EGS is approximately 5 x 106 kg per year.
 [1.5 Crystal Silicon Ingot Formation]
[1.5.1 Silicon Ingot Grown by CZ Method]
Czochralski method/ Czochralski technique /Czochralski process/CZ method-

a). What is CZ method?

The Czochralski method is a method of crystal growth used to obtain single crystals of
semiconductors (e.g. silicon, germanium and gallium arsenide). This is the dominant technique
for manufacturing single crystals. It is especially suited for the large wafers that are currently
used in IC fabrication.

b). Who discover it & what is the need of studying the topic?
Jan Czochralski was a Polish chemist who invented the Czochralski process, which is used for
growing single crystals and in the production of semiconductor wafers. It is still used in over 90
percent of all electronics in the world that use semiconductors. He is the most cited Polish
scholar.

[Figure13: Czochralski puller apparatus]

c). Czochralski Construction details-

A schematic of this growth process is shown in figure. The various components of the process
are:
1. Furnace: It includes fused silicon crucible, a graphite susceptor, a rotation mechanism
(clockwise), heating element and power supply.
2. A crystal pulling mechanism: It includes a seed holder and a rotation mechanism counter
clockwise.
3. Ambient control: It is very important in growth system. There must not be any oxygen inside
the system. The graphite susceptor and graphite heater will react with oxygen to form CO2. It
should not react with Si. Therefore, oxygen should be removed from the chamber and fill it with
Argon. It includes gas source, a flow control & an exhaust system.
4. Control system: A puller has microprocessor based control system to control the process
parameters such as temperatures, crystal diameter, pull rate & rotation speed.

[Figure14: Czochralski furnace]

The starting material for the CZ process is electronic grade silicon, which is melted in the
furnace. To minimize contamination, the crucible is made of SiO2 or SiNx. The drawback is
that at the high temperature the inner liner of the crucible also starts melting and has to replace
periodically.
The furnace is heated above 1500◦C, since Si melting point is 1412◦C. A small seed crystal, with
the desired orientation of the final wafer, is dipped in the molten Si and slowly withdrawn by
the crystal pulling mechanism. The seed crystal is also rotated while it is being pulled, to ensure
uniformity across the surface. The furnace is rotated in the direction opposite to the crystal
puller. The molten Si sticks to the seed crystal and starts to solidify with the same orientation
as the seed crystal is withdrawn. Thus, a single crystal ingot is obtained. To create doped
crystals, the dopant material is added to the Si melt so that it can be incorporated in the growing
crystal.
The process control, i.e. speed of withdrawal and the speed of rotation of the crystal puller, is
crucial to obtain a good quality single crystal. There is a feedback system that control this
process. Similarly there is another ambient gas control system. The final solidified Si obtained
is the single crystal ingot. A 450 mm wafer ingot can be as heavy as 800 kg. A picture of such
an ingot is show in figure below-

[Figure15: Single crystal ingot]

d). Working of CZ method (Step wise)

1. Pieces of EGS (Electronic Grade Silicon) are placed in silicon/SiO2 crucible along with a
small amount of doped silicon & melted. The melt temperature is stabilized at just above the
silicon melting point (14170C).
2. A small single crystal seed suitably oriented is suspended over the crucible in a chuck.

[Figure15: Schematic of the Czochralski growth technique]

3. For growth the seed is lowered into the melt until its end is molten.
4. It is now slowly withdrawn resulting in a single crystal which grows by progressive fusing at
the liquid- solid interface.
5. The crystal orientation of this seed will determine the orientation of the resulting pulled
crystal and wafers. The amount of dopant placed in a crucible with silicon charge will determine
the doping concentration in the resulting crystal.
6. The silicon atoms from the melt bond to the atoms in the seed, lattice plane by lattice plane
forming a single crystal as the seed is pulled upwards.
7. The diameter is controlled by the pull rate. Fast pulling results in smaller diameter crystal.
8. The seed & crucible are rotated in opposite direction to promote more uniform growth.

The control of gaseous and liquid convection is very important in achieving good crystal growth.
The rate of pulling is another important factor. If the rate of shaft withdrawal is fp and the crystal
of radius `r' is growing from a crucible of radius rc, then since the material is conserved, the
average growth rate f can be obtained by equating the mass of solid that has formed and effective
decrease in mass of liquid. If ds and dl are the densities of solid and liquid, respectively, then-

If the densities of the liquid and solid are same then the average growth rate is given by-

Thus the average growth rate of crystal is determined by the pulling rate and the radii of the
crucible and the crystal. The radius of the crystal is however controlled by the melt temperature
and the temperature gradient at the growing interface.

e). Advantages of CZ method-

 One of the main advantages of Czochralski method is the relatively high growth rate.
 Capable of easily producing large diameter crystals from which large diameter wafers
can be cut.
 O2 in interstitial sites improves yield strength.

f). Disadvantages of CZ method-

 Impurities such as oxygen and carbon from the quartz and graphite crucible, lowers the
minority carrier diffusion length in the finished silicon wafer.
 Comparably low homogeneity of the axial and radial dopant concentration in the crystal
caused by oscillations in the melt during crystal growth. This makes it difficult to attain
high-ohmic CZ-wafers.

g). Application of CZ method-

 Monocrystalline silicon (mono-Si) grown by the Czochralski method is often referred to
as monocrystalline Czochralski silicon (CZ-Si). It is the basic material in the production
of integrated circuits used in computers, TVs, mobile phones and all types of electronic
equipment and semiconductor devices.
 Monocrystalline silicon is also used in large quantities by the photovoltaic industry for
the production of conventional mono-Si solar cells. The almost perfect crystal structure
yields the highest light-to-electricity conversion efficiency for silicon.
 [1.5.2 Float Zone process]

The float zone technique is suited for small wafer production, with low oxygen impurity.
The schematic of the process is shown in figure. A polycrystalline EGS rod is fused with the
single crystal seed of desired orientation. This is taken in an inert gas furnace and then melted
along the length of the rod by a traveling radio frequency (RF) coil. The RF coil starts from the
fused region, containing the seed, and travels up, as shown in figure. When the molten region
solidifies, it has the same orientation as the seed. The furnace is filled with an inert gas like
argon to reduce gaseous impurities.

Also, since no crucible is needed it can be used to produce oxygen ’free’ Si wafers. The
difficulty is to extend this technique for large wafers, since the process produces large number
of dislocations. It is used for small specialty applications requiring low oxygen content wafers.

[Figure16: Schematic of the float zone technique]

Float zone technique is mainly used for small sized wafers. The float zone technique is
used for producing specialty wafers that have low oxygen impurity concentration.

The float-zone process has some advantages over the Czochralski process for the growth
of certain types of silicon crystals. The molten silicon in the float-zone apparatus is not
contained in a crucible, and is thus not subject to the oxygen contamination present in CZ-Si
crystals. The float-zone process is also necessary to obtain crystals with a high resistivity (>>
25 Ω-cm).
 [1.6 Wafer Preparation- Silicon Shaping]
a). What is Wafer Preparation?
The process of conversion of silicon ingots into polished wafers is wafer preparation or
simply the silicon shaping.

b). What is the need?

Without cutting silicon ingot and giving it proper shape of so called “wafers”, IC
fabrication on these wafers is not possible. Also all the steps must be taken into consideration
failing which wafer and hence IC’s may damage.

c). Construction details-

Figure shows the simple structure of Silicon ingot obtained through the crystal grown
method and the way that how it should be cut to obtain the circular wafers.

[Figure17: Silicon ingot to wafer prepration]

d). Steps of wafer preparation-

Shaping operations involved in Preparing Wafers from Single crystal Silicon -
1.6.1 Cropping ingot-
Usually, industrial grade diamond tipped saws are used for this process. The shaping operations
consist of two steps
1. The seed and tang ends of the ingot are removed.
2. The surface of the ingot is ground to get a uniform diameter across the length of the ingot.

1.6.2 Grinding-
The ingot is cut into some blocks having the specified length after its periphery is ground to the
specified diameter. Either an orientation flat or a notch is added to a part of the peripheral to
indicate the crystal orientation.

1.6.3 Flats-
Flats are ground along the length of the ingot. There are two types of flats.
1. Primary flat - this is ground relative to a specific crystal direction. This acts as a visual
reference to the orientation of the wafer.
2. Secondary flat - this used for identification of the wafer, dopant type and orientation.

1.6.4 Cutting wafers-

In production of large diameter wafers, the block is sliced at once too many wafers with wire-
saw. In small diameter wafering process, wafers are sliced one by one from the ingot using a
rotating diamond inner peripheral blade.

1.6.5 Edge contouring-

The periphery of a wafer is ground with a diamond tool to attain the required product diameter.
Various types of grinding stones are used to shape wafer edge.

[Figure18: Ingot cropping, flat and grinding]

1.6.6 Etching-
Wafers are placed and etched in a carrier cage that rotates in an etching solution to completely
remove the damaged surface resulting from the previous slicing and lapping. Acid is used for
etching solution, but combination with alkaline is recently used also.

1.6.7 Lapping-
Wafers are set in a carrier, which spins between two rotating lapping plates. Both surfaces of
the wafers are lapped to remove damaged surface layer and to achieve predetermined uniform
thickness.

1.6.8 Polishing-
A wafer mounted onto a ceramics plate is pressed against the surface of a rotating plate covered
with a polishing cloth. It is polished to have a mirror surface by a combined mechanical-
chemical action.
1.6.9 Chemical Cleaning-
Wafers are physically and chemically cleaned using ultra-pure water and chemicals.

1.6.10 Inspection-
Wafer flatness and surface cleanliness (particle-free) are key factors as a substrate for recent
leading edge VLSI devices. Individual wafer flatness and surface particles are measured using
specially designed inspection tools to assure wafer quality.
 [1.7 Wafer Cleaning Technology]

a). What is Wafer Cleaning?

Wafer cleaning process is the removal of chemical and particle impurities without
altering or damaging the wafer surface or substrate. The surface of the wafer must be maintained
not affected so that roughness, corrosion or pitting negates the results of the wafer cleaning
process.

b). What is the need of Wafer Cleaning?

The main goal is to remove the contaminants from the wafer surface and to control
chemically grown oxide on the wafer surface. Modern integrated electronics would not be
possible without unless the technologies for leaning and contamination control would have been
developed, and further reduction of the contamination level of the silicon wafer is mandatory
for the further reduction of the IC element dimensions. Further smooth surface is necessary for
further operations as oxide growth at a uniform level onto the entire surface of wafer, diffusion,
ion implantation on specific areas etc.

c). Working/Operation of Wafer Cleaning-

Pre-Diffusion Clean- Creates a surface that is free from metallic, particulate and organic
contaminants. In certain cases native oxide or chemical oxides need to be removed.

Metallic Ion Removal- Clean Eliminate metallic ions which can have detrimental effect on
device operation.

Particle Removal Clean- Particle removal from surface using chemical or mechanical
scrubbing using Megasonic cleaning.

Post Etch Clean- Remove photo resist and polymers left after etching process. Remove photo
resist and solid residue including “etch polymer”.

Film Removal Clean- Silicon nitride etching/strip, Oxide etching/strip, Silicon etching and
metal etching/strip

RCA Clean-

The RCA clean process was originally developed by RCA Corporation and is a cleaning
method to remove organic residue from silicon wafers. The cleaning solution is made up of 5
parts water, 1 part 30% hydrogen peroxide, and 1 part 27% ammonium hydroxide. It is an
effective way to remove organic contaminants and leaves a thin layer of oxidized silicon on the
surface of the wafer.

Standard Clean 1 and 2 (SC1 Clean, SC2 clean)-

The RCA cleaning process can be carried out in two steps called SC1 and SC2. SC1
clean process uses the APM solution (ammonia hydroxide-hydrogen peroxide water mixture)
of the RCA cleaning method which removes organic matter and particles. This treatment forms
a thin silicon dioxide layer on the wafer surface with some metallic contamination that will be
removed in subsequent steps.
 The SC2 cleaning method uses a solution that is typically made up of 6 parts deionized
water, 1 part hydrochloric acid and 1 part hydrogen peroxide or HPM (hydrochloric/peroxide
mixture). This step effectively removes remaining traces of metallic (ionic) contaminants some
of which were introduced in the SC1 cleaning step. In addition it leaves a thin passivation layer
on the wafer surface that protects it from subsequent contamination. These two steps prepare
the silicon wafer for further processing.

Piranha Etch Clean-

Piranha etch is a popular process for cleaning silicon wafers, but it must be tightly
controlled to be effective. Piranha etch clean, also known as Piranha solution, is used to remove
large amounts of organic residues from wafer substrates. It effectively removes photoresist and
other hard to remove organic materials. The typical mixture ratio is 3 parts of sulfuric acid and
1 part of 30 percent hydrogen peroxide. Other protocols use higher sulfuric acid ratios of 4 to 1
or as high as 7 to 1. Since the mixture is a strong oxidizing agent, it not only removes most
organic matter, it will also hydroxylate most surfaces and make them hydrophilic (water-
compatible). The mixture is highly corrosive and must be prepared and handled with special
care. The piranha etch process can be done in heated quartz tanks where both temperature and
chemical concentration affect the etch rate.

Pre-Diffusion Clean-

Pre-diffusion cleans are critical steps during the wafer manufacturing process. They are
done several times during the manufacturing sequence and require a significant amount of
equipment capacity. They are done as the final step before the silicon wafer goes through a
diffusion furnace operation. Particle and metallic contamination must be minimized and etch
uniformity must be optimized while high throughput is maintained.

Depending on the nature of the contaminant, a variety of aggressive chemicals, including

those from the cleaning methods mentioned above, may be used to achieve clean surfaces. Pre-
diffusion cleaning is a critical process because particles or contaminants on the wafer surface
are likely to be driven into the wafer as well, causing unpredictable electrical properties that
result in defective or low-quality semiconductor output.

Megasonic Cleaning-

These methods include mechanical and wet chemical baths in combination with the use
of high frequency megasonic cleaning equipment. Megasonic wafer cleaning involves using
various complex mechanisms that include mechanical vibration and cavitation within a cleaning
tank. Megasonic cleaning does not require the use of expensive chemicals and simultaneously
removals of both contaminant films and submicron particles.

Ozone Cleaning-
Ozone cleaning process can clean or strip wafers faster and more cost-effectively than
traditional cleaning processes. Advanced Ozone Cleaning Process does not require the use of
expensive chemicals and improves process performance while reducing environmentally
harmful waste. The process uses DI water in Dry Zone gradient dryer to clean wafer substrates
to eliminate inorganic impurities before exposing them in an ozone chamber. All traces of
organic materials are converted to carbon dioxide. The resulting substrate surfaces are free from
particles, trace organic materials and moisture with a stable hydrophilic surface.
Wet and Dry cleaning of wafers- Cleaning can be implemented using liquid chemicals (wet
cleaning) of gases (dry cleaning).

1.7.2 Wet cleaning – The process of contaminants removal from the wafer surface in the liquid-
phase; prevailing cleaning method in semiconductor manufacturing; wet cleaning chemistries
are selected to form soluble compounds of surface contaminants; often enhanced by megasonic
agitation; always followed by deionized water rinse and dry cycle.
Typical wet cleaning sequence includes:
1. Sulphuric acid/hydrogen peroxide/ deionized water (SPM, H2SO4/H2O2/H2O@110-
1300C). SPM usually used to remove organic contaminations (often called "piranha clean").
2. Hydrofluoric acid or diluted hydrofluoric acid (HF or DHF @ 20-25 degrees C). It removes
oxides from area of interest, etches silicone oxides and dioxides, and reduces metals
contamination of the surface. Sometimes buffered oxide etch, (BOE or BHF, / NH4/HF/H2O
@60-80degrees C) is used in place of DHF in some processes, but exposure to it can lead to
NH4F precipitation and contamination.
3. Ammonium hydroxide/ hydrogen peroxide/ DI water mixture (APM,
NH4OH/H2O2/H2O@60-80degrees C). APM oxidizes and slightly etches to undercut and
remove particles from the surface; it also removes organic and metal contaminants.
4. Hydrochloric acid/hydrogen peroxide/DI water (HPM, HCL/H2O2/H2O@60-80degrees C)
HPM removes metallic contaminants from silicone substrate and acts as oxidizing agent.
5. Ultra-pure water (UPW). Commonly called as DI water, it dilutes chemicals, and rinses
solutions after chemical cleans.

1.7.3 Dry cleaning – The process of contaminants removal from the wafer surface in the gas-
phase; driven by either conversion of contaminant into volatile compound through chemical
reaction, or its "knocking" off the surface via momentum transfer, or lift-off during slight
etching of contaminated surface.
Conventional wet chemistries are very effective for most applications, though there are
growing concerns regarding environmental safety and economics. Most likely dry methods will
not directly replace wet chemistries in mainstream applications, but instead will supplement wet
techniques at various points such as single 300 mm wafer processing.
In theory, larger wafers should favor dry chemistries because of increased demand on
chemical, water and waste .disposal. Cost effectiveness may also be seen if dry surface
cleaning/conditioning modules are added to existing cluster tools. In addition to reduction of
chemicals and water, a key advantage of dry surface processing technology is in its
compatibility with process integration.
 Cryogenic Cleaning
The need for very specific spot cleans is coming into focus with emphasis on dry processes
such as vapor cleans and cryogenics.
 Laser cleaning
Laser cleaning can reduce particulates from a wafer surface without the use of water
chemicals and with no hazardous wastes.

d). Characteristics related to the topic-

[Types and sources of contamination]

Particles- dust, pollen, clothing particles, bacteria, etc. In ordinary room there are as much as
10 6 particles more than 0.5 micron in diameter per cut. Particles with diameter more than 20
micron will settle down readily. Particles of diameter from 0.1 to 20 micron are the main
problem.

[Figure19-Contamination on the silicon surface]

Inorganic contaminants- salts, positive and negative ions in solution, heavy metal atoms.
Inorganics are removed by cleaning the wafer in water recirculation systems and using special
solutions.
Organic contaminants- smog, skin oil, fluxes, lubricants, solvent vapors, monomers from
plastic tubing and storage boxes that can condense on substrate. They usually removed using
strong oxidizers, gaseous or liquid.
Impurities- incorporated during the formation of substrates or over layer films. Generally, they
cannot be removed.

e). Advantages and Disadvantages of Wafer Cleaning -

Wafer cleaning is an important step which is used a no. of times during complete IC
manufacturing process. IC fabrication is not possible without using this step a no. of times. Si
wafer semiconductor devices have more advantages than disadvantages, which is why a lot of
industries utilize them in various applications.

f). Application of Wafer Cleaning -

An Si wafer can be used for several purposes, including semiconductor devices like solar
cells, electronic components, devices and integrated circuits.
 [1.8 An example of circuit (IC) implementation in industries]
[IC 555]

The 555 timer IC is an integral part of electronics especially projects, be it a simple

project involving a single 8-bit Micro-controller and some peripherals or a complex one
involving system on chips (SoCs), its working is involved.

It was introduced in 1971 by the American company Signetics in the original bipolar
and low-power CMOS types. The widespread use of this timer is due to its low price, ease of
use and stability. Some of the major features of the IC-555(timer) are-

Supply voltage (VCC) 4.5 to 15 V

Supply current (VCC = +5 V) 3 to 6 mA
Supply current (VCC = +15 V) 10 to 15 mA
Output current (maximum) 200 mA
Maximum Power dissipation 600 mW
Power consumption (minimum operating) 30 mW@5V, 225 mW@15V
Operating temperature 0 to 75 °C
 [Figure20: internal circuit diagram of IC 555 using BJTs]

The internal circuit diagram of IC 555 is shown in figure which indicates that a no. of transistors
(Either BJT or MOSFET), resistors and diodes are used to implement this IC.
 [Figure21: internal circuit diagram of IC 555 using MOSFETs]

The major implementation steps to fabricate this IC will include the following-

1). Wafer preparation (Includes all the steps of IC fabrication as mentioned from 1.4 to 1.7 i.e.
• 1.4 Crystal Growth Process
O MGS from Raw Material
o Electronic Grade Silicon
o CVD Process
o Pyrolysis of Silane
• 1.5 Crystal Silicon Ingot Formation
O Silicon Ingot Grown by CZ Method
o Float Zone process
• 1.6 Wafer Preparation- Silicon Shaping
o Cropping ingot
o Grinding
o Flats (primary and secondary)
o Cutting wafers (Slicing)
o Edge contouring
o Etching
o Lapping
o Polishing
o Chemical Cleaning
o Inspection
• 1.7 Wafer Cleaning Technology

2). Design of complete circuit using CAD design tools on computer.

3). Simulation and testing of the designed circuit.

4). Designing of complete circuit layout its floor planning placement and routing.
5). Final testing of this design before sending to fabrication unit.

6). All subsequent steps of IC fabrication to implement a no. of such cores onto the wafer.

7). Cutting of all such core and dies from the wafer.

8). Final packaging and passivation of these cores and dies to obtain “IC 555” as per the
designed circuit.

9). The last and final step is then to test all these IC’s before using it for any practical application
in academic or in industry.
 [1.9 University & Additional questions related to the topics]
[1.9.1 University Questions related to the topic]

[Two-mark questions]

Q1). Explain the terms: SSI, LSI, MSI and VLSI.

A1.
SSI - The first integrated circuits contained only a few transistors and so were called “Small-
Scale Integration (SSI). They used circuits containing transistors numbering in the tens.

MSI - SSI was followed by introduction of the devices which contained hundreds of transistors
on each chip, and so were called “Medium-Scale Integration (MSI).

LSI- Next development was of Large Scale Integration (LSI). The development of LSI was
driven by economic factors and each chip comprised tens of thousands of transistors. It was in
1970s, when LSI started getting manufactured in huge quantities.

VLSI- LSI was followed by Very Large Scale Integration (VLSI) where hundreds of thousands
of transistors were used and still being developed. It was for the first time that a CPU was
fabricated on a single integrated circuit, to create a microprocessor. In 1986, with the
introduction of first one megabit RAM chips, more than one million transistors were integrated.

Q2). Define the crystal structure of Silicon.

A2. Silicon which is widely used as a substrate material in IC fabrication has the basic diamond
crystal structure - two merged FCC cells offset by a/4 in x, y and z.

[Figure22: Silicon crystal structure]

Q3). What are point defects?

A3. These are missing atoms, atoms in positions where an atom would not normally be
(interstitials), and impurities. Point defects include the Frenkel type, the Schottky type, and the
impurity type.
 [Figure23: Point defects]

The Frenkel defect involves a single ion, which is displaced from its normal lattice point and
shifts to a nearby interstice, or space, between atoms in the lattice.

In the Schottky defect, two ions of opposite sign leave the lattice.

Q4). List the steps used in the preparation of Si wafers.

A4.
Step 1 [Raw material to polysilicon]-
1). MGS production from Raw material
2). (i) Pulverization of solid Si material
(ii) Trichlorosilane (TCS) production
(iii) TCS purification using Fractional distillation
3). CVD process – Hydrogen reduction of TCS in CVD chamber

Step 2 [Polycrystalline to Single crystal Silicon]-

- Widely by using either Czochralaski method or Float zone process to obtain large single
crystal ingots.

Step 3 [Single crystal Silicon ingot to Silicon wafers]-

- Cropping ingot
- Grinding
- Flats
- Cutting wafers
- Edge contouring
- Etching
- Lapping
- Gettering
- Polishing
- Chemical Cleaning
- Inspection
Q5). Differentiate among Point, Frankel and Schottky Defects.
A5. In point defect, the defect occurs only at certain positions of the lattice. Point defect is
further classified as stoichiometric and non-stoichiometric defect.
o When the chemical formula of the crystal remains the same due to the defect, it is a
stoichiometric defect. It arises when an atom is displaced from its position or when two
or more atoms change their position within the lattice.
o When the chemical formula of the crystal altars, then the defect is a non-stoichiometric
defect. It arises if certain different impurities are added in the crystal lattice.
-Both Schottky and Frenkel defects are an example of stoichiometric defects. The differences
between the two defects are-
Schottky defect Frenkel defect
It occurs when the atoms are just displaced
It occurs when the atoms are totally
from their position to some voids or interstitial
missing from the crystal lattice.
sites of the crystal lattice.
It generally occurs in crystal lattice where
It occurs generally in the lattice where the size
the size ratio of cation and anion is nearly
ratio of cation and anion is large
1
In this, both the cation and the anion In this, only the smaller ion is displaced. Cation
leave the lattice, thus ensuring that the is smaller and so it gets displaced in interstitial
overall crystal is neutral. sites.
Two atoms are removed from the lattice Number of atoms remain same before and after
for 1 single defect the defect.
Thus, there is decrease in the density of
Thus, the density of the crystal is unaffected
the crystal
Two vacancies are created when 1 pair of One vacancy is created and one interstitial site
ions are removed is occupied

[Ten-mark questions]

Q1). Describe CZ process in detail with neat diagram. Mention the importance of inert
ambient during the process.
or
Describe CZ process in detail with neat diagram. What is the pull rate in CZ technique?
How pull rate is controlled during the CZ crystal growth process?
A1.
Czochralski Crystal Growth Process: The highly refined silicon (EGS) though free from
impurities, is still polycrystalline. Hence it is to be processed to become single crystal. The
Czochralski crystal growth process is often used for producing single-crystal silicon ingots.
 Since monolithic ICs are usually fabricated on a substrate which is doped with impurity,
the poly-crystalline silicon with an appropriate amount of dopant is-put into a quartz crucible,
which is then placed inside a crystal growth furnace. The material is then heated to a temperature
that is slightly in excess of the silicon melting pint of 1420 degree Celsius. A small single-
crystal rod of silicon called a seed crystal is then dipped into the silicon melt. The conduction
of heat up the seed crystal will produce a reduction in the temperature of the melt in contact
with the seed crystal to slightly below the silicon melting point. The silicon will therefore freeze
onto the end of the seed crystal, and as the seed crystal is slowly pulled up out of the melt it will
pull up with it a solidified mass of silicon that will be a crystallographic continuation of the seed
crystal. Both the seed crystal and the crucible are rotated but in opposite directions during the
crystal pulling process in order to produce crystalline ingots of circular cross section.
The liquid solid interface remains near to the surface of the melt if the temperature and
pulling rate are correctly chosen. Even a long single crystal silicon is pulled from it. The
diameter of the ingot is controlled by the pulling rate and the melt temperature, with ingot
diameters of about 100 to 150 mm (4 to 6 inches) being the most common. The ingot length
will generally be of the order of 3 meter, and several hours are required for the “pulling” of a
complete ingot. The crystal pulling is done in an inert-gas atmosphere (usually argon or
helium), and sometimes a vacuum is used. This is done to prevent oxidation”
The pull-rate is closely related to the heat input and losses, crystal properties and
dimensions. The conditions for crystal pulling are therefore carefully controlled. For example,
the melt temperature is monitored with a thermocouple and feedback controller. Longer
diameter crystals have commercial advantages and can be grown. However, difficulties may be
encountered because of resistivity gradient across finished slices.
The crystal growth apparatus shown in the figure above consists of the following parts.
 Furnace
 Crystal pulling mechanism
  Ambient control facility
 Control system circuitry
The furnace consists of a crucible, susceptor (crucible support) and rotational mechanism,
heating element and power supply, and a chamber. As the crucible contains the melt, it is the
most important component of the growth apparatus. The crucible material should be chemically
unreactive with molten silicon. Also, the material should have high melting point, thermal
stability, and hardness. The materials for crucible, which satisfy these properties, are silicon
nitride (Si3N4) and fused silica (SiO2). The latter is in exclusive use nowadays. Fused silica;
however, reacts with silicon, releasing silicon and oxygen into the melt. In tins process the
crucible undergoes erosion. The susceptor, is used to support the silica crucible. It also provides
for better thermal conditions. Graphite is the material of choice because of its high-temperature
properties. The graphite should be pure to prevent contamination of the crystal from impurities
that would be volatilized from the graphite at the temperature involved. The susceptor rests on
a pedestal whose shaft is connected to a motor that provides rotation. The whole assembly can
usually be raised and lowered to keep the melt level equidistant from a fixed reference point,
which is needed for automatic diameter control.
The chamber housing the furnace must provide easy access to the furnace components to
facilitate maintenance and cleaning. The furnace structure must be airtight to prevent
contamination from the atmosphere, and have a specific design that does not allow any part of
the chamber to become so hot that its vapour pressure would be a factor in contaminating the
crystal. Hottest parts of the apparatus are water cooled Insulation is usually provided between
the heater and the chamber wall.
The crystal-pulling mechanism consists of seed shaft or chain, rotation mechanism, and seed
chuck. The mechanism controls two parameters of die growth process: pull rate and crystal
rotation. Also, the pulling mechanism must have minimum vibration and great precision. The
seed holder and pulling mechanism must maintain precise orientation perpendicular to the melt
surface.
From the figure shown below you can see that the crystal leaves the furnace through a purge
tube, where ambient gas, if present, is directed along the surface of the crystal to cool it. From
the purge tube, the crystal enters an upper chamber, which is usually separated from the furnace
by an isolation valve.
The ambient control for the crystal growth apparatus consists of gas source, flow control,
purge lube, and exhaust or vacuum system. The crystal growth must be conducted in an inert
gas or vacuum. The hot graphite parts must be protected from oxygen to prevent erosion.
The gas around the process should not react with the molten silicon. Growth in vacuum
meets these requirements.
Growth in a gaseous atmosphere, generally used on large growers, must use an inert gas
such as helium or argon. The inert gas may be at atmospheric pressure or at reduced pressure.
The control system for crystal growing may consist of micro processing sensors, and outputs
and provides control of process parameters such as temperature, crystal diameter, pull rate and
rotation speed. The use of digital or microprocessor-based systems for control is more common
because these rely less on operator intervention and have many parts of the process pre-
programmed.
We can see that the maximum pull rate is inversely proportional to the square root of the crystal
radius (diameter). Actual pull crystal pull rates are less than those calculated by the formula
above.

Q2). Explain production process of Electronic grade Silicon from silica with neat diagram.
A2.
Electronic-Grade Silicon-
Electronic-grade silicon (EGS), a polycrystalline material of high purity, is the starting material
for the preparation of single crystal silicon. EGS is made from metallurgical-grade silicon
(MGS) which in turn is made from quartzite, which is a relatively pure form of sand. MGS is
purified by the following reaction:

Si (solid) + 3HCl (gas) SiHCl3 (gas) + H2 (gas) + heat

The boiling point of trichlorosilane (SiHCl3) is 32oC and can be readily purified using fractional
distillation. EGS is formed by reacting trichlorosilane with hydrogen:

2SiHCl3 (gas) + 2H2 (gas) 2Si (solid) + 6HCl (gas)

[Figure25: Schematic of the process to purify MGS to obtain EGS. The process involves conversion of
silicon to trichlorosilane gas, which is purified, and then reduced to obtain silicon.]

The process flow is shown in figure. A Si rod is used to nucleate the reduced Si obtained from
the silane gas, as shown in figure. During the conversion of silicon to trichlorosilane impurities
are removed and process can be cycled to increase purity of the formed Si. The final material
obtained is the EGS. This is a polycrystalline form of Si, like MGS, but has much smaller
impurity levels, closer to what is desired in the final single crystal wafer. EGS is still
polycrystalline and needs to be converted into a single crystal Si ingot for producing the wafers.

[Figure26: The Seimens deposition reactor where the purified Si is condensed. This is the electronic
grade Si, same purity level as Si wafers, but polycrystalline.]
Q3). Why is cleaning of Silicon wafer necessary before any processing steps? Explain the
crystal structure.
A3. Cleaning of wafers - The main goal is to remove the contaminants from the wafer surface
and to control chemically grown oxide on the wafer surface. Modern integrated electronics
would not be possible without unless the technologies for leaning and contamination control
would have been developed, and further reduction of the contamination level of the silicon wafer
is mandatory for the further reduction of the IC element dimensions. Further smooth surface is
necessary for further operations as oxide growth at a uniform level onto the entire surface of
wafer, diffusion, ion implantation on specific areas etc.

Types and sources of contamination

Particles- dust, pollen, clothing particles, bacteria, etc. In ordinary room there are as much as
10 6 particles more than 0.5 micron in diameter per cut. Particles with diameter more than 20
micron will settle down readily. Particles of diameter from 0.1 to 20 micron are the main
problem.

[Figure27-Contamination on the silicon surface]

Inorganic contaminants- salts, positive and negative ions in solution, heavy metal atoms.
Inorganics are removed by cleaning the wafer in water recirculation systems and using special
solutions.
Organic contaminants- smog, skin oil, fluxes, lubricants, solvent vapors, monomers from
plastic tubing and storage boxes that can condense on substrate. They usually removed using
strong oxidizers, gaseous or liquid.
Impurities- incorporated during the formation of substrates or over layer films. Generally, they
cannot be removed.

Methods /solutions/techniques
Most cleaning methods can be loosely divided into two big groups: wet and dry methods.
Liquid chemical cleaning processes are generally referred to as wet cleaning. They rely
on combination of solvents, acids and water to spray, scrub, etch and dissolve contaminants
from wafer surface.
Dry cleaning processes use gas phase chemistry, and rely on chemical reactions required
for wafer cleaning, as well as other techniques such as laser, aerosols and ozonated chemistries.
Generally , dry cleaning technologies use less chemicals and less hazardous for
environment but usually do not perform as well as wet methods, especially for particle removal.
Crystal Structure-

A crystal is a solid material in which the atoms are arranged in a definite pattern and whose
surface regularity reflects its internal symmetry. In other words, a crystal structure is a unique
arrangement of atoms in a crystal.

Crystal Structure is obtained by attaching atoms, groups of atoms or molecules. This structure
occurs from the intrinsic nature of the constituent particles to produce symmetric patterns. A
small group of a repeating pattern of the atomic structure is known as the unit cell of the
structure. A unit cell is the building block of the crystal structure and it also explains in detail
the entire crystal structure and symmetry with the atom positions along with its principal axes.
The length, edges of principal axes and the angle between the unit cells are called lattice
constants or lattice parameters.

There are four types of crystals: covalent, ionic, metallic, and molecular. Each type has a
different type of connection, or bond, between its atoms. The type of atoms and the arrangement
of bonds dictate what type of crystal is formed.

Q4). Discuss different shaping operations involved in Preparing Wafers with diagram.
A4.
Shaping operations involved in Preparing Wafers from Single crystal Silicon -
Cropping ingot-
Usually, industrial grade diamond tipped saws are used for this process. The shaping operations
consist of two steps
1. The seed and tang ends of the ingot are removed.
2. The surface of the ingot is ground to get a uniform diameter across the length of the ingot.

Grinding-
The ingot is cut into some blocks having the specified length after its periphery is ground to the
specified diameter. Either an orientation flat or a notch is added to a part of the peripheral to
indicate the crystal orientation.

Flats-
Flats are ground along the length of the ingot. There are two types of flats.
1. Primary flat - this is ground relative to a specific crystal direction. This acts as a visual
reference to the orientation of the wafer.
2. Secondary flat - this used for identification of the wafer, dopant type and orientation.

Cutting wafers-
In production of large diameter wafers, the block is sliced at once too many wafers with wire-
saw. In small diameter wafering process, wafers are sliced one by one from the ingot using a
rotating diamond inner peripheral blade.

Edge contouring-
The periphery of a wafer is ground with a diamond tool to attain the required product diameter.
Various types of grinding stones are used to shape wafer edge.

Etching-
Wafers are placed and etched in a carrier cage that rotates in an etching solution to completely
remove the damaged surface resulting from the previous slicing and lapping. Acid is used for
etching solution, but combination with alkaline is recently used also.
Lapping-
Wafers are set in a carrier, which spins between two rotating lapping plates. Both surfaces of
the wafers are lapped to remove damaged surface layer and to achieve predetermined uniform
thickness.

Polishing-
A wafer mounted onto a ceramics plate is pressed against the surface of a rotating plate covered
with a polishing cloth. It is polished to have a mirror surface by a combined mechanical-
chemical action.

Chemical Cleaning-
Wafers are physically and chemically cleaned using ultra-pure water and chemicals.

Inspection-
Wafer flatness and surface cleanliness (particle-free) are key factors as a substrate for recent
leading edge VLSI devices. Individual wafer flatness and surface particles are measured using
specially designed inspection tools to assure wafer quality.

[Figure28: Basic Process Steps for Wafer Preparation]

Q5). Explain Electronic Grade Silicon with neat diagram. Explain the polishing process
of Silicon in detail.
A5. Electronic-Grade Silicon
Electronic-grade silicon (EGS), a polycrystalline material of high purity, is the starting material
for the preparation of single crystal silicon. EGS is made from metallurgical-grade silicon
(MGS) which in turn is made from quartzite, which is a relatively pure form of sand (Table 2.1).
MGS is purified by the following reaction:

Si (solid) + 3HCl (gas) SiHCl3 (gas) + H2 (gas) + heat

The boiling point of trichlorosilane (SiHCl3) is 32oC and can be readily purified using fractional
distillation. EGS is formed by reacting trichlorosilane with hydrogen:

2SiHCl3 (gas) + 2H2 (gas) 2Si (solid) + 6HCl (gas)

Polishing process of Silicon
Wafers thinned using conventional wafer grinding methods often have a mirror-like
surface. However, hidden to the naked eye is subsurface damage caused by wafer backgrinding.
Even though the damage is typically only a few microns, it can affect a semiconductor wafer’s
strength and flexibility.

Semiconductor wafer polishing, also referred to as Chemical Mechanical Polishing

(CMP), removes this subsurface damage to create thinner and more flexible silicon wafers. Post-
backgrind wafer polishing removes between 5 and 10 microns of silicon from the backside of
the wafer and dramatically reduces the micro-sized peaks and valley micro-damage caused by
processes. Polishing also removes stresses and prevents warping that weakens wafers, giving
you a stronger semiconductor wafer.

Two steps are used for silicon wafers: “Pre-polishing” (stock removal) end “Final Polishing”.

The “Pre-polishing” process generates the required geometrical properties of the wafer. Two
polishing processes are possible:

SSP (Single Side Polishing) - Only one face is polished, the second one named backside is
etched

DSP (Double Side Polishing) - Both faces of the wafer are polished. This process is suitable
when high flatness is required

The “Final Polishing” process generates the final roughness of the wafer. With the standard
process the RMS (Root Mean Square) is closed to 5 Å. If needed, we can perform a specific
“final Polishing” process to obtain a RMS less than 3 Å.

[Figure29: Schematic of polishing process]

 [1.9.2 Concept based questions & answers]
Q1. Explain briefly feature size, chips and wafers.
A1.
Feature Size -
Features i.e. the elements that make up the structures on a chip, the size of the features are
measured in nanometers. A 22 nm process technology refers to features 22 nm or 0.022 µm in
size.

Semiconductor Feature Sizes

(approximate for all vendors)

Nanometers Micrometers
Year (nm) (µm)

1957 120,000 120.0

1963 30,000 30.0
1971 10,000 10.0
1974 6,000 6.0
1976 3,000 3.0
1982 1,500 1.5
1985 1,300 1.3
1989 1,000 1.0
1993 600 0.6
1996 350 0.35
1998 250 0.25
1999 180 0.18
2001 130 0.13
2003 90 0.09
2005 65 0.065
2007 45 0.045
2009 32 0.032
2012 22 0.022
2014 14 0.014
2016 10 0.010
2018 7 0.007
 2020 5 0.005

Chips-
An electronic circuit whose components, such as transistors and resistors, are etched or
deposited on a single slice of semiconductor material is called an IC or a chip.
A device made of interconnected electronic components that are etched or imprinted
onto a tiny slice of a semiconducting material, such as silicon or germanium. Chip is an
integrated circuit smaller than a fingernail can hold millions of circuits.

Wafers-
A wafer, also called a slice or substrate is a thin slice of semiconductor material, such
as a crystalline silicon, used in electronics for the fabrication of integrated circuits and in
photovoltaics for conventional, wafer-based solar cells.
The wafer serves as the substrate for microelectronic devices built in and over the wafer
and undergoes many microfabrication process steps such as doping or ion implantation, etching,
deposition of various materials, and photolithographic patterning. Finally the individual
microcircuits are separated (dicing) and packaged.

Q2. What are hybrid and monolithic circuits? What are thin and thick film technology?
Compare them.
A2.
Monolithic Integrated Circuits-
The word ‘monolithic’ comes from the Greek words ‘monos’ and ‘lithos’ which means
‘single’ and ’stone’. As the name suggests, monolithic IC’s refer to a single stone or a single
crystal. The single crystal refers to a single chip of silicon as the semiconductor material, on top
of which all the active and passive components needed are interconnected.
So a monolithic integrated circuit has the full circuit constructed on a single piece of
silicon or other semiconductor, then (usually) enclosed in a package with connecting leads.
This is the best mode of manufacturing IC’ as they can be made identical, and produces
high reliability. The cost factor is also low and can be manufactured in bulk in very less time.
They have been found applicable for IC’s used for AM receivers, TV circuits, computer circuits,
voltage regulators, amplifiers and so on.

[Figure30: Monolithic IC]

Being as it is, monolithic IC’s have some limitations as well.

1. Monolithic IC’s have low power rating. They cannot be used for low power applications as
they cannot have a power rating of more than 1 watt.

2. The isolation between the components inside the IC is poor.

3. Components like inductor cannot be fabricated to the IC.

4. The passive components that are fabricated inside the IC will be if small value. For higher
values they have to be connected externally to the IC pins.

5. It is difficult to make a circuit flexible for any kind of variation; a new set of masks is required.

Thin and Thick Film Integrated Circuit-

Thick and thin film IC’s are comparatively larger than monolithic IC’s and smaller than
discrete circuits. They find their use in high power applications. Though it is a little large in
size, these IC’s cannot be integrated with transistors and diodes. Such devices have to be
externally connected on to its corresponding pins. Passive components like resisters and
capacitors can be integrated.

Both thick and thin film IC’s have similar appearance, properties, and general
characteristics, the main difference between the two of them is the manner in which the film is
deposited on to the IC.

Thin Film Integrated Circuits-

This IC is fabricated by depositing films of conducting material on the surface of a glass
or ceramic base. The resistors are fabricated by controlling the width and thickness of the films
and by using different materials selected for their resistivity. For capacitors, a film of insulating
oxide is sandwiched between two conducting films. A spiral form of film is deposited onto the
IC to create an inductor.

Mainly two methods are used for producing thin films. One method, called vacuum evaporation
is used in which vaporized material is deposited on a substrate contained in a vacuum. The other
method is called cathode sputtering in which atoms from a cathode made of the desired film
material are deposited on a substrate located between a cathode and an anode.

Thick Film Integrated Circuits-

They are also commonly called as printed thin film circuits. The desired circuit pattern
is obtained on a ceramic substance by using a manufacturing process called silk-screen printing
technique.

The inks used for printing are usually materials that have resistive, conductive, or
dielectric properties. They are selected accordingly by the manufacturer. The screens are
actually made of fine stainless steel wire mesh. The films are fused to the substrate after printing
by placing them in hot high temperature furnaces.

The fabrication techniques used for thin film passive components are adopted for thick
films as well. As with thin-film circuits, active components are added as separate devices. A
portion of thick-film circuit is given in the figure below.
 [Figure31: Thick film IC]

When compared to monolithic IC’s, thick and thin film IC’s do have some advantages.
They have the advantage of better tolerance, better isolation between components, and greater
flexibility in circuit design that further helps in providing high frequency performance. But,
these are the only factors that must be considered for the application of such IC’s as they are
costly in making, and has higher dimensions than monolithic IC’s. They also cannot be used to
fabricate active components which further increase the size.

Hybrid or Multi-chip Integrated Circuits-

As the name suggests, the circuit is fabricated by interconnecting a number of individual

chips.

A Hybrid circuit consists of a (often ceramic) substrate carrying one or more silicon
chips (which may themselves be monolithic integrated circuits, individual diodes, or
transistors). Resistors and conductive tracks may be deposited on the substrate, and other parts
may be soldered to the tracks to form a complete circuit. A hybrid can also use mixed
technology, such as GaAs chips along with silicon chips.

Hybrids ICs are mostly used for high power audio amplifier applications from 5 Watts
to more than 50 Watts. The active components are diffused transistors or diodes. The passive
components may be group of diffused resistors or capacitors on a single chip, or they may be
thin-film components. Interconnection between the individual chips is made by wiring process
or a metallized pattern.
 [Figure32: Hybrid IC]

Hybrid IC’s are also known to provide a better performance than monolithic IC’s.
Although the process is too expensive for mass production, multi-chip techniques are quite
economical for small quantity production and are more often used as prototypes for monolithic
ICs.

Based upon the active devices employed the ICs can be classified as bipolar ICs using
bipolar active devices (BJT) and unipolar IC’s using unipolar active
Q3. State Moore’s law and explain the deviation from the predicted path.
A3. Moore's law is the observation that the number of transistors in a dense integrated circuit
(IC) doubles about every two years. Moore's law is an observation and projection of a historical
trend. Rather than a law of physics, it is an empirical relationship linked to gains from
experience in production.
The observation is named after Gordon Moore, the co-founder of Fairchild
Semiconductor and CEO and co-founder of Intel, who in 1965 posited a doubling every year in
the number of components per integrated circuit, and projected this rate of growth would
continue for at least another decade. In 1975, looking forward to the next decade, he revised the
forecast to doubling every two years, a compound annual growth rate (CAGR) of 40%. While
Moore did not use empirical evidence in forecasting that the historical trend would continue,
his prediction held since 1975 and has since become known as a "law."
 [Figure33: A semi-log plot of transistor counts for microprocessors against dates of introduction,
nearly doubling every two years]

Moore's prediction has been used in the semiconductor industry to guide long-term
planning and to set targets for research and development, thus functioning a bit like a self-
fulfilling prophecy. Advancements in digital electronics, such as the reduction in quality-
adjusted microprocessor prices, the increase in memory capacity (RAM and flash), the
improvement of sensors, and even the number and size of pixels in digital cameras, are strongly
linked to Moore's law. These step changes in digital electronics have been a driving force of
technological and social change, productivity, and economic growth.
Industry experts have not reached a consensus on exactly when Moore's law will cease
to apply. Microprocessor architects report that semiconductor advancement has slowed
industry-wide since around 2010, below the pace predicted by Moore's law. However, as of
now, leading semiconductor manufacturers have developed IC fabrication processes in mass
production which are claimed to keep pace with Moore's law.

Q4. Distinguish between wet and dry cleaning of wafers.

A4.
Cleaning of wafers- Cleaning is the process of removing contaminants (particles as well as
metallic and organic) from the surface of the wafer; can be implemented using liquid chemicals
(wet cleaning) of gases (dry cleaning).

Dry cleaning – The process of contaminants removal from the wafer surface in the gas-phase;
driven by either conversion of contaminant into volatile compound through chemical reaction,
or its "knocking" off the surface via momentum transfer, or lift-off during slight etching of
contaminated surface.
Conventional wet chemistries are very effective for most applications, though there are
growing concerns regarding environmental safety and economics. Most likely dry methods will
not directly replace wet chemistries in mainstream applications, but instead will supplement wet
techniques at various points such as single 300 mm wafer processing.
In theory, larger wafers should favor dry chemistries because of increased demand on
chemical, water and waste .disposal. Cost effectiveness may also be seen if dry surface
cleaning/conditioning modules are added to existing cluster tools. In addition to reduction of
chemicals and water, a key advantage of dry surface processing technology is in its
compatibility with process integration.
 Cryogenic Cleaning
The need for very specific spot cleans is coming into focus with emphasis on dry processes
such as vapor cleans and cryogenics.
 Laser cleaning
Laser cleaning can reduce particulates from a wafer surface without the use of water
chemicals and with no hazardous wastes.

Wet cleaning – The process of contaminants removal from the wafer surface in the liquid-
phase; prevailing cleaning method in semiconductor manufacturing; wet cleaning chemistries
are selected to form soluble compounds of surface contaminants; often enhanced by megasonic
agitation; always followed by deionized water rinse and dry cycle.
Typical wet cleaning sequence includes:
1. Sulphuric acid/hydrogen peroxide/ deionized water (SPM, H2SO4/H2O2/H2O@110-
1300C). SPM usually used to remove organic contaminations (often called "piranha clean").
2. Hydrofluoric acid or diluted hydrofluoric acid (HF or DHF @ 20-25 degrees C). It removes
oxides from area of interest, etches silicone oxides and dioxides, and reduces metals
contamination of the surface. Sometimes buffered oxide etch, (BOE or BHF, / NH4/HF/H2O
@60-80degrees C) is used in place of DHF in some processes, but exposure to it can lead to
NH4F precipitation and contamination.
3. Ammonium hydroxide/ hydrogen peroxide/ DI water mixture (APM,
NH4OH/H2O2/H2O@60-80degrees C). APM oxidizes and slightly etches to undercut and
remove particles from the surface; it also removes organic and metal contaminants.
4. Hydrochloric acid/hydrogen peroxide/DI water (HPM, HCL/H2O2/H2O@60-80degrees C)
HPM removes metallic contaminants from silicone substrate and acts as oxidizing agent.
5. Ultra-pure water (UPW). Commonly called as DI water, it dilutes chemicals, and rinses
solutions after chemical cleans.

Q5. Why (100) orientation is preferred over (111) orientation for starting material in
NMOS/CMOS IC fabrication?
A5.
In single crystalline silicon material the crystal orientation is defined by Miller indices. A
particular crystal plane is noted using parenthesis such as (100). Silicon has a cubic symmetrical
cubic structure and so (100), (010) etc are equivalent planes and collectively referred to using
braces {100}. Similarly, the crystal directions are defined using square brackets, e.g. [100] and
referred collectively using triangular brackets, <100>.

Comparison between (100) and (111) orientation-

<111> <100>
 The plane {111} has the highest density of
atoms on the surface, so crystal grow is easy
on this plane.
Mechanical property like tensile strength is
high in<111> direction
Processing characteristics like oxidation is
also dependent on orientation. For example
{111} is oxidized faster than {100} plane
because they have more atom per unit
surface.
For bipolar circuits <111> orientation is
preferred.
MOS technology use silicon wafer with the
crystal surface in hundred orientations
because it introduce 10 times less interface
trap density, which can charge Si-Sio2
interface. This charging introduces variation
in threshold voltage which is undesirable

Given the cost, lead times and availability,

the vast majority of substrates used in bulk
micromachining have <100> orientation.
The Si/SiO2 interface state density is
minimum in <100> orientation compared to
others. Therefore, to get higher carrier
mobility and/or drive current 100 orientation
of Si is preferred in industry.
In BJT we use Si(111) wafers because they In MOSFET we use Si(100) wafers because
offers high oxidation rates and it helps in they have less broken bonds on surface than
reducing time for oxidation process. Si(111) and we want clean surface for
MOSFET.
100 gives you a lesser dangling bonds on
surface. So less impurity accumulation thus
better control. A required characteristic for a
MOSFET.
A 111 gives you advantage of fast oxidation
as more atoms are available on surface to
text with oxygen. Desire for BJTs

Q6. Compare between CZ and FZ method.

A6.
Comparison of the CZ and FZ Growth Methods -

Characteristic CZ FZ
Growth Speed (mm/min) 1 to 2 3 to 5
Dislocation-Free? Yes Yes
Crucible? Yes No
Consumable Material Cost High Low
Heat-Up/Cool-Down Times Long Short
Axial Resistivity Uniformity Poor Good
Oxygen Content (atoms/cm3) >1x1018 <1x1016
Carbon Content (atoms/cm3) >1x1017 <1x1016
Metallic Impurity Content Higher Lower
Bulk Minority Charge Carrier
5-100 1,000-20,000
Lifetime (ms)
Mechanical Strengthening 1017 Oxygen 1015 Nitrogen
Production Diameter (mm) 150-200 100-150
Operator Skill Less More
Polycrystalline Si Feed Form Any Crack-free rod
 [1.9.3 Electronics Industry based questions & answers]

Q1. What are the initial investment costs of development of VLSI chip?
A1. Investment costs –
In the microelectronics industry a semiconductor fabrication plant (commonly called a
fab; sometimes foundry) is a factory where devices such as integrated circuits are manufactured.
Fabs require many expensive devices to function. Estimates put the cost of building a
new fab over one billion U.S. dollars with values as high as $3–4 billion not being uncommon.
TSMC invested $9.3 billion in its Fab15 300 mm wafer manufacturing facility in Taiwan. The
same company estimations suggest that their future fab might cost $20 billion.
The central part of a fab is the clean room. The clean room contains the steppers for
photolithography, etching, cleaning, doping and dicing machines. All these devices are
extremely precise and thus extremely expensive.
Prices for most common pieces of equipment for the processing of 300 mm wafers range
from $700,000 to upwards of $4,000,000 each with a few pieces of equipment reaching as high
as $50,000,000 each (e.g. steppers). A typical fab will have several hundred equipment items.

Q2. What is the wafer size used in VLSI industries to fabricate chips?
A2. The current (as of 2020), state-of-the-art for wafer size is 300 mm (12 in). The industry is
aiming to move to the 450 mm wafer size by 2025.

Q3. What are clean room standards? What do you mean by “class 1000 clean room”?
A3. Clean room -
A cleanroom is a controlled environment that has a low level of pollutants such as dust,
airborne microbes, aerosol particles, and chemical vapours. To be exact, a cleanroom has a
controlled level of contamination that is specified by the number of particles per cubic meter at
a specified particle size.
A cleanroom is any given contained space where provisions are made to reduce
particulate contamination and control other environmental parameters such as temperature,
humidity and pressure. The key component is the High Efficiency Particulate Air (HEPA) filter
that is used to trap particles that are 0.3 micron and larger in size. All of the air delivered to a
cleanroom passes through HEPA filters, and in some cases where stringent cleanliness
performance is necessary, Ultra Low Particulate Air (ULPA) filters are used.

Personnel selected to work in cleanrooms undergo extensive training in contamination

control theory. They enter and exit the cleanroom through airlocks, air showers and/or gowning
rooms, and they must wear special clothing designed to trap contaminants that are naturally
generated by skin and the body.

Depending on the room classification or function, personnel gowning may be as limited

as lab coats and hairnets, or as extensive as fully enveloped in multiple layered bunny suits with
self-contained breathing apparatus.

Cleanroom clothing is used to prevent substances from being released off the wearer’s
body and contaminating the environment. The cleanroom clothing itself must not release
particles or fibers to prevent contamination of the environment by personnel. This type of
personnel contamination can degrade product performance in the semiconductor and
pharmaceutical industries and it can cause cross-infection between medical staff and patients in
the healthcare industry for example
 It only takes a quick monitor of the air in a cleanroom compared to a typical office
building to see the difference. Typical office building air contains from 500,000 to 1,000,000
particles (0.5 microns or larger) per cubic foot of air. A Class 100 cleanroom is designed to
never allow more than 100 particles (0.5 microns or larger) per cubic foot of air. Class 1000 and
Class 10,000 cleanrooms are designed to limit particles to 1000 and 10,000 respectively.

A human hair is about 75-100 microns in diameter. A particle 200 times smaller
(0.5 micron) than the human hair can cause major disaster in a cleanroom. Contamination can
lead to expensive downtime and increased production costs. In fact, the billion dollar NASA
Hubble Space Telescope was damaged and did not perform as designed because of a particle
smaller than 0.5 microns.

Cleanroom Classifications-

Cleanrooms are classified according to the number and size of particles permitted per
volume of air. Large numbers like "class 100" or "class 1000" refer to FED-STD-209E, and
denote the number of particles of size 0.5 µm or larger permitted per cubic foot of air.

Class 10,000 cleanrooms may use simple smocks, head covers, and booties. For Class
10 cleanrooms, careful gown wearing procedures with a zipped cover all, boots, gloves and
complete respirator enclosure are required.

Both FS 209E and ISO 14644-1 assume log-log relationships between particle size and
particle concentration. For that reason, there is no such thing as zero particle concentration.
Ordinary room air is approximately class 1,000,000 or ISO 9.

US FED STD 209E

Maximum Particles/ft³
Class >0.1 um >0.2 um >0.3 um >0.5 um >5 um ISO equivalent
1 35 7 3 1 ISO3
10 350 75 30 10 ISO4
100 100 ISO5
1000 1000 7 ISO6
10,000 10,000 70 ISO7
100,000 100,000 700 ISO8

Q4. Why Silicon is so popular in VLSI technology?

A4. Silicon prevailed because it has superior physical and technological properties compared to
the other semiconductor materials.
-Silicon is abundant in the earth crust as an ore in the form of quartzite
-There are effective extraction and purification methods of silicon from its raw material.
- There are effective and economical crystallization methods for silicon.
-Silicon crystallizes in a diamond form with relatively strong bond gaining the crystals relatively
strong mechanical properties which is advantageous for mechanical handling and processing.
-The energy gap of silicon is moderate resulting in an intrinsic concentration of about one
1010/cm3. Which is relatively low leading to small leakage currents.
-The maximum solid solubility of dopants is about 1021/cm3. Therefore one can change the
carrier type and concentration in a very large range for optimum operation of the devices.
- Easy doping by the suitable impurities. Development of powerful doping technologies.
-Silicon dioxide has very superior characteristics enabled the planar technology one of the
marking stone in semiconductor industry.
-Silicon dioxide is a building layer in the MOS devices which revolutionized the integrated
circuits especially the digital ones.
-Silicon dioxide is used also as an insulator and passivation layer.
-Silicon has efficient response to solar radiation and light.
-Silicon has relatively high dielectric strength and therefore is suitable for power devices.
Q5. What is a Semiconductor Foundry?
A5. In simple terms, a semiconductor foundry (also known as a fab) is a factory where silicon
wafers are manufactured. The main customers of a semiconductor foundry are chip makers such
as: Broadcom, Qualcomm, Intel, AMD and more.

Semiconductor foundries today are at the core of our modern-day society, as almost everything
that we use in day-to-day life is electronic and made from chips, which all need to be made
produced somewhere. Fabs appeared as a response to the rapidly increasing need for
semiconductor devices all around the world, which pushed the electronics industry towards
better and larger fabrication plants, where economies of scale truly become worthwhile.

Wafer fabs are built in various places around the world. But as you expect, the big fabs are
located across Asia, more specially in Taiwan. This interactive map shows the location of major
semiconductor foundries.

There are two types of business models for semiconductor foundry: a pure-play foundry and a
non-pure-play foundry. A non-pure-play foundry is a company that provides foundry services
(wafer manufacturing) but in parallel they also produce and sell their own ICs. Pure-play
semiconductor foundries are producing wafers as a service for other companies: fabless
semiconductor companies, integrated device manufacturers (IDMs), and sometimes product
companies such as Apple that is making its own chips. TSMC is the largest pure-play foundry.

Wafers produced by a semiconductor foundry come in a pre-defined size. The major wafer sizes
today are 300mm and 200mm. This paper explains the economy of scale related to wafer size,
and the image below shows the various wafer size available in the market today.

Q6. What are the advantages of IC’s over discrete component circuits?
A6. Advantages of IC
ICs have a no. of advantages over discrete circuits however the main advantages can be said as:
cost and performance. Cost is low because the chips, with all their components, are printed as a
unit by photolithography rather than being constructed one transistor at a time. Furthermore,
packaged ICs use much less material than discrete circuits.
o The entire physical size of IC is extremely small than that of discrete circuit.
o The weight of an IC is very less as compared entire discrete circuits.
o It's more reliable.
o Because of their smaller size it has lower power consumption.
o It can easily replace but the drawback can be added as it can hardly repair, in case of
failure.
 [1.9.4 Questions asked in competitive examinations with answers]

Q1. In MOSFET fabrication, the channel length is defined during the process of-
[GATE ECE 2014]
a) Isolation oxide growth
b) Channel Stop Implant
c) Poly Silicon Gate Patterning
d) Lithography step leading to gate patterning
Answer: c

Q2.
In CMOS technology, shallow P-well or N-well regions can be formed using-
[GATE ECE 2014]
a) Low Pressure CVD
b) Low Energy Sputtering
c) Low temperature dry oxidation
d) Low energy Ion Implantation

Answer: d

Q3. Why Silicon is preferred over Germanium for Semiconductor Devices?

A3.

 At room temperature, Silicon crystal has fewer free electrons than Germanium crystal.
This implies that silicon will have much smaller Collector cut off current than
Germanium.
 The variation of Collector cut off current with temperature is less in Silicon compared
to Germanium.
 The structure of Germanium crystals will be destroyed at higher temperature. However,
Silicon crystals are not easily damaged by excess heat.
 Peak Inverse Voltage ratings of Silicon diodes are greater than Germanium diodes.
 Si is less expensive due to the greater abundance of element. The major raw material for
Si wafer fabrication is sand and there is lots of sand available in nature.
Q4. For a die size of 0.25in x 0.25inch, calculate the number of dice in a 50 wafer lot of 6 in
wafer?
A4. Silicon dies which are placed on a wafer can also be described as many squares placed
inside a circle — thus the calculation is about first finding the overall circle area using both the
mathematical number Pi (approximately equal to 3.14159) and the wafer size.

[Figure34: Dies on wafer]

The wafer size and the die size are known in advance, however, as our “squares” have spaces
between them (e.g. scribe lines) and the area located at the edge of the wafer cannot be used,
the calculation is a bit tricky, therefore, some recommend using the Die per Wafer tools results
as an estimation rather than a calculation.

d – Wafer diameter [mm]

S – Die size [square mm]

No. of dies = 399x50 = 19953.

Q5. How can u distinguish between bipolar, MOS and film IC?
A5.
Bipolar and MOS Integrated Circuits
On the basis of the active devices used, the ICs are classified as bipolar ICs and unipolar
ICs. The bipolar ICs use bipolar junction transistors (BJTs), while the unipolar ICs use field
effect transistors (FETs).

Film IC –
 Film integrated circuits are larger than monolithic ICs but smaller than discrete circuits.
Film components are made of either conductive or non-conductive material that is deposited in
desired patterns onto a ceramic or glass substrate.
Film integrated circuits are broken down into two categories, thin film and thick film
according to the thickness of the film layer. Film can only be used for passive circuit
components, such as resistors and capacitors. Transistors and/or diodes are added as discrete
components to the substrate to complete the circuit.

Q6. How many gates per chip are used in first generation Integrated Circuits?
a) 3-30
b) 30-300
c) 300-3000
d) More than 3000

Answer: a
Explanation: The first generation ICs belongs to small scale integration, which consists of 3-30
gates per chip (approximately).

Q7. What type of integration is chosen to fabricate Integrated Circuits like Counters,
multiplexers and Adders?
a) Small Scale Integration (SSI)
b) Medium Scale Integration (MSI)
c) Large Scale Integration (LSI)
d) Very Large Scale Integration (VLSI)

Answer: b
Explanation: Fabrication of ICs like counter, multiplexers and Adders requires 30-300 gates per
chip. Therefore, Medium Scale Integration is best suitable.

Q8. The concept of Integrated circuits was introduced at the beginning of 1960 by
a) Texas instrument and Fairchild Semiconductor
b) Bell telephone laboratories and Fair child Semiconductor
c) Fairchild Semiconductor
d) Texas instrument and Bell telephone Laboratories

Answer: a
Explanation: The concept of Integrated circuits was introduced by Texas instrument and
Fairchild Semiconductor, whereas Bell telephone laboratories developed the concept of
transistors.

Q9. In Crzochralski crystal growth process, the materials are heated up to

a) 950oC
b) 1000oC
c) 1420oC
d) 1200oC

Answer: c
Explanation: The materials are heated above 1420oc which is greater than the silicon melting
point.
Q10. Which method is most suitable for silicon crystal growth in silicon wafer
preparation?
a) Float zone process
b) Bridgeman-Stockbarger method
c) Czochralski crystal growth process
d) Laser heated pedestal growth

Answer: c
Explanation: Czochralski crystal growth processes obtain single crystal of semiconductor. The
most important application of this method may be growth of large cylindrical ingot of single
crystal silicon.

Q11. ……………… ICs are the most commonly used

a) Thin films
b) Monolithic
c) Hybrid
d) None of the above

Answer: b
Explanation: Monolithic ICs are the most commonly used

Q12. ……………. cannot be fabricated on an IC

a) Transistors
b) Diodes
c) Resistors
d) Large inductors and transformers

Answer: d
Explanation: Large inductors and transformers cannot be fabricated on an IC.

Q13. How to obtain silicon ingots of 10-15 cm diameter?

a) By crystal pulling process
b) By crystal melting process
c) By crystal growing process
d) All of the mentioned

Answer: a
Explanation: During crystal pulling process, the seed crystal and the crucible rotate in opposite
direction, in order to produce ingots of circular cross section (diameter of 10/15cm normally
obtained).

Q14. If the thickness of wafer after all polishing steps in silicon wafer preparation is 23-
40 mils. Find its raw cut slice thickness?
a) 16-32 mils
b) 23-40 mils
c) 8-12 mils
d) None of the mentioned

Answer: a
Explanation: Usually the silicon wafer obtained has a very rough surface due to slicing
operation. So, these wafers undergo a number of polishing steps to produce flat and smooth
polished surface. Therefore, the thickness of wafers will be reduced from its raw cut slice.