A B C D E

1 1

LCFC Confidential

T
M
rS
Yx70 GN20E M/B Schematics Document
fo
y
2

Alder Lake P-Processor with DDR5 + NV GN20-E GPU 2

nl
lO
tia
en

2021-11-29
fid

3
REV:A0 3
on
C
FC
LC

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y550 A.0

Date: Monday, November 29, 2021 Sheet 1 of 110

A B C D E
 A B C D E

VBIOS ROM/2MB

nVidia GN20-P0/P1
PCI-Express 8X DDR5-SO-DIMM x1
1 1
HDMI Conn.
DDR5 4800MT/s
GDDR6 4/8GB UP TO 16G x 1
eDP x4 Lane 8.1Gbps

T
DDR5-SO-DIMM x1
eDP Conn eDP x4 Lane MUX DDR5 4800MT/s

M
FHD 8.1Gbps PS8461E for 8.1G sw

PS8361L for 5.4G

UP TO 16G x 1
5.4Gbps
DP x4 Lane 8.1Gbps
type-C Left port
Type-C Conn Burnside Bridge eDP x4 Lane 8.1Gbps
JUSB1 support DP

rS
JUSBC1 TBT retimer TCP
page 52
left port

type-C PDC
page 51

fo
left port
DP x4 Lane 8.1Gbps

Type-C Conn. type-C MUX

JUSBC2 page 55 USB 3.2Gen2 x 10Gbps y
DP x4 Lane 8.1Gbps USB3.2 USB2.0
Back type-C Type-C Conn. USB3.2 Port3 USB2.0 Port3 SUB-Board
2
JUSBC3 type-C MUX USB 3.2Gen2 x 10Gbps
2
nl
JUSBC3 support DP&charge page 61
Intel CPU
SSD M.2 Conn.
ADL-P 45W
type-C PDC PCIe 4x Gen4 USB2.0 USB3.2 USB HUB
lO

Port 1 USB3.2 Port3 USB2.0 Port2 USB Back port

page 60 GL3523
PCIe Port 8-11
Lidless BGA
SSD M.2 Conn. 25mm*35mm USB2.0 1x
PCIe 4x Gen4 Port 2
Normal Camera for Y5/IR Camera for Y7
PCIe Port 4-7
tia

LAN Realtek PCIe 1x USB2.0 1x Y5 & Y7 colay

RJ45 Conn. RTL8111H-CG EC IT8176 int. keyboard

PCIe Port0

HD Audio EC IT8258 LED driver int LED conn

for Y7 MBIA045 *2
USB2.0 1x
en

Touch Pad IIC int LED conn

PCIe 1x
USB 2.0 1x
M.2 Card (WLAN&BT)
USB 2.0 1x USB2.0 Port10
PCIe 1x PCIe Port13

CNVio Page 54
SPI BUS M.2 CRF Module
fid

3 3
TOF sensor hub ESPI
SMBUS SPI BUS SPI ROM
SPK Conn. Codec 32MB
ALC3287-CG
on

SMBUS EC I2C
int. DMIC conn IT8227E-256CX MCU Force sensor conn

HP&Mic Combo Conn.

Sub-board
C

Battery Thermal Sensor Thermal Sensor CPU FAN

F75303M NCT7718W GPU FAN
USB3.2 x1 Y570 DB
I2C
Reserved
FC

RGB KB conn USB3.1 x1 Y570P DB

for RGB SKU

sensor board for Y570

MIC board for Y570P

LC

4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Block Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
YX70 intel A0

Date: Monday, November 29, 2021 Sheet 2 of 110

A B C D E
 5 4 3 2 1

B+ +5VLP/
Richtek
Adaptor RT6585C +5VALW/20A
EC_ON_3VALW_R EN1 Switch Mode
ALW_PWRGD
100W/TYPEC FOR SYS PGOOD
Page 91
D
300W/Wall-Plug D
EC_ON_5VALW_R EN2 +3VL/100mA

+3VALW/8A ANPEC
APL5934 +2.5V/1A

T
SYSON EN LDO
FOR DDR PGOOD

M
Richtek Page 93
+1.2V/11.4A
RT8231A
Switch Mode +0.6VS/1.1A

rS
SYSON_VDDQ S5 FOR DDR Richtec
SM_PG_CTRL S3 Page 93 PGOOD +0.95VGS/3.5A
RT8068
0.95V_MAIN_EN EN Converter
FOR GPU PGOOD 0.95VGS_PG
Page 103

fo
TI MPS
B+
BQ24800RUYR MP2950+MP86941 +VCCIN/61A
Switch Mode
Battery Charger FOR CPU Core
CPUCORE_ON EN
Page 95 PGOOD CPU_PWRGD
y
C
Switch Mode C
nl
Page 89
AOS
AOZ2264VQI
lO

VCCIN_AUX/18A
Converter
VCCIN_AUX_EN EN FOR CPU PGOOD
SMBus Page 96

Silergy
tia

SY8288 +1.8VALW/ 8A
Converter
EC_1.8VALW_EN EN FOR PCH PGOOD
en

Page 97

AOS
AOZ2264 VCCIN_AUX_PCH/10A
fid

Converter
VCCIN_AUX_EN EN FOR PCH PGOOD
Page 99
B B
on

Battery
Li-ion ON
NCP81610+NCP303150 NVVDD/115A
60Wh/80Wh Switch Mode
C

NVVDD_EN EN FOR GPU NVVDD PGOOD NVVDD_PWRGD

Page 102

Richtek
FC

RT8816 FBVDDQ/ 36A

Switch Mode
FBVDDQ_PWR_EN EN PGOOD FBVDDQ_PWROK
FOR GPU
Page 107
LC

AOS
AOZ2151 +10V/4A
Converter
SUSP_N EN
A FOR Fan & Audio A
Page 90 PGOOD

Security Classification LC Future Center Secret Data Title

Issued Date 2020/09/16 Deciphered Date 2020/09/16 Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y560 INTEL
Date: Monday, November 29, 2021 Sheet 3 of 110
5 4 3 2 1
 5 4 3 2 1

+3VS
DDR DIMMA
DDR DIMMB
2.2K
+3VALW_PCH

+3VALW_AG
+3VS
PS8419_VDD33
2.2K
Dual MOS
Anti Ghost Thermal Sensor
IT8176 or IT8258 2.2K
HDMI Retimer
NCT7718W 2.2K
PS8419QFN46
UI22 or UI1 US134 EDP CONN +LCD_VDD 2.2K
U3401 PCH_SMBDATA
PCH_SMBCLK +USB_VBUS
+3VALW_SYS
D
SN2011060YBGR D

RGB U5410
2.2K

2.2K
Dual MOS Dual MOS FXMA2102UMX Dual MOS +1.8VALW

Reserved Reserved

2.2K
Isolator
EC_SMB_CK0
EC_SMB_DA0

T
SML0DATA
SML0CLK VBUS_TBTA
SN2011060YBGR
U5411

M
2.2K
+1.8VALW

+3VALW_R
Change IC

rS
Battery BQ24800RUYR 2.2K Isolator
JBATT1 PU5401
2.2K

SML1DATA
SML1CLK

fo
+1.8VS_AON
EC EC_SMB_CK1
EC_SMB_DA1
PCH
2.2K
+3VS
C
VGA( UG1 ) C

UE1 Elan TP Synaptics TP

IT8227E +3VS
VGA_SMB_CK2
VGA_SMB_DA2
Thermal sensor NVDD controller eDP MUX
y
UH1
TGL-H
PK09000C190 PK09000G920
F75303M PAC1934T-I PS8461 2.2K
NCP81610AMNTXG
nl
+1.8VS_AON
US1 PU7902 UV12 (Reserve)
2.2K
Dual MOS Control PU2007(Reserved)

PCH_I2C1_SCL
lO

PCH_I2C1_SDA

EC_SMB_CK2
EC_SMB_DA2
+3VALW_R
PD Controller 1 PD Controller 2 +3V_SENSORHUB
SN2011062YBGR SN2011060YBGR
tia

2.2K
U5410 U5411
Sensor
2.2K

EC_SMB_CK4_PD
en

EC_SMB_DA4_PD +3VALW_PCH

2.2K
Dual MOS
fid

PCH_I2C2_CLK
PCH_I2C2_SDA
B B

+3VS +3VS
on

GPU PWR Monitor NVDD controller

2.2K 2.2K
PU7801 PU2007
SMBUS Control Table
C

SOURCE VGA BATT IT8226E SODIMM WLAN Thermal PCH TP Charger RGB KB USB-C HiFi Audio Anti-ghost
WiMAX Sensor Module Backlight PD +1.8VS_AON

EC_SMB_CK0 IT8226E
X X X X X X X X X X V X V
EC_SMB_DA0 +3VALW
+5VS +3VALW_AG

2.2K
Dual MOS Dual MOS
FC

EC_SMB_CK1 IT8226E X V V X X X X X V X X X X
EC_SMB_DA1 +3VALW_R +3VALW_R +3VALW_R +3VALW_R

EC_SMB_CK2 IT8226E V X V X X V V X X X X X X
+3VS
EC_SMB_DA2 +3VS +1.8VS_AON +3VS Reserve +3VALW_PCH

PCH_SMBCLK
PCH V V GPU I2CC_SCL
PCH_SMBDATA +3VALW_PCH X X X +3VS X X X +3VS X X X X X I2CC_SDA
PCH_RGBKB_SCL V
PCH_RGBKB_SDA X X X X X X X X X X +LDO_3V3 X X X
LC

EC_SMB_CK0 IT8226E
+3VALW V
EC_SMB_DA0 X X X X X X X X X X +5VS X X EDP
UG1
EC SMBus address CPU SMBus address CPU I2C ADDRESS GPU I2C ADDRESS
GN20-E3/E5
Device Address Device Address Device Address Device Address +1.8VS_AON
Thermal Sensor 1001_101xb DDR DIMMA 1010 000X b TP TBD GPU PWR Monitor 0x35

RGB TBD DDR DIMMB 1010 010X b sensor 0XF01800 NVDD controller 0x40
AG 8258&8176 TBD PD1-U5411 0X27 EDP TBD
sensor
Battery
0XF03500
TBD
PD2-U5410 0X24
2.2K
Dual MOS
Charger 0x12H
A VGA 0X9E A

HDMI retimer 0X30-0X4F

PAC1934T-I 0010_001

PD1-UU5411 0X23

PD2-UU5410 0X20 I2CB_SCL

I2CB_SDA

Security Classification
Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Blank4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
E
Y550 A0

Date: Monday, November 29, 2021 Sheet 4 of 110

5 4 3 2 1
 5 4 3 2 1

GN20x-E GPIO H=High: Tied to 1.8V

M=Middle: Tied to 0.9V
GPIO I/O GPIO Name Function Description Net name I/O Termination
L=Low: Tied to 0V FS_OVERT# FUNCTION
GPIO0 OUT NVVDD_PWM_VID PWM Output to control NVVDD NVVDD_PWM_VID
STRAP2 STRAP1 STRAP0 RAMCFG[4:0] GN20x-E VRAM ROM_SO ROM_SI ROM_SCLK FS_OVERT# FUNCTION
GPIO1 OUT GC6:GC6_FB_EN FB Enable for GC6 FB_GC6_EN (10K PD) Samsung
L L L 0 (0x0000) K4Z80325BC-HC14 L L H FS_OVERT# function ENABLE
GPIO2 IN GC6:GPU_EVENT* Wake the GPU from GC6 state GPU_EVENT#_R (10K PU) Micron FS_OVERT# function DISABLED
L L H 1 (0x0001) MT61K256M32JE-14:A L L L Reserved; do not configure
GPIO3 OUT DISP_MUX_CNTL Display MUX control signal GPU_MUX_CNTL (10K PD) Hynix
D L H L 2 (0x0002) H56C8H24AIR-S2C D

GPIO4 OUT MSVDD_EN GPU power sequencing for GC6 ---MSVDD_EN GPIO4_GC6_MSVDD_EN (10K PU)
L H H 3 (0x0003)
GPIO5 OUT FRAME_LOCK* Active low Frame Lock for NVSR panel UNUSED
H L L 4 (0x0004)
GPIO6 OUT NVVDD_PSI* Phase Shedding, NVVDD_PSI NVVDD_PSI (10K PU) RSVD
H L H 5 (0x0005)
GPIO7 OUT LCD_BL_PWM LCD Panel Backlight PWM GPU_EDP_PWM (100K PD)
H H L 6 (0x0006)

T
GPIO8 OUT MEM_VDD_CTL Memory voltage Control FBVDDQ_SEL (10K PD)
H H H 7 (0x0007)

M
GPIO9 I/O THERM_ALERT* Active Low Thermal Alert VGA_ALERT# (10K PU)
L L M 8 (0x0008)
GPIO10 OUT MEM_VREF_CTL Memory VREF Control MEM_VREF_CTL (100K PD) Samsung(for E7)
L M L 9 (0x0009) K4ZAF325BM-HC 14

rS
GPIO11 OUT LCD_VDD LED Panel power enable GPU_EDP_ENVDD (10K PD)
L M H 10 (0x000A)
GPIO12 IN PWR_LEVEL AC power detect or power supply overdraw input VGA_AC_DET_R (10K PU)
L H M 11 (0x000B)
GPIO13 IN IGPU_BL_EN Signal indicating when the IGPU has EN the BL iGPU_EDP_ENBKL (100K PU)
M L L 12 (0x000C)

fo
GPIO14 IN HPD_IFPA* Hot Plug Detect for IFPA IFPA_HPD (10K PU)
M L H 13 (0x000D)
GPIO15 IN HPD_IFPB* Hot Plug Detect for IFPB IFPB_HPD (10K PU)

C GPIO16 OUT DISP_MUX_PWM_CNTL Allows switching the PWM between IGPU & DGPU PWM_SW_SELECT (10K PD) C
y
GPIO17 IN HPD_IFPD* Hot Plug Detect for IFPD GPU_EDP_HPD (10K PU)
nl
GPIO18 IN HPD_IFPE* Hot Plug Detect for IFPE UNUSED
lO

GPIO19 OUT UNUSED

GPIO20 OUT UNUSED

GPIO21 OUT LCD_BLEN LCD Panel Backlight Enable GPU_EDP_ENBKL (100K PD)
tia

GPIO22 OUT ADC_MUX_SEL OVRM MUX Input SEL ADC_MUX_SEL (2.2K PU)

GPIO23 OUT UNUSED UNUSED

HPD_IFPF*/USBC_HPD*
GPIO24 IN or DONGLE_DET* Hot Plug Detect for IFPF or USBC UNUSED
en

GPIO25 OUT FBVDD_PSI Turns off phases of the Frame buffer power supply FBVDDQ_PSI (5.1K PU)
1:SMB_ALT_ADDR ENABLE
ROM_WP* Connect to WP pin of the GPU EEPROM GPIO26_ROM_WP (10K PD) STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE
GPIO26 OUT 0:SMB_ALT_ADDR DISABLE
FP_FUSE N18P-G61-A Control FP_FUSE GPIO26_FP_FUSE (10K PD) RSVD
M H H 1 1 1 1
fid

GPIO27 IN HPD_IFPC* Hot Plug Detect for IFPC IFPC_HPD (10K PU) 1:DEVID_SEL REBRAND
M H L 1 1 1 0 0:DEVID_SEL ORIGNAL
GPIO28 OUT MSVDD_PWM_VID PWM Ooutput to CNTL MSVDD UNUSED
B B
M L H 1 1 0 1 1:PCIE_CFG LOW POWER
GPIO29 OUT NVVDD_EN NVVDD Enable RSVD GPIO29_NVVDD_EN (100K PU)RSVD
on

0:PCIE_CFG HIGH POWER

M L L 1 1 0 0
GPIO30 OUT MSVDD_PSI* Phase Shedding UNUSED
1:VGA_DEVICE ENABLE
L H M 1 0 1 1
0:VGA_DEVICE DISABLE
C

L M H 1 0 1 0
GN20x-E Power Sequence
L M L 1 0 0 1
PLT_RST_VGA_N
L L M 1 0 0 0
FC

PLT_RST_VGA_N PXS_PWREN
H H H 0 1 1 1

PXS_PWREN +0.95VGS H H L 0 1 1 0

+1.8VS_VGA(VPP) NVVDD H L H 0 1 0 1 1 DEFAULT

LC

NVVDD FBVDDQ H L L 0 1 0 0
+1.8VS_VGA(VPP)
+0.95VGS L H H 0 0 1 1
VGA_PWRGD
FBVDDQ L H L 0 0 1 0

VGA_PWRGD L L H 0 0 0 1
A A

L L L 0 0 0 0
1. The ramp time for any rail must be more than 40us 1. For GDDR6, VPP must be equal to or higher than
and is recommended to be less than 2ms. FBVDD/Q at all times;use gate logic and discharge
circuit as needed
2. It is recommended that the delay from 1V8 on to
PEXVDD/GPU_PGOOD assertion not exceed 20ms. 2. All 3.3V devices that connect to the GPU must be
ramp down before 1V8; GPU can NOT have any 3.3V
3.The ramp-up overshoot should not exceed the silicon leakage path after 1V8 power down.
reliability limit voltage. Title
3. Power down of PEXVDD must be less than 10% before Security Classification LCFC Highly Confidential Information
4. Power up NVVDD must be 90% before PEXVDD can NVVDD can start ramp-down. Issued Date 2018/08/02 N18E VGA Notes List
ramp-up. 2018/08/02 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
5. Refer to the JEDEC Memory SPEC for memory-related power sequencing. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
7. FBVDD/Q, USB_VDDP and 1V8_AON don't need power cycle for GC6
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y550
Date: Monday, November 29, 2021 Sheet 5 of 110
5 4 3 2 1
 Voltage Rails ( O --> Means ON
5
, X --> Means OFF )
4 3 2 1
+5VS
+3VS
Power Plane VCCIO
VCCSA
VCCSTG
+3VALW
+3VALW_PCH +1.2V VCCCPUCORE
B+ VCCGFXCORE
+5VALW +1.8VS_AON
+1.8VGS
State
NVVDD
+1.0VGS

FBVDDQ

S0 O O O O O
D S3 O O O O X
D
S3
Battery only O O O O X

S5 S4/AC Only O O O X X

T
S5 S4
Battery only O X X X X
S5 S4
AC & Battery X X X X X

M
don't exist

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

rS
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF

BOM Structure Control Table

USB2.0 Port table BOM Structure BTO Item

fo
Port Function @ Not stuff
Codec@ SPK USED CODEC STUFF
1 DB USB Port DDS@ NV DDS Logic Part
2 Back USB Port RGB@ RGB KB Stuff
8111GUL@ LAN Chip 8111GUL part
3 Back AOU Port 8111H@ LAN Chip 8111H part
4 Back Type-C port AG@ IT8176 Stuff
BL@ BL
5 Anti Ghost

C 6
7
Camera
TBT A Port
EMC@
EMC_NS@
EMC_8111H@
ME@
EMC part
EMC not stuff
LAN 8111H EMC Part
ME part(connector, hole)
y C
nl
8 TBT B Port RF@ RF Stuff
RF_NS@ RF Unstuff
9 RGB & MCU Colay OPT@ For NV GPU part
10 BT Shutter@ Shutter Stuff
Y5@ Y570&Y570P Stuff
Y7@ Y770 Stuff
lO

USB3.0 Port table X76@ VRAM

Port Function E5@ GN20E_E5 Stuff

USB1 BACK USB E3@ GN20E_E3 Stuff
10V@ For 10V FAN Stuff
USB2 DB USB
BOM Structure BTO Item
USB3 Back USB AOU 5V@ For 5V FAN Stuff
USB4 BACK Type-C A2@ EDP MUX A2 stuff,A3 unstuff
CNVI@ CNVI Stuff
Debug@ USB-A support Debug stuff
tia

USB@ USB-A not support Debug stuff

SATA Port table Lighting@ Support Lighting function stuff
Port Function Mirror@ EC Mirror need stuff
NON_Mirror@ EC not mirror stuff
0 NA NON_E3@ E3 GPU unstuff
1 NA SYS_LED@ Systerm LED function stuff
Y570@ Y570 project stuff
Y570P@ Y570P project stuff
en

I7@ Stuff I7 CPU

PCIE Port table I5@ Stuff I5 CPU
Port Function 8Gb@ 8Gb VRAM stuff
16Gb@ 16Gb VRAM stuff
1--4 USB PORT
5--8 TBT
9 WLAN
10 LAN
fid

11--12 Not used

B B
on
C
FC
LC

A A
Security Classification LCFC Highly Confidential Information Title

Issued Date Deciphered Date

<Title>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A0 <Doc> EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS
DEPARTMENT A0 SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, November 29, 2021 6 110 Date: Sheet of

5 4 3 2 1
 5 4 3 2 1

D D

?
?

UC1A BMAP_REV = ? 220nF AC cap should be placed on DRX lines close to SOC side.
CPU_EDP_TX3_P
Can be placed near Re-timer as well.
W3 BE8
45 CPU_EDP_TX3_P CPU_EDP_TX3_N DDIA_TXP_3 TCP0_TXRX_P1 TCP0_CRX_DTX1_P 52
AA3 BE6
45 CPU_EDP_TX3_N CPU_EDP_TX2_P DDIA_TXN_3 TCP0_TXRX_N1 TCP0_CRX_DTX1_N 52
AA1 BG8
45 CPU_EDP_TX2_P CPU_EDP_TX2_N DDIA_TXP_2 TCP0_TXRX_P0 TCP0_CRX_DTX0_P 52
AB1 BG6
45 CPU_EDP_TX2_N CPU_EDP_TX1_P DDIA_TXN_2 TCP0_TXRX_N0 TCP0_CRX_DTX0_N 52
AB3 AY3
45 CPU_EDP_TX1_P CPU_EDP_TX1_N DDIA_TXP_1 TCP0_TX_P1 TCP0_CTX_DRX1_P 52

T
AD3 BB3
45 CPU_EDP_TX1_N CPU_EDP_TX0_P DDIA_TXN_1 TCP0_TX_N1 TCP0_CTX_DRX1_N 52 +3VALW_PCH
AF1 BD3
45 CPU_EDP_TX0_P CPU_EDP_TX0_N DDIA_TXP_0 TCP0_TX_P0 TCP0_CTX_DRX0_P 52
AD1 BE3
45 CPU_EDP_TX0_N DDIA_TXN_0 TCP0_TX_N0 TCP0_CTX_DRX0_N 52
BB1
CPU_EDP_AUXP TCP0_AUX_P TCP0_AUX_P 52
AF3 BD1

M
45 CPU_EDP_AUXP CPU_EDP_AUXN DDIA_AUXP TCP0_AUX TCP0_AUX_N 52
AG3
45 CPU_EDP_AUXN DDIA_AUXN AV8
ER23 TCP1_TXRX_P1 AV6 GPP_E21 RC1117 1 @ 2 1/20W_4.7K_5%_0201
ET23 GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1 AY8
GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0 AY6 CPU_TBT_LSX0_RXD RC2491 1 @ 2 4.7K_0402_1%

rS
PCH_EDP_HPD EV25 TCP1_TXRX_N0 AP3
45 PCH_EDP_HPD GPP_E14/DDSP_HPDA/DISP_MISC_A TCP1_TX_P1 AR3
AP6 TCP1_TX_N1 AU3
AP8 DDIB_TXP_3 TCP1_TX_P0 AW3
AM6 DDIB_TXN_3 TCP1_TX_N0 AR1
AM8 DDIB_TXP_2 TCP1_AUX_P AU1 GPP_E21 RC1121 1 @ 2 1/20W_20K_5%_0201
AK6 DDIB_TXN_2 TCP1_AUX CPU_TBT_LSX0_RXD RC2490 1 @ 2 1/20W_20K_5%_0201
AK8 DDIB_TXP_1 BN8
AH6 DDIB_TXN_1 TCP2_TXRX_P1 BN6

fo
AH8 DDIB_TXP_0 TCP2_TXRX_N1 BL8 PCH_EDP_PWM RC1113 1 2 100K_0201_5%
DDIB_TXN_0 TCP2_TXRX_P0 BL6
AE6 TCP2_TXRX_N0 BK3 PCH_EDP_ENBKL RC1114 1 2 100K_0201_5%
AE8 DDIB_AUXP TCP2_TX_P1 BM3
DDIB_AUXN TCP2_TX_N1 BG3 PCH_EDP_ENVDD RC1115 1 2 100K_0201_5%
EK46 TCP2_TX_P0 BH3
C EL46 GPP_H15/DDPB_CTRLCLK/PCIE_LINK_DOWN TCP2_TX_N0 BH1 LCD_OD_N RC1109 1 2 10K_0201_5% C

CNVI_EN_N RC2509 1 @ 2 0_0201_5% CPU_GPP_A18 EB47

GPP_H17/DDPB_CTRLDATA

GPP_A18/DDSP_HPDB/DISP_MISCB
yTCP2_AUX_P
TCP2_AUX
BK1

BW8
CPU_TBT_LSX0_TXD RC341 1 @ 2 1/20W_1M_1%_0201

EC_SCI_K2_R TCP3_TXRX_P1
nl
DV54 BW6
LCD_OD_N DV52 GPP_A21/DDPC_CTRLCLK TCP3_TXRX_N1 BU8
47 LCD_OD_N GPP_A22/DDPC_CTRLDATA TCP3_TXRX_P0 BU6
CPU_TBT_LSX0_TXD ER26 TCP3_TXRX_N0 BU3
52 CPU_TBT_LSX0_TXD CPU_TBT_LSX0_RXD GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD/BSSB_LS0_RX TCP3_TX_P1
ET26 BV3
52 CPU_TBT_LSX0_RXD GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD/BSSB_LS0_TX TCP3_TX_N1 BN3
lO

EL26 TCP3_TX_P0 BR3

GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD/BSSB_LS1_RX TCP3_TX_N0 LCD over drive control
GPP_E21 EN26 BR1
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD/BSSB_LS1_TX TCP3_AUX_P OD: low for OD off(*Default) +3VS
BU1
FC37 TCP3_AUX High for OD on
EV37 GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/BSSB_LS2_RX/GSPI2_CS0# AL3 LCD_OD_N RC1110 1 @ 2 10K_0201_5%
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/BSSB_LS2_TX/GSPI2_CLK VSS_589 AM1 TCRCOMPN
EY37 TCP_RCOMP
FA37 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/BSSB_LS3_RX/GSPI2_MISO AF32 DSI_DE_TE_2
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/BSSB_LS3_TX/GSPI2_MOSI DISP_UTILS_2
tia

DDIA_RCOMP
DY54 AJ1
CNVI_EN_N RC2508 1 @ 2 0_0201_5% CPU_GPP_A19 EB49 GPP_A17/DISP_MISCC DDIA_RCOMP AL1 DDIB_RCOMP
71 CNVI_EN_N CPU_HDMI_HPD GPP_I1 GPP_A19/DDSP_HPD1/DISP_MISC1 DDIB_RCOMP
50 CPU_HDMI_HPD RC1105 1 @ 2 0_0201_5% EB51
GPP_A20/DDSP_HPD2/DISP_MISC2 DJ1 1 TP2
DY47 DISP_UTILS_1 @ PAD
14 USB_OC1_N GPP_A14/USB_OC1#/DDSP_HPD3/DISP_MISC3
DY49
14,51,60 USB_OC2_N GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4
1

2
1/20W_100K_1%_0201

1/20W_2.2K_+-1%_0201
en

150_0402_1%

ET21
RC1103

2 RC1102

RC1101

RC1104
150_0402_1%

46 PCH_EDP_ENVDD VDDEN
EN21
46 PCH_EDP_ENBKL EDP_BKLTEN
EL21
46 PCH_EDP_PWM EDP_BKLTCTL
2

1 OF 22
INTEL_ADL-P-682_BGA1744
fid

B B
on

+3VS
1

RC1112
@ 10K_0201_5%
C

EC_SCI_N RC1111 1 @ 2 0_0201_5% EC_SCI_K2_R

79 EC_SCI_N
FC
LC

A A

Security Classification LCFC Highly Confidential Information Title

ORS-ADL_P
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. YX0 ORS
Date: Monday, November 29, 2021 Sheet 7 of 110
5 4 3 2 1
 5 4 3 2 1

?
?

UC1B BMAP_REV = ?
D D
DDR4(IL) / DDR4(NIL) / DDR5(NIL) / LP4x-LP5(NIL)
DDRA_DQ7 DH58 CD49
DDRA_DQ6 DDR0_DQ_0_7/DDR0_DQ_0_7/DDR0_DQ_0_7/DDR0_DQ_0_7 DDR0_CLK_P_1/DDR3_CLK_P/DDR3_CLK_P/DDR3_CLK_P/DDR1_CLK_P_1 CD48 DDRA_CLK3_P 25
DG57
DDRA_DQ5 DDR0_DQ_0_6/DDR0_DQ_0_6/DDR0_DQ_0_6/DDR0_DQ_0_6 DDR0_CLK_N_1/DDR3_CLK_N/DDR3_CLK_N/DDR3_CLK_N/DDR1_CLK_N_1 CH61 DDRA_CLK3_N 25
DH56
DDRA_DQ4 DDR0_DQ_0_5/DDR0_DQ_0_5/DDR0_DQ_0_5/DDR0_DQ_0_5 NC/DDR2_CLK_P/DDR2_CLK_P/DDR2_CLK_P/DDR1_CLK_P_0 CF61 DDRA_CLK2_P 25
DG60
DDRA_DQ3 DDR0_DQ_0_4/DDR0_DQ_0_4/DDR0_DQ_0_4/DDR0_DQ_0_4 NC/DDR2_CLK_N/DDR2_CLK_N/DDR2_CLK_N/DDR1_CLK_N_0 CN49 DDRA_CLK2_N 25
DL60
DDRA_DQ2 DDR0_DQ_0_3/DDR0_DQ_0_3/DDR0_DQ_0_3/DDR0_DQ_0_3 NC/DDR1_CLK_P/DDR1_CLK_P/DDR1_CLK_P/DDR0_CLK_P_1 CN48 DDRA_CLK1_P 25
DK56
DDRA_DQ1 DDR0_DQ_0_2/DDR0_DQ_0_2/DDR0_DQ_0_2/DDR0_DQ_0_2 NC/DDR1_CLK_N/DDR1_CLK_N/DDR1_CLK_N/DDR0_CLK_N_1 CU61 DDRA_CLK1_N 25
DL57
DDRA_DQ0 DDR0_DQ_0_1/DDR0_DQ_0_1/DDR0_DQ_0_1/DDR0_DQ_0_1 DDR0_CLK_P_0/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P_0 CR61 DDRA_CLK0_P 25
DK58
DDRA_DQ15 DDR0_DQ_0_0/DDR0_DQ_0_0/DDR0_DQ_0_0/DDR0_DQ_0_0 DDR0_CLK_N_0/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK_N_0 DDRA_CLK0_N 25
DA58
DDRA_DQ[0..63] DDRA_DQ14 CY57 DDR0_DQ_1_7/DDR0_DQ_1_7/DDR0_DQ_1_7/DDR0_DQ_1_7 CF51
25 DDRA_DQ[0..63] DDRA_DQ13 DDR0_DQ_1_6/DDR0_DQ_1_6/DDR0_DQ_1_6/DDR0_DQ_1_6 NC/DDR3_CKE_0/DDR3_WCK_P/DDR3_WCK_P/NC CH51
DB56
DDRA_DQ12 DDR0_DQ_1_5/DDR0_DQ_1_5/DDR0_DQ_1_5/DDR0_DQ_1_5 NC/DDR3_CKE_1/DDR3_WCK_N/DDR3_WCK_N/NC CE57

T
CY60
DDRA_DQ11 DE60 DDR0_DQ_1_4/DDR0_DQ_1_4/DDR0_DQ_1_4/DDR0_DQ_1_4 NC/DDR2_CKE_0/DDR2_WCK_P/DDR2_WCK_P/NC CF58
DDRA_DQ10 DD56 DDR0_DQ_1_3/DDR0_DQ_1_3/DDR0_DQ_1_3/DDR0_DQ_1_3 NC/DDR2_CKE_1/DDR2_WCK_N/DDR2_WCK_N/NC CR51
DDRA_DQ9 DE57 DDR0_DQ_1_2/DDR0_DQ_1_2/DDR0_DQ_1_2/DDR0_DQ_1_2 NC/DDR1_CKE_0/DDR1_WCK_P/DDR1_WCK_P/NC CU51
DDRA_DQ8 DD58 DDR0_DQ_1_1/DDR0_DQ_1_1/DDR0_DQ_1_1/DDR0_DQ_1_1 NC/DDR1_CKE_1/DDR1_WCK_N/DDR1_WCK_N/NC CR58

M
DDRA_DQ23 DG50 DDR0_DQ_1_0/DDR0_DQ_1_0/DDR0_DQ_1_0/DDR0_DQ_1_0 NC/DDR0_CKE_0/DDR0_WCK_P/DDR0_WCK_P/NC CP57
DDRA_DQ22 DG47 DDR1_DQ_0_7/DDR0_DQ_2_7/DDR0_DQ_2_7/DDR1_DQ_0_7 NC/DDR0_CKE_1/DDR0_WCK_N/DDR0_WCK_N/NC
DDRA_DQ21 DH48 DDR1_DQ_0_6/DDR0_DQ_2_6/DDR0_DQ_2_6/DDR1_DQ_0_6 BN51 DDRA_DQS7_P
DDRA_DQ20 DDR1_DQ_0_5/DDR0_DQ_2_5/DDR0_DQ_2_5/DDR1_DQ_0_5 DDR1_DQSP_3/DDR0_DQSP_7/DDR1_DQSP_3/DDR3_DQSP_1 BL51 DDRA_DQS7_N DDRA_DQS7_P 25
DG53
DDRA_DQ19 DDR1_DQ_0_4/DDR0_DQ_2_4/DDR0_DQ_2_4/DDR1_DQ_0_4 DDR1_DQSN_3/DDR0_DQSN_7/DDR1_DQSN_3/DDR3_DQSN_1 BW51 DDRA_DQS6_P DDRA_DQS7_N 25
DL53
DDRA_DQS6_P 25

rS
DDRA_DQ18 DK48 DDR1_DQ_0_3/DDR0_DQ_2_3/DDR0_DQ_2_3/DDR1_DQ_0_3 DDR1_DQSP_2/DDR0_DQSP_6/DDR1_DQSP_2/DDR3_DQSP_0 BU51 DDRA_DQS6_N
DDRA_DQ17 DDR1_DQ_0_2/DDR0_DQ_2_2/DDR0_DQ_2_2/DDR1_DQ_0_2 DDR1_DQSN_2/DDR0_DQSN_6/DDR1_DQSN_2/DDR3_DQSN_0 BL61 DDRA_DQS5_P DDRA_DQS6_N 25
DM47
DDRA_DQ16 DDR1_DQ_0_1/DDR0_DQ_2_1/DDR0_DQ_2_1/DDR1_DQ_0_1 DDR0_DQSP_3/DDR0_DQSP_5/DDR1_DQSP_1/DDR2_DQSP_1 BN61 DDRA_DQS5_N DDRA_DQS5_P 25
DL50
DDRA_DQ31 DDR1_DQ_0_0/DDR0_DQ_2_0/DDR0_DQ_2_0/DDR1_DQ_0_0 DDR0_DQSN_3/DDR0_DQSN_5/DDR1_DQSN_1/DDR2_DQSN_1 BU61 DDRA_DQS4_P DDRA_DQS5_N 25
CY50
DDRA_DQ30 DDR1_DQ_1_7/DDR0_DQ_3_7/DDR0_DQ_3_7/DDR1_DQ_1_7 DDR0_DQSP_2/DDR0_DQSP_4/DDR1_DQSP_0/DDR2_DQSP_0 BW61 DDRA_DQS4_N DDRA_DQS4_P 25
CY47
DDRA_DQ29 DDR1_DQ_1_6/DDR0_DQ_3_6/DDR0_DQ_3_6/DDR1_DQ_1_6 DDR0_DQSN_2/DDR0_DQSN_4/DDR1_DQSN_0/DDR2_DQSN_0 DC51 DDRA_DQS3_P DDRA_DQS4_N 25
DB48
DDRA_DQ28 DDR1_DQ_1_5/DDR0_DQ_3_5/DDR0_DQ_3_5/DDR1_DQ_1_5 DDR1_DQSP_1/DDR0_DQSP_3/DDR0_DQSP_3/DDR1_DQSP_1 DB51 DDRA_DQS3_N DDRA_DQS3_P 25
DA53
DDRA_DQ27 DDR1_DQ_1_4/DDR0_DQ_3_4/DDR0_DQ_3_4/DDR1_DQ_1_4 DDR1_DQSN_1/DDR0_DQSN_3/DDR0_DQSN_3/DDR1_DQSN_1 DK51 DDRA_DQS2_P DDRA_DQS3_N 25
DE53
DDRA_DQ26 DDR1_DQ_1_3/DDR0_DQ_3_3/DDR0_DQ_3_3/DDR1_DQ_1_3 DDR1_DQSP_0/DDR0_DQSP_2/DDR0_DQSP_2/DDR1_DQSP_0 DH51 DDRA_DQS2_N DDRA_DQS2_P 25
DC48

fo
DDRA_DQ25 DDR1_DQ_1_2/DDR0_DQ_3_2/DDR0_DQ_3_2/DDR1_DQ_1_2 DDR1_DQSN_0/DDR0_DQSN_2/DDR0_DQSN_2/DDR1_DQSN_0 DB61 DDRA_DQS1_P DDRA_DQS2_N 25
DE47
DDRA_DQ24 DDR1_DQ_1_1/DDR0_DQ_3_1/DDR0_DQ_3_1/DDR1_DQ_1_1 DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1 DC61 DDRA_DQS1_N DDRA_DQS1_P 25
DE50
DDRA_DQ39 DDR1_DQ_1_0/DDR0_DQ_3_0/DDR0_DQ_3_0/DDR1_DQ_1_0 DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1 DH61 DDRA_DQS0_P DDRA_DQS1_N 25
BU58
DDRA_DQ38 DDR0_DQ_2_7/DDR0_DQ_4_7/DDR1_DQ_0_7/DDR2_DQ_0_7 DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0 DK61 DDRA_DQS0_N DDRA_DQS0_P 25
BT57
DDRA_DQ37 DDR0_DQ_2_6/DDR0_DQ_4_6/DDR1_DQ_0_6/DDR2_DQ_0_6 DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0 DDRA_DQS0_N 25
BU56
DDRA_DQ36 BT60 DDR0_DQ_2_5/DDR0_DQ_4_5/DDR1_DQ_0_5/DDR2_DQ_0_5 CM60
C DDRA_DQ35 BY60 DDR0_DQ_2_4/DDR0_DQ_4_4/DDR1_DQ_0_4/DDR2_DQ_0_4 DDR0_MA_5/DDR0_CA_5/DDR0_CA_6/DDR0_CA_0/NC CL55 C
DDRA_DQ34
DDRA_DQ33
DDRA_DQ32
BW56
BY57
BW58
DDR0_DQ_2_3/DDR0_DQ_4_3/DDR1_DQ_0_3/DDR2_DQ_0_3
DDR0_DQ_2_2/DDR0_DQ_4_2/DDR1_DQ_0_2/DDR2_DQ_0_2
DDR0_DQ_2_1/DDR0_DQ_4_1/DDR1_DQ_0_1/DDR2_DQ_0_1
y
DDR0_MA_7/DDR0_CA_4/DDR0_CA_5/DDR0_CA_1/NC CM57
DDR0_MA_6/DDR0_CA_3/DDR0_CA_4/DDR0_CS_1/NC CP60
DDR0_MA_8/DDR0_CA_2/DDR0_CA_3/DDR0_CS_0/DDR0_CA_9 CU58
DDRA_0_CA9
DDRA_0_CA0 DDRA_0_CA9 25
DDRA_DQ47 DDR0_DQ_2_0/DDR0_DQ_4_0/DDR1_DQ_0_0/DDR2_DQ_0_0 NC/DDR0_CA_1/DDR0_CA_1/DDR0_CA_5/DDR0_CA_0 CU56 DDRA_0_CA1 DDRA_0_CA0 25
nl
BL58
DDRA_DQ46 DDR0_DQ_3_7/DDR0_DQ_5_7/DDR1_DQ_1_7/DDR2_DQ_1_7 NC/DDR0_CA_0/DDR0_CA_0/DDR0_CA_6/DDR0_CA_1 CM47 DDRA_0_CA10 DDRA_0_CA1 25
BK57
DDRA_DQ45 DDR0_DQ_3_6/DDR0_DQ_5_6/DDR1_DQ_1_6/DDR2_DQ_1_6 DDR0_BA_1/DDR1_CA_5/DDR1_CA_6/DDR1_CA_0/DDR0_CA_10 CM53 DDRA_0_CA8 DDRA_0_CA10 25
BL56
DDRA_DQ44 DDR0_DQ_3_5/DDR0_DQ_5_5/DDR1_DQ_1_5/DDR2_DQ_1_5 DDR0_MA_16/DDR1_CA_4/DDR1_CA_5/DDR1_CA_1/DDR0_CA_8 CT46 DDRA_0_CA7 DDRA_0_CA8 25
BK60
DDRA_DQ43 DDR0_DQ_3_4/DDR0_DQ_5_4/DDR1_DQ_1_4/DDR2_DQ_1_4 DDR0_MA_15/DDR1_CA_3/DDR1_CA_4/DDR1_CS_1/DDR0_CA_7 CP53 DDRA_0_CA11 DDRA_0_CA7 25
BP60
DDRA_DQ42 DDR0_DQ_3_3/DDR0_DQ_5_3/DDR1_DQ_1_3/DDR2_DQ_1_3 DDR0_MA_14/DDR1_CA_2/DDR1_CA_3/DDR1_CS_0/DDR0_CA_11 CW47 DDRA_0_CA2 DDRA_0_CA11 25
BN56
lO

DDRA_DQ41 DDR0_DQ_3_2/DDR0_DQ_5_2/DDR1_DQ_1_2/DDR2_DQ_1_2 DDR0_CS_1/DDR1_CA_1/DDR1_CA_1/DDR1_CA_5/DDR0_CA_2 CV53 DDRA_0_CA3 DDRA_0_CA2 25

BP57
DDRA_DQ40 DDR0_DQ_3_1/DDR0_DQ_5_1/DDR1_DQ_1_1/DDR2_DQ_1_1 DDR0_ODT_1/DDR1_CA_0/DDR1_CA_0/DDR1_CA_6/DDR0_CA_3 CC60 DDRA_0_CA3 25
BN58
DDRA_DQ55 BT50 DDR0_DQ_3_0/DDR0_DQ_5_0/DDR1_DQ_1_0/DDR2_DQ_1_0 DDR0_CKE_0/DDR2_CA_5/DDR2_CA_6/DDR2_CA_0/NC CB55
DDRA_DQ54 BT47 DDR1_DQ_2_7/DDR0_DQ_6_7/DDR1_DQ_2_7/DDR3_DQ_0_7 DDR0_CKE_1/DDR2_CA_4/DDR2_CA_5/DDR2_CA_1/NC CC57
DDRA_DQ53 BU48 DDR1_DQ_2_6/DDR0_DQ_6_6/DDR1_DQ_2_6/DDR3_DQ_0_6 DDR0_BG_0/DDR2_CA_3/DDR2_CA_4/DDR2_CS_1/NC CE60 DDRA_1_CA4
DDRA_DQ52 DDR1_DQ_2_5/DDR0_DQ_6_5/DDR1_DQ_2_5/DDR3_DQ_0_5 DDR0_BG_1/DDR2_CA_2/DDR2_CA_3/DDR2_CS_0/DDR1_CA_4 CH56 DDRA_1_CA12 DDRA_1_CA4 25
BT53
DDRA_DQ51 DDR1_DQ_2_4/DDR0_DQ_6_4/DDR1_DQ_2_4/DDR3_DQ_0_4 DDR0_MA_12/DDR2_CA_1/DDR2_CA_1/DDR2_CA_5/DDR1_CA_12 CH58 DDRA_1_CA7 DDRA_1_CA12 25
BY53
DDRA_DQ50 DDR1_DQ_2_3/DDR0_DQ_6_3/DDR1_DQ_2_3/DDR3_DQ_0_3 DDR0_MA_9/DDR2_CA_0/DDR2_CA_0/DDR2_CA_6/DDR1_CA_7 CC53 DDRA_1_CS1 DDRA_1_CA7 25
BW48
DDR1_DQ_2_2/DDR0_DQ_6_2/DDR1_DQ_2_2/DDR3_DQ_0_2 NC/DDR3_CA_5/DDR3_CA_6/DDR3_CA_0/DDR1_CS_1 CC47 DDRA_1_CS1 25
tia

DDRA_DQ49 CA47 DDRA_1_CS0

DDRA_DQ48 DDR1_DQ_2_1/DDR0_DQ_6_1/DDR1_DQ_2_1/DDR3_DQ_0_1 NC/DDR3_CA_4/DDR3_CA_5/DDR3_CA_1/DDR1_CS_0 CE53 DDRA_1_CA0 DDRA_1_CS0 25
BY50
DDRA_DQ63 DDR1_DQ_2_0/DDR0_DQ_6_0/DDR1_DQ_2_0/DDR3_DQ_0_0 NC/DDR3_CA_3/DDR3_CA_4/DDR3_CS_1/DDR1_CA_0 CH46 DDRA_1_CA6 DDRA_1_CA0 25
BJ50
DDRA_DQ62 DDR1_DQ_3_7/DDR0_DQ_7_7/DDR1_DQ_3_7/DDR3_DQ_1_7 NC/DDR3_CA_2/DDR3_CA_3/DDR3_CS_0/DDR1_CA_6 CK47 DDRA_1_CA8 DDRA_1_CA6 25
BJ47
DDRA_DQ61 DDR1_DQ_3_6/DDR0_DQ_7_6/DDR1_DQ_3_6/DDR3_DQ_1_6 DDR0_MA_10/DDR3_CA_1/DDR3_CA_1/DDR3_CA_5/DDR1_CA_8 CJ53 DDRA_1_CA10 DDRA_1_CA8 25
BL48
DDRA_DQ60 DDR1_DQ_3_5/DDR0_DQ_7_5/DDR1_DQ_3_5/DDR3_DQ_1_5 DDR0_BA_0/DDR3_CA_0/DDR3_CA_0/DDR3_CA_6/DDR1_CA_10 DDRA_1_CA10 25
BK53
DDRA_DQ59 BP53 DDR1_DQ_3_4/DDR0_DQ_7_4/DDR1_DQ_3_4/DDR3_DQ_1_4 CV60 DDRA_0_CS1
DDR1_DQ_3_3/DDR0_DQ_7_3/DDR1_DQ_3_3/DDR3_DQ_1_3 DDR0_MA_3/DDR0_CS_1/DDR0_CS_0/DDR0_CA_3/DDR0_CS_1 CR56 DDRA_0_CS1 25
en

DDRA_DQ58 BN48 DDRA_0_CA12

DDRA_DQ57 DDR1_DQ_3_2/DDR0_DQ_7_2/DDR1_DQ_3_2/DDR3_DQ_1_2 DDR0_MA_4/DDR0_CS_0/DDR0_CA_2/DDR0_CA_2/DDR0_CA_12 CU48 DDRA_0_CA5 DDRA_0_CA12 25
BP47
DDRA_DQ56 DDR1_DQ_3_1/DDR0_DQ_7_1/DDR1_DQ_3_1/DDR3_DQ_1_1 DDR0_MA_13/DDR1_CS_1/DDR1_CS_0/DDR1_CA_3/DDR0_CA_5 CM50 DDRA_0_CA6 DDRA_0_CA5 25
BP50
DDR1_DQ_3_0/DDR0_DQ_7_0/DDR1_DQ_3_0/DDR3_DQ_1_0 DDR0_ODT_0/DDR1_CS_0/DDR1_CA_2/DDR1_CA_2/DDR0_CA_6 CJ57 DDRA_1_CA9 DDRA_0_CA6 25
DDR0_ACT_N/DDR2_CS_1/DDR2_CS_0/DDR2_CA_3/DDR1_CA_9 CF56 DDRA_1_CA2 DDRA_1_CA9 25
NC/DDR2_CS_0/DDR2_CA_2/DDR2_CA_2/DDR1_CA_2 CH48 DDRA_1_CA3 DDRA_1_CA2 25
DDR0_PAR/DDR3_CS_1/DDR3_CS_0/DDR3_CA_3/DDR1_CA_3 CC50 DDRA_1_CA1 DDRA_1_CA3 25
DDR0_MA_2/DDR3_CS_0/DDR3_CA_2/DDR3_CA_2/DDR1_CA_1 DDRA_1_CA1 25
fid

CV50 DDRA_0_CA4
DDRA_0_CA4 25
+VDD2_CPU
DDR0_CS_0/NC/DDR1_CS_1/DDR1_CA_4/DDR0_CA_4 CJ50 DDRA_1_CA5
DDR0_MA_0/NC/DDR3_CS_1/DDR3_CA_4/DDR1_CA_5 CV57 DDRA_0_CS0 DDRA_1_CA5 25
DDR0_MA_1/NC/DDR0_CS_1/DDR0_CA_4/DDR0_CS_0 CJ60 DDRA_1_CA11 DDRA_0_CS0 25
DDR0_MA_11/NC/DDR2_CS_1/DDR2_CA_4/DDR1_CA_11 DDRA_1_CA11 25
B
BF61 1 B
RC803
DDR0_ALERT BG60 1/16W_470_1%_0402
on

DDR0_VREF_CA0
BG50 DDR_VTT_CTRL PAD 1 @
TC7803
2

DDR_VTT_CTL EE53 CPU_DRAMRST_N RC801 1 @ 2 0_0201_5% DRAM_RESET_N

DRAM_RESET# DRAM_RESET_N 25,26
RC802
DDR_COMP
A56 2 1
DDR_COMP_1 B56
DDR_COMP_2 1/20W_100_1%_0201
C

2 OF 22
INTEL_ADL-P-682_BGA1744
@ <PART_NUMBER>
FC
LC

A A

Security Classification LCFC Highly Confidential Information Title

ORS-ADL_P
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. YX0 ORS
Date: Monday, November 29, 2021 Sheet 8 of 110
5 4 3 2 1
 5 4 3 2 1

D D

DDRB_DQ[0..63]
26 DDRB_DQ[0..63]

?
?

UC1C BMAP_REV = ?

T
DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5
DDRB_DQ7 BB58 V48
DDRB_DQ6 DDR0_DQ_4_7/DDR1_DQ_0_7/DDR2_DQ_0_7/DDR4_DQ_0_7 DDR1_CLK_P_1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P/DDR3_CLK_P_1 V49 DDRB_CLK3_P 26
BA57
DDRB_DQ5 DDR0_DQ_4_6/DDR1_DQ_0_6/DDR2_DQ_0_6/DDR4_DQ_0_6 DDR1_CLK_N_1/DDR7_CLK_N/DDR7_CLK_N/DDR7_CLK_N/DDR3_CLK_N_1 AB61 DDRB_CLK3_N 26
BB56
DDRB_DQ4 DDR0_DQ_4_5/DDR1_DQ_0_5/DDR2_DQ_0_5/DDR4_DQ_0_5 NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P/DDR3_CLK_P_0 Y61 DDRB_CLK2_P 26
BA60

M
DDRB_DQ3 DDR0_DQ_4_4/DDR1_DQ_0_4/DDR2_DQ_0_4/DDR4_DQ_0_4 NC/DDR6_CLK_N/DDR6_CLK_N/DDR6_CLK_N/DDR3_CLK_N_0 AG49 DDRB_CLK2_N 26
BE60
DDRB_DQ2 DDR0_DQ_4_3/DDR1_DQ_0_3/DDR2_DQ_0_3/DDR4_DQ_0_3 NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P/DDR2_CLK_P_1 AG48 DDRB_CLK1_P 26
BD56
DDRB_DQ1 DDR0_DQ_4_2/DDR1_DQ_0_2/DDR2_DQ_0_2/DDR4_DQ_0_2 NC/DDR5_CLK_N/DDR5_CLK_N/DDR5_CLK_N/DDR2_CLK_N_1 AL61 DDRB_CLK1_N 26
BE57
DDRB_DQ0 DDR0_DQ_4_1/DDR1_DQ_0_1/DDR2_DQ_0_1/DDR4_DQ_0_1 DDR1_CLK_P_0/DDR4_CLK_P/DDR4_CLK_P/DDR4_CLK_P/DDR2_CLK_P_0 AJ61 DDRB_CLK0_P 26
BD58
DDRB_DQ15 DDR0_DQ_4_0/DDR1_DQ_0_0/DDR2_DQ_0_0/DDR4_DQ_0_0 DDR1_CLK_N_0/DDR4_CLK_N/DDR4_CLK_N/DDR4_CLK_N/DDR2_CLK_N_0 DDRB_CLK0_N 26
AR58

rS
DDRB_DQ14 AP57 DDR0_DQ_5_7/DDR1_DQ_1_7/DDR2_DQ_1_7/DDR4_DQ_1_7 AB51
DDRB_DQ13 AR56 DDR0_DQ_5_6/DDR1_DQ_1_6/DDR2_DQ_1_6/DDR4_DQ_1_6 NC/DDR7_CKE_0/DDR7_WCK_P/DDR7_WCK_P/NC Y51
DDRB_DQ12 AP60 DDR0_DQ_5_5/DDR1_DQ_1_5/DDR2_DQ_1_5/DDR4_DQ_1_5 NC/DDR7_CKE_1/DDR7_WCK_N/DDR7_WCK_N/NC W57
DDRB_DQ11 AV60 DDR0_DQ_5_4/DDR1_DQ_1_4/DDR2_DQ_1_4/DDR4_DQ_1_4 NC/DDR6_CKE_0/DDR6_WCK_P/DDR6_WCK_P/NC Y58
DDRB_DQ10 AU56 DDR0_DQ_5_3/DDR1_DQ_1_3/DDR2_DQ_1_3/DDR4_DQ_1_3 NC/DDR6_CKE_1/DDR6_WCK_N/DDR6_WCK_N/NC AL51
DDRB_DQ9 AV57 DDR0_DQ_5_2/DDR1_DQ_1_2/DDR2_DQ_1_2/DDR4_DQ_1_2 NC/DDR5_CKE_0/DDR5_WCK_P/DDR5_WCK_P/NC AJ51
DDRB_DQ8 AU58 DDR0_DQ_5_1/DDR1_DQ_1_1/DDR2_DQ_1_1/DDR4_DQ_1_1 NC/DDR5_CKE_1/DDR5_WCK_N/DDR5_WCK_N/NC AJ58
DDRB_DQ23 BA50 DDR0_DQ_5_0/DDR1_DQ_1_0/DDR2_DQ_1_0/DDR4_DQ_1_0 NC/DDR4_CKE_0/DDR4_WCK_P/DDR4_WCK_P/NC AH57
DDRB_DQ22 AY47 DDR1_DQ_4_7/DDR1_DQ_2_7/DDR2_DQ_2_7/DDR5_DQ_0_7 NC/DDR4_CKE_1/DDR4_WCK_N/DDR4_WCK_N/NC

fo
DDRB_DQ21 BB48 DDR1_DQ_4_6/DDR1_DQ_2_6/DDR2_DQ_2_6/DDR5_DQ_0_6 N51
DDRB_DQ20 DDR1_DQ_4_5/DDR1_DQ_2_5/DDR2_DQ_2_5/DDR5_DQ_0_5 DDR1_DQSP_7/DDR1_DQSP_7/DDR3_DQSP_3/DDR7_DQSP_1 L51 DDRB_DQS7_P 26
BA53
DDRB_DQ19 DDR1_DQ_4_4/DDR1_DQ_2_4/DDR2_DQ_2_4/DDR5_DQ_0_4 DDR1_DQSN_7/DDR1_DQSN_7/DDR3_DQSN_3/DDR7_DQSN_1 N61 DDRB_DQS7_N 26
BE53
DDRB_DQ18 DDR1_DQ_4_3/DDR1_DQ_2_3/DDR2_DQ_2_3/DDR5_DQ_0_3 DDR1_DQSP_6/DDR1_DQSP_6/DDR3_DQSP_2/DDR7_DQSP_0 L61 DDRB_DQS6_P 26
BD48
DDRB_DQ17 DDR1_DQ_4_2/DDR1_DQ_2_2/DDR2_DQ_2_2/DDR5_DQ_0_2 DDR1_DQSN_6/DDR1_DQSN_6/DDR3_DQSN_2/DDR7_DQSN_0 A43 DDRB_DQS6_N 26
BE47
DDRB_DQ16 DDR1_DQ_4_1/DDR1_DQ_2_1/DDR2_DQ_2_1/DDR5_DQ_0_1 DDR0_DQSP_7/DDR1_DQSP_5/DDR3_DQSP_1/DDR6_DQSP_1 A44 DDRB_DQS5_P 26
BE50
DDRB_DQ31 DDR1_DQ_4_0/DDR1_DQ_2_0/DDR2_DQ_2_0/DDR5_DQ_0_0 DDR0_DQSN_7/DDR1_DQSN_5/DDR3_DQSN_1/DDR6_DQSN_1 A49 DDRB_DQS5_N 26
C AP50 C
DDRB_DQS4_P 26
DDRB_DQ30
DDRB_DQ29
DDRB_DQ28
AP47
AR48
AP53
DDR1_DQ_5_7/DDR1_DQ_3_7/DDR2_DQ_3_7/DDR5_DQ_1_7
DDR1_DQ_5_6/DDR1_DQ_3_6/DDR2_DQ_3_6/DDR5_DQ_1_6
DDR1_DQ_5_5/DDR1_DQ_3_5/DDR2_DQ_3_5/DDR5_DQ_1_5
y
DDR0_DQSP_6/DDR1_DQSP_4/DDR3_DQSP_0/DDR6_DQSP_0 A51
DDR0_DQSN_6/DDR1_DQSN_4/DDR3_DQSN_0/DDR6_DQSN_0 AU51
DDR1_DQSP_5/DDR1_DQSP_3/DDR2_DQSP_3/DDR5_DQSP_1 AR51
DDRB_DQS4_N
DDRB_DQS3_P
26
26
DDRB_DQ27 DDR1_DQ_5_4/DDR1_DQ_3_4/DDR2_DQ_3_4/DDR5_DQ_1_4 DDR1_DQSN_5/DDR1_DQSN_3/DDR2_DQSN_3/DDR5_DQSN_1 BD51 DDRB_DQS3_N 26
nl
AV53
DDRB_DQ26 DDR1_DQ_5_3/DDR1_DQ_3_3/DDR2_DQ_3_3/DDR5_DQ_1_3 DDR1_DQSP_4/DDR1_DQSP_2/DDR2_DQSP_2/DDR5_DQSP_0 BB51 DDRB_DQS2_P 26
AU48
DDRB_DQ25 DDR1_DQ_5_2/DDR1_DQ_3_2/DDR2_DQ_3_2/DDR5_DQ_1_2 DDR1_DQSN_4/DDR1_DQSN_2/DDR2_DQSN_2/DDR5_DQSN_0 AR61 DDRB_DQS2_N 26
AW47
DDRB_DQ24 DDR1_DQ_5_1/DDR1_DQ_3_1/DDR2_DQ_3_1/DDR5_DQ_1_1 DDR0_DQSP_5/DDR1_DQSP_1/DDR2_DQSP_1/DDR4_DQSP_1 AU61 DDRB_DQS1_P 26
AV50
DDRB_DQ39 DDR1_DQ_5_0/DDR1_DQ_3_0/DDR2_DQ_3_0/DDR5_DQ_1_0 DDR0_DQSN_5/DDR1_DQSN_1/DDR2_DQSN_1/DDR4_DQSN_1 BB61 DDRB_DQS1_N 26
C49
DDRB_DQ38 DDR0_DQ_6_7/DDR1_DQ_4_7/DDR3_DQ_0_7/DDR6_DQ_0_7 DDR0_DQSP_4/DDR1_DQSP_0/DDR2_DQSP_0/DDR4_DQSP_0 BD61 DDRB_DQS0_P 26
E48
lO

DDRB_DQ37 DDR0_DQ_6_6/DDR1_DQ_4_6/DDR3_DQ_0_6/DDR6_DQ_0_6 DDR0_DQSN_4/DDR1_DQSN_0/DDR2_DQSN_0/DDR4_DQSN_0 DDRB_DQS0_N 26

F49
DDRB_DQ36 B48 DDR0_DQ_6_5/DDR1_DQ_4_5/DDR3_DQ_0_5/DDR6_DQ_0_5 AE60
DDRB_DQ35 B52 DDR0_DQ_6_4/DDR1_DQ_4_4/DDR3_DQ_0_4/DDR6_DQ_0_4 DDR1_MA_5/DDR4_CA_5/DDR4_CA_6/DDR4_CA_0/NC AE55
DDRB_DQ34 F51 DDR0_DQ_6_3/DDR1_DQ_4_3/DDR3_DQ_0_3/DDR6_DQ_0_3 DDR1_MA_7/DDR4_CA_4/DDR4_CA_5/DDR4_CA_1/NC AF57
DDRB_DQ33 E52 DDR0_DQ_6_2/DDR1_DQ_4_2/DDR3_DQ_0_2/DDR6_DQ_0_2 DDR1_MA_6/DDR4_CA_3/DDR4_CA_4/DDR4_CS_1/NC AH60
DDRB_DQ32 DDR0_DQ_6_1/DDR1_DQ_4_1/DDR3_DQ_0_1/DDR6_DQ_0_1 DDR1_MA_8/DDR4_CA_2/DDR4_CA_3/DDR4_CS_0/DDR2_CA_9 AL56 DDRB_0_CA9 26
C51
DDRB_DQ47 DDR0_DQ_6_0/DDR1_DQ_4_0/DDR3_DQ_0_0/DDR6_DQ_0_0 NC/DDR4_CA_1/DDR4_CA_1/DDR4_CA_5/DDR2_CA_1 AL58 DDRB_0_CA1 26
E41
DDRB_DQ46 DDR0_DQ_7_7/DDR1_DQ_5_7/DDR3_DQ_1_7/DDR6_DQ_1_7 NC/DDR4_CA_0/DDR4_CA_0/DDR4_CA_6/DDR2_CA_0 AE47 DDRB_0_CA0 26
C42
DDR0_DQ_7_6/DDR1_DQ_5_6/DDR3_DQ_1_6/DDR6_DQ_1_6 DDR1_BA_1/DDR5_CA_5/DDR5_CA_6/DDR5_CA_0/DDR2_CA_10 AE53 DDRB_0_CA10 26
tia

DDRB_DQ45 F43
DDRB_DQ44 DDR0_DQ_7_5/DDR1_DQ_5_5/DDR3_DQ_1_5/DDR6_DQ_1_5 DDR1_MA_16/DDR5_CA_4/DDR5_CA_5/DDR5_CA_1/DDR2_CA_8 AK46 DDRB_0_CA8 26
B41
DDRB_DQ43 DDR0_DQ_7_4/DDR1_DQ_5_4/DDR3_DQ_1_4/DDR6_DQ_1_4 DDR1_MA_15/DDR5_CA_3/DDR5_CA_4/DDR5_CS_1/DDR2_CA_7 AH53 DDRB_0_CA7 26
B46
DDRB_DQ42 DDR0_DQ_7_3/DDR1_DQ_5_3/DDR3_DQ_1_3/DDR6_DQ_1_3 DDR1_MA_14/DDR5_CA_2/DDR5_CA_3/DDR5_CS_0/DDR2_CA_11 AM47 DDRB_0_CA11 26
F44
DDRB_DQ41 DDR0_DQ_7_2/DDR1_DQ_5_2/DDR3_DQ_1_2/DDR6_DQ_1_2 DDR1_CS_1/DDR5_CA_1/DDR5_CA_1/DDR5_CA_5/DDR2_CA_2 AM53 DDRB_0_CA2 26
E46
DDRB_DQ40 DDR0_DQ_7_1/DDR1_DQ_5_1/DDR3_DQ_1_1/DDR6_DQ_1_1 DDR1_ODT_1/DDR5_CA_0/DDR5_CA_0/DDR5_CA_6/DDR2_CA_3 T55 DDRB_0_CA3 26
C45
DDRB_DQ55 L58 DDR0_DQ_7_0/DDR1_DQ_5_0/DDR3_DQ_1_0/DDR6_DQ_1_0 DDR1_CKE_0/DDR6_CA_5/DDR6_CA_6/DDR6_CA_0/NC T60
DDR1_DQ_6_7/DDR1_DQ_6_7/DDR3_DQ_2_7/DDR7_DQ_0_7 DDR1_CKE_1/DDR6_CA_4/DDR6_CA_5/DDR6_CA_1/NC W60
en

DDRB_DQ54 K57
DDRB_DQ53 DDR1_DQ_6_6/DDR1_DQ_6_6/DDR3_DQ_2_6/DDR7_DQ_0_6 DDR1_BG_0/DDR6_CA_3/DDR6_CA_4/DDR6_CS_1/DDR3_CA_4 U57 DDRB_1_CA4 26
L56
DDRB_DQ52 K60 DDR1_DQ_6_5/DDR1_DQ_6_5/DDR3_DQ_2_5/DDR7_DQ_0_5 DDR1_BG_1/DDR6_CA_2/DDR6_CA_3/DDR6_CS_0/NC AB58
DDRB_DQ51 DDR1_DQ_6_4/DDR1_DQ_6_4/DDR3_DQ_2_4/DDR7_DQ_0_4 DDR1_MA_12/DDR6_CA_1/DDR6_CA_1/DDR6_CA_5/DDR3_CA_7 AC60 DDRB_1_CA7 26
P60
DDRB_DQ50 DDR1_DQ_6_3/DDR1_DQ_6_3/DDR3_DQ_2_3/DDR7_DQ_0_3 DDR1_MA_9/DDR6_CA_0/DDR6_CA_0/DDR6_CA_6/DDR3_CA_11 T53 DDRB_1_CA11 26
N56
DDRB_DQ49 DDR1_DQ_6_2/DDR1_DQ_6_2/DDR3_DQ_2_2/DDR7_DQ_0_2 NC/DDR7_CA_5/DDR7_CA_6/DDR7_CA_0/DDR3_CS_1 T47 DDRB_1_CS1 26
P57
DDRB_DQ48 DDR1_DQ_6_1/DDR1_DQ_6_1/DDR3_DQ_2_1/DDR7_DQ_0_1 NC/DDR7_CA_4/DDR7_CA_5/DDR7_CA_1/DDR3_CS_0 W53 DDRB_1_CS0 26
N58
DDRB_DQ63 DDR1_DQ_6_0/DDR1_DQ_6_0/DDR3_DQ_2_0/DDR7_DQ_0_0 NC/DDR7_CA_3/DDR7_CA_4/DDR7_CS_1/DDR3_CA_0 AA46 DDRB_1_CA0 26
K50
fid

DDRB_DQ62 DDR1_DQ_7_7/DDR1_DQ_7_7/DDR3_DQ_3_7/DDR7_DQ_1_7 NC/DDR7_CA_2/DDR7_CA_3/DDR7_CS_0/DDR3_CA_6 AC47 DDRB_1_CA6 26

F58
DDRB_DQ61 DDR1_DQ_7_6/DDR1_DQ_7_6/DDR3_DQ_3_6/DDR7_DQ_1_6 DDR1_MA_10/DDR7_CA_1/DDR7_CA_1/DDR7_CA_5/DDR3_CA_8 AC53 DDRB_1_CA8 26
F54
DDRB_DQ60 DDR1_DQ_7_5/DDR1_DQ_7_5/DDR3_DQ_3_5/DDR7_DQ_1_5 DDR1_BA_0/DDR7_CA_0/DDR7_CA_0/DDR7_CA_6/DDR3_CA_10 DDRB_1_CA10 26
L48
DDRB_DQ59 H56 DDR1_DQ_7_4/DDR1_DQ_7_4/DDR3_DQ_3_4/DDR7_DQ_1_4 AM57
DDRB_DQ58 DDR1_DQ_7_3/DDR1_DQ_7_3/DDR3_DQ_3_3/DDR7_DQ_1_3 DDR1_MA_3/DDR4_CS_1/DDR4_CS_0/DDR4_CA_3/DDR2_CS_1 AJ56 DDRB_0_CS1 26
K53
B DDRB_DQ57 DDR1_DQ_7_2/DDR1_DQ_7_2/DDR3_DQ_3_2/DDR7_DQ_1_2 DDR1_MA_4/DDR4_CS_0/DDR4_CA_2/DDR4_CA_2/DDR2_CA_12 AK48 DDRB_0_CA12 26 B
P50
DDRB_DQ56 DDR1_DQ_7_1/DDR1_DQ_7_1/DDR3_DQ_3_1/DDR7_DQ_1_1 DDR1_MA_13/DDR5_CS_1/DDR5_CS_0/DDR5_CA_3/DDR2_CA_5 AE50 DDRB_0_CA5 26
P53
on

DDR1_DQ_7_0/DDR1_DQ_7_0/DDR3_DQ_3_0/DDR7_DQ_1_0 DDR1_ODT_0/DDR5_CS_0/DDR5_CA_2/DDR5_CA_2/DDR2_CA_6 AC57 DDRB_0_CA6 26

DDR1_ACT_N/DDR6_CS_1/DDR6_CS_0/DDR6_CA_3/DDR3_CA_9 Y56 DDRB_1_CA9 26
NC/DDR6_CS_0/DDR6_CA_2/DDR6_CA_2/DDR3_CA_2 AA48 DDRB_1_CA2 26
DDR1_PAR/DDR7_CS_1/DDR7_CS_0/DDR7_CA_3/DDR3_CA_3 T50 DDRB_1_CA3 26
DDR1_MA_2/DDR7_CS_0/DDR7_CA_2/DDR7_CA_2/DDR3_CA_1 DDRB_1_CA1 26
AM50
DDR1_CS_0/NC/DDR5_CS_1/DDR5_CA_4/DDR2_CA_4 AC50 DDRB_0_CA4 26
DDR1_MA_0/NC/DDR7_CS_1/DDR7_CA_4/DDR3_CA_5 AM60 DDRB_1_CA5 26
C

DDR1_MA_1/NC/DDR4_CS_1/DDR4_CA_4/DDR2_CS_0 AB56 DDRB_0_CS0 26

DDR1_MA_11/NC/DDR6_CS_1/DDR6_CA_4/DDR3_CA_12 DDRB_1_CA12 26
BG57
DDR1_ALERT BG55
DDR1_VREF_CA0
3 OF 22
FC

INTEL_ADL-P-682_BGA1744
<PART_NUMBER>
@
LC

A A

Security Classification LCFC Highly Confidential Information Title

ORS-ADL_P
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. YX0 ORS
Date: Monday, November 29, 2021 Sheet 9 of 110

5 4 3 2 1
 5 4 3 2 1

+VCCST_CPU +3VALW_PCH

H_PROCHOT_N RC1259 2 1 1K_0402_5% GPPC_H2

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201
GPPC_H1

1
@
D H_PROCHOT_R_N +VCCST_CPU D
CC1201 1 2 0.1u_0201_10V6K
GPPC_H0 GPP_H0: Boot Strap 1

RC1255

RC1249

RC1251
@ @ @ GPP_H1: Boot Strap 2 H_CATERR_N RC2461 1 2 1K_0402_1%
GPP_H2: Boot Strap 3
Boot Strap, Rising edge of RSMRST#

2
These straps has a 20 kohm ± 30% internal pull-down.
GPPC_H_0 They are bit [3:1] of a total of 4-bit encoded pin straps
+VCCST_CPU GPPC_H_1 for boot configuration.
GPPC_H_2 Refer to Boot Strap 0 (on GPP_C5) for the encoding. +VCCST_CPU
THRMTRIP_CPU_N RC1261 1 2 1K_0402_5% Notes: 1. The internal pull-down is disabled after
RSMRST# de-asserts. PROC_PREQ_N RC57 1 @ 2 51_0402_5%
CPU_POPIRCOMP RC1201 1 2 1/20W_49.9_1%_0201 2. This signal is in the primary well.
1/20W_20K_5%_0201

1/20W_20K_5%_0201

1/20W_20K_5%_0201
1

T
PCH_OPIRCOMP
* 0000 = Master Attached Flash Configuration (BIOS / CSME on SPI). eSPI is enabled
RC1202 1 2 1/20W_49.9_1%_0201 +3VALW_PCH
RC1256

RC1250

RC1252
0010 = Master Attached Flash Configuration (BIOS / CSME on SPI). eSPI is disabled
@ @ @ 0100 = BIOS on eSPI Peripheral Channel; CSME on master attached SPI
1000 = Slave Attached Flash Configuration (BIOS / CSME on eSPI attached device).

M
1100 = BIOS on eSPI peripheral Channel; CSME on slave attached SPI.
2

2
GPPC_F_7 RC1254 1 @ 2 1/20W_4.7K_5%_0201
+VCC1P05_OUT GPPC_F_10 RC1257 1 @ 2 1/20W_4.7K_5%_0201

rS
RC2476 1 @ 2 1/20W_1K_1%_0201 GPPC_F_7 RC1253 1 @ 2 1/20W_20K_5%_0201
DBG_PMODE RC1204 1 @ 2 1/20W_1K_1%_0201
GPPC_F_10 RC1258 1 @ 2 1/20W_20K_5%_0201
ITP_PMODE

fo
?

UC1V BMAP_REV = ?

H_CATERR_N AF15 R6
CPU_PECI CATERR# PROC_JTAG_TRST# PROC_TRST_N 23
DG3 U8
79 CPU_PECI H_PROCHOT_R_N PECI PROC_JTAG_TMS PROC_TMS 23
C 19,79,95 H_PROCHOT_N RC1260 1 2 499_0402_1% AK32 AA6 PROC_TDO 23 C
THRMTRIP_CPU_N

CPU_POPIRCOMP
AH32

DV60
PROCHOT#
THERMTRIP#
PROC_JTAG_TDO
PROC_JTAG_TDI
PROC_JTAG_TCK
W8
N6
y PROC_TDI
PROC_TCK
23
23
PCH_OPIRCOMP PROC_POPIRCOMP
nl
DG1 N8
TP_PCH_OPIICCOBS DMI_RCOMP PCH_JTAGX JTAGX 23
TH2988 PAD @ 1 DV11 U6 +VCCST_CPU
TP_PCH_OPIICCCTL TP_3 PCH_JTAG_TMS PCH_TMS 23
TH2989 PAD @ 1 DV10 AA8
TP_2 PCH_JTAG_TDO PCH_TDO 23
W6
DBG_PMODE PCH_JTAG_TDI PCH_TDI 23 CPU_EAR_N
ET14 FB6 RC1262 1 2 1K_0201_5%
DBG_PMODE PCH_JTAG_TCK PCH_TCK 23
R8
lO

PCH_PROC_TRST# PCH_JTAG_RST_N 23
EB56 RC1263 1 @ 2 1K_0201_5%
EB57 GPP_B4/PROC_GP3/ISH_GP5B L6 PROC_PREQ_N 1 TP5 @
RC58 1 @ 2 0_0201_5% CPU_TBT_FORCE_PWR FB23 GPP_B3/PROC_GP2/ISH_GP4B PROC_PREQ# L8 PROC_PRDY_N 1 TP6 @
51 CPU_TBT_FORCE_PWR_R GPP_E3 GPP_E7/PROC_GP1 PROC_PRDY#
TH3048 PAD 1 EY23
@ GPP_E3/PROC_GP0 AF25 CPU_EAR_N
GPPC_H_2 EAR# Stall CPU reset sequence until de-asserted
ET46
GPPC_H_1 EL48 GPP_H2 EN28 GPPC_F_7
 1 (Default) Normal Operation;
GPPC_H_0 EK48 GPP_H1
GPP_H0
GPP_F7
GPP_F9/BOOTMPC
ET28 *No stall.
tia

EF28 GPPC_F_10
32 PXS_PWREN
RC2495 1 @ 2 0_0201_5% PXS_PWREN_CPU DY61 GPP_F10 CPU_EAR_N
DW56 GPP_B15/TIME_SYNC0/ISH_GP7
66 PCH_BEEP GPP_B14/SPKR/TIME_SYNC1/SATA_LED#/ISH_GP6  0 Stall.
79 TOP_SWAP_EN RC2480 1 @ 2 0_0201_5%
22 OF 22
INTEL_ADL-P-682_BGA1744
en

@ <PART_NUMBER>
+3VALW_PCH

S
P
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PCH_BEEP RC1234 1 @ 2 1K_0402_5%

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+3VS
FC

RC60
10K_0402_5%
OPT@
1

PXS_PWREN
LC

RC61
10K_0402_5%
@
2

A NOTE: A
PXS_PWREN pull up with +3VALW_SYS for AMD and support modern standby

Security Classification LCFC Highly Confidential Information Title

ORS-ADL_P
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. YX0 ORS
Date: Monday, November 29, 2021 Sheet 10 of 110
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH

RPC16
CPU_SML0_CLK 1 4
? CPU_SML0_DATA 2 3
? +3VALW_PCH
2.2K_0404_4P2R_5%
UC1E BMAP_REV = ?

D EG56 EL38 PCH_SMBCLK +1.8VALW D

27 PCH_SPI0_CLK EC59 SPI0_CLK GPP_C0/SMBCLK EK38 PCH_SMBDATA RC2492 1 2 1/20W_20K_5%_0201
27 PCH_SPI0_IO3 EC61 SPI0_IO3 GPP_C1/SMBDATA EN38 SMB_ALERT_N
27 PCH_SPI0_IO2 EF59 SPI0_IO2 GPP_C2/SMBALERT# GPP_E6 RC1721 1 @ 2 1/20W_20K_5%_0201
27 PCH_SPI0_SO EF57 SPI0_MISO EE38 CPU_SML0_CLK

T
27 PCH_SPI0_SI EG58 SPI0_MOSI GPP_C3/SML0CLK EF38 CPU_SML0_DATA CPU_SML0_CLK 52 ESPI_ALERT0_N RC1718 2 @ 1 10K_0201_5%
27 PCH_SPI0_CS1_N EF61 SPI0_CS1# GPP_C4/SML0DATA EH38 SML0_ALERT_N CPU_SML0_DATA 52
27 PCH_SPI0_CS0_N EF56 SPI0_CS0# GPP_C5/SML0ALERT# ESPI_CS0_N RC1707 2 @ 1 10K_0201_5%
SPI0_CS2# ET38 SML1CLK
FC28 GPP_C6/SML1CLK ER38 SML1DATA ESPI_CS0_N Internal PU 20K
EF23 GPP_E11/THC0_SPI1_CLK/GSPI0_CLK GPP_C7/SML1DATA EF41 SML1_ALERT_N ESPI_CS0_N RC1723 1 @ 2 1/20W_75K_5%_0201
EE23 GPP_E2/THC0_SPI1_IO3 GPP_B23/SML1ALERT#/PCHHOT#

M
71 PCH_WLAN_OFF_N EL23 GPP_E1/THC0_SPI1_IO2 DT49 ESPI_CLK_R ESPI_RST_N
RC1725 1 2 33_0402_5% RC1728 1 2 1/20W_75K_5%_0201
EN23 GPP_E12/THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO GPP_A9/ESPI_CLK DP52 ESPI_IO3_R ESPI_CLK 79
RC1712 1 2 33_0402_5%
NUM_LED_PCH GPP_E13/THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI GPP_A3/ESPI_IO3/SUSACK# ESPI_IO2_R ESPI_IO3 79 GPP_E6
RC1829 1 @ 2 0_0201_5% FA28 DT54 RC1730 1 2 33_0402_5% RC1702 1 @ 2 1/20W_4.7K_5%_0201
81 NUM_LED PCH_FNLK_R GPP_E10/THC0_SPI1_CS#/GSPI0_CS0# GPP_A2/ESPI_IO2/SUSWARN#/SUSPWRDNACK ESPI_IO1_R ESPI_IO2 79
81 PCH_FNLK RC1831 1 @ 2 0_0201_5% EY25 DT44 RC1714 1 2 33_0402_5%
GPP_E6 EH23 GPP_E17/THC0_SPI1_INT# GPP_A1/ESPI_IO1 DP51 ESPI_IO0_R ESPI_IO1 79
RC1732 1 2 33_0402_5% EMC_NS@
GPP_E6/THC0_SPI1_RST# GPP_A0/ESPI_IO0 DP44 ESPI_CS0_N ESPI_IO0 79 ESPI_CLK 1 2
CC1702 10P_0402_50V8J
GPP_A4/ESPI_CS0# ESPI_CS0_N 79
RC2475 1 @ 2 0_0201_5% EN33 DT46
32 PCH_FB_GC6_EN EN36 GPP_F11/THC1_SPI2_CLK/GSPI1_CLK GPP_A23/ESPI_CS1# DT51 ESPI_RST_N PCH_SPI0_IO2 RC1719 1 @ 2 1K_0402_1%
71 PCH_PCIE_WAKE_N_WLAN EL36 GPP_F15/GSXSRESET#/THC1_SPI2_IO3 GPP_A10/ESPI_RESET# DP47 ESPI_ALERT0_N ESPI_RST_N 79

rS
ET33 GPP_F14/GSXDIN/THC1_SPI2_IO2 GPP_A5/ESPI_ALERT0# DP54 ESPI_ALERT0_N 79
EL31 GPP_F13/GSXSLOAD/THC1_SPI2_IO1/GSPI1_MISIO/I2C1A_SDA GPP_A6/ESPI_ALERT1#
EL33 GPP_F12/GSXDOUT/THC1_SPI2_IO0/GSPI1_MOSI/I2C1A_SCL
ET36 GPP_F16/GSXCLK/THC1_SPI2_CS#/GSP1_CS0#
ER33 GPP_F18/THC1_SPI2_INT#
GPP_F17/THC1_SPI2_RST#
Glitch Free Requirements:
EE26 Cap or pull-down resistor is required
EF26 CL_CLK
EH26 CL_DATA
CL_RST# 100K for 3.3V Signaling Mode
75K for 1.8V Signaling Mode
5 OF 22
INTEL_ADL-P-682_BGA1744 PCH_SPI0_CLK
<PART_NUMBER> RC1704 1 2 100K_0201_5%

fo
@

CC1701 1 2 5P_50V_B_NPO_0402

EMC_NS@

20191226

SMBus RPC4
+3VS
y DIMM1, DIMM2
RPC7 Internal 20K PD @PCH
2

1 4 2N7002KDWH 1 4 +3VALW_PCH VIH=0.7VCC @SPI ROM

G

+3VALW_PCH Vth= min 1V, max 2.5V +3VS

C 2 3 2 3 C
ESD 2KV
nl
PCH_SPI0_CS0_N
GPP_C2 /SMBALERT#
2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5% 1/20W_150K_5%_0201 2 1 RC1710 This signal has a weak internal pull-down.
Signal:CPU_SML1_CLK/DATA PCH_SMBCLK 6 1 SMB_CLK_S3
0 = Disable Intel ME Crypto Transport Layer Security
S

Voltage Level:3.3V SMB_CLK_S3 25,26 2 1 PCH_SPI0_CS1_N

1/20W_150K_5%_0201 RC1706
D

(TLS) cipher suite (no confidentiality). (Default)

5

L2N7002KN3T5G_SOT883-3
G

Vds max=60V QH1A 1 = Enable Intel ME Crypto Transport Layer Security

+3VALW_PCH +3VALW_PCH Vgs max=+/- 20V 2N7002KDWH_SOT363-6 1/20W_4.7K_5%_0201 1 2 RC1715 PCH_SPI0_SI (TLS) cipher suite (with confidentiality). Must be
Vgs(th)=1.0V/2.5V(min/max) pulled up to support Intel AMT with TLS.
Rds(ON)=2.7ohm(max,Vgs=5 V) PCH_SMBDATA 3 4 SMB_DATA_S3 2 1 RC1726 PCH_SPI0_IO2
100K_0201_5%
lO

Id=320mA(TA =25 C )
S

SMB_DATA_S3 25,26
D

Ton Delay=9.9ns GPP_C5 /SML0ALERT#

4
3

100K_0201_5% 2 1 RC1701 PCH_SPI0_IO3

Rise time=5ns This signal has a weak internal pull-down.
RPC8 QH1B
2N7002KDWH_SOT363-6 0 = eSPI Enable (for EC). (Default)
2.2K_0404_4P2R_5% SPI0_MOSI(PCH_SPI_SI ): 1 = eSPI Disable (for EC).
1

Rising edge of RSMRST#

G

External pull-up is required. Recommend 4.7 kohm pull up.

1
2

This strap should sample HIGH. There should NOT be any onboard GPP_B23 /SML1ALERT# /PCHHOT#
device driving it to opposite direction during strap sampling. This strap has a 20 kOhm ± 30% internal pull-down.
SML1CLK 3 CPU_SML1_CLK_M
2
SML1_CLK_TBT 51,60 0 = 38.4 MHz clock (direct from crystal) (default)
S

SPI0_IO2 and SPI0_IO3: 1 = 19.2 MHz clock (derived from 38.4 MHz crystal)
QC2 Rising edge of RSMRST# Notes: 1. The internal pull-down is disabled after RSMRST#
+3VALW_PCH External pull-up is required. 8M de-asserts.
L2N7002KN3T5G_SOT883-3
Recommend 100K if pulled up to 3.3V or 75K if pulled up to 1.8V. 2. When used as PCHHOT# and strap low, a 150K
tia

This strap should sample HIGH. There should NOT be any onboard pull-up is needed to ensure it does not override
device driving it to opposite direction during strap sampling.
1

RC1727 1 2 2.2K_0402_5% SMB_ALERT_N RC1708 1 @ 2 2.2K_0402_5% the internal pull-down strap sampling.
G

RC1705 2 1 1/20W_4.7K_5%_0201 SML0_ALERT_N RC1720 1 2 2.2K_0402_5%

@
SML1_ALERT_N
@ 3. This signal is in the primary well.
RC1711 1 @ 2 1/20W_150K_5%_0201 RC1709 1 2 1/20W_20K_5%_0201 20191213
SML1DATA 3 CPU_SML1_DATA_M
2
SML1_DATA_TBT 51,60 Strap
S

QC4
L2N7002KN3T5G_SOT883-3
en
fid

B B
on
C
FC
LC

A A

Security Classification LCFC Highly Confidential Information Title

ORS-ADL_P
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
YX0 ORS A0

Date: Monday, November 29, 2021 Sheet 11 of 110

5 4 3 2 1
 5 4 3 2 1

D D

+3VS

PCH_UART2_RXD RC606 1 2 1/20W_2.2K_5%_0201

PCH_UART2_TXD RC607 1 2 1/20W_2.2K_5%_0201

T
PCH_UART2_TXD ITE9 1 @ PAD ?
Layer BOT PCH_UART2_RXD ITE10 1 @ PAD ?

M
UC1F BMAP_REV = ?

PCH_UART2_TXD EN48 EY28

PCH_UART2_RXD EN46 GPP_H11/UART0_TXD/M2_SKT2_CFG1 GPP_D14/ISH_UART0_TXD/I2C4B_SCL EV28 PCH_TP_INT_N
CAPS_LED GPP_H10/UART0_RXD/M2_SKT2_CFG0 GPP_D13/ISH_UART0_RXD/I2C4B_SDA EY36 CPU_EDP_SW PCH_TP_INT_N 83
EL41
81 CAPS_LED GPP_H13/I2C7_SCL/UART0_CTS#/M2_SKT2_CFG3/ISH_GP7B/DEVSLP1B GPP_D16/ISH_UART0_CTS#/I2C7B_SCL EW36 CPU_EDP_SW 46
EK41

rS
GPP_H12/I2C7_SDA/UART0_RTS#/M2_SKT2_CFG2/ISH_GP6B/DEVSLP0B GPP_D15/ISH_UART0_RTS#/I2C7B_SDA
EW30 FA34
VGA_ALERT_PCH_N GPP_D18/UART1_TXD/ISH_UART1_TXD GPP_D3/ISH_GP3/BK3/SBK3 EY30 TYPE-C_DP_HPD1 61
EV34
GPP_D17/UART1_RXD/ISH_UART1_RXD GPP_D2/ISH_GP2/BK2/SBK2 EY31 TYPE-C_DP_HPD2 55
GPP_D1/ISH_GP1/BK1/SBK1 EV31 PCH_SMI_N VGA_PWRGD 28,32
EH46 RC1209 1 @ 2 0_0201_5%
GPP_H5/I2C0_SCL GPP_D0/ISH_GP0/BK0/SBK0 EC_SMI_N 79
EF46
GPP_H4/I2C0_SDA DR61 GPPC_RCOMP RC1804 1 2 200_0402_1%
PCH_I2C1_SCL EH43 GPPC_RCOMP
83 PCH_I2C1_SCL PCH_I2C1_SDA GPP_H7/I2C1_SCL
TP EF43

fo
83 PCH_I2C1_SDA GPP_H6/I2C1_SDA
DT57 +3VS RC1217 2 1 10K_0402_5% PCH_SMI_N
DT56 GPP_B6/ISH_I2C0_SCL/I2C2_SCL
GPP_B5/ISH_I2C0_SDA/I2C2_SDA
DR56
DR58 GPP_B8/ISH_I2C1_SCL/I2C3_SCL
C
GPP_B7/ISH_I2C1_SDA/I2C3_SDA C
32 PXS_RST_N
PXS_RST_N EN43
EL43 GPP_H9/I2C4_SCL/CNV_MFUART2_TXD
GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
y
nl
DN60
73 LAN_PWR_ON_N GPP_B17/I2C5_SCL/ISH_I2C2_SCL
NV 建建建建 RC2474 1 @ 2 0_0201_5% DN57
32 PCH_GPU_EVENT_N GPP_B16/I2C5_SDA/ISH_I2C2_SDA
6 OF 22
INTEL_ADL-P-682_BGA1744
lO

@ <PART_NUMBER>

New Add +3VS

tia
2

+1.8VS_AON
RC1161
@ 10K_0201_5% +3VALW_PCH
1
2
G

@
1
en

3 1 VGA_ALERT_PCH_N RC1823
32 VGA_ALERT_N
@ 1/20W_4.7K_5%_0201
S

QC23
2

LBSS139WT1G_SC70-3 +3VS CPU_EDP_SW

RPC14
fid

1 4 PCH_I2C1_SCL
2 3 PCH_I2C1_SDA RC1808
1/20W_4.7K_5%_0201
1/16W_1K_5%_4P2R_0404
2

B B
on

V0.4
C
FC
LC

A A

Security Classification LCFC Highly Confidential Information Title

ORS-ADL_P
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. YX0 ORS
Date: Monday, November 29, 2021 Sheet 12 of 110
5 4 3 2 1
 5 4 3 2 1

?
?

BMAP_REV = ? UC1G

RC1833 1 2 33_0402_5% HDA_BIT_CLK ER56 EY34

66 HDA_BITCLK_AUDIO HDA_SYNC GPP_R0/HDA_BCLK/I2S0_SCLK/DMIC_CLK_B0/HDAPROC_BCLK GPP_D19/I2S_MCLK1_OUT
RC1814 1 2 33_0402_5% EP60
66 HDA_SYNC_AUDIO HDA_SDOUT GPP_R1/HDA_SYNC/I2S0_SFRM/DMIC_CLK_B1 BOARD_ID5
RC1828 1 2 33_0402_5% ER57 EV53
66 HDA_SDOUT_AUDIO HDA_SDIN0 GPP_R2/HDA_SDO/I2S0_TXD/HDAPROC_SDO GPP_S0/SNDW0_CLK/I2S1_SCLK EY53 BOARD_ID4
ER59
66 HDA_SDIN0 GPP_R3/HDA_SDI0/I2S0_RXD/HDAPROC_SDI GPP_S1/SNDW0_DATA/I2S1_SFRM
TH2976 1 HDA_RST_N ER53 FA50 BOARD_ID6
PAD @ ET53 GPP_R4/HDA_RST#/I2S2_SCLK/DMIC_CLK_A0 GPP_S2/SNDW1_CLK/DMIC_CKL_A0/I2S1_TXD FC50 BOARD_ID7
D
EB44 GPP_R5/HDA_SDI1/I2S2_SFRM/DMIC_DATA0 GPP_S3/SNDW1_DATA/DMIC_DATA0/I2S1_RXD D
EB46 GPP_R6/I2S2_TXD/DMIC_CLK_A1 EV50 BOARD_ID1
GPP_R7/I2S2_RXD/DMIC_DATA1 GPP_S4/SNDW2_CLK/DMIC_CLK_B0 EY50 BOARD_ID0
DV51 GPP_S5/SNDW2_DATA/DMIC_CLK_B1
BT_OFF change to GPP_A13 DV47 GPP_A11 EW48 BOARD_ID3
71 PCH_BT_OFF_N GPP_A13 GPP_S6/SNDW3_CLK/DMIC_CLK_A1 EY48 BOARD_ID2
RC1820 1 2 1/20W_200_1%_0201 SNDW_RCOMP FA53 GPP_S7/SNDW3_DATA/DMIC_DATA1
FC53 SNDW_RCOMP_1
SNDW_RCOMP_2
7 OF 22

<PART_NUMBER> INTEL_ADL-P-682_BGA1744
@

T
M
+1.8VALW

rS
2

RC1822
1K_0402_5%

BOARD ID0 BOARD ID1 BOARD ID2 BOARD ID3 BOARD ID4 BOARD ID5
1

HDA_SDOUT
Function GPP_S5 GPP_S4 GPP_S7 GPP_S6 GPP_S1 GPP_S0
RC1821 1 @ 2 0_0201_5%
79 ME_FLASH

SKU Size GPU Type VRAM SIZE

fo
*

need confirm HDA LINK power level with CODEC

Y570_E3_8Gb 0 0 0 0 0 0
C C

Y570-E6_8Gb 0 0
y 0 0 1 0
nl
HDA_SDO This signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash Descriptor.
Y570-E6_16Gb 0 0 0 0 1 1
1 = Disable Flash Descriptor Security (override). This
lO

strap should only be asserted high using external pull-

up in manufacturing/debug environments ONLY. Y570P_E3_8Gb 0 1 0 0 0 0
Y570P-E6_8Gb 0 1 0 0 1 0
Y570P-E6_16Gb 0 1 0 0 1 1
tia

HDA_SYNC CC351 1 2 33P_50V_J_NPO_0201

EMC_NS@
Y570_P0_8Gb 0 0 0 1 1 0
HDA_SDOUT CC352 1 2 2P_25V_C_NPO_0201
en

EMC_NS@
Y570_P1_8Gb 0 0 1 0 0 0
HDA_BIT_CLK CC350 1 2 33P_50V_J_NPO_0201

EMC_NS@
Y570P_P0_8Gb 0 1 0 1 1 0
Follow C970 reserved for EMC/RF
fid

Y570P_P1_8Gb 0 1 1 0 0 0
B +1.8VALW
Y770_E3_8Gb 1 1 0 0 0 0 B
on

Y770_E6_8Gb 1 1 0 0 1 0
1

1
10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

RC1805 RC1816 RC1803 RC1809 RC1801 RC1824 RC2499 RC2501

@ @ @ @ @ @ @ @
Y770_E6_16Gb 1 1 0 0 1 1
C
2

BOARD_ID0
BOARD_ID1
BOARD_ID2 Y770_E8_16Gb 1 1 0 1 0 1
BOARD_ID3
BOARD_ID4
Y570_E5_8Gb 0 0 1 0 1 0
FC

BOARD_ID5
BOARD_ID6
BOARD_ID7

Y570P_E5_8Gb 0 1 1 0 1 0
1

1
10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%
1
10K_0201_5%

RC1818 RC1825 RC1834 RC1802 RC1806 RC1815 RC2500 RC2502

@ @ @ @ @
Y770_E7_8Gb 1 1 1 1 0 0
LC

@
2

2
2

Y770_E7_16Gb 1 1 1 1 0 1
Board ID6 and Board ID7 reserved ,PD
SKU Size Board ID0 Board ID1
Y570 0 0
Y570P 0 1
A Y770 1 1 A

GPU Type Board ID2 Board ID3 Board ID4

E3 0 0 0
E6 0 0 1
E8 0 1 0
P0 0 1 1
P1 1 0 0
E5 1 0 1
E7 1 1 0
Security Classification LCFC Highly Confidential Information Title
VRAM Size Board ID5
8Gb 0 ORS-ADL_P
16Gb 1 Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. YX0 ORS
Date: Monday, November 29, 2021 Sheet 13 of 110
5 4 3 2 1
 5 4 3 2 1

?
?

UC1I BMAP_REV = ?

DY10 EM5 USB20_14_P

DY11 PCIE12_TXP/SATA1_TXP USB2P_10 EM6 USB20_14_N USB20_14_P 71
EA4 PCIE12_TXN/SATA1_TXN USB2N_10 USB20_14_N 71 BT
EA6 PCIE12_RXP/SATA1_RXP EL18 USB20_9_P USB20_9_P RC6611 Y7@ 2 0_0201_5%
PCIE12_RXN/SATA1RXN USB2P_9 EN18 USB20_9_N USB20_9_N USB20_9_MCU_P 76
RC6621 Y7@ 2 0_0201_5%
EB10 USB2N_9 RGB USB20_9_MCU_N 76
EB11 PCIE11_TXP/SATA0_TXP EN1 USB20_8_P RC663 1 @ 2 0_0201_5%
EC5 PCIE11_TXN/SATA0_TXN USB2P_8 EN3 USB20_8_N USB20_8_P 56 1 2 0_0201_5% USB20_9_RGB_P 80
RC664 @
EC6 PCIE11_RXP/SATA0_RXP USB2N_8 USB20_8_N 56 TBT USB_B USB20_9_RGB_N 80
D PCIE11_RXN/SATA0_RXN ER16 USB20_7_P D
PCIE_PTX_DRX7_P ED10 USB2P_7 ET16 USB20_7_N USB20_7_P 53 Pls share pad
73 PCIE_PTX_DRX7_P PCIE_PTX_DRX7_N ED11 PCIE10_TXP/UFS11_TXP USB2N_7 USB20_7_N 53 TBT USB_A
LAN 73
73
PCIE_PTX_DRX7_N
PCIE_PRX_DTX7_P
PCIE_PRX_DTX7_P EC1 PCIE10_TXN/UFS11_TXN EP4 USB20_6_P
USB20_6_P 47
PCIE_PRX_DTX7_N EC3 PCIE10_RXP/UFS11_RXP USB2P_6 EP6 USB20_6_N
Camera

T
73 PCIE_PRX_DTX7_N PCIE10_RXN/UFS11_RXN USB2N_6 USB20_6_N 47
PCIE_PTX_DRX6_P EF10 FA15 USB20_5_P
71 PCIE_PTX_DRX6_P PCIE_PTX_DRX6_N EF11 PCIE9_TXP/UFS10_TXP USB2P_5 FC15 USB20_5_N USB20_5_P 82
71 PCIE_PTX_DRX6_N PCIE_PRX_DTX6_P EF5 PCIE9_TXN/UFS10_TXN USB2N_5 USB20_5_N 82 Anti Ghost
WLAN 71
71
PCIE_PRX_DTX6_P
PCIE_PRX_DTX6_N
PCIE_PRX_DTX6_N EF6 PCIE9_RXP/UFS10_RXP ER5 USB20_4_P
USB20_4_P 62
PCIE9_RXN/UFS10_RXN USB2P_4 ER6 USB20_4_N
EH10 USB2N_4 USB20_4_N 62 Back Type-C

M
EH11 PCIE8_TXP ER18
EF1 PCIE8_TXN USB2P_3 ET18
EF3 PCIE8_RXP USB2N_3
PCIE8_RXN EH16 USB20_2_P
EL10 USB2P_2 EK16 USB20_2_N USB20_2_P 58
EL11 PCIE7_TXP USB2N_2 USB20_2_N 58 Back HUB
EG4 PCIE7_TXN EL16 USB20_1_P
EG6 PCIE7_RXP USB2P_1 EN16 USB20_1_N USB20_1_P 78
PCIE7_RXN USB2N_1 USB20_1_N 78 DB USB

rS
EN10 FC25 USB_OC0_N
EN11 PCIE6_TXP GPP_E9/USB_OC0#/ISH_GP4 DY51 USB_OC3_R_N RC1 1 2 0_0402_5% USB_OC0_N 57,59
@
EJ5 PCIE6_TXN GPP_A16/USB_OC3#/ISH_GP5 USB_OC3_N 78 RC1 Y770 unstuff
EJ6 PCIE6_RXP FA25 GPP_E5 1 @ PAD TH3051
PCIE6_RXN GPP_E5/DEVSLP1 FC22 GPP_E4 1 @ PAD TH3050
ER10 GPP_E4/DEVSLP0
ER11 PCIE5_TXP DY1 MPHY_RCOMPP 1/20W_100_1%_0201 1 2 RC1601
EJ1 PCIE5_TXN MPHY_RCOMPP DY3 MPHY_RCOMPN
EJ3 PCIE5_RXP MPHY_RCOMPN
PCIE5_RXN EF18 USB2_VBUSSENSE
USB30_TX4_P FB10 USB_VBUSSENSE EF16 USB2_ID
61 USB30_TX4_P USB30_TX4_N FA9 PCIE4_TXP/USB32_4_TXP USB_ID FB20 USB2_COMP
BACK Type-C 61 USB30_TX4_N USB30_RX4_P EV16 PCIE4_TXN/USB32_4_TXN USB2_COMP

fo
61 USB30_RX4_P USB30_RX4_N EY16 PCIE4_RXP/USB32_4_RXP DL8
61 USB30_RX4_N PCIE4_RXN/USB32_4_RXN UFS_RESET#
USB30_TX3_P EW11
58 USB30_TX3_P USB30_TX3_N EY11 PCIE3_TXP/USB32_3_TXP
Back HUB 58 USB30_TX3_N USB30_RX3_P EW17 PCIE3_TXN/USB32_3_TXN +3VALW_PCH
58 USB30_RX3_P USB30_RX3_N EY17 PCIE3_RXP/USB32_3_RXP
58 USB30_RX3_N PCIE3_RXN/USB32_3_RXN RPC1
USB30_TX2_N FA12
USB30_TX2_P FC12 PCIE2_TXP/USB32_2_TXP 5 4 USB_OC0_N
DB USB USB30_RX2_N FA18 PCIE2_TXN/USB32_2_TXN 6 3 USB_OC3_R_N
USB30_RX2_P FC18 PCIE2_RXP/USB32_2_RXP 7 2 USB_OC1_N
PCIE2_RXN/USB32_2_RXN 8 1 USB_OC2_N USB_OC1_N 7

C
Left Type-C
55
55
55
55
USB30_TX1_P
USB30_TX1_N
USB30_RX1_P
USB30_RX1_N
USB30_TX1_P
USB30_TX1_N
USB30_RX1_P
USB30_RX1_N
EV12
EY12
EV19
EY19
PCIE1_TXP/USB32_1_TXP
PCIE1_TXN/USB32_1_TXN
PCIE1_RXP/USB32_1_RXP
PCIE1_RXN/USB32_1_RXN
10K_1206_8P4R_5%
y USB_OC2_N 7,51,60

C
USB2_VBUSSENSE RC1604 1
nl
9 OF 22 2 10K_0201_5%
INTEL_ADL-P-682_BGA1744 USB2_ID RC1603 1 2 10K_0201_5%
@ <PART_NUMBER>
0_0402_5% 1 @ 2 RC2445 USB30_TX2_N USB2_COMP RC1602 1 2 1/16W_113_1%_0402
78 USB30_TX2_N_IO 1 2 RC2446 USB30_TX2_P
0_0402_5% @
78 USB30_TX2_P_IO 1 2 RC2447 USB30_RX2_N
78 USB30_RX2_N_IO 0_0402_5% @
0_0402_5% 1 @ 2 RC2448 USB30_RX2_P
78 USB30_RX2_P_IO
lO

RC2453 1 @ 2 0_0402_5% USB30_TX2_N

23 USB30_TX2_N_DBG USB30_TX2_P
RC2454 1 @ 2 0_0402_5%
23 USB30_TX2_P_DBG USB30_RX2_N
23 USB30_RX2_N_DBG RC2455 1 @ 2 0_0402_5%
RC2456 1 @ 2 0_0402_5% USB30_RX2_P
23 USB30_RX2_P_DBG
RC2445-RC2448与RC2453-RC2456 share pad
tia
en
fid

B ? B
?

UC1H BMAP_REV = ?
PCIE4A_CTX_DRX3_P A20 C33 PEG_GPU_RX7_P CC7141 2 0.22U_6.3V_K_X5R_0201 PEG_CTX_C_GRX7_P
63 PCIE4A_CTX_DRX3_P PCIE4A_CTX_DRX3_N C20 PCIEX4_A_TX_P_3 PCIEX8_TX_P_7 D33 PEG_GPU_RX7_N PEG_CTX_C_GRX7_N PEG_CTX_C_GRX7_P 28
CC7091 2 0.22U_6.3V_K_X5R_0201
63 PCIE4A_CTX_DRX3_N PCIE4A_CRX_DTX3_P M22 PCIEX4_A_TX_N_3 PCIEX8_TX_N_7 J33 PEG_GPU_RX6_P PEG_CTX_C_GRX6_P PEG_CTX_C_GRX7_N 28
CC7031 2 0.22U_6.3V_K_X5R_0201
on

63 PCIE4A_CRX_DTX3_P PCIE4A_CRX_DTX3_N M24 PCIEX4_A_RX_P_3 PCIEX8_TX_P_6 G33 PEG_GPU_RX6_N PEG_CTX_C_GRX6_N PEG_CTX_C_GRX6_P 28

CC7081 2 0.22U_6.3V_K_X5R_0201
63 PCIE4A_CRX_DTX3_N PCIEX4_A_RX_N_3 PCIEX8_TX_N_6 C30 PEG_GPU_RX5_P PEG_CTX_C_GRX5_P PEG_CTX_C_GRX6_N 28
CC7101 2 0.22U_6.3V_K_X5R_0201
PCIE4A_CTX_DRX2_P G20 PCIEX8_TX_P_5 D30 PEG_GPU_RX5_N PEG_CTX_C_GRX5_N PEG_CTX_C_GRX5_P 28
CC7111 2 0.22U_6.3V_K_X5R_0201
63 PCIE4A_CTX_DRX2_P PCIE4A_CTX_DRX2_N F20 PCIEX4_A_TX_P_2 PCIEX8_TX_N_5 J30 PEG_GPU_RX4_P PEG_CTX_C_GRX4_P PEG_CTX_C_GRX5_N 28
CC7041 2 0.22U_6.3V_K_X5R_0201
63 PCIE4A_CTX_DRX2_N PCIE4A_CRX_DTX2_P V22 PCIEX4_A_TX_N_2 PCIEX8_TX_P_4 G30 PEG_GPU_RX4_N PEG_CTX_C_GRX4_N PEG_CTX_C_GRX4_P 28
CC7161 2 0.22U_6.3V_K_X5R_0201
63 PCIE4A_CRX_DTX2_P PCIE4A_CRX_DTX2_N U22 PCIEX4_A_RX_P_2 PCIEX8_TX_N_4 C26 PEG_GPU_RX3_P PEG_CTX_C_GRX3_P PEG_CTX_C_GRX4_N 28
CC7121 2 0.22U_6.3V_K_X5R_0201
For MAIN SSD1 63 PCIE4A_CRX_DTX2_N
PCIE4A_CTX_DRX1_P A17
PCIEX4_A_RX_N_2 PCIEX8_TX_P_3
PCIEX8_TX_N_3
D26
J26
PEG_GPU_RX3_N
PEG_GPU_RX2_P
CC7071
CC7061
2
2
0.22U_6.3V_K_X5R_0201
0.22U_6.3V_K_X5R_0201
PEG_CTX_C_GRX3_N
PEG_CTX_C_GRX2_P
PEG_CTX_C_GRX3_P
PEG_CTX_C_GRX3_N
28
28
63 PCIE4A_CTX_DRX1_P PCIE4A_CTX_DRX1_N C17 PCIEX4_A_TX_P_1 PCIEX8_TX_P_2 G26 PEG_GPU_RX2_N PEG_CTX_C_GRX2_N PEG_CTX_C_GRX2_P 28
CC7021 2 0.22U_6.3V_K_X5R_0201
63 PCIE4A_CTX_DRX1_N PCIE4A_CRX_DTX1_P AC22 PCIEX4_A_TX_N_1 PCIEX8_TX_N_2 C23 PEG_GPU_RX1_P PEG_CTX_C_GRX1_P PEG_CTX_C_GRX2_N 28
CC7051 2 0.22U_6.3V_K_X5R_0201
63 PCIE4A_CRX_DTX1_P PCIE4A_CRX_DTX1_N AA22 PCIEX4_A_RX_P_1 PCIEX8_TX_P_1 D23 PEG_GPU_RX1_N PEG_CTX_C_GRX1_N PEG_CTX_C_GRX1_P 28
CC7151 2 0.22U_6.3V_K_X5R_0201
63 PCIE4A_CRX_DTX1_N PCIEX4_A_RX_N_1 PCIEX8_TX_N_1 J23 PEG_GPU_RX0_P PEG_CTX_C_GRX0_P PEG_CTX_C_GRX1_N 28
CC7011 2 0.22U_6.3V_K_X5R_0201
C

PCIE4A_CTX_DRX0_P G17 PCIEX8_TX_P_0 G23 PEG_GPU_RX0_N PEG_CTX_C_GRX0_N PEG_CTX_C_GRX0_P 28

CC7131 2 0.22U_6.3V_K_X5R_0201
63
63
PCIE4A_CTX_DRX0_P
PCIE4A_CTX_DRX0_N
PCIE4A_CTX_DRX0_N
PCIE4A_CRX_DTX0_P
F17
M18
PCIEX4_A_TX_P_0
PCIEX4_A_TX_N_0
PCIEX8_TX_N_0
M39 PEG_CRX_GTX7_P
PEG_CTX_C_GRX0_N 28
For GPU
63 PCIE4A_CRX_DTX0_P PCIE4A_CRX_DTX0_N M19 PCIEX4_A_RX_P_0 PCIEX8_RX_P_7 M37 PEG_CRX_GTX7_N PEG_CRX_GTX7_P 28
63 PCIE4A_CRX_DTX0_N PCIEX4_A_RX_N_0 PCIEX8_RX_N_7 U37 PEG_CRX_GTX6_P PEG_CRX_GTX7_N 28
PCIEX4_A_B_RCOMP_N F6 PCIEX8_RX_P_6 V37 PEG_CRX_GTX6_N PEG_CRX_GTX6_P 28
2 1 1/20W_2.2K_+-1%_0201 PCIEX4_A_RCOMP_P A6 PCIEX4_RCOMP PCIEX8_RX_N_6 AA37 PEG_CRX_GTX5_P PEG_CRX_GTX6_N 28
RC703
C6 PCIEX4_A_RCOMP_P_1 PCIEX8_RX_P_5 AC37 PEG_CRX_GTX5_N PEG_CRX_GTX5_P 28
1 2 1/20W_2.2K_+-1%_0201 PCIEX4_B_RCOMP_P A5 PCIEX4_A_RCOMP_P_2 PCIEX8_RX_N_5 U32 PEG_CRX_GTX4_P PEG_CRX_GTX5_N 28
RC702
D6 PCIEX4_B_RCOMP_P_1 PCIEX8_RX_P_4 V32 PEG_CRX_GTX4_N PEG_CRX_GTX4_P 28
PCIEX4_B_RCOMP_P_2 PCIEX8_RX_N_4 AA32 PEG_CRX_GTX3_P PEG_CRX_GTX4_N 28
FC

PCIE4B_CTX_DRX3_P A14 PCIEX8_RX_P_3 AC32 PEG_CRX_GTX3_N PEG_CRX_GTX3_P 28

63 PCIE4B_CTX_DRX3_P PCIE4B_CTX_DRX3_N C14 PCIEX4_B_TXP_3 PCIEX8_RX_N_3 M29 PEG_CRX_GTX2_P PEG_CRX_GTX3_N 28
63 PCIE4B_CTX_DRX3_N PCIE4B_CRX_DTX3_P V17 PCIEX4_B_TXN_3 PCIEX8_RX_P_2 M27 PEG_CRX_GTX2_N PEG_CRX_GTX2_P 28
63 PCIE4B_CRX_DTX3_P PCIE4B_CRX_DTX3_N U17 PCIEX4_B_RXP_3 PCIEX8_RX_N_2 U27 PEG_CRX_GTX1_P PEG_CRX_GTX2_N 28
63 PCIE4B_CRX_DTX3_N PCIEX4_B_RXN_3 PCIEX8_RX_P_1 V27 PEG_CRX_GTX1_N PEG_CRX_GTX1_P 28
PCIE4B_CTX_DRX2_P G14 PCIEX8_RX_N_1 AA27 PEG_CRX_GTX0_P PEG_CRX_GTX1_N 28
63 PCIE4B_CTX_DRX2_P PCIE4B_CTX_DRX2_N F14 PCIEX4_B_TXP_2 PCIEX8_RX_P_0 AC27 PEG_CRX_GTX0_N PEG_CRX_GTX0_P 28
63 PCIE4B_CTX_DRX2_N PCIE4B_CRX_DTX2_P AC17 PCIEX4_B_TXN_2 PCIEX8_RX_N_0 PEG_CRX_GTX0_N 28
63 PCIE4B_CRX_DTX2_P PCIE4B_CRX_DTX2_N AA17 PCIEX4_B_RXP_2 A8
PCIEX8_RCOMP_P
1 2 1/20W_150_1%_0201
RC701
63 PCIE4B_CRX_DTX2_N PCIEX4_B_RXN_2 PCIEX8_RCOMP_P_1 C8
For SSD2 63 PCIE4B_CTX_DRX1_P
PCIE4B_CTX_DRX1_P
PCIE4B_CTX_DRX1_N
A11
C11 PCIEX4_B_TXP_1
PCIEX8_RCOMP_P_2
PCIEX8_RCOMP
D8 PCIEX8_RCOMP_N

63
63
PCIE4B_CTX_DRX1_N
PCIE4B_CRX_DTX1_P
PCIE4B_CRX_DTX1_P M13 PCIEX4_B_TXN_1 Stone 1021:Need to change 0.1%
PCIE4B_CRX_DTX1_N M14 PCIEX4_B_RXP_1
LC

63 PCIE4B_CRX_DTX1_N PCIEX4_B_RXN_1
PCIE4B_CTX_DRX0_P G11
63 PCIE4B_CTX_DRX0_P PCIE4B_CTX_DRX0_N F11 PCIEX4_B_TXP_0
63 PCIE4B_CTX_DRX0_N PCIE4B_CRX_DTX0_P V12 PCIEX4_B_TXN_0
63 PCIE4B_CRX_DTX0_P PCIE4B_CRX_DTX0_N U12 PCIEX4_B_RXP_0
A 63 PCIE4B_CRX_DTX0_N PCIEX4_B_RXN_0 A
8 OF 22
INTEL_ADL-P-682_BGA1744
@ <PART_NUMBER>

Security Classification LCFC Highly Confidential Information Title

ORS-ADL_P
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
YX0 ORS A0

Date: Monday, November 29, 2021 Sheet 14 of 110

5 4 3 2 1
 5 4 3 2 1

D D
?

T
?

UC1J BMAP_REV = ?

M
AD41 FC46 CNVI_WT_D1_P
CSI_D_DP_1/CSI_C_DP_2 CNV_WT_D1P CNVI_WT_D1_P 71
AB41 FA46 CNVI_WT_D1_N
CSI_D_DN_1/CSI_C_DN_2 CNV_WT_D1N CNVI_WT_D1_N 71
AG41 EV43 CNVI_WT_D0_P
CSI_D_DP_0/CSI_C_DP_3 CNV_WT_D0P CNVI_WT_D0_P 71
AF41 EY43 CNVI_WT_D0_N

rS
CSI_D_DN_0/CSI_C_DN_3 CNV_WT_D0N CNVI_WT_D0_N 71
J41 EV47 CNVI_WT_CLK_P
CSI_D_CLK_P CNV_WT_CLKP CNVI_WT_CLK_P 71
L41 EY47 CNVI_WT_CLK_N
CSI_D_CLK CNV_WT_CLKN CNVI_WT_CLK_N 71
P44 EV40 CNVI_WR_D1_P
CSI_C_DP_1 CNV_WR_D1P CNVI_WR_D1_P 71
M44 EY40 CNVI_WR_D1_N
T41 CSI_C_DN_1 CNV_WR_D1N EW42CNVI_WR_D0_P CNVI_WR_D1_N 71

fo
CSI_C_DP_0 CNV_WR_D0P CNVI_WR_D0_P 71
P41 EY42 CNVI_WR_D0_N
CSI_C_DN_0 CNV_WR_D0N CNVI_WR_D0_N 71
J44 FA43 CNVI_WR_CLK_P
K44 CSI_C_CLK_P CNV_WR_CLKP FC43 CNVI_WR_CLK_N CNVI_WR_CLK_P 71
CSI_C_CLK CNV_WR_CLKN CNVI_WR_CLK_N 71
W41 FC40 CNV_WT_RCOMP 150_0402_1% 1 2
CSI_B_DP_1 CNV_WT_RCOMP
AA41
C38 CSI_B_DN_1 EK33
y RC2103
CNVI_BRI_RSP 71
A38 CSI_B_DP_0 GPP_F1/CNV_BRI_RSP/UART2_RXD EH33 0_0402_5% 1 @ 2 RC2107
nl
C CSI_B_DN_0 GPP_F0/CNV_BRI_DT/UART2_RTS# CNVI_BRI_DT 71 C
G39 ER31 CNVI_RGI_RSP 71
F39 CSI_B_CLK_P GPP_F3/CNV_RGI_RSP/UART2_CTS# EN31 RC2105 1 @ 2 0_0201_5%
CSI_B_CLK GPP_F2/CNV_RGI_DT/UART2_TXD CNVI_RGI_DT 71
C36 EF36 CNVI_MODEM_CLKREQ
lO

A36 CSI_A_DP_1/CSI_B_DP_2 GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ EH36 CNVI_MODEM_CLKREQ 71

G37 CSI_A_DN_1/CSI_B_DN_2 GPP_F6/CNV_PA_BLANKING ET31 CNVI_RF_RESET_N
E37 CSI_A_DP_0/CSI_B_DP_3 GPP_F4/CNV_RF_RESET# CNVI_RF_RESET_N 71
F36 CSI_A_DN_0/CSI_B_DN_3
G36 CSI_A_CLK_P
CSI_A_CLK
tia

1/20W_150_1%_0201 2 1 RC2106 CSI_RCOMP A55

B54 CSI_RCOMP_1
CSI_RCOMP_2
ET41
ER41 GPP_H22/IMGCLKOUT3
GPP_H21/IMGCLKOUT2
en

EN41
FA31 GPP_H20/IMGCLKOUT1
GPP_D4/IMGCLKOUT0/BK4/SBK4
10 OF 22 +1.8VALW
INTEL_ADL-P-682_BGA1744
<PART_NUMBER> CNVI_BRI_DT
RC2104 1 @ 2 20K_0402_5%
fid

@
RC2108 1 @ 2 20K_0402_5% CNVI_BRI_RSP
B B
RC21021 2 1/20W_75K_5%_0201 CNVI_RF_RESET_N
on

RC21011 @ 2 1/20W_75K_5%_0201 CNVI_MODEM_CLKREQ

C
FC
LC

A A

Title
ORS-ADL_P

Size Document Number Rev

B YX0 ORS A0

Date: Monday, November 29, 2021 Sheet 15 of 110

5 4 3 2 1
 5 4 3 2 1

D D

?
?

UC1K BMAP_REV = ?

DP1 DY46
DP3 CLKOUT_PCIE_P6 GPP_A12/SATAXPCIE1/SATAGP1 EV22 GPP_E0 1 @ PAD TH3045
CLKOUT_PCIE_N6 GPP_E0/SATAXPCIE0/SATAGP0

T
EY22 0201 For Intel Debug Request
DU5 GPP_E16 EB54
DU6 CLKOUT_PCIE_P5 GPP_A8 EF31
CLKOUT_PCIE_N5 GPP_F19/SRCCLKREQ6# ET43 GPU_CLKREQ_R_5_N
RC2506 1 @ 2 0_0201_5%
CLK_PCIE_GPU_P DP5 GPP_H23/SRCCLKREQ5# ER48 GPU_CLKREQ_R_N
RC2507 1 2 0_0201_5% GPU_CLKREQ_N

M
28 CLK_PCIE_GPU_P CLKOUT_PCIE_P4 GPP_H19/SRCCLKREQ4# GPU_CLKREQ_N 28
CLK_PCIE_GPU_N DP6 FC34 SSD_CLKREQ0_N
28 CLK_PCIE_GPU_N CLKOUT_PCIE_N4/UFS_REF_CLK GPP_D8/SRCCLKREQ3# WLAN_CLKREQ_N SSD_CLKREQ0_N 63
FC31 WLAN_CLKREQ_N 71
CLK_PCIE_SSD2_P DN10 GPP_D7/SRCCLKREQ2# FB36 LAN_CLKREQ_N
63 CLK_PCIE_SSD2_P CLK_PCIE_SSD2_N DN11 CLKOUT_PCIE_P3 GPP_D6/SRCCLKREQ1# SSD_CLKREQ_N LAN_CLKREQ_N 73
FB29
63 CLK_PCIE_SSD2_N CLKOUT_PCIE_N3 GPP_D5/SRCCLKREQ0# SSD_CLKREQ_N 63

rS
CLK_PCIE_WLAN_P DR4 EV6 XTAL_PCH_38P4M_OUT
71 CLK_PCIE_WLAN_P CLK_PCIE_WLAN_N CLKOUT_PCIE_P2 XTAL_OUT XTAL_PCH_38P4M_IN
DR6 EV8
71 CLK_PCIE_WLAN_N CLKOUT_PCIE_N2 XTAL_IN
CLK_PCIE_LAN_P DU1 EJ61 RC506 1 2 33_0402_5%
73 CLK_PCIE_LAN_P CLK_PCIE_LAN_N CLKOUT_PCIE_P1 GPD8/SUSCLK SUSCLK 63,71
DU3
73 CLK_PCIE_LAN_N CLKOUT_PCIE_N1 PCH_RTCX2
EV58
CLK_PCIE_SSD1_P DT10 RTCX2 EV56 PCH_RTCX1
63 CLK_PCIE_SSD1_P CLK_PCIE_SSD1_N CLKOUT_PCIE_P0 RTCX1
DT11
63 CLK_PCIE_SSD1_N CLKOUT_PCIE_N0 PCH_RTCRST_N
FA55

fo
RC1909 1 2 1/20W_60.4_1%_0201 CLK_BIASREF DJ3 RTCRST# FB56 PCH_SRTCRST_N
XCLK_BIASREF SRTCRST#
EB52
GPP_A7 EW23 SRCCLK_OEB8_NC 1 @ PAD TH2999
GPP_E15
11 OF 22
C C
INTEL_ADL-P-682_BGA1744
<PART_NUMBER>
@
y
nl
lO
tia

+3VS

PCH_RTCX1 All processor based platforms are required to provide a 38.4MHz input to
WLAN_CLKREQ_N
RC2498 1 2 10K_0201_5% the PCH to enable the PCH to generate all of its internal reference clocks
en

RPC15 RC1902 1 2 10M_0402_5% PCH_RTCX2_R RC2503 1 2 0_0402_5% PCH_RTCX2 and all of the single-ended and differential platform clock outputs
1 8 SSD_CLKREQ_N
2 7 SSD_CLKREQ0_N
3 6 LAN_CLKREQ_N YC1
4 5 GPU_CLKREQ_N 1 2

10K_0804_8P4R_5% 32.768KHZ_9PF_9H03200062 XTAL_PCH_38P4M_IN RC1903 1 @ 2 0_0402_5% XTAL_PCH_38P4M_IN_R

fid

1 1
RC1907 1 @ 2 10K_0201_5% GPU_CLKREQ_N CC1901 CC1902
12P_0402_50V8-J 12P_0402_50V8-J EXC24CH500U_4P
RC2462 1 @ 2 1/20W_1K_1%_0201 SUSCLK 2 2 4 3
4 3
B B
1 2
on

1 2
LC5 EMC_NS@

XTAL_PCH_38P4M_OUT RC1901 1 @ 2 0_0402_5% XTAL_PCH_38P4M_OUT_R

C

VCCRTC

XTAL_PCH_38P4M_IN_R RC19081 2 200K_0402_1% XTAL_PCH_38P4M_OUT_R

RC1906 1 2 20K_0402_5% PCH_SRTCRST_N

RC1910 1 2 20K_0402_5% PCH_RTCRST_N YC2

FC

PCH_RTCRST_N 79
4 3
NC1 OSC2
EMC_NS@ 1 2
PCH_SRTCRST_N CC1907 1 2 1000P_50V_K_X7R_0201 OSC1 NC2
1 1
CC1903 1 2 1U_0402_6.3V6K CC1905 CC1906
38.4MHZ_10PF_7R38400001
PCH_RTCRST_N CC1904 1 2 1U_0402_6.3V6K 10P_0402_50V8J 10P_0402_50V8J
LC

2 2
@
JCMOS1 1 2 SHORT PADS

A A

Security Classification LCFC Highly Confidential Information Title

ORS-ADL_P
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. YX0 ORS
Date: Monday, November 29, 2021 Sheet 16 of 110
5 4 3 2 1
 5 4 3 2 1

?
?

UC1L BMAP_REV = ?

EN53 EM61 PM_PWRBTN_R_N 0_0201_5% 2 @ 1 RC1267

79 SLP_SUS_N SLP_SUS# GPD3/PWRBTN# CPU_BATLOW_N PBTN_OUT_N 79
EM56
PM_SLP_S5_N EG60 GPD0/BATLOW# EJ59 PCH_AC_PRESENT_R 0_0201_5% 2 @ 1 RC1228
47 PM_SLP_S5_N PM_SLP_S4_R_N GPD10/SLP_S5# GPD1/ACPRESENT AC_PRESENT 79
RC1266 1 @ 2 0_0201_5% EP56
25,26,79,84 PM_SLP_S4_N PM_SLP_S3_R_N GPD5/SLP_S4# PCH_PMC_ALERT_PD_N_R +VCCST_CPU
D RC1237 1 @ 2 0_0201_5% EM59 EA56 0_0201_5% 2 @ 1 RC2496 D
79,84 PM_SLP_S3_N SLP_A_N EM57 GPD4/SLP_S3# GPP_B11/PMCALERT# ER46 CPU_C10_GATE_N PCH_PMC_ALERT_PD_N 51,60
EJ57 GPD6/SLP_A# GPP_H18/PROC_C10_GATE# ET48 CPU_TBT_PERST_N RC227 1 2 1/20W_20K_5%_0201
71 PM_SLP_WLAN_N GPD9/SLP_WLAN# GPP_H3/SX_EXIT_HOLDOFF# RC1265 2 1 1K_0201_5% EC_VCCST_PWRGD
DW59 ET51 WAKE_N
79 PM_SLP_S0_N GPD7(BB_TBT_PERST#):

T
GPP_B12/SLP_S0# WAKE# PCIE_WAKE_N 73,79
@ 1 PAD SLP_LAN_N EK53 Reserved
TH2986 SLP_LAN# EP58 PCH_LAN_WAKE_N
EC_RSMRST_N GPD2/LAN_WAKE# Rising edge of DSW_PWROK +3VALW_PCH
EH53 EJ56
EK26 RSMRST# GPD11/LANPHYPC This signal has a 20K+-30% internal pull-down.
23 SYS_RESET_N PLT_RST_N DW57 SYS_RESET# EK60 CPU_TBT_PERST_N
This strap should sample LOW. There should NOT be any on-board device
GPP_B13/PLTRST# GPD7 CPU_TBT_PERST_N 52 driving it to opposite direction during strap sampling PCH_PMC_ALERT_PD_N_R
RC1233 2 1 10K_0201_5%
RC1225 1 2 0_0201_5% PCH_DPWROK_R EE48 FA22 PM_SLP_DRAM_N Notes:

M
17,79 PCH_DPWROK @
RC1243 1 @ 2 0_0201_5% SYS_PWROK_R EK23 DSW_PWROK GPP_E8 PM_SLP_DRAM_N 79 1. The internal pull-down is disabled after DSW_PWROK is high. RC1208 1 2 100K_0201_5% SLP_SUS_N
79 EC_SYS_PWROK PCH_PWROK_R SYS_PWROK VCCST_PWRGD 2. This signal is in the DSW well
EH51 DJ8 RC1264 1 2 62_0402_1%
79 PCH_PWROK PCH_PWROK VCCST_PWRGD VCCST_OVERRIDE_R RC1248 1 EC_VCCST_PWRGD 79 PM_SLP_S4_R_N
DK4 @ 2 0_0201_5% RC1205 1 2 100K_0201_5%
RTC_INTRUDER_N DY44 VCCST_OVERRIDE VCCST_OVERRIDE 18,84
SPI_VCC_SEL EL53 INTRUDER# EH28 RC1239 1 2 100K_0201_5% PM_SLP_S3_R_N
SPIVCCIOSEL GPP_F20/RSVD EH31
BG11 GPP_F21/RSVD RC1214 1 @ 2 100K_0201_5% PM_SLP_WLAN_N
Delete PROCPWRGD
RC1241 1 2 10K_0201_5% PCH_AC_PRESENT_R

rS
12 OF 22 @
RC1206 2 @ 10_0201_5% PCH_DPWROK_R
17,79 EC_RSMRST_N INTEL_ADL-P-682_BGA1744 PM_SLP_DRAM_N
RC1268 1 2 100K_0201_5%
@ <PART_NUMBER>
RC2444 1 2 100K_0201_5% SYS_PWROK_R

RC231 1 @ 2 100K_0201_5% PM_SLP_S5_N

RC2465 1 @ 2 100K_0201_5% SLP_A_N

RC1247 1 2 10K_0201_5% PCH_PWROK_R

RC1232 1 2 100K_0201_5%

fo
@
CC1203 1 2 0.1u_0201_10V6K PCH_DPWROK

RC2489 1 @ 2 100K_0201_5% CPU_C10_GATE_N

+VCCPDSW_3P3

+VCCPRTC_3P3

follow Y550 pull high, PDG/EDS Pull Up

y RC1211
RC1210
RC1221
RC2443
1
1
1
1 @
2 10K_0201_5%
2 100K_0201_5%
2 10K_0201_5%
2 100K_0201_5%
PCH_LAN_WAKE_N
PCH_AC_PRESENT_R
PM_PWRBTN_R_N
PCH_DPWROK
1

C CRB SPI select strap RC2515 1 @ 2 100K_0201_5% CPU_BATLOW_N C

WAKE_N
nl
RC1226 RC2479 2 1 1K_0201_5%
1/20W_1M_5%_0201
Follow Check list and C970 change RC2479 to 1K
2

RTC_INTRUDER_N
1U_6.3V_M_X5R_0201

lO

1
CC1205

RC1238
@ 1/20W_1M_5%_0201
2
2

tia

Emergency Power Loss Early De-assertion of DSW_PWROK control circuit

en

DC1201
RC1244 1 @ 2 0_0201_5% ALW_PWRGD_R 1 2 EC_RSMRST_N
SPI select strap
91 ALW_PWRGD EC_RSMRST_N 17,79 +VCCPDSW_3P3
low: 3.3V
RB751V-40_SOD323-2
DC1202
high: 1.8V
1

EC_RSMRST_N RC1231 2 1 100K_0201_5% 1 2

PCH_DPWROK 17,79
RC1207
CC1204 1 2 0.1U_25V_K_X5R_0201 RB751V-40_SOD323-2 @ 1/20W_4.7K_5%_0201
EMC_NS@
2

SPI_VCC_SEL
fid

B RC1220 B

PLT_RST_N 1/20W_4.7K_5%_0201
32,52,63,71,73,76,79 PLT_RST_N
1

1
CC1202 RC1230
EMC_NS@
220P_0201_25V7-K
on

2 100K_0201_5%
2

1000P 25V K X7R 0201 1 2 CC20 EMC_NS@ EC_RSMRST_N

1000P 25V K X7R 0201 1 2 CC21 EMC_NS@ PCH_DPWROK_R

1
0.1U_6.3V_K_X5R_0201 2 CC16 EMC_NS@ PLT_RST_N

1
0.1U_6.3V_K_X5R_0201 2 CC17 EMC_NS@ PCH_PWROK_R

1
0.1U_6.3V_K_X5R_0201 2 CC18 EMC_NS@ SYS_PWROK_R
C

Follow C970 reserved for EMC/RF

FC
LC

A A

Security Classification LCFC Highly Confidential Information Title

ORS-ADL_P
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
YX0 ORS A0

Date: Monday, November 29, 2021 Sheet 17 of 110

5 4 3 2 1
 5 4 3 2 1

+VCC1P8A_LDO +VCC1P8A_CPU

RC2424 1 @ 2 0_0402_5%

0.1U_6.3V_K_X5R_0201
1 +1.8VALW

CC7278
D D
@
EMC Suggested reserved LC6 1 @ 2 1/10W_0_5%_0603
2

T
+VCCCORE
+VCCCORE
? EMC Suggested reserved

22UC_6.3VC_MC_X5RC_0603
?

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1 1 1 1

CC1302

CC7276

CC7277
UC1M BMAP_REV = ?

M
CC1301 @ @
BA44 CF8 10U 6.3V M X5R 0402
BB43 VCCCORE_1 VCCCORE_51 CF9 2 2 2 2
BB45 VCCCORE_2 VCCCORE_52 CG14
BC44 VCCCORE_3 VCCCORE_53 CG4 CC1301 close to Pin AM41
BD43 VCCCORE_4 VCCCORE_54 CH1
BD45 VCCCORE_5 VCCCORE_55 CH3
BE44 VCCCORE_6 VCCCORE_56 CK11
BH43 VCCCORE_7 VCCCORE_57 CK12
BK43 VCCCORE_8 VCCCORE_58 CK4

rS
BK44 VCCCORE_9 VCCCORE_59 CK6
BL45 VCCCORE_10 VCCCORE_60 CK8
BM44 VCCCORE_11 VCCCORE_61 CK9
BN11 VCCCORE_12 VCCCORE_62 CL1
BN12 VCCCORE_13 VCCCORE_63 CL14
BN45 VCCCORE_14 VCCCORE_64 CL3
BP14 VCCCORE_15 VCCCORE_65 CM11 +VCCST_CPU
BR11 VCCCORE_16 VCCCORE_66 CM12
BR12 VCCCORE_17 VCCCORE_67 CM4
BT14 VCCCORE_18 VCCCORE_68 CM6
BT44 VCCCORE_19 VCCCORE_69 CM8
BU11 VCCCORE_20 VCCCORE_70 CM9 Change to 0402 1
2

BU12 VCCCORE_21 VCCCORE_71 CN1

fo
BU43 VCCCORE_22 VCCCORE_72 CN14 CC1303 @
BU45 VCCCORE_23 VCCCORE_73 CN3 0.1u_0201_10V6K RC1302 @ RC1303 RC1304
BV14 VCCCORE_24 VCCCORE_74 CP1 2 100_0402_1% 100_0402_1% 56.2_0402_1%
BV44 VCCCORE_25 VCCCORE_75 CP11
1

BW12 VCCCORE_26 VCCCORE_76 CP12

BW43 VCCCORE_27 VCCCORE_77 CP3
BW45 VCCCORE_28 VCCCORE_78 CP4
BY1 VCCCORE_29 VCCCORE_79 CP6 95 SVID_DATA
BY44 VCCCORE_30 VCCCORE_80 CP8 95 SVID_CLK
CA1 VCCCORE_31 VCCCORE_81 CP9 95 SVID_ALERT_N
CA3 VCCCORE_32 VCCCORE_82 CR4
CB12 VCCCORE_33 VCCCORE_83

C
CC14
CC3
CD11
CD12
CD6
VCCCORE_34
VCCCORE_35
VCCCORE_36
VCCCORE_37
VCCCORE_38
VCC_SENSE
VSS_SENSE

VIDSOUT
CT3
CT1

R9
U9
VCCCORE_SENSE
VSSCORE_SENSE

SVID_DATA
SVID_CLK
y C
VCCCORE_39 VIDSCK SVID_ALERT_N
nl
CD8 W9
CD9 VCCCORE_40 VIDALERT#
CE1 VCCCORE_41 AU14
VCCCORE_42 VCC1P05_PROC_OUT_3 +VCC1P05_OUT
CE14
CE3 VCCCORE_43 DJ6 VCCSTPWRGOODTCSS_R
RC1308 1 @ 2 0_0201_5%
CE4 VCCCORE_44 VCCST_PWRGD_SX VCCST_OVERRIDE 17,84
CF1 VCCCORE_45
CF11 VCCCORE_46
CF12 VCCCORE_47
lO

CF3 VCCCORE_48
CF6 VCCCORE_49 CRB place to CPU
VCCCORE_50
13 OF 22 +VCCCORE

INTEL_ADL-P-682_BGA1744 VCCIN_SENSE
1

@ <PART_NUMBER> RC1307
100_0402_1%
2

95 VCCCORE_SENSE
tia

95 VSSCORE_SENSE
1

RC1301
100_0402_1%
2
en

+VDD2_CPU ?
? +VCCGT

UC1O BMAP_REV = ?

AD61 CP44
AG61 VDD2_1 VCCGT_1 CR45
AN61 VDD2_2 VCCGT_2 CT44
AP41 VDD2_3 VCCGT_3 CU43
AP44 VDD2_4 VCCGT_4 CU45
AR43 VDD2_5 VCCGT_5 CV4 CRB place to CPU
AR45 VDD2_6 VCCGT_6 CV44
fid

AT44 VDD2_7 VCCGT_7 CW1 +VCCGT

AU43
AU45
VDD2_8
VDD2_9
VCCGT_8
VCCGT_9
CW11
CW12
VCCGT_SENSE
1

B AV44 VDD2_10 VCCGT_10 CW3 RC1305 B

AY61 VDD2_11 VCCGT_11 CW6 100_0402_1%
BH61 VDD2_12 VCCGT_12 CW8
BR61 VDD2_13 VCCGT_13 CW9
CA61 VDD2_14 VCCGT_14 CY14
2

CC44 VDD2_15 VCCGT_15 CY4

CD43 VDD2_16 VCCGT_16 CY44 95 VCCGT_SENSE
CD61 VDD2_17 VCCGT_17 DA1
on

CE44 VDD2_18 VCCGT_18 DA3 95 VSSGT_SENSE

1

CF43 VDD2_19 VCCGT_19 DA43

CF45 VDD2_20 VCCGT_20 DB45
CG44 VDD2_21 VCCGT_21 DC1 RC1306
CH45 VDD2_22 VCCGT_22 DC11 100_0402_1%
CK61 VDD2_23 VCCGT_23 DC12
2

CN61 VDD2_24 VCCGT_24 DC3

CW61 VDD2_25 VCCGT_25 DC4
DF61 VDD2_26 VCCGT_26 DC44
+VCC1P05_OUT J61 VDD2_27 VCCGT_27 DC6
R61 VDD2_28 VCCGT_28 DC8
V61 VDD2_29 VCCGT_29 DC9
C

VDD2_30 VCCGT_30 DD1

AR14 VCCGT_31 DD14
AT12 VCC1P05_PROC_OUT_1 VCCGT_32 DD3
VCC1P05_PROC_OUT_2 VCCGT_33 DD43
CM44 VCCGT_34 DD45
+VCC1P8A_CPU EA14 RSVD_TP_32 VCCGT_35 DE11
RSVD_TP_48 VCCGT_36 DE12
E61 VCCGT_37 DE4
G61 VCC1P8_PROC_8 VCCGT_38 DE6
H59 VCC1P8_PROC_9 VCCGT_39 DE8
AH44 VCC1P8_PROC_10 VCCGT_40 DE9
FC

AJ45 VCC1P8_PROC_1 VCCGT_41 DF1

AK44 VCC1P8_PROC_2 VCCGT_42 DF14 +VCCCORE +VCCCORE
AL45 VCC1P8_PROC_3 VCCGT_43 DF3 Follow C970 reserved for EMC/RF
AM41 VCC1P8_PROC_4 VCCGT_44 DG4
AM44 VCC1P8_PROC_5 VCCGT_45
AN43 VCC1P8_PROC_6
VCC1P8_PROC_7
0.1U_6.3V_K_X5R_0201

VCCGT_SENSE 1 1 1 1 1 1 1
CC22
100P_0402_50V8J

CC23
12P_50V_F_COG_0402

CC24

CC25
12P_50V_F_COG_0402

CC26
12P_50V_F_COG_0402

CC27
12P_50V_F_COG_0402

CC28
12P_50V_F_COG_0402

CV1
VSSGT_SENSE VCCGT_SENSE
CV3
VSSGT_SENSE
15 OF 22 2 2 2 2 2 2 2
RF_NS@

RF_NS@

RF_NS@

RF_NS@

RF_NS@

RF_NS@

RF_NS@

INTEL_ADL-P-682_BGA1744
<PART_NUMBER>
@
LC

A A
Place as close as possible to the
package (less than 5mm). Place as close as possible to the
package (less than 5mm).

Security Classification LCFC Highly Confidential Information Title

ORS-ADL_P
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
YX0 ORS A0

Date: Monday, November 29, 2021 Sheet 18 of 110

5 4 3 2 1
 5 4 3 2 1

+1.8VALW +VCCA_CLKLDO_1P8

+VCCIN_AUX 0.165A
RC1418 1 @ 2 0_5%_0603

0_0402_5%
1
? +VCCPRIM_1P8 1 2 LC1401

RC1401
UC1N BMAP_REV = ? @
0.68UH_SDTT25201B-R68MS_3.3A_20%
AL20 DW20

2
AL32 VCCIN_AUX_1 VCCPRIM_1P8_1 DW22 VCCA_CLKLDO_R
VCCIN_AUX_2 VCCPRIM_1P8_2 @

47U_6.3V_M_X5R_0805_H1.25

1U_6.3V_M_X5R_0201
AN20 DW27 1 1
VCCIN_AUX_3 VCCPRIM_1P8_3

CC1407

CC1404
AN22 DW30 @
AN30 VCCIN_AUX_4 VCCPRIM_1P8_4 DY21
AN32 VCCIN_AUX_5 VCCPRIM_1P8_5 DY23
AN37 VCCIN_AUX_6 VCCPRIM_1P8_6 DY26 2 2
AP17 VCCIN_AUX_7 VCCPRIM_1P8_7 DY28
AP27 VCCIN_AUX_8 VCCPRIM_1P8_8 DY31
D AP30 VCCIN_AUX_9 VCCPRIM_1P8_9 EB18 D
AP32 VCCIN_AUX_10 VCCPRIM_1P8_12 EB21
AP37 VCCIN_AUX_11 VCCPRIM_1P8_13 EB23
B3 VCCIN_AUX_12 VCCPRIM_1P8_14 EB28
VCCIN_AUX_13 VCCPRIM_1P8_15 PDG: VCCA_CLKLDO_1P8
D3 EC14

T
E1 VCCIN_AUX_14 VCCPRIM_1P8_16 EC16
F1 VCCIN_AUX_33 VCCPRIM_1P8_17 EC23 Inductor by default is a placeholder. If stuffed, the
VCCIN_AUX_36 VCCPRIM_1P8_18
680nF inductor needs to meet following requirement:
F3 EC26 (Placeholder) 1 Rated at least 150mA; DCR = 0.036Ohm +/- 20%
G3 VCCIN_AUX_37 VCCPRIM_1P8_19 EE14
H4 VCCIN_AUX_38 VCCPRIM_1P8_20 EE28
J1 VCCIN_AUX_39 VCCPRIM_1P8_21 EG14 Option 1: stuff with 0 ohm if the inductor is not stuffed.
VCCIN_AUX_40 VCCPRIM_1P8_22 0 ohm_0603 1 Option 2: stuff 100 mohm if the inductor stuffed
J3 FB33

M
VCCIN_AUX_41 VCCPRIM_1P8_23 100 mohm_0603
L1
L3 VCCIN_AUX_42 DV41
VCCIN_AUX_43 VCCPRIM_3P3_1 +VCCPRIM_3P3
N3 DW40 47u_0603 1 Place the cap near to package pin DR15 and DR12
VCCIN_AUX_44 VCCPRIM_3P3_2 EB33 right after signal breakout

DH45 VCCPRIM_3P3_3 EC31

DJ41 VCCIN_AUX_15 VCCPRIM_3P3_5 EC33
DJ44 VCCIN_AUX_16 VCCPRIM_3P3_6 EE31
DK40 VCCIN_AUX_17 VCCPRIM_3P3_7
DK43 VCCIN_AUX_18 FB45 +3VALW_PCH

rS
+VCCPRIM_3P3
DK45 VCCIN_AUX_19 RSVD_24 Need stuff
DL44 VCCIN_AUX_20 FB52 @
VCCIN_AUX_21 VCCLDOSTD_0P85 +VCCLDOSTD_OUT_0P85 0.202A
DM1 JH4 1 2 JUMP_43X39
VCCIN_AUX_22 1 2

10U 6.3V M X5R 0402

DM14 EJ14

1M_0402_5%
1
VCCIN_AUX_23 VCCA_CLKLDO_1P8_1

0.01UF_25V_K_X7R_0402
DM43 EM14 1 1
VCCIN_AUX_24 VCCA_CLKLDO_1P8_2 +VCCA_CLKLDO_1P8

RC1417

CC1405
DP41
VCCIN_AUX_25

CC1409
DP42 FB39 @ @ @
VCCIN_AUX_26 VCCDPHY_1P24 +VCCDPHY_1P24
DR14
@ DR40 VCCIN_AUX_27 BN43 2 2

2
VNN_TP1 CC1408 1 2 10U 6.3V M X5R 0402 DT41 VCCIN_AUX_28 RSVD_TP_27 AY11
VNN_TP2 DU14 VCCIN_AUX_29 RSVD_TP_17 BP44
1P05_TP1 CC30 1 2 22UC_6.3VC_MC_X5RC_0603 DU40 VCCIN_AUX_30 RSVD_TP_28 BL12
1P05_TP2 DV2 VCCIN_AUX_31 RSVD_TP_26 CN43

fo
CC31 1 2 22UC_6.3VC_MC_X5RC_0603 ED2 VCCIN_AUX_32 RSVD_TP_33 BJ11
EL2 VCCIN_AUX_34 RSVD_TP_23
P1 VCCIN_AUX_35 EB36
+VCCIN_AUX_FIL VCCIN_AUX_FLTR VCCPRIM1P05_OUT_PCH_1 +VCC1P05_OUT_PCH +3VALW_PCH +VCCPRIM_1P8 +VCCPGPPR
EC36
VCCIN_AUX_VSSSEN
AH30 VCCPRIM1P05_OUT_PCH_3 EE41
2 2 2 2
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

VCCIN_AUX_VCCSEN VSSINAUX_SENSE VCCDSW_1P05 VCCMIPI_TP VCCDSW_1P05

AF30 V1 1 @ PAD TH3044
VCCINAUX_SENSE VCC_MIPILP
CC11

CC12

CC13

CC14

EB38
VNN_TP1 VCCPRIM1P05_OUT_PCH_2 +VCC1P05_OUT_PCH
EF21 EE36
1 1 1 1 VNN_TP2 EH21 VCC_VNNEXT_1P05_1 VCCPRIM1P05_OUT_PCH_4 RU3529 1 @ 2 0_0402_5%
@ @ @ @ VCC_VNNEXT_1P05_2 EC38
1P05_TP1 VCCRTC V3P3A_DSW_R +VCCPRTC_3P3
EE18 EB42 RC1416 1 @ 2 0_0402_5% RC1404 1 @ 2 0_0402_5%
1P05_TP2 VCC_V1P05EXT_1P05_1 VCCPDSW_3P3 +VCCPDSW_3P3
EE21 EE33
+VCCPGPPR

C
GPPC_B2_VRALERT_N DT59
EK31
EL28
VCC_V1P05EXT_1P05_2

GPP_B2/VRALERT#
GPP_F22/VNN_CTRL
GPP_F23/V1P05_CTRL
VCCPGPPR

VCCPRIM_3P3_4
VCCPRIM_1P8_10
VCCPRIM_1P8_11
EB41
DY41
DY42
y
+VCCPRIM_3P3

+VCCPRIM_1P8
+3VALW_SYS +3VALW_PCH
C
VCCIN_AUX_PCH_VID0
nl
EA60 EU1
84,99 VCCIN_AUX_PCH_VID0 VCCIN_AUX_PCH_VID1 GPP_B0/CORE_VID0 VCC1P05_PROC_1 +VCCST_CPU
EA58 EU4
84,99 VCCIN_AUX_PCH_VID1 GPP_B1/CORE_VID1 VCC1P05_PROC_2 RC2442 2 @ 1 0_0805_5%
EV3
VCC1P05_OUT_FET_1 EW1
VCC1P05_OUT_FET_2 EY1
VCC1P05_OUT_FET_3 +VCC1P05_OUT_FET
AM15
VCC_DISPIO +VCC1P05_OUT
lO

BJ12
RSVD_TP_24 BK14 +3VALW_SYS +VCCPDSW_3P3
RSVD_TP_25 BF14
RSVD_TP_20
14 OF 22 RC1412 1 @ 2 0_0402_5%
INTEL_ADL-P-682_BGA1744
<PART_NUMBER>
@
+3VALW_PCH

1U_6.3V_M_X5R_0201
@
RC1407 1 2 0_0402_5%
1

CC1401
PDG: VCCDSW_3P3
tia

Placeholder 1* 0402 capacitor on primary side

as close as possible to the vias. 2@

+VCCST_CPU
+VCC1P05_OUT_FET
+VCCLDOSTD_OUT_0P85 +VCCDPHY_1P24 VCCDSW_1P05

VCCRTC +VCCPRTC_3P3
4.7U_0402_6.3V6M

en

2
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 RC1422 1 @ 2 0_0402_5%
CC1406

CC1412

CC1416

CC1411

CC1413
1M_0402_5%
1

1U_0402_6.3V6K
2.2U_0402_6.3V6M @ 1

0.1u_0201_10V6K
1
1
RC1410

100K_0402_5%
1 1
2 2 2 2

CC1403
@ CC2204

RC1415

CC1402
1U_6.3V_M_X5R_0201 @
2
2

2 2

2
trace width >40mil
CV1537 need within 3mm from PCH dege PDG: VCCDPHY_1P24
fid

4.7u_0402 *1
Require minimum power plane
width of 3mm from BGA to
B Capacitor. Require immediate +3VALW B
GND reference

+1.8VALW +VCCPRIM_1P8
Need stuff
1

@ 1.3A
RC2523 JH2 1 2 JUMP_43X79
on

VCCIN_AUX_PCH_VID1 1 2

10U 6.3V M X5R 0402

CRB place to CPU 100K_0201_5%
+VCCIN_AUX

1M_0402_5%
1
1

RC1419
2

CC1414
@ @
6

D
2
AUX_CPU_SENSE 2 QC24A

2
+VCCIN_AUX +VCCIN_AUX +VCCIN_AUX G LBSS138DW1T1G_SOT363-6
1

RC1403 S
1

100_0402_1%
+3VALW_PCH
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1000P 25V K X7R 0201

1000P 25V K X7R 0201

1000P 25V K X7R 0201

VCCIN_AUX_PCH_VID0
12P_50V_F_COG_0402

12P_50V_F_COG_0402

12P_50V_F_COG_0402

12P_50V_F_COG_0402

12P_50V_F_COG_0402

1 1 1 1 1 1 1 1 1 1 1 1 QC25 D RC2521
C
2

VCCIN_AUX_PCH_VID1
CC481 RF_NS@
100P_0402_50V8J

CC491 RF_NS@

CC511 RF_NS@

CC521 RF_NS@

CC531 RF_NS@

CC541 RF_NS@

CC826

CC827

CC828

CC829

CC830

CC831

2 RC1409 1 2 100K_0201_5% 1 @ 2 100K_0402_5%

@ @ @ @ @ @ 79 EC_VCCIN_AUX_3P3_ON G LBSS139WT1G_SC70-3 RC2522
3

VCCIN_AUX_VCCSEN D RC1406 1 2 100K_0201_5% VCCIN_AUX_PCH_VID0

1 @ 2 100K_0402_5%
99 VCCIN_AUX_VCCSEN S
3

2 2 2 2 2 2 2 2 2 2 2 2 5 QC24B
1

G LBSS138DW1T1G_SOT363-6
RC2524 S
4

@ 10K_0201_5%
VCCIN_AUX_VSSSEN
99 VCCIN_AUX_VSSSEN
2
FC
1

RC1413 Follow C970 reserved for EMC/RF

EMC Suggested reserved
100_0402_1%
2

Note: +3VALW_PCH

RC2524--EC 直直直直enable 时 需需需需

2

+VCCIN_AUX AUX_EN delay 直直时，不需需需； RC1421

100K_0201_5%
RB521CM-30T2R_VMN2M-2
LC

1
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

DC5 2 1 GPPC_B2_VRALERT_N
2 2 2 2 2 2 2 2 2 2 10,79,95 H_PROCHOT_N
CC10
CC1

CC2

CC3

CC4

CC5

CC6

CC7

CC8

CC9

2 1
A A
1 1 1 1 1 1 1 1 1 1 RC1414 1 @ 2 0_0402_5%

0_0201_5% 2 @ 1 RC2467
60 PD_GPPC_B2_VRALERT_N

need confirm GPIO pull level

For power request 0603

Security Classification LCFC Highly Confidential Information Title

ORS-ADL_P
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
YX0 ORS A0

Date: Monday, November 29, 2021 Sheet 19 of 110

5 4 3 2 1
 5 4 3 2 1

D D

T
M
rS
fo
C C
y
nl
lO
tia
en
fid

B B
on
C
FC
LC

A A

Title
ORS-ADL_P

Size Document Number Rev

E YX0 ORS A0

Date: Monday, November 29, 2021 Sheet 20 of 110

5 4 3 2 1
 5 4 3 2 1

D D

? ? ? ? ?
? ? ? ? ?

UC1P BMAP_REV = ? UC1Q BMAP_REV = ? UC1R BMAP_REV = ? UC1S BMAP_REV = ? UC1D BMAP_REV = ?

A3 AL15 BF58 CD58 DC47 ED58 F56 M36 AF27

VSS_7 VSS_74 VSS_149
VSS_222 VSS_295
VSS_369 VSS_443
VSS_517 RSVD_1

T
A10 AL17 BG1 CE51 DC54 ED6 F59 M47 AH20
A21 VSS_1 VSS_75 AL22 BG12 VSS_150
VSS_223 CE55 DC57 VSS_296
VSS_370 ED60 F9 VSS_444
VSS_518 M57 AK22 RSVD_2
A23 VSS_2 VSS_76 AL4 BG44 VSS_151
VSS_224 CF47 DC59 VSS_297
VSS_371 ED8 FA40 VSS_445
VSS_519 M59 AK40 RSVD_4
A25 VSS_3 VSS_77 AL41 BG52 VSS_152
VSS_225 CF49 DE44 VSS_298
VSS_372 EE16 FA7 VSS_446
VSS_520 N1 AL30 RSVD_6
A26 VSS_4 VSS_78 AL54 BG9 VSS_153
VSS_226 CF54 DE51 VSS_299
VSS_373 EE43 FB1 VSS_447
VSS_521 N4 AL40 RSVD_7

M
A28 VSS_5 VSS_79 AM11 BH4 VSS_154
VSS_227 CG57 DE55 VSS_300
VSS_374 EE51 FB14 VSS_448
VSS_522 N40 BG47 RSVD_8
A30 VSS_6 VSS_80 AM3 BH46 VSS_155
VSS_228 CG59 DF43 VSS_301
VSS_375 EF13 FB26 VSS_449
VSS_523 N41 BG53 RSVD_9
A31 VSS_8 VSS_81 AM51 BH48 VSS_156
VSS_229 CH11 DF46 VSS_302
VSS_376 EF8 FB42 VSS_450
VSS_524 N48 DT42 RSVD_10
A33 VSS_9 VSS_82 AM55 BH58 VSS_157
VSS_230 CH12 DF48 VSS_303
VSS_377 EH13 FB48 VSS_451
VSS_525 N54 EE46 RSVD_13
A40 VSS_10 VSS_83 AM9 BJ51 VSS_158
VSS_231 CH54 DF58 VSS_304
VSS_378 EH8 FB59 VSS_452
VSS_526 N9 EF33 RSVD_15

rS
A47 VSS_11 VSS_84 AN17 BJ55 VSS_159
VSS_232 CH6 DG11 VSS_305
VSS_379 EK21 FB61 VSS_453
VSS_527 P11 EH41 RSVD_16
A53 VSS_12 VSS_85 AN40 BJ6 VSS_160
VSS_233 CH8 DG12 VSS_306
VSS_380 EK28 FC2 VSS_454
VSS_528 P16 RSVD_20
A60 VSS_13 VSS_86 AN46 BJ8 VSS_161
VSS_234 CH9 DG51 VSS_307
VSS_381 EK36 FC55 VSS_455
VSS_529 P21 4 OF 22
AA11 VSS_14 VSS_87 AN48 BJ9 VSS_162
VSS_235 CJ14 DG55 VSS_308
VSS_382 EK43 FC56 VSS_456
VSS_530 P26
VSS_15 VSS_88 VSS_163
VSS_236 VSS_309
VSS_383 VSS_457
VSS_531 INTEL_ADL-P-682_BGA1744
AA21 AN58 BL11 CJ4 DG6 EK51 FC58 P3 <PART_NUMBER>
AA26 VSS_16 VSS_89 AP1 BL4 VSS_164
VSS_237 CJ44 DG8 VSS_310
VSS_384 EK56 FC60 VSS_458
VSS_532 P31 @
AA31 VSS_17 VSS_90 AP15 BL54 VSS_165
VSS_238 CK1 DG9 VSS_311
VSS_385 EK58 G21 VSS_459
VSS_533 P35
AA35 VSS_18 VSS_91 AP20 BL9 VSS_166
VSS_239 CK3 DH4 VSS_312
VSS_386 EL13 G25 VSS_460
VSS_534 P47
AA40 VSS_19 VSS_92 AP22 BM1 VSS_167
VSS_240 CK43 DH54 VSS_313
VSS_387 EL4 G28 VSS_461
VSS_535 P51

fo
AA44 VSS_20 VSS_93 AP25 BM14 VSS_168
VSS_241 CK46 DJ47 VSS_314
VSS_388 EL6 G31 VSS_462
VSS_536 P55
AA57 VSS_21 VSS_94 AP35 BM47 VSS_169
VSS_242 CK48 DJ57 VSS_315
VSS_389 EL8 G34 VSS_463
VSS_537 R12
AA59 VSS_22 VSS_95 AP51 BM57 VSS_170
VSS_243 CK51 DJ59 VSS_316
VSS_390 EN13 G42 VSS_464
VSS_538 R17
AB16 VSS_23 VSS_96 AP55 BM59 VSS_171
VSS_244 CK55 DK14 VSS_317
VSS_391 EN8 G43 VSS_465
VSS_539 R22
AB21 VSS_24 VSS_97 AP9 BN1 VSS_172
VSS_245 CK58 DK54 VSS_318
VSS_392 EP14 G50 VSS_466
VSS_540 R27
AB26 VSS_25 VSS_98 AR4 BN54 VSS_173
VSS_246 CM52 DL10 VSS_319
VSS_393 ER1 H1 VSS_467
VSS_541 R32
C AB31 VSS_26 VSS_99 AR54 BN9 VSS_174
VSS_247 CN46 DL11 VSS_320
VSS_394 ER13 H13 VSS_468
VSS_542 R37 C
AB35
AB54
AC4
VSS_27VSS_100
VSS_28VSS_101
VSS_29VSS_102
AT47
AT57
AT59
BP4
BP51
BP55
VSS_175
VSS_248
VSS_176
VSS_249
VSS_177
VSS_250
CN58
CP51
CP55
DL13
DM4
DM41
VSS_321
VSS_322
VSS_323
y
VSS_395
VSS_396
VSS_397
ER21
ER28
ER3
H16
H18
H34
VSS_469
VSS_543
VSS_470
VSS_544
VSS_471
VSS_545
R44
R48
R58
VSS_30VSS_103 VSS_178
VSS_251 VSS_324
VSS_398 VSS_472
VSS_546
nl
AC40 AT6 BR43 CR43 DM46 ER36 H37 T1
AC44 VSS_31VSS_104 AT8 BR46 VSS_179
VSS_252 CR47 DM48 VSS_325
VSS_399 ER43 H52 VSS_473
VSS_547 T11
AC51 VSS_32VSS_105 AU54 BR48 VSS_180
VSS_253 CR49 DM51 VSS_326
VSS_400 ER51 H58 VSS_474
VSS_548 T16
AC55 VSS_33VSS_106 AV11 BR58 VSS_181
VSS_254 CR54 DM55 VSS_327
VSS_401 ER61 H6 VSS_475
VSS_549 T21
AC6 VSS_34VSS_107 AV4 BR6 VSS_182
VSS_255 CT11 DM58 VSS_328
VSS_402 ER8 H8 VSS_476
VSS_550 T26
AC8 VSS_35VSS_108 AV9 BR8 VSS_183
VSS_256 CT57 DM6 VSS_329
VSS_403 EU11 H9 VSS_477
VSS_551 T3
lO

AD21 VSS_36VSS_109 AW1 BR9 VSS_184

VSS_257 CT59 DM61 VSS_330
VSS_404 EU56 J11 VSS_478
VSS_552 T31
AD26 VSS_37VSS_110 AW14 BT4 VSS_185
VSS_258 CT6 DN13 VSS_331
VSS_405 EU58 J14 VSS_479
VSS_553 T35
AD31 VSS_38VSS_111 AW51 BT51 VSS_186
VSS_259 CT8 DN40 VSS_332
VSS_406 EU8 J17 VSS_480
VSS_554 T40
AD35 VSS_39VSS_112 AW55 BT55 VSS_187
VSS_260 CT9 DN8 VSS_333
VSS_407 EV14 J20 VSS_481
VSS_555 T52
AD46 VSS_40VSS_113 AY1 BU54 VSS_188
VSS_261 CU4 DP46 VSS_334
VSS_408 EV20 J21 VSS_482
VSS_556 U16
AD48 VSS_41VSS_114 AY43 BU9 VSS_189
VSS_262 CU54 DP49 VSS_335
VSS_409 EV26 J25 VSS_483
VSS_557 U21
AD58 VSS_42VSS_115 AY46 BV1 VSS_190
VSS_263 CV14 DT13 VSS_336
VSS_410 EV33 J28 VSS_484
VSS_558 U26
AE12 VSS_43VSS_116 AY48 BV47 VSS_191
VSS_264 CW43 DT52 VSS_337
VSS_411 EV39 J31 VSS_485
VSS_559 U31
VSS_44VSS_117 VSS_192
VSS_265 VSS_338
VSS_412 VSS_486
VSS_560
tia

AE17 AY51 BV57 CW46 DT8 EV4 J36 U35

AE22 VSS_45VSS_118 AY55 BV59 VSS_193
VSS_266 CW48 DV13 VSS_339
VSS_413 EV45 J39 VSS_487
VSS_561 U44
AE27 VSS_46VSS_119 AY58 BW4 VSS_194
VSS_267 CW51 DV4 VSS_340
VSS_414 EV52 J47 VSS_488
VSS_562 U46
AE32 VSS_47VSS_120 AY9 BW54 VSS_195
VSS_268 CW55 DV44 VSS_341
VSS_415 EV59 J48 VSS_489
VSS_563 V3
AE37 VSS_48VSS_121 B34 BW9 VSS_196
VSS_269 CW58 DV49 VSS_342
VSS_416 EW61 J51 VSS_490
VSS_564 V40
AE40 VSS_49VSS_122 B4 BY3 VSS_197
VSS_270 CY51 DV56 VSS_344
VSS_417 EY14 J55 VSS_491
VSS_565 V41
AE44 VSS_50VSS_123 B43 C1 VSS_198
VSS_271 CY55 DV58 VSS_345
VSS_418 EY20 K4 VSS_492
VSS_566 V51
VSS_51VSS_124 VSS_199
VSS_272 VSS_346
VSS_419 VSS_493
VSS_567
en

AE52 B50 C21 D11 DV6 EY26 L12 V55

AE9 VSS_52VSS_125 B58 C25 VSS_200
VSS_273 D14 DV8 VSS_347
VSS_420 EY3 L13 VSS_494
VSS_568 V58
AF4 VSS_53VSS_126 B61 C28 VSS_201
VSS_274 D17 DW14 VSS_348
VSS_421 EY33 L15 VSS_495
VSS_569 W1
AF46 VSS_54VSS_127 BA4 C31 VSS_202
VSS_275 D20 DW25 VSS_349
VSS_422 EY39 L17 VSS_496
VSS_570 W11
AG1 VSS_55VSS_128 BB12 C34 VSS_203
VSS_276 D21 DW35 VSS_350
VSS_423 EY4 L18 VSS_497
VSS_571 W16
AG51 VSS_56VSS_130 BB54 C40 VSS_204
VSS_277 D25 DY13 VSS_351
VSS_424 EY45 L20 VSS_498
VSS_572 W21
AG55 VSS_57VSS_131 BB6 C47 VSS_205
VSS_278 D28 DY33 VSS_352
VSS_425 EY52 L22 VSS_499
VSS_573 W26
AG58 VSS_58VSS_132 BB8 C9 VSS_206
VSS_279 D31 DY36 VSS_353
VSS_426 EY56 L23 VSS_500
VSS_574 W31
fid

AH9 VSS_59VSS_133 BB9 CA14 VSS_207

VSS_280 D4 DY38 VSS_354
VSS_427 EY58 L27 VSS_501
VSS_575 W35
AJ3 VSS_60VSS_134 BC14 CA43 VSS_208
VSS_281 D53 DY52 VSS_355
VSS_428 EY59 L30 VSS_502
VSS_576 W44
AJ41 VSS_61VSS_135 BC47 CA46 VSS_209
VSS_282 D56 DY8 VSS_356
VSS_429 EY6 L33 VSS_503
VSS_577 Y12
AJ47 VSS_62VSS_136 BC57 CA48 VSS_210
VSS_283 D58 E43 VSS_357
VSS_430 EY9 L35 VSS_504
VSS_578 Y17
AJ49 VSS_63VSS_137 BC59 CA51 VSS_211
VSS_284 D59 E50 VSS_358
VSS_431 F21 L36 VSS_505
VSS_579 Y22
B
AJ54 VSS_64VSS_138 BD4 CA55 VSS_212
VSS_285 D9 EB13 VSS_359
VSS_432 F23 L38 VSS_506
VSS_580 Y27 B
AK20 VSS_65VSS_139 BD54 CA58 VSS_213
VSS_286 DA11 EB26 VSS_360
VSS_433 F26 L40 VSS_507
VSS_581 Y32
on

AK25 VSS_66VSS_140 BE1 CB4 VSS_214

VSS_287 DA12 EB31 VSS_361
VSS_434 F28 L54 VSS_508
VSS_582 Y37
AK30 VSS_67VSS_141 BE12 CB6 VSS_215
VSS_288 DA6 EB8 VSS_362
VSS_435 F30 L9 VSS_509
VSS_583 Y4
AK37 VSS_68VSS_143 BE51 CB8 VSS_216
VSS_289 DA8 EC21 VSS_363
VSS_436 F33 M16 VSS_510
VSS_584 Y45
AK4 VSS_69VSS_144 BE55 CB9 VSS_217
VSS_290 DA9 EC28 VSS_364
VSS_437 F4 M21 VSS_511
VSS_585 Y47
AK57 VSS_70VSS_145 BE9 CC1 VSS_218
VSS_291 DB14 ED13 VSS_365
VSS_438 F40 M26 VSS_512
VSS_586 Y49
AK59 VSS_71VSS_146 BF46 CC52 VSS_219
VSS_292 DB4 ED4 VSS_366
VSS_439 F46 M31 VSS_513
VSS_587 Y54
AK9 VSS_72VSS_147 BF48 CD46 VSS_220
VSS_293 DB54 ED56 VSS_367
VSS_440 F47 M32 VSS_514
VSS_588
VSS_73VSS_148 VSS_221
VSS_294 VSS_368
VSS_441 VSS_515
C

F52 M34
16 OF 22 17 OF 22 VSS_442 VSS_516
18 OF 22 19 OF 22
INTEL_ADL-P-682_BGA1744
<PART_NUMBER> <PART_NUMBER>
INTEL_ADL-P-682_BGA1744
@ INTEL_ADL-P-682_BGA1744
<PART_NUMBER> INTEL_ADL-P-682_BGA1744
<PART_NUMBER>
@
@ @
FC
LC

A A

Security Classification LCFC Highly Confidential Information Title

ORS-ADL_P
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. YX0 ORS
Date: Monday, November 29, 2021 Sheet 21 of 110
5 4 3 2 1
 5 4 3 2 1

?
?

UC1U BMAP_REV = ? CFG STRAPS for CPU

DDR_TP9
CFG15 AF37 A58 1 @ PAD TH3011
CFG14 AH35 CFG_15 RSVD_TP_1 B59 DDR_TP10
1 @ PAD TH3032
AF35 CFG_14 RSVD_TP_18 D61 DDR_TP11
1 @ PAD TH3033
AH37 CFG_13 RSVD_TP_36
AH25 CFG_12 AF40 Digital_TP1
1 @ PAD TH3034
CFG10 AF20 CFG_11 RSVD_TP_4 AH40 Digital_TP2
1 @ PAD TH3035
CFG9 AH22 CFG_10 RSVD_TP_5
CFG_9 Reserved configuration lane
AK17 DG44
CFG7 AJ15 CFG_8 RSVD_TP_37 DH43
23 CFG7 CFG_7 RSVD_TP_39
23 CFG6 CFG6 AH17
CFG5 AG15 CFG_6 BB11
23
23
CFG5
CFG4 CFG4 AD11 CFG_5 VSS_129 BE11 CFG[1:0] N/A
CFG3 AC12 CFG_4 VSS_142
D 23 CFG3 CFG_3 D
23 CFG2 CFG2 AA12 FB3
CFG1 AD16 CFG_2 RSVD_23 FC6
23 CFG1 CFG_1 RSVD_25
23 CFG0 CFG0 AA16 PCI Express* Static x8 Lanes Numbering Reversal
CFG_0 DY5


1
=
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CFG_RCOMP
F8 RSVD_TP_46 DY6
CFG_RCOMP RSVD_TP_47
AF22 FC9


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a
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23 CFG16 CFG16 AF17 CFG_17 RSVD_27 FC7 CFG2
CFG_16 RSVD_26
+VCC_CFG_PU_OUT RC24601 2 10K_0201_5% BPM#_3 AF12
BPM#_3 RSVD_TP_53
FB4 *
2

RC24581 2 10K_0201_5% BPM#_2 AH12 FC4

BPM#_1 AK12 BPM#_2 RSVD_TP_55 Place near PCH
RC24591 2 10K_0201_5%
BPM#_0 AL12 BPM#_1 GPP_B18_NO_REBOOT Reserved configuration lane

T
RC1002 RC24571 2 10K_0201_5% DT61 RC2416 1 @ 2 1K_0402_5% +1.8VS
G
P
_==Om
P
B
1
8s
_
N
O
_e
R
E
B
O
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T
49.9_0402_1% BPM#_0 GPP_B18
01T
D
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ab
be
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Re
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tt a
md
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de .
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DC
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fw
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AK27 R4
〃
1

RSVD_5 RSVD_28
*
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N eT
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P i
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AH27 AC9 N/A
RSVD_3 RSVD_TP_3 〃 CFG3
CT

M
CFG_VSS_590
iw
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rn

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b/
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AY12 DL1
AT9 VSS_590 RSVD_11 DL3
h
e
u
n
n
n
g
P
D
AT11 RSVD_TP_16 RSVD_12
AP11 RSVD_TP_15 EU61
RSVD_TP_13 RSVD_22 Reserved
2

AP12 EC18

rS
RC1004 BA14 RSVD_TP_14 RSVD_14
RSVD_TP_19 DV46
0_0201_5% VSS_343
CT12 DV42
CR14 RSVD_TP_35 TP_4 DT47
CFG4 N/A
1

EK18 RSVD_TP_34 TP_1 CB11

@ RSVD_TP_51 RSVD_TP_30
EH18 BW11
RSVD_TP_50 RSVD_TP_29
AL25 AK35
AN25 RSVD_TP_6 SKTOCC#

fo
RSVD_TP_10 AN27
RSVD_TP_11 PCI Express* Bifurcation
AL27
RSVD_TP_7
AL35
RSVD_TP_8 AN35
RSVD_TP_12
EL51
C
CFG[6:5] N/A C

21 OF 22
GPP_T3
GPP_T2
EN51
y
nl
INTEL_ADL-P-682_BGA1744
<PART_NUMBER>
@

?
Reserved configuration lane
?
lO

UC1T BMAP_REV = ?

EF48
RSVD_17 RSVD_TP_21
BF43 DDR_TP1 1 @ PAD TH3031 CFG[13:7] N/A
AA9
EF51 RSVD_TP_2 DJ9 +VCC_CFG_PU_OUT
RSVD_18 RSVD_TP_42
DDR_TP2
TH3036 PAD @ 1 ANA_TP1 FB58 DJ12 1 @ PAD TH3024 0.1u_0201_10V6K
RSVD_TP_54 RSVD_TP_41
tia

TH3037 PAD @ 1 ANA_TP2 EY61 AV12 1

RSVD_TP_52 VCC_CFG_PU_OUT CH43 DDR_TP3
1 @ PAD TH3025
CC2203

EH48 RSVD_TP_31 DH14 DDR_TP4

1 @ PAD TH3026
PEG60 Lane Reversal
EF53 RSVD_21 RSVD_TP_38 DW32 DDR_TP5
1 @ PAD TH3027
RSVD_19 RSVD_TP_43 BH14 DDR_TP6
1 @ PAD TH3028 2
DJ11
RSVD_TP_40
RSVD_TP_22
RSVD_TP_44
DW37
AL37
DDR_TP7
DDR_TP8
1 @ PAD TH3029 * 1 (default) normal
1 @ PAD TH3030
RSVD_TP_9  0 Reversed
en

TH3038
TH3039
PAD
PAD
@ 1
@ 1
ANA_TP3
ANA_TP4
EB16
DY18 RSVD_TP_49 CFG14
RSVD_TP_45
20 OF 22
INTEL_ADL-P-682_BGA1744
<PART_NUMBER>
@
R
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.
fid

+VCC_CFG_PU_OUT

B
PEG62 Lane Reversal: B
Follow Check list will PU
CFG[15] 1 - (Default) Normal
on

0 - Reversed
R
e
s
e
r
v
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d
c
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f
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.
1

1
C

RC2431 RC2488 RC2432 RC2433 RC2434

CFG[17:16] N/A
1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5%
2

2
FC

CFG15

CFG10
CFG9

CFG3 Signal Name Description

Vss Ground: Processor ground node
Vss_NCTF Non-Critical To Function: These signals are for package mechanical
CFG14
LC

CFG7
reliability and should not be connected on the board.
CFG6 RSVD Reserved: All signals that are RSVD should not be connected on the
CFG5 board.
CFG4 RSVD_NCTF Reserved Non-Critical To Function: RSVD_NCTF should not be
CFG2 connected on the board.
CFG1 RSVD_TP
Test Point: Intel recommends to route each RSVD_TP to an accessible
1

test point. Intel may require these test points for platform specific
RC1010 RC2435 RC2436 RC2477 RC2437 RC2438 RC1006 RC2439 RC1001 RC1011 RC1009 debug. Leaving these test points inaccessible could delay debug by
@ @ @ @ @ @ @ @ @ @ @ Intel.
1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5%
2

A A

Security Classification LCFC Highly Confidential Information Title

ORS-ADL_P
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. YX0 ORS
Date: Monday, November 29, 2021 Sheet 22 of 110
5 4 3 2 1
 5 4 3 2 1

TABLE : CPU ITP DEBUG REPORT

@ 1 PAD RC2410 1 @ 2 0_0201_5% PCH_TCK
ITH14 PCH_TCK 10
Individual DCI 2.0 +VCCST_CPU RC2402
No use Port w/o connector 2 @ 1

51_0402_1%
GND

R591 NO ASM NO ASM ASM

D 1 D

2
R593 NO ASM NO ASM ASM RC2403 RC2417 RC2421
51_0402_1% 51_0402_1%
R594 NO ASM NO ASM ASM 100_0402_5%
R595 NO ASM NO ASM ASM
2

1
PCH_TDO @ @ @
RC2415 1 @ 2 0_0201_5% XDP_TDO PAD 1 @
R596 NO ASM NO ASM ASM 10 PCH_TDO ITH9
PCH_TDI RC2412 1 @ 2 0_0201_5% XDP_TDI PAD 1 @
R657 NO ASM NO ASM ASM 10 PCH_TDI ITH10
PCH_TMS RC2405 1 @ 2 0_0201_5% XDP_TMS PAD 1 @
R658 NO ASM NO ASM ASM 10 PCH_TMS ITH11
PCH_JTAG_RST_N RC2406 1 @ 2 0_0201_5% PCH_PROC_RST# PAD 1 @
10 PCH_JTAG_RST_N ITH12
R102 NO ASM ASM NO ASM JTAGX RC2419 1 @ 2 0_0201_5% XDP_TCK0 PAD 1 @
10 JTAGX ITH13
R597 NO ASM ASM NO ASM

T
R9907 NO ASM ASM ASM
2

RC2420
JXDP1 NO ASM ASM NO ASM

M
2

@ 51_0402_1%
RC2407
C70 NO ASM ASM NO ASM @ 51_0402_1%
1

+VCCST_CPU
R96 NO ASM ASM NO ASM

rS
1

R101 NO ASM ASM NO ASM

R9909 NO ASM ASM ASM DEFENSIVE A0 PO BOARDS.
INTERNAL 60 - 100OHM ODT TO GND
R9910 NO ASM ASM ASM
RC2422

R9916 NO ASM ASM ASM

RC2463

RC2411

fo
1

R99 NO ASM ASM ASM

Change RC2463 to 100Ω @
R9912 NO ASM ASM ASM
C C
100_0402_5%

R9934 NO ASM ASM ASM

2

1
51_0402_1%

51_0402_1%

R9930 NO ASM ASM ASM

y
R9931 NO ASM ASM ASM
nl
RC2404 1 @ 2 0_0201_5% XDP_TDO
R9932 NO ASM ASM ASM 10 PROC_TDO
RC2413 1 @ 2 0_0201_5% XDP_TDI
R9933 NO ASM ASM ASM 10 PROC_TDI +3VALW_PCH
lO

RC2518 1 @ 2 0_0201_5% XDP_TMS

10 PROC_TMS
RC2414 1 @ 2 0_0201_5% XDP_TCK0
10 PROC_TCK
LOGIC RC2408 1 @ 2 0_0201_5% PCH_PROC_RST#
10 PROC_TRST_N

2
2

RC2423
51_0402_1%

TABLE : PCH ITP DEBUG REPORT

RC2401

RC2409

tia

10K_0201_5%
2

Follow Check list change RC2423 to 10K

No use Individual DCI 2.0

1
@
1

Port w/o connector

1

en

R93 NO ASM ASM NO ASM PAD 1 @

51_0402_1%

17 SYS_RESET_N ITH18
JXDP1 NO ASM ASM NO ASM
R9917 NO ASM ASM NO ASM
fid

R101 NO ASM ASM NO ASM

R9908 NO ASM ASM NO ASM
R9911 NO ASM ASM NO ASM
on

B R9913 NO ASM ASM NO ASM B

R9915 NO ASM ASM NO ASM

C

JCTC_40506W90-NPX-SHLOATCR-D9
LOGIC
22
21 GND2
GND1
FC

PCH_TCK 20
19 20
CFG7 18 19
22 CFG7 18
22 CFG6
CFG6 17
CFG5 16 17
22 CFG5 16
22 CFG4
CFG4 15
CFG3 14 15
22 CFG3 14
22 CFG2
CFG2 13
LC

CFG1 12 13
22 CFG1 12
22 CFG0
CFG0 11
CFG16 10 11
22 CFG16 PCH_JTAG_RST_N 10
9
PCH_TDI 8 9
JTAGX 7 8
PCH_TMS 6 7
PCH_TDO 5 6
4 5
14 USB30_RX2_N_DBG 4
3
14 USB30_RX2_P_DBG 3
2
14 USB30_TX2_N_DBG 2
1
14 USB30_TX2_P_DBG 1
JCDBG1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 ORS-ADL_P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. YX0 ORS
Date: Monday, November 29, 2021 Sheet 23 of 110
5 4 3 2 1
 5 4 3 2 1

D D

T
M
rS
fo
C y C
nl
lO
tia
en
fid
on

B B
C
FC
LC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 XDP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, November 29, 2021 Sheet 24 of 110
5 4 3 2 1
 5 4 3 2 1

RD2501 +5VALW_DDR5
1 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
10K_0201_5%

0.1U_25V_K_X5R_0201
D 1 1 1 1 1 D

CD2501

CD2502

CD2503

CD2504

CD2505
DESIGN NOTE:
HID address for 1st DIMM is 000
JP2C
and resistor value is 10K 2 2 2 2 2
DDRA_DQ[0..63]
8 DDRA_DQ[0..63] STD
DDR0_HSA 2 1
SMB_CLK_S3
4 HSA VIN_BULK_1 3 RD2502
11,26 SMB_CLK_S3 SMB_DATA_S3 HSCL VIN_BULK_3
6 0_0201_5%
11,26 SMB_DATA_S3 HSDA PM_SLP_S4_N
8 2 @ 1 PM_SLP_S4_N 17,26,79,84
DRAM_RESET_N
163 PWR_EN 7 DRAM_PWER_GOOD
8,26 DRAM_RESET_N RESET_N PWR_GOOD DRAM_PWER_GOOD 79

T
JP2A 5 MP1
128 RFU_5 MP1 MP2
DDRA_DQ14 92
STD 102 143 RFU_128 MP2
DDRA_DQ12 91 DQ31_A DQS4_A_P 100 RFU_143
DDRA_DQ13 88 DQ30_A DQS4_AN 83 DDRA_DQS1_P 9 136

M
DDRA_DQ15 DQ29_A DQS3_A_P DDRA_DQS1_N DDRA_DQS1_P 8 VSS_9 VSS_136
87 81 10 141
DDRA_DQ9 DQ28_A DQS3_AN DDRA_DQS0_P DDRA_DQS1_N 8 VSS_10 VSS_141
80 64 13 142
DDRA_DQ11 DQ27_A DQS2_A_P DDRA_DQS0_N DDRA_DQS0_P 8 VSS_13 VSS_142
77 62 14 147
DDRA_DQ10 DQ26_A DQS2_AN DDRA_DQS3_P DDRA_DQS0_N 8 VSS_14 VSS_147
76 41 17 148
DDRA_DQ8 DQ25_A DQS1_A_P DDRA_DQS3_N DDRA_DQS3_P 8 VSS_17 VSS_148
73 39 18 153
DDRA_DQS3_N 8

rS
DDRA_DQ6 72 DQ24_A DQS1_AN 22 DDRA_DQS2_P 21 VSS_18 VSS_153 154
DDRA_DQ4 DQ23_A DQS0_A_P DDRA_DQS2_N DDRA_DQS2_P 8 VSS_21 VSS_154
69 20 24 159
DDRA_DQ5 DQ22_A DQS0_AN DDRA_DQS2_N 8 VSS_24 VSS_159
68 25 160
DDRA_DQ7 65 DQ21_A 108 28 VSS_25 VSS_160 166
DDRA_DQ1 58 DQ20_A ALERT_N 29 VSS_28 VSS_166 167
DDRA_DQ3 57 DQ19_A 127 DDRA_0_CA12 32 VSS_29 VSS_167 170
DDRA_DQ2 DQ18_A CA12_A DDRA_0_CA11 DDRA_0_CA12 8 VSS_32 VSS_170 DRAM_RESET_N
54 126 33 173
DDRA_DQ0 DQ17_A CA11_A DDRA_0_CA10 DDRA_0_CA11 8 VSS_33 VSS_173
53 125 36 174
DDRA_DQ28 DQ16_A CA10_A DDRA_0_CA9 DDRA_0_CA10 8 VSS_36 VSS_174
50 122 37 177

fo
DQ15_A CA9_A DDRA_0_CA9 8 VSS_37 VSS_177 1
DDRA_DQ30 49 121 DDRA_0_CA8 40 178
DDRA_DQ29 DQ14_A CA8_A DDRA_0_CA7 DDRA_0_CA8 8 VSS_40 VSS_178
46 120 43 181 CD2506
DDRA_DQ31 DQ13_A CA7_A DDRA_0_CA6 DDRA_0_CA7 8 VSS_43 VSS_181 0.1U_25V_K_X5R_0201
45 119 44 182
DDRA_DQ26 DQ12_A CA6_A DDRA_0_CA5 DDRA_0_CA6 8 VSS_44 VSS_182 2
38 116 47 185 @
DDRA_DQ25 DQ11_A CA5_A DDRA_0_CA4 DDRA_0_CA5 8 VSS_47 VSS_185
35 115 48 186
DDRA_DQ24 DQ10_A CA4_A DDRA_0_CA3 DDRA_0_CA4 8 VSS_48 VSS_186
34 114 51 189
DDRA_DQ27 DQ09_A CA3_A DDRA_0_CA2 DDRA_0_CA3 8 VSS_51 VSS_189 CAD NOTE:
C 31 113 52 192 C
DDRA_0_CA2 8
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
30
27
26
DQ8_A
DQ7_A
DQ6_A
CA2_A
CA1_A
CA0_A
109
107
DDRA_0_CA1
DDRA_0_CA0 DDRA_0_CA1
DDRA_0_CA0
8
8
y 55
56
59
VSS_52
VSS_55
VSS_56
VSS_192
VSS_193
VSS_196
193
196
197
PLACE THE CAP WITHIN 200 MILS FROM THE
SODIMM

DDRA_DQ23 DQ5_A VSS_59 VSS_197

nl
23 103 60 200
DDRA_DQ19 16 DQ4_A CB3_A 99 63 VSS_60 VSS_200 201
DDRA_DQ16 15 DQ3_A CB2_A 96 66 VSS_63 VSS_201 204
DDRA_DQ18 12 DQ2_A CB1_A 95 67 VSS_66 VSS_204 205
DDRA_DQ17 11 DQ1_A CB0_A 70 VSS_67 VSS_205 208
DQ0_A 132 71 VSS_70 VSS_208 211
lO

CK1_A_P DDRA_CLK1_P 8 VSS_71 VSS_211

134 74 212
CK1_AN DDRA_CLK1_N 8 VSS_74 VSS_212
131 75 215
CK0_A_P DDRA_CLK0_P 8 VSS_75 VSS_215
84 133 78 216
DM3_A_N CK0_AN DDRA_CLK0_N 8 VSS_78 VSS_216
61 79 219
42 DM2_A_N 110 DDRA_0_CS1 82 VSS_79 VSS_219 220
DM1_A_N CS1_A_N DDRA_0_CS0 DDRA_0_CS1 8 VSS_82 VSS_220
19 106 85 223
DM0_A_N CS0_A_N DDRA_0_CS0 8 VSS_85 VSS_223
86 224
1 OF 3 VSS_86 VSS_224
89 227
VSS_89 VSS_227
tia

ME@ 90 228
ARGOSY_D5ASX-262XX-XX52-CXA 93 VSS_90 VSS_228 231
94 VSS_93 VSS_231 234
97 VSS_94 VSS_234 235
JP2B 98 VSS_97 VSS_235 238
101 VSS_98 VSS_238 239
DDRA_DQ62 260
STD 171 104 VSS_101 VSS_239 242
DQ31_B DQS4_B_P VSS_104 VSS_242
en

DDRA_DQ58 259 169 105 243

DDRA_DQ61 256 DQ30_B DQS4_BN 251 DDRA_DQS7_P 111 VSS_105 VSS_243 246
DDRA_DQ63 DQ29_B DQS3_B_P DDRA_DQS7_N DDRA_DQS7_P 8 VSS_111 VSS_246
255 249 112 247
DDRA_DQ60 DQ28_B DQS3_BN DDRA_DQS6_P DDRA_DQS7_N 8 VSS_112 VSS_247
248 232 117 250
DDRA_DQ56 DQ27_B DQS2_B_P DDRA_DQS6_N DDRA_DQS6_P 8 VSS_117 VSS_250
245 230 118 253
DDRA_DQ59 DQ26_B DQS2_BN DDRA_DQS5_P DDRA_DQS6_N 8 VSS_118 VSS_253
244 209 123 254
DDRA_DQ57 DQ25_B DQS1_B_P DDRA_DQS5_N DDRA_DQS5_P 8 VSS_123 VSS_254
241 207 124 257
DDRA_DQ54 DQ24_B DQS1_BN DDRA_DQS4_P DDRA_DQS5_N 8 VSS_124 VSS_257
240 190 129 258
fid

DDRA_DQ52 DQ23_B DQS0_B_P DDRA_DQS4_N DDRA_DQS4_P 8 VSS_129 VSS_258

237 188 130 261
DDRA_DQ53 DQ22_B DQS0_BN DDRA_DQS4_N 8 VSS_130 VSS_261
236 135 262
DDRA_DQ55 233 DQ21_B 144 DDRA_1_CA12 VSS_135 VSS_262
DDRA_DQ49 DQ20_B CA12_B DDRA_1_CA11 DDRA_1_CA12 8 3 OF 3
226 145
DDRA_DQ50 DQ19_B CA11_B DDRA_1_CA10 DDRA_1_CA11 8
225 146 ME@
B DDRA_DQ51 DQ18_B CA10_B DDRA_1_CA9 DDRA_1_CA10 8 B
222 149 ARGOSY_D5ASX-262XX-XX52-CXA
DDRA_DQ48 DQ17_B CA9_B DDRA_1_CA8 DDRA_1_CA9 8
221 150
on

DDRA_DQ45 DQ16_B CA8_B DDRA_1_CA7 DDRA_1_CA8 8

218 151
DDRA_DQ47 DQ15_B CA7_B DDRA_1_CA6 DDRA_1_CA7 8
217 152
DDRA_DQ44 DQ14_B CA6_B DDRA_1_CA5 DDRA_1_CA6 8
214 155
DDRA_DQ46 DQ13_B CA5_B DDRA_1_CA4 DDRA_1_CA5 8
213 156
DDRA_DQ43 DQ12_B CA4_B DDRA_1_CA3 DDRA_1_CA4 8
206 157
DDRA_DQ40 DQ11_B CA3_B DDRA_1_CA2 DDRA_1_CA3 8
203 158
DDRA_DQ41 DQ10_B CA2_B DDRA_1_CA1 DDRA_1_CA2 8
202 162
DQ9_B CA1_B DDRA_1_CA1 8
C

DDRA_DQ42 199 164 DDRA_1_CA0

DDRA_DQ37 DQ8_B CA0_B DDRA_1_CA0 8
198
DDRA_DQ39 195 DQ7_B 175
DDRA_DQ36 194 DQ6_B CB3_B 176
DDRA_DQ38 191 DQ5_B CB2_B 172
DDRA_DQ33 184 DQ4_B CB1_B 168
DDRA_DQ32 183 DQ3_B CB0_B
FC

DDRA_DQ35 180 DQ2_B 138

DDRA_DQ34 DQ1_B CK1_B_P DDRA_CLK3_P 8
179 140
DQ0_B CK1_BN DDRA_CLK3_N 8
137
CK0_B_P DDRA_CLK2_P 8
252 139
229 DM3_B_N CK0_BN DDRA_CLK2_N 8 +5VALW_DDR5
210 DM2_B_N 165 DDRA_1_CS1
DM1_B_N CS1_B_N DDRA_1_CS0 DDRA_1_CS1 8
187 161
DM0_B_N CS0_B_N DDRA_1_CS0 8
2 OF 3
68P_50V_J_NPO_0201

68P_50V_J_NPO_0201
LC

56P_50V_J_NPO_0201

39P_50V_J_COG_0201

56P_50V_J_NPO_0201

39P_50V_J_COG_0201

56P_50V_J_NPO_0201

39P_50V_J_COG_0201

56P_50V_J_NPO_0201

56P_50V_J_NPO_0201

ME@ 1 1 1 1 1 1 1 1 1 1
ARGOSY_D5ASX-262XX-XX52-CXA
CD7275

CD7281

CD7276

CD7282

CD7277

CD7283

CD7278

CD7284

CD7279

CD7285
EMC_NS@

EMC_NS@

2 2 2 2 2 2 2 2 2 2

EMC@ EMC@ EMC@ EMC@ EMC@ EMC@ EMC@ EMC@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 DDRVI SO-DIMM A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. YX0 ORS
Date: Monday, November 29, 2021 Sheet 25 of 110
5 4 3 2 1
 5 4 3 2 1

DESIGN NOTE:

[SA2 SA1 SA0] = [1 1 0]

9 DDRB_DQ[0..63]
DDRB_DQ[0..63] +5VALW_DDR5

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
RD2601
1 2

0.1U_25V_K_X5R_0201
GND
JP3B
1/16W_22.6K_1%_0402 1 1 1 1 1
TBR: 23.2K 0201

CD2602

CD2603

CD2604

CD2605

CD2606
D D
DDRB_DQ17 260
STD 171 DESIGN NOTE: 2 2 2 2 2
DDRB_DQ21 259 DQ31_B DQS4_B_P 169 HID address for 2nd DIMM is 010

DDRB_DQ18 256 DQ30_B DQS4_BN 251 and resistor value is 23.2K

JP3C
DDRB_DQ16 DQ29_B DQS3_B_P DDRB_DQS2_P 9
255 249
DDRB_DQ19 DQ28_B DQS3_BN DDRB_DQS2_N 9
248 232
DDRB_DQ22 245 DQ27_B DQS2_B_P 230
DDRB_DQS3_P 9 STD
DDRB_DQ23 DQ26_B DQS2_BN DDRB_DQS3_N 9 DDR1_HSA
244 209 2 1
DDRB_DQ20 DQ25_B DQS1_B_P DDRB_DQS0_P 9 SMB_CLK_S3 HSA VIN_BULK_1
241 207 4 3 RD2602
DDRB_DQ27 DQ24_B DQS1_BN DDRB_DQS0_N 9 11,25 SMB_CLK_S3 SMB_DATA_S3 HSCL VIN_BULK_3
240 190 6 0_0201_5%
DDRB_DQ26 DQ23_B DQS0_B_P DDRB_DQS1_P 9 11,25 SMB_DATA_S3 HSDA PM_SLP_S4_N
237 188 8 2 @ 1 PM_SLP_S4_N 17,25,79,84
DDRB_DQ25 DQ22_B DQS0_BN DDRB_DQS1_N 9 DRAM_RESET_N PWR_EN
236 163 7 DRAM_PWER_GOOD
DDRB_DQ24 DQ21_B 8,25 DRAM_RESET_N RESET_N PWR_GOOD DRAM_PWER_GOOD 79

T
233 144
DDRB_DQ30 DQ20_B CA12_B DDRB_0_CA12 9
226 145 5 MP1
DDRB_DQ31 DQ19_B CA11_B DDRB_0_CA11 9 RFU_5 MP1
225 146 128 MP2
DDRB_DQ29 DQ18_B CA10_B DDRB_0_CA10 9 RFU_128 MP2
222 149 143
DDRB_DQ28 DQ17_B CA9_B DDRB_0_CA9 9 RFU_143
221 150

M
DDRB_DQ0 DQ16_B CA8_B DDRB_0_CA8 9
218 151 9 136
DDRB_DQ2 DQ15_B CA7_B DDRB_0_CA7 9 VSS_9 VSS_136
217 152 10 141
DDRB_DQ3 DQ14_B CA6_B DDRB_0_CA6 9 VSS_10 VSS_141
214 155 13 142
DDRB_DQ1 DQ13_B CA5_B DDRB_0_CA5 9 VSS_13 VSS_142
213 156 14 147
DDRB_DQ7 DQ12_B CA4_B DDRB_0_CA4 9 VSS_14 VSS_147
206 157 17 148
DDRB_0_CA3 9

rS
DDRB_DQ4 203 DQ11_B CA3_B 158 18 VSS_17 VSS_148 153 DRAM_RESET_N
DDRB_DQ5 DQ10_B CA2_B DDRB_0_CA2 9 VSS_18 VSS_153
202 162 21 154
DDRB_DQ6 DQ9_B CA1_B DDRB_0_CA1 9 VSS_21 VSS_154
199 164 24 159 1
DDRB_DQ8 DQ8_B CA0_B DDRB_0_CA0 9 VSS_24 VSS_159
198 25 160
DDRB_DQ11 195 DQ7_B 175 28 VSS_25 VSS_160 166 CD2601
DDRB_DQ10 194 DQ6_B CB3_B 176 29 VSS_28 VSS_166 167 0.1U_25V_K_X5R_0201
DDRB_DQ9 191 DQ5_B CB2_B 172 32 VSS_29 VSS_167 170 2
DDRB_DQ13 DQ4_B CB1_B VSS_32 VSS_170 @
184 168 33 173
DDRB_DQ12 183 DQ3_B CB0_B 36 VSS_33 VSS_173 174

fo
DDRB_DQ14 180 DQ2_B 138 37 VSS_36 VSS_174 177
DDRB_DQ15 DQ1_B CK1_B_P DDRB_CLK1_P 9 VSS_37 VSS_177
179 140 40 178
DQ0_B CK1_BN DDRB_CLK1_N 9 VSS_40 VSS_178
137 43 181
CK0_B_P DDRB_CLK0_P 9 VSS_43 VSS_181 CAD NOTE:
252 139 44 182
DM3_B_N CK0_BN DDRB_CLK0_N 9 VSS_44 VSS_182
229 47 185
210 DM2_B_N 165 48 VSS_47 VSS_185 186 PLACE THE CAP WITHIN 200 MILS FROM THE
DM1_B_N CS1_B_N DDRB_0_CS1 9 VSS_48 VSS_186 SODIMM
C 187 161 51 189 C
DDRB_0_CS0 9
DM0_B_N

ME@
CS0_B_N
2 OF 3
y 52
55
56
VSS_51
VSS_52
VSS_55
VSS_189
VSS_192
VSS_193
192
193
196
VSS_56 VSS_196
nl
ARGOSY_D5ASX-262XX-XX52-CXA 59 197
60 VSS_59 VSS_197 200
63 VSS_60 VSS_200 201
66 VSS_63 VSS_201 204
67 VSS_66 VSS_204 205
70 VSS_67 VSS_205 208
lO

JP3A 71 VSS_70 VSS_208 211

74 VSS_71 VSS_211 212
DDRB_DQ49 92
STD 102 75 VSS_74 VSS_212 215
DDRB_DQ51 91 DQ31_A DQS4_A_P 100 78 VSS_75 VSS_215 216
DDRB_DQ48 88 DQ30_A DQS4_AN 83 79 VSS_78 VSS_216 219
DDRB_DQ50 DQ29_A DQS3_A_P DDRB_DQS6_P 9 VSS_79 VSS_219
87 81 82 220
DDRB_DQ54 DQ28_A DQS3_AN DDRB_DQS6_N 9 VSS_82 VSS_220
80 64 85 223
DDRB_DQ52 DQ27_A DQS2_A_P DDRB_DQS7_P 9 VSS_85 VSS_223
77 62 86 224
DQ26_A DQS2_AN DDRB_DQS7_N 9 VSS_86 VSS_224
tia

DDRB_DQ53 76 41 89 227
DDRB_DQ55 DQ25_A DQS1_A_P DDRB_DQS4_P 9 VSS_89 VSS_227
73 39 90 228
DDRB_DQ56 DQ24_A DQS1_AN DDRB_DQS4_N 9 VSS_90 VSS_228
72 22 93 231
DDRB_DQ59 DQ23_A DQS0_A_P DDRB_DQS5_P 9 VSS_93 VSS_231
69 20 94 234
DDRB_DQ57 DQ22_A DQS0_AN DDRB_DQS5_N 9 VSS_94 VSS_234
68 97 235
DDRB_DQ62 65 DQ21_A 108 98 VSS_97 VSS_235 238
DDRB_DQ61 58 DQ20_A ALERT_N 101 VSS_98 VSS_238 239
DQ19_A VSS_101 VSS_239
en

DDRB_DQ58 57 127 104 242

DDRB_DQ63 DQ18_A CA12_A DDRB_1_CA12 9 VSS_104 VSS_242
54 126 105 243
DDRB_DQ60 DQ17_A CA11_A DDRB_1_CA11 9 VSS_105 VSS_243
53 125 111 246
DDRB_DQ33 DQ16_A CA10_A DDRB_1_CA10 9 VSS_111 VSS_246
50 122 112 247
DDRB_DQ35 DQ15_A CA9_A DDRB_1_CA9 9 VSS_112 VSS_247
49 121 117 250
DDRB_DQ32 DQ14_A CA8_A DDRB_1_CA8 9 VSS_117 VSS_250
46 120 118 253
DDRB_DQ34 DQ13_A CA7_A DDRB_1_CA7 9 VSS_118 VSS_253
45 119 123 254
DDRB_DQ37 DQ12_A CA6_A DDRB_1_CA6 9 VSS_123 VSS_254
38 116 124 257
fid

DDRB_DQ39 DQ11_A CA5_A DDRB_1_CA5 9 VSS_124 VSS_257

35 115 129 258
DDRB_DQ36 DQ10_A CA4_A DDRB_1_CA4 9 VSS_129 VSS_258
34 114 130 261
DDRB_DQ38 DQ09_A CA3_A DDRB_1_CA3 9 VSS_130 VSS_261
31 113 135 262
DDRB_DQ41 DQ8_A CA2_A DDRB_1_CA2 9 VSS_135 VSS_262
30 109
DDRB_DQ40 DQ7_A CA1_A DDRB_1_CA1 9 3 OF 3
27 107
B DDRB_DQ46 DQ6_A CA0_A DDRB_1_CA0 9 B
26 ME@
DDRB_DQ42 23 DQ5_A 103 ARGOSY_D5ASX-262XX-XX52-CXA
on

DDRB_DQ45 16 DQ4_A CB3_A 99

DDRB_DQ43 15 DQ3_A CB2_A 96
DDRB_DQ44 12 DQ2_A CB1_A 95
DQ1_A CB0_A BPAGE DRAWING
DDRB_DQ47 11
DQ0_A 132 adl_p_dg2_384eu_aep.
CK1_A_P DDRB_CLK3_P 9
134 Wed Sep 30 13:40:00 2020
CK1_AN DDRB_CLK3_N 9
131
CK0_A_P DDRB_CLK2_P 9
C

84 133
DM3_A_N CK0_AN DDRB_CLK2_N 9
61
42 DM2_A_N 110
DM1_A_N CS1_A_N DDRB_1_CS1 9 +5VALW_DDR5
19 106
DM0_A_N CS0_A_N DDRB_1_CS0 9
1 OF 3
1

ME@
FC

ARGOSY_D5ASX-262XX-XX52-CXA RD699
+5VALW_DDR5 Discharge 470_0603_5%
reserve
@

+5VALW
+5VALW_DDR5_DIS
2
1

RD700
LC

47K_0402_5%
@
2

D
EC_ON_5VALW_DDR_N 2 QD1A
G LBSS138DW1T1G_SOT363-6
3

D @ S
1

5 QD1B
79,92 EC_ON_5VALW_DDR
G LBSS138DW1T1G_SOT363-6
@ S
4

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 DDRVI SO-DIMM B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. YX0 ORS
Date: Monday, November 29, 2021 Sheet 26 of 110
5 4 3 2 1
 5 4 3 2 1

D D

T
+3VALW_SYS +3V_SPI

M
RB2 1 @ 2 0_0402_5%

DB1 2 1

rS
@
2 1

RB1 1 2 0_0201_5% SPI_CS1_N RB521CM-30T2R_VMN2M-2 +3V_SPI

11 PCH_SPI0_CS1_N
RB8 1 2 0_0201_5% SPI_CLK
11 PCH_SPI0_CLK
1
RB3 1 2 0_0201_5% SPI_SI
11 PCH_SPI0_SI
UB3
New change CB1

fo
RB6 1 2 0_0201_5% SPI_SO 0.1U_6.3V_K_X5R_0201
11 PCH_SPI0_SO 2
RB4 1 2 0_0201_5% SPI_IO2 SPI_CS1_N 0_0201_5% 1 2 RB14 SPI_16M_CS1_N 1 8
11 PCH_SPI0_IO2 /CS VCC
RB5 1 2 0_0201_5% SPI_IO3 SPI_SO 1/20W_15_5%_0201 1 2 RB15 SPI_16M_SO 2 7 SPI_16M_IO3 RB17 1 2 1/20W_15_5%_0201 SPI_IO3
11 PCH_SPI0_IO3 DO(IO1) /HOLD/RESET(IO3)
C SPI_IO2 1/20W_15_5%_0201 1 2 RB16 SPI_16M_IO2 3 6 SPI_16M_CLK RB18 1 2 1/20W_15_5%_0201 SPI_CLK C
y 4
/WP(IO2)

GND
CLK

DI(IO0)
5 SPI_16M_SI RB19 1 2 1/20W_15_5%_0201 SPI_SI
nl
RB13 1 2 0_0201_5% SPI_CS1_N W25Q128JVSIN_SOIC8
79 EC_SPI_CS0_N
RB10 1 2 1/20W_100_1%_0201 SPI_CLK
lO

79 EC_SPI_CLK
RB11 1 2 1/20W_100_1%_0201 SPI_SI
79 EC_SPI_SI
RB12 1 2 1/20W_100_1%_0201 SPI_SO
79 EC_SPI_SO
+3V_SPI

SPI_SO RB7 1 @ 2 100K_0201_5%

1
tia

New change
UB2 CB3
0.1U_6.3V_K_X5R_0201
2
SPI_CS0_N 0_0201_5% 1 2 RB20 SPI_8M_CS0_N 1 8
/CS VCC
SPI_SO 1/20W_15_5%_0201 1 2 RB21 SPI_8M_SO 2 7 SPI_8M_IO3 RB22 1 2 1/20W_15_5%_0201 SPI_IO3
IO1 IO3
en

SPI_IO2 1/20W_15_5%_0201 1 2 RB23 SPI_8M_IO2 3 6 SPI_8M_CLK RB24 1 2 1/20W_15_5%_0201 SPI_CLK

IO2 CLK
4 5 SPI_8M_SI RB25 1 2 1/20W_15_5%_0201 SPI_SI
GND IO0
EC_SPI_CS0_N RB26 1 @ 2 0_0201_5%
fid

RB9 1 2 0_0201_5% SPI_CS0_N W25R64JVSSIN_SOIC8

11 PCH_SPI0_CS0_N

B B
UB1 ,UB2 co-lay
on

+3V_SPI

UB1
1 8
/CS VCC
C

2 7
IO1 IO3
3 6
IO2 CLK
4 5
GND IO0
9
FC

PTH

W25R256JVEIN_WSON8_8X6
@ New change
LC

A A

Security Classification LCFC Highly Confidential Information Title

Common Module
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. SPI ROM/TPM
Date: Monday, November 29, 2021 Sheet 27 of 110
5 4 3 2 1
 5 4 3 2 1

CORE_PLLVDD
UG1A UG1X
+0.95VGS 13/24 XTAL/PLL
1/24 PCI_EXPRESS
VID_PLLVDD_GPU_BD12 BG22
under GPU

1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201
PEX_WAKE_N SP_PLLVDD

CG1781
1 BR31 under GPU near GPU
TG12@
PEX_WAKE* 2.9A

CG140
BF32 BG25
PLT_RST_VGA_N BT30 PEX_DVDD_1 BF34 VID_PLLVDD
32 PLT_RST_VGA_N 1 1
4.7U_6.3V_K_X6S_0603

4.7U_6.3V_K_X6S_0603
PEX_RST* PEX_DVDD_2

OPT@

OPT@
BF35
1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603
CLK_REQ_GPU_N BP31 PEX_DVDD_3 BF37
PEX_CLKREQ* PEX_DVDD_4 BG32
CLK_PCIE_GPU_P BJ30 PEX_DVDD_5 BG34 2 2
16 CLK_PCIE_GPU_P CLK_PCIE_GPU_N PEX_REFCLK PEX_DVDD_6 1 1 1 1 1 1 1 1 2 2 2 1 1
OPT@

OPT@

OPT@

OPT@

OPT@
@

BK30 BG35
16 CLK_PCIE_GPU_N PEX_REFCLK* PEX_DVDD_7
OPT@

OPT@

OPT@

OPT@
BG37
PEG_CRX_GTX0_P OPT@ PEG_CRX_C_GTX0_P BL31 PEX_DVDD_8

CG1575

CG1576
14 PEG_CRX_GTX0_P CG8 1 2 0.22U_6.3V_K_X5R_0201 BH32
PEG_CRX_GTX0_N OPT@ PEG_CRX_C_GTX0_N BM31 PEX_TX0 PEX_DVDD_9 2 2 2 2 2 2 2 2 1 1 1 2 2

OPT@

OPT@
@
14 PEG_CRX_GTX0_N CG9 1 2 0.22U_6.3V_K_X5R_0201 BH34
PEX_TX0* PEX_DVDD_10 CORE_PLLVDD_GPU

CG1718

CG1719

CG1720
CG177

CG178

CG179

CG180

CG181

CG182
CG1

CG3

BH35 under GPU BF9

PEG_CTX_C_GRX0_P BR32 PEX_DVDD_11 BH37 GPCADC_AVDD
14 PEG_CTX_C_GRX0_P PEG_CTX_C_GRX0_N BT32 PEX_RX0 PEX_DVDD_12

1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201
14 PEG_CTX_C_GRX0_N PEX_RX0*
D PEG_CRX_GTX1_P CG13 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX1_P BJ32 BF25 D
14 PEG_CRX_GTX1_P PEG_CRX_GTX1_N PEX_TX1 CORE_PLL_AVDD
14 PEG_CRX_GTX1_N CG15 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX1_N BK32 6 x 0201 1uF (X6S) 2 x 0603 4.7uF (X6S) 3 x 0603 10uF (X6S) 2 x 0603 22uF (X6S)
PEX_TX1* BF31
PEG_CTX_C_GRX1_P BP33 PEX_CVDD_1 1 1

OPT@

OPT@
BG31
14 PEG_CTX_C_GRX1_P PEG_CTX_C_GRX1_N BR33 PEX_RX1 PEX_CVDD_2 +1.8VS_AON
BH31

T
14 PEG_CTX_C_GRX1_N PEX_RX1* PEX_CVDD_3
PEG_CRX_GTX2_P CG18 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX2_P BL33 2 2
14 PEG_CRX_GTX2_P

1
PEG_CRX_GTX2_N OPT@ PEG_CRX_C_GTX2_N BM33 PEX_TX2

CG142

CG143
14 PEG_CRX_GTX2_N CG19 1 2 0.22U_6.3V_K_X5R_0201
PEX_TX2* RG93
PEG_CTX_C_GRX2_P BR34 100K_0402_1%
14 PEG_CTX_C_GRX2_P PEG_CTX_C_GRX2_N BT34 PEX_RX2
14 PEG_CTX_C_GRX2_N @
PEX_RX2*

2
PEG_CRX_GTX3_P CG20 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX3_P BJ34 XTALSSIN BK8 BP5 XTALOUT Voltage SmartFan PWM %
14 PEG_CRX_GTX3_P PEG_CRX_GTX3_N PEX_TX3 EXT_REFCLK_FL XTAL_OUTBUFF
14 PEG_CRX_GTX3_N CG21 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX3_N BK34 0 V GPIO DISABLED

10K_0402_1%
PEX_TX3* BT5 BR5 0.9 V 33% PWM

1
PEG_CTX_C_GRX3_P BP35 XTAL_IN XTAL_OUT 1.8 V 66% PWM
14 PEG_CTX_C_GRX3_P

1
PEG_CTX_C_GRX3_N BR35 PEX_RX3
14 PEG_CTX_C_GRX3_N

110K_0402_1%
PEX_RX3*

@
RG31
PEG_CRX_GTX4_P CG22 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX4_P BL35 100K_0402_1%
14 PEG_CRX_GTX4_P PEG_CRX_GTX4_N PEX_TX4
14 PEG_CRX_GTX4_N CG23 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX4_N BM35 @ GN20E-FCBGA2714_BGA2714 OPT@

XTALSSIN_RC 2
PEX_TX4*

RG687
rS

2
PEG_CTX_C_GRX4_P BR36 RG92 1 2 10M_0402_5%
14 PEG_CTX_C_GRX4_P PEG_CTX_C_GRX4_N BT36 PEX_RX4
14 PEG_CTX_C_GRX4_N OPT@
PEX_RX4*

18P_0402_50V8J
PEG_CRX_GTX5_P OPT@ PEG_CRX_C_GTX5_P BJ36

OPT@
CG24 1 2 0.22U_6.3V_K_X5R_0201 +1.8VS_AON
14 PEG_CRX_GTX5_P PEG_CRX_GTX5_N PEX_TX5 YG1
14 PEG_CRX_GTX5_N CG25 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX5_N BK36
PEX_TX5* 4 3 XTAL_OUT
Under GPU near GPU
PEG_CTX_C_GRX5_P BP37 BF38 3.5A 1 NC2 3
10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

14 PEG_CTX_C_GRX5_P

RG98 2
PEG_CTX_C_GRX5_N BR37 PEX_RX5 PEX_HVDD_1

@
BF40 2
22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

14 PEG_CTX_C_GRX5_N
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

4.7U_6.3V_K_X6S_0603

4.7U_6.3V_K_X6S_0603

PEX_RX5* PEX_HVDD_2 BF41 XTAL_IN 1 2 CG132

PEG_CRX_GTX6_P CG26 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX6_P BL37 PEX_HVDD_3 BG38 2 1 NC1
14 PEG_CRX_GTX6_P PEG_CRX_GTX6_N PEX_TX6 PEX_HVDD_4 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1
OPT@ PEG_CRX_C_GTX6_N BM37

CG1540
14 PEG_CRX_GTX6_N CG30 1 2 0.22U_6.3V_K_X5R_0201 BG40 10P_0402_50V8J
PEX_TX6* PEX_HVDD_5 27MHZ_10PF_7R27000002 1
OPT@

OPT@

BG41 2
PEG_CTX_C_GRX6_P BR38 PEX_HVDD_6
CG1577

CG1578

BG43 CG131
14 PEG_CTX_C_GRX6_P

fo
PEG_CTX_C_GRX6_N BT38 PEX_RX6 PEX_HVDD_7 2 2 2 2 2 2 2 2 2 2 2 1 1 1 2 2
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
@

BG44
14 PEG_CTX_C_GRX6_N PEX_RX6* PEX_HVDD_8
CG1734
CG658

CG168

CG169

CG170

CG171

CG172

CG659

CG660

CG173

CG174

CG135

CG662

CG175

BH38 10P_0402_50V8J YG1 Change to SJ10000X300

PEG_CRX_GTX7_P CG31 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX7_P BJ38 PEX_HVDD_9 BH40 1
14 PEG_CRX_GTX7_P PEG_CRX_GTX7_N PEX_TX7 PEX_HVDD_10
14 PEG_CRX_GTX7_N CG32 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX7_N BK38 BH41
PEX_TX7* PEX_HVDD_11 BH43
PEG_CTX_C_GRX7_P BP39 PEX_HVDD_12 BH44
14 PEG_CTX_C_GRX7_P PEG_CTX_C_GRX7_N BR39 PEX_RX7 PEX_HVDD_13 9x 0402 1uF (X6S) 2 x 0603 4.7uF (X6S) 3 x 0603 10uF (X6S) 2 x 0603 22uF (X6S)
14 PEG_CTX_C_GRX7_N PEX_RX7*
BL39 under GPU +1.8VS_AON
BM39 PEX_TX8
PEX_TX8* BF43 PEX_PLL_HVDD RG3 1 @ 2 0_0402_5%
BR40 PEX_PLL_HVDD
1U_6.3V_K_X6S_0402

C
BT40

BJ40
BK40
PEX_RX8
PEX_RX8*

PEX_TX9
PEX_TX9*
1
y near GPU
C
2
OPT@

nl
BP41 30ohms (ESR=0.01) Bead
PEX_RX9
CG166

BR41 +1.8VS_AON CORE_PLLVDD

PEX_RX9* P/N;SM01000M300
BL41 N18 change
BM41 PEX_TX10 LG3 1 2 HCB1608KF-300T60_2P
PEX_TX10*

22U_6.3V_M_X6S_0603

4.7U_6.3V_K_X6S_0603
BR42 OPT@
BT42 PEX_RX10
PEX_RX10*
lO

1 1

OPT@

OPT@
BJ42
BK42 PEX_TX11
PEX_TX11*

CG1579
BP43 2 2
PEX_RX11

CG138
BR43
PEX_RX11*
BL43
BM43 PEX_TX12
PEX_TX12*
BR44
BT44 PEX_RX12
PEX_RX12*
BJ44
PEX_TX13
tia

BK44
PEX_TX13*
BP45
BR45 PEX_RX13
PEX_RX13*
BL45 TG13
BM45 PEX_TX14 BK46 PEX_CVDD_SENSE 1
PEX_TX14* PEX_CVDD_SENSE
BR46 @
BT46 PEX_RX14
PEX_RX14* +1.8VS_AON
BL47
en

BM47 PEX_TX15
PEX_TX15*
BP47 BT50 PEX_TERMP RG22 1 2 2.49K_0402_1%
BR47 PEX_RX15 PEX_TERMP OPT@
PEX_RX15*

2
RG1369
For AMD MS solution stuff RG19 & QG2 ,unstuff RG1362 @ 0_0402_5%
2

@ GN20E-FCBGA2714_BGA2714 If AMD platform can PU 3VALW_PCH, RG19 & QG2 unstuff

RG18

1
1/16W_5.6K_1%_0402
fid

@
+3VS +3VALW_PCH
1

+1.8VS_AON
1 2 VGA_PWRGD_R
B 12,32 VGA_PWRGD B
RG21
0_0402_5% 1
2

RG50 @ @
RG19 CG58

2
@ 0_0402_5% @ 0.1u_0201_10V6K RG1361
2
10K_0402_5% OPT@
1

1
on

10K_0402_5%
1
2

3 1 1 3 CLK_REQ_GPU_N
16 GPU_CLKREQ_N

QG2 QG127
LSI1012XT1G_SC-89-3 LSI1012XT1G_SC-89-3
@
Vgs(th)≤0.9V
FS_OVERT# FUNCTION
C

+3VS RG1362 1 @ 2 0_0402_5%

10K_0402_5%
1
RG1337 OPT@

FC
2

OPT@
OVERT_R_N RG183 1 2 0_0402_5%
OVERT_N_NVEN 32
For OVERT Enable
+3VS
10K_0402_5%

@
1
RG1 OPT@

RG11 1 2 0_0402_5% For SWG mode

WRST_N_EC 79
2

D
OVERT_R 5 QG24B
G LBSS138DW1T1G_SOT363-6
OPT@
LC

S
6

D
OVERT_N 2 QG24A
32 OVERT_N
G LBSS138DW1T1G_SOT363-6
OPT@ OVERT_RR_N
S
1

A A
0.1u_0201_10V6K
1

D
PLT_RST_VGA_N PLT_RST_VGA_R_N 2 1
RG2 1 @ 2 0_0402_5% QG16
OPT@

CG16

G LBSS139WT1G_SC70-3
S OPT@
3

2
1
CG17
@
0.1u_0201_10V6K
2

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_PEG I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y550 A0

Date: Monday, November 29, 2021 Sheet 28 of 110

5 4 3 2 1
 5 4 3 2 1

UG1R

7/24 IFPAB

DL-DVI DVI/HDMI DP UG1S

8/24 IFPC

BT10 GPU_IFPA_AUXN GPU_IFPA_AUXN RG6 1 OPT@ 2 100K_0201_5% RG56 1 OPT@ 2 1/20W_1K_1%_0201 IFPCD_RSET BH20
SDA SDA IFPA_AUX_SDA* BT11 GPU_IFPA_AUXP GPU_IFPA_AUXN 55 GPU_IFPA_AUXP 1 OPT@ 2 100K_0201_5% IFPCD_RSET
RG7
SCL SCL IFPA_AUX_SCL GPU_IFPA_AUXP 55 CORE_PLLVDD DVI/HDMI DP

D BR20 GPU_IFPA_TX3_N RG1338 1 @ 2 0_0402_5% +IFPCD_PLLVDD BH19 BM10 D

1U_6.3V_M_X6S_0201
IFPAB_RSET TXC TXC IFPA_L3* BP20 GPU_IFPA_TX3_P GPU_IFPA_TX3_N 55 IFPCD_PLLVDD SDA IFPC_AUX_SDA* HDMI1_DAT 50
RG51 1 OPT@ 2 1/20W_1K_1%_0201 BH23 BL10
IFPAB_RSET TXC TXC IFPA_L3 GPU_IFPA_TX3_P 55 SCL IFPC_AUX_SCL HDMI1_CLK 50
1

OPT@
CORE_PLLVDD BP22 GPU_IFPA_TX2_N BK17 GPU_HDMI_CLK_N
Type-C DP 1

T
TXD0 TXD0 IFPA_L2* BR22 GPU_IFPA_TX2_P GPU_IFPA_TX2_N 55 TXC IFPC_L3* BL17 GPU_HDMI_CLK_P GPU_HDMI_CLK_N 50
+IFPAB_PLLVDD TXD0 TXD0 IFPA_L2 GPU_IFPA_TX2_P 55 2 TXC IFPC_L3 GPU_HDMI_CLK_P 50
RG52 1 @ 2 0_0402_5% BH22
1U_6.3V_M_X6S_0201

IFPAB_PLLVDD GPU_HDMI_TX0_N

CG112
BL19
BT22 GPU_IFPA_TX1_N TXD0 IFPC_L2* BM19 GPU_HDMI_TX0_P GPU_HDMI_TX0_N 50 HDMI
1 IFPA_L1* GPU_IFPA_TX1_N 55 TXD0 IFPC_L2 GPU_HDMI_TX0_P 50
TXD1 TXD1 BT23 GPU_IFPA_TX1_P
OPT@

TXD1 TXD1 IFPA_L1 GPU_IFPA_TX1_P 55 IFPC BK19 GPU_HDMI_TX1_N

TXD1 IFPC_L1* GPU_HDMI_TX1_P GPU_HDMI_TX1_N 50
BJ19

M
TXD1 IFPC_L1 GPU_HDMI_TX1_P 50
2 BR23 GPU_IFPA_TX0_N under GPU
TXD2 TXD2 IFPA_L0* GPU_IFPA_TX0_N 55
BP23 GPU_IFPA_TX0_P GPU_HDMI_TX2_N
CG4

BK20
TXD2 TXD2 IFPA_L0 GPU_IFPA_TX0_P 55 TXD2 IFPC_L0* GPU_HDMI_TX2_P GPU_HDMI_TX2_N 50
BL20
+IFPX_IOVDD TXD2 IFPC_L0 GPU_HDMI_TX2_P 50

+IFPX_IOVDD BF19
under GPU BF20 IFP_IOVDD_5

1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201
4.7U_6.3V_K_X6S_0603
IFP_IOVDD_6
BR11 GPU_IFPB_AUXN GPU_IFPB_AUXN RG2321 OPT@ 2 100K_0201_5%

rS
SDA IFPB_AUX_SDA* BP11 GPU_IFPB_AUXP GPU_IFPB_AUXN 61 GPU_IFPB_AUXP RG2331 OPT@ 2 100K_0201_5% 1 1 1 1 @ GN20E-FCBGA2714_BGA2714
SCL IFPB_AUX_SCL GPU_IFPB_AUXP 61

OPT@

OPT@

OPT@

@
+0.95VGS +IFPX_IOVDD
BL22 GPU_IFPB_TX3_N
1 2 0_5%_0603 +IFPX_IOVDD BF14 TXC IFPB_L3* BM22 GPU_IFPB_TX3_P GPU_IFPB_TX3_N 61 2 2 2 2
RG55 @
IFP_IOVDD_2 TXC IFPB_L3 GPU_IFPB_TX3_P 61

CG159

CG903

CG113

CG59
BF13
IFP_IOVDD_1
1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201
4.7U_6.3V_K_X6S_0603

BF16 BK22 GPU_IFPB_TX2_N

BF17 IFP_IOVDD_3 TXD3 TXD0 IFPB_L2* BJ22 GPU_IFPB_TX2_P GPU_IFPB_TX2_N 61
IFP_IOVDD_4 TXD3 TXD0 IFPB_L2 GPU_IFPB_TX2_P 61
1 1 1 1 Type-C DP 2
OPT@

OPT@

OPT@

OPT@

under GPU
BK23 GPU_IFPB_TX1_N near GPU
TXD4 TXD1 IFPB_L1* BL23 GPU_IFPB_TX1_P GPU_IFPB_TX1_N 61
C,D share the filter

fo
2 2 2 2 TXD4 TXD1 IFPB_L1 GPU_IFPB_TX1_P 61
CG63

CG60

CG664

CG61

BK25 GPU_IFPB_TX0_N
TXD5 TXD2 IFPB_L0* GPU_IFPB_TX0_N 61
TXD5
BJ25 GPU_IFPB_TX0_P
TXD2 IFPB_L0 GPU_IFPB_TX0_P 61
under GPU IFPAB
near GPU
A,B share the filter @ GN20E-FCBGA2714_BGA2714 y
1.If an IFP link is unused, The main and AUX links,
IFPxy_RSET can be left unconnected,and IFPxy_PLLVDD
C
should be 10K PD to GND. C
nl
2.IFP_IOVDD rail can be left unconnected if no IFP link is
used. If any IFP is used, all IFP_IOVDD balls must be
connected to power rail.
UG1T
9/24 IFPD UG1U
10/24 IFPE
lO

DVI/HDMI DP
DVI/HDMI DP

RG54 1 @ 2 1/20W_1K_1%_0201 IFPEF_RSET BH17 BJ11

IFPEF_RSET SDA IFPE_AUX_SDA*
BL11 GPU_EDP_AUXN GPU_EDP_AUXN RG1931 OPT@ 2 100K_0201_5% BK11
SDA IFPD_AUX_SDA* GPU_EDP_AUXN 45 SCL IFPE_AUX_SCL
BM11 GPU_EDP_AUXP GPU_EDP_AUXP RG1941 OPT@ 2 100K_0201_5%
SCL IFPD_AUX_SCL GPU_EDP_AUXP 45 CORE_PLLVDD under GPU
BL13
BT16 GPU_EDP_TX3_N RG1339 1 @ 2 0_0402_5% +IFPEF_PLLVDD BH16 TXC IFPE_L3* BM13
TXC IFPD_L3* GPU_EDP_TX3_N 45 IFPEF_PLLVDD TXC IFPE_L3
BT17 GPU_EDP_TX3_P
1U_6.3V_M_X6S_0201

TXC IFPD_L3 GPU_EDP_TX3_P 45 BK13

10K_0201_5%

TXD0
2

BR17 GPU_EDP_TX2_N IFPE_L2* BJ13

TXD0 IFPD_L2* GPU_EDP_TX2_N 45 1 TXD0 IFPE_L2
BP17 GPU_EDP_TX2_P
RG1340

TXD0 IFPD_L2 GPU_EDP_TX2_P 45

*
1 OPT@

@ BK14
IFPD BP19 GPU_EDP_TX1_N
TXD1 IFPE_L1*
tia

TXD1
BL14
TXD1 IFPD_L1* GPU_EDP_TX1_N 45 IFPE_L1
TXD1 BR19 GPU_EDP_TX1_P 2 IFPE
IFPD_L1 GPU_EDP_TX1_P 45
CG155

BL16
TXD2 IFPE_L0*
BT19 GPU_EDP_TX0_N TXD2
BM16
+IFPX_IOVDD TXD2 IFPD_L0* BT20 GPU_EDP_TX0_P GPU_EDP_TX0_N 45 +IFPX_IOVDD IFPE_L0
TXD2 IFPD_L0 GPU_EDP_TX0_P 45

+IFPX_IOVDD BF22 +IFPX_IOVDD BG13

BF23 IFP_IOVDD_7 BG14 IFP_IOVDD_9
1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201

IFP_IOVDD_8 BG23 IFP_IOVDD_10

1U_6.3V_M_X6S_0201

IFP_IOVDD_15
1
@

@ GN20E-FCBGA2714_BGA2714
en

1 1
OPT@

OPT@

@ GN20E-FCBGA2714_BGA2714

2
2 2
CG158
CG189

CG114

near GPU under GPU under GPU

fid

B B
on

UG1V
6/24 IFPF

DVI/HDMI DP
C

BK10
SDA IFPF_AUX_SDA* BJ10
SCL IFPF_AUX_SCL

BP13
TXC IFPF_L3* BR13
TXC IFPF_L3
BT13
TXD0 IFPF_L2* BT14
TXD0 IFPF_L2
FC

IFPF BR14
TXD1 IFPF_L1* BP14
+IFPX_IOVDD TXD1 IFPF_L1
BP16
TXD2 IFPF_L0* BR16
+IFPX_IOVDD BG19 TXD2 IFPF_L0
BG20 IFP_IOVDD_13
BG16 IFP_IOVDD_14
1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201
4.7U_6.3V_K_X6S_0603

BG17 IFP_IOVDD_11
IFP_IOVDD_12
1 1 1 1
OPT@

OPT@

OPT@

OPT@

@ GN20E-FCBGA2714_BGA2714
LC

2 2 2 2
CG541

CG665

CG666

CG542

A A
near GPU
E,F share the filter under GPU

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_DIGITAL OUT I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y550 A0

Date: Monday, November 29, 2021 Sheet 29 of 110

5 4 3 2 1
 5 4 3 2 1

UG1C
UG1B 3/24 FBB
39,40 FBB_D[0..63] FBB_CMD[0..24] 39
2/24 FBA
37,38 FBA_D[0..63] FBA_CMD[0..24] 37 FBB_D0 FBB_CMD0
D37 B37
FBA_D0 AC51 Y53 FBA_CMD0 FBB_D1 J37 FBB_D0 FBB_CMD0 A37 FBB_CMD1
FBA_D1 AB48 FBA_D0 FBA_CMD0 AA56 FBA_CMD1 FBB_D2 G37 FBB_D1 FBB_CMD1 A38 FBB_CMD2
FBA_D2 AC52 FBA_D1 FBA_CMD1 AB55 FBA_CMD2 FBB_D3 F37 FBB_D2 FBB_CMD2 D38 FBB_CMD3
FBA_D3 AC49 FBA_D2 FBA_CMD2 AB56 FBA_CMD3 FBB_D4 H38 FBB_D3 FBB_CMD3 A39 FBB_CMD4
FBA_D4 AF52 FBA_D3 FBA_CMD3 AC56 FBA_CMD4 FBB_D5 E38 FBB_D4 FBB_CMD4 B40 FBB_CMD5
FBA_D5 AC54 FBA_D4 FBA_CMD4 AC53 FBA_CMD5 FBB_D6 F40 FBB_D5 FBB_CMD5 A40 FBB_CMD6
FBA_D6 AE51 FBA_D5 FBA_CMD5 AD56 FBA_CMD6 FBB_D7 D40 FBB_D6 FBB_CMD6 A41 FBB_CMD7
FBA_D7 AF51 FBA_D6 FBA_CMD6 AE55 FBA_CMD7 FBB_D8 F34 FBB_D7 FBB_CMD7 D41 FBB_CMD8
FBA_D8 W51 FBA_D7 FBA_CMD7 AE56 FBA_CMD8 FBB_D9 J34 FBB_D8 FBB_CMD8 A42 FBB_CMD9
FBA_D9 W50 FBA_D8 FBA_CMD8 AF56 FBA_CMD9 FBB_D10 D34 FBB_D9 FBB_CMD9 B43 FBB_CMD10
FBA_D10 W53 FBA_D9 FBA_CMD9 AF53 FBA_CMD10 FBB_D11 G34 FBB_D10 FBB_CMD10 A43 FBB_CMD11
FBA_D11 Y54 FBA_D10 FBA_CMD10 AG56 FBA_CMD11 FBB_D12 E35 FBB_D11 FBB_CMD11 A44 FBB_CMD12
D D
FBA_D12 Y52 FBA_D11 FBA_CMD11 AH55 FBA_CMD12 GA1XX GDDR6 CMD Mapping FBB_D13 K34 FBB_D12 FBB_CMD12 D44 FBB_CMD13
FBA_D13 Y51 FBA_D12 FBA_CMD12 AH56 FBA_CMD13 Lower 0..31 Upper 32..63 FBB_D14 H35 FBB_D13 FBB_CMD13 A45 FBB_CMD14
FBA_D14 Y49 FBA_D13 FBA_CMD13 AJ56 FBA_CMD14 DRAM1 DRAM2 FBB_D15 K35 FBB_D14 FBB_CMD14 B46 FBB_CMD15
FBA_D15 AB51 FBA_D14 FBA_CMD14 AJ53 FBA_CMD15 CHA-Byte 0,1 CHA-Byte 4,5 FBB_D16 G47 FBB_D15 FBB_CMD15 A46 FBB_CMD16
FBA_D16 AM54 FBA_D15 FBA_CMD15 AK56 FBA_CMD16 FBB_D17 E44 FBB_D16 FBB_CMD16 A47 FBB_CMD17
FBA_D17 AL51 FBA_D16 FBA_CMD16 AL55 FBA_CMD17 CA0_A CMD1 CMD33 FBB_D18 F46 FBB_D17 FBB_CMD17 D47 FBB_CMD18
FBA_D18 AM52 FBA_D17 FBA_CMD17 AL56 FBA_CMD18 CA1_A CMD13 CMD45 FBB_D19 F44 FBB_D18 FBB_CMD18 A48 FBB_CMD19
FBA_D19 AJ54 FBA_D18 FBA_CMD18 AM56 FBA_CMD19 CA2_A CMD12 CMD35 FBB_D20 E46 FBB_D19 FBB_CMD19 B49 FBB_CMD20
FBA_D20 AM47 FBA_D19 FBA_CMD19 AM53 FBA_CMD20 CA3_A CMD24 CMD46 FBB_D21 C47 FBB_D20 FBB_CMD20 A49 FBB_CMD21
FBA_D21 AM51 FBA_D20 FBA_CMD20 AN56 FBA_CMD21 CA4_A CMD11 CMD36 FBB_D22 E47 FBB_D21 FBB_CMD21 B50 FBB_CMD22

T
FBA_D22 AP50 FBA_D21 FBA_CMD21 AP55 FBA_CMD22 CA5_A CMD15 CMD43 FBB_D23 C49 FBB_D22 FBB_CMD22 A50 FBB_CMD23
FBA_D23 AM49 FBA_D22 FBA_CMD22 AP56 FBA_CMD23 CA6_A CMD22 CMD48 FBB_D24 G40 FBB_D23 FBB_CMD23 C50 FBB_CMD24
FBA_D24 AF54 FBA_D23 FBA_CMD23 AR56 FBA_CMD24 CA7_A CMD23 CMD47 FBB_D25 C41 FBB_D24 FBB_CMD24 A51 FBB_CMD25
FBA_D25 AF49 FBA_D24 FBA_CMD24 AR53 FBA_CMD25 CA8_A CMD0 CMD34 FBB_D26 E41 FBB_D25 FBB_CMD25_NC B52 FBB_CMD26
FBA_D26 FBA_D25 FBA_CMD25_NC FBB_D26 FBB_CMD26_NC FBB_CMD[28..52] 40
AT56 FBA_CMD26 FBB_D27

M
AH51 CA9_A CMD2 CMD32 F41 C52
FBA_D27 FBA_D26 FBA_CMD26_NC FBA_CMD[28..52] 38 FBB_D28 FBB_D27 FBB_CMD27 FBB_CMD28
AF47 AR55 CABI_A CMD10 CMD37 F43 Y56
FBA_D28 AJ52 FBA_D27 FBA_CMD27 BM56 FBA_CMD28 CKE_A CMD14 CMD44 FBB_D29 C44 FBB_D28 FBB_CMD28 W56 FBB_CMD29
FBA_D29 AJ51 FBA_D28 FBA_CMD28 BM55 FBA_CMD29 FBB_D30 H41 FBB_D29 FBB_CMD29 W55 FBB_CMD30
FBA_D30 AH48 FBA_D29 FBA_CMD29 BL56 FBA_CMD30 CHB-Byte 2,3 CHB-Byte 6,7 FBB_D31 H44 FBB_D30 FBB_CMD30 V56 FBB_CMD31
FBA_D31 AJ49 FBA_D30 FBA_CMD30 BK55 FBA_CMD31 CA0_B CMD5 CMD29 FBB_D32 L51 FBB_D31 FBB_CMD31 U53 FBB_CMD32
FBA_D32 BA49 FBA_D31 FBA_CMD31 BK56 FBA_CMD32 CA1_B CMD18 CMD52 FBB_D33 L52 FBB_D32 FBB_CMD32 U56 FBB_CMD33

rS
FBA_D33 BD47 FBA_D32 FBA_CMD32 BJ56 FBA_CMD33 CA2_B CMD7 CMD40 FBB_D34 N51 FBB_D33 FBB_CMD33 T56 FBB_CMD34
FBA_D34 BD54 FBA_D33 FBA_CMD33 BJ55 FBA_CMD34 CA3_B CMD20 CMD50 FBB_D35 L49 FBB_D34 FBB_CMD34 T55 FBB_CMD35
FBA_D35 BD52 FBA_D34 FBA_CMD34 BH56 FBA_CMD35 CA4_B CMD8 CMD39 FBB_D36 L54 FBB_D35 FBB_CMD35 R56 FBB_CMD36
FBA_D36 BC51 FBA_D35 FBA_CMD35 BG53 FBA_CMD36 CA5_B CMD16 CMD42 FBB_D37 N47 FBB_D36 FBB_CMD36 P53 FBB_CMD37
FBA_D37 BD51 FBA_D36 FBA_CMD36 BG56 FBA_CMD37 CA6_B CMD21 CMD49 FBB_D38 P51 FBB_D37 FBB_CMD37 P56 FBB_CMD38
FBA_D38 BF51 FBA_D37 FBA_CMD37 BF56 FBA_CMD38 CA7_B CMD19 CMD51 FBB_D39 P49 FBB_D38 FBB_CMD38 N56 FBB_CMD39
FBA_D39 BD49 FBA_D38 FBA_CMD38 BF55 FBA_CMD39 CA8_B CMD6 CMD28 FBB_D40 T51 FBB_D39 FBB_CMD39 N55 FBB_CMD40
FBA_D40 BG52 FBA_D39 FBA_CMD39 BE56 FBA_CMD40 CA9_B CMD4 CMD30 FBB_D41 P52 FBB_D40 FBB_CMD40 M56 FBB_CMD41
FBA_D41 BG51 FBA_D40 FBA_CMD40 BD53 FBA_CMD41 CABI_B CMD9 CMD38 FBB_D42 P54 FBB_D41 FBB_CMD41 L53 FBB_CMD42
FBA_D42 BG54 FBA_D41 FBA_CMD41 BD56 FBA_CMD42 FBB_D43 U47 FBB_D42 FBB_CMD42 L56 FBB_CMD43

fo
CKE_B CMD17 CMD41
FBA_D43 BF49 FBA_D42 FBA_CMD42 BC56 FBA_CMD43 FBB_D44 U51 FBB_D43 FBB_CMD43 K56 FBB_CMD44
FBA_D44 BJ54 FBA_D43 FBA_CMD43 BC55 FBA_CMD44 RESET* CMD3 CMD31 FBB_D45 U52 FBB_D44 FBB_CMD44 K55 FBB_CMD45
FBA_D45 BG50 FBA_D44 FBA_CMD44 BB56 FBA_CMD45 FBB_D46 U54 FBB_D45 FBB_CMD45 J56 FBB_CMD46
FBA_D46 BJ52 FBA_D45 FBA_CMD45 BA53 FBA_CMD46 FBB_D47 U49 FBB_D46 FBB_CMD46 H53 FBB_CMD47
FBA_D47 BK53 FBA_D46 FBA_CMD46 BA56 FBA_CMD47 FBB_D48 D52 FBB_D47 FBB_CMD47 H56 FBB_CMD48
FBA_D48 AP51 FBA_D47 FBA_CMD47 AY56 FBA_CMD48 FBB_D49 C53 FBB_D48 FBB_CMD48 G56 FBB_CMD49
FBA_D49 AP53 FBA_D48 FBA_CMD48 AY55 FBA_CMD49 FBB_D50 C54 FBB_D49 FBB_CMD49 G55 FBB_CMD50
FBA_D50 AR52 FBA_D49 FBA_CMD49 AW56FBA_CMD50 FBB_D51 C55 FBB_D50 FBB_CMD50 E56 FBB_CMD51

C
FBA_D51
FBA_D52
FBA_D53
AR54
AU51
AR51
FBA_D50
FBA_D51
FBA_D52
FBA_CMD50
FBA_CMD51
FBA_CMD52
AV53 FBA_CMD51
AV56 FBA_CMD52
AU56 FBA_CMD53
y FBB_D52
FBB_D53
FBB_D54
D55
D54
F56
FBB_D51
FBB_D52
FBB_D53
FBB_CMD51
FBB_CMD52
FBB_CMD53_NC
B54
B53
A52
FBB_CMD52

FBB_CMD54
C

FBA_D54 AV51 FBA_D53 FBA_CMD53_NC AU55 FBA_CMD54 FBB_D55 F49 FBB_D54 FBB_CMD54_NC E55
nl
FBA_D55 AR49 FBA_D54 FBA_CMD54_NC AV55 FBB_D56 G53 FBB_D55 FBB_CMD55
FBA_D56 AV49 FBA_D55 FBA_CMD55 FBB_D57 H49 FBB_D56
FBA_D57 AV54 FBA_D56 FBB_D58 H51 FBB_D57
FBA_D58 AY51 FBA_D57 FBB_D59 G51 FBB_D58
FBA_D59 AV52 FBA_D58 FBB_D60 H52 FBB_D59
FBA_D60 AY48 FBA_D59 FBB_D61 H54 FBB_D60
lO

FBA_D61 BA54 FBA_D60 FBB_D62 K48 FBB_D61 K44 FBB_CLK0_P

FBA_D62 BA52 FBA_D61 AP48 FBA_CLK0_P FBB_D63 K51 FBB_D62 FBB_CLK0 J44 FBB_CLK0_N FBB_CLK0_P 39
FBA_D63 BA51 FBA_D62 FBA_CLK0 AP47 FBA_CLK0_N FBA_CLK0_P 37 FBB_D63 FBB_CLK0* J46 FBB_CLK1_P FBB_CLK0_N 39
FBA_D63 FBA_CLK0* AR48 FBA_CLK1_P FBA_CLK0_N 37 FBB_CLK1 K46 FBB_CLK1_N FBB_CLK1_P 40
FBA_CLK1 AR47 FBA_CLK1_N FBA_CLK1_P 38 FBB_DBI0_N F38 FBB_CLK1* FBB_CLK1_N 40
FBA_DBI0_N AE50 FBA_CLK1* FBA_CLK1_N 38 39 FBB_DBI0_N FBB_DBI1_N F35 FBB_DQM0
37 FBA_DBI0_N FBA_DBI1_N AB50 FBA_DQM0 39 FBB_DBI1_N FBB_DBI2_N G46 FBB_DQM1 J40 FBB_WCK01_P
37 FBA_DBI1_N FBA_DBI2_N AL50 FBA_DQM1 AE48 FBA_WCK01_P 39 FBB_DBI2_N FBB_DBI3_N G43 FBB_DQM2 FBB_WCK01 K40 FBB_WCK01_N FBB_WCK01_P 39
37 FBA_DBI2_N FBA_DBI3_N AH50 FBA_DQM2 FBA_WCK01 AE47 FBA_WCK01_N FBA_WCK01_P 37 39 FBB_DBI3_N FBB_DBI4_N N50 FBB_DQM3 FBB_WCK01* K38 FBB_WCKB01_P FBB_WCK01_N 39
37 FBA_DBI3_N FBA_DBI4_N BC50 FBA_DQM3 FBA_WCK01* AC48 FBA_WCKB01_P FBA_WCK01_N 37 40 FBB_DBI4_N FBB_DBI5_N T50 FBB_DQM4 FBB_WCKB01 J38 FBB_WCKB01_N FBB_WCKB01_P 39
tia

38 FBA_DBI4_N FBA_DBI5_N BF50 FBA_DQM4 FBA_WCKB01 AC47 FBA_WCKB01_N FBA_WCKB01_P 37 40 FBB_DBI5_N FBB_DBI6_N E49 FBB_DQM5 FBB_WCKB01* J43 FBB_WCK23_P FBB_WCKB01_N 39
38 FBA_DBI5_N FBA_DBI6_N AU50 FBA_DQM5 FBA_WCKB01* AL48 FBA_WCK23_P FBA_WCKB01_N 37 40 FBB_DBI6_N FBB_DBI7_N K50 FBB_DQM6 FBB_WCK23 K43 FBB_WCK23_N FBB_WCK23_P 39
38 FBA_DBI6_N FBA_DBI7_N AY50 FBA_DQM6 FBA_WCK23 AL47 FBA_WCK23_N FBA_WCK23_P 37 40 FBB_DBI7_N FBB_DQM7 FBB_WCK23* K41 FBB_WCKB23_P FBB_WCK23_N 39
38 FBA_DBI7_N FBA_DQM7 FBA_WCK23* AJ48 FBA_WCKB23_P FBA_WCK23_N 37 FBB_WCKB23 J41 FBB_WCKB23_N FBB_WCKB23_P 39
FBA_WCKB23 AJ47 FBA_WCKB23_N FBA_WCKB23_P 37 FBB_EDC0 C38 FBB_WCKB23* P47 FBB_WCK45_P FBB_WCKB23_N 39
FBA_EDC0 AE53 FBA_WCKB23* BA47 FBA_WCK45_P FBA_WCKB23_N 37 39 FBB_EDC0 FBB_EDC1 C35 FBB_DQS_WP0 FBB_WCK45 P48 FBB_WCK45_N FBB_WCK45_P 40
37 FBA_EDC0 FBA_EDC1 AB53 FBA_DQS_WP0 FBA_WCK45 BA48 FBA_WCK45_N FBA_WCK45_P 38 39 FBB_EDC1 FBB_EDC2 D46 FBB_DQS_WP1 FBB_WCK45* T48 FBB_WCKB45_P FBB_WCK45_N 40
37 FBA_EDC1 FBA_EDC2 AL53 FBA_DQS_WP1 FBA_WCK45* BC48 FBA_WCKB45_P FBA_WCK45_N 38 39 FBB_EDC2 FBB_EDC3 D43 FBB_DQS_WP2 FBB_WCKB45 T47 FBB_WCKB45_N FBB_WCKB45_P 40
en

37 FBA_EDC2 FBA_EDC3 AH53 FBA_DQS_WP2 FBA_WCKB45 BC47 FBA_WCKB45_N FBA_WCKB45_P 38 39 FBB_EDC3 FBB_EDC4 N53 FBB_DQS_WP3 FBB_WCKB45* K47 FBB_WCK67_P FBB_WCKB45_N 40
37 FBA_EDC3 FBA_EDC4 BC53 FBA_DQS_WP3 FBA_WCKB45* AU48 FBA_WCK67_P FBA_WCKB45_N 38 40 FBB_EDC4 FBB_EDC5 T53 FBB_DQS_WP4 FBB_WCK67 J47 FBB_WCK67_N FBB_WCK67_P 40
38 FBA_EDC4 FBA_EDC5 BF53 FBA_DQS_WP4 FBA_WCK67 AU47 FBA_WCK67_N FBA_WCK67_P 38 40 FBB_EDC5 FBB_EDC6 E53 FBB_DQS_WP5 FBB_WCK67* L47 FBB_WCKB67_P FBB_WCK67_N 40
38 FBA_EDC5 FBA_EDC6 AU53 FBA_DQS_WP5 FBA_WCK67* AV48 FBA_WCKB67_P FBA_WCK67_N 38 40 FBB_EDC6 FBB_EDC7 K53 FBB_DQS_WP6 FBB_WCKB67 L48 FBB_WCKB67_N FBB_WCKB67_P 40
38 FBA_EDC6 FBA_EDC7 AY53 FBA_DQS_WP6 FBA_WCKB67 AV47 FBA_WCKB67_N FBA_WCKB67_P 38 40 FBB_EDC7 FBB_DQS_WP7 FBB_WCKB67* FBB_WCKB67_N 40
38 FBA_EDC7 FBA_DQS_WP7 FBA_WCKB67* FBA_WCKB67_N 38
BN44
BN37 BN45 GND_702
fid

BN38 GND_694 BN46 GND_703

BN39 GND_695 BN47 GND_704
BN4 GND_696 BN48 GND_705 +FB_PLLAVDD
BN40 GND_697 +FB_PLLAVDD BN6 GND_706
BN41 GND_698 BN9 GND_707
BN42 GND_699 BP1 GND_708 L17
B BN43 GND_700 AC46 GND_709 FB_PLLVDD_4 B
GND_701 FB_PLLVDD_1 AE11

1U_6.3V_K_X6S_0402
FB_PLLVDD_2
on

AP46
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

22U_6.3V_M_X6S_0603

1
4.7U_6.3V_K_X6S_0603

4.7U_6.3V_K_X6S_0603

FB_PLLVDD_3
1 1 1 1 1 1
2
OPT@

OPT@
CG151

CG153
2 2 2 2 2 2
OPT@

OPT@

OPT@

@ GN20E-FCBGA2714_BGA2714
@
OPT@
CG56

@ GN20E-FCBGA2714_BGA2714
CG152

CG149

CG192

CG150
C

Under GPU Near GPU Under GPU

30ohms (ESR=0.01) Bead

FC

FBVDDQ
P/N;SM01000M300 FBVDDQ
+1.8VS_AON N18 change +FB_PLLAVDD
1

FBVDDQ CKE_B
1

OPT@ FBVDDQ CKE_A RG236 RG237

LG1 1 2 HCB1608KF-300T60_2P RG67 RG68 10K_0402_1% 10K_0402_1%
10K_0402_1% 10K_0402_1% OPT@ OPT@
1

Place close to BGA CKE_A CKE_B OPT@ OPT@

2

2
1

RG234 RG235 FBB_CMD17

2

FBB_CMD14 FBB_CMD41
LC

RG42 RG57 10K_0402_1% 10K_0402_1%

10K_0402_1% 10K_0402_1% OPT@ OPT@ FBB_CMD44
OPT@ OPT@
2

FBA_CMD17 FBB_CMD3
2

FBA_CMD14 FBA_CMD41 FBB_CMD31

FBA_CMD44

FBA_CMD3
1

FBA_CMD31
RESET RG69 RG70 FBB_CMD25
10K_0402_1% 10K_0402_1% FBB_CMD26
OPT@ OPT@
1

FBB_CMD54
2

A A
RESET RG58 RG62
10K_0402_1% 10K_0402_1%
OPT@ OPT@
FBA_CMD25
2

FBA_CMD26
FBA_CMD53
FBA_CMD54

Security Classification
Classification LCFC Highly Confidential Information Title
Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_VRAM A/B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A2 Y550 A0

Date: Monday, November 29, 2021 Sheet 30 of 110

5 4 3 2 1
 5 4 3 2 1

UG1D UG1E
4/24 FBC 5/24 FBD
41,42 FBC_D[0..63] FBC_CMD[0..24] 41 43,44 FBD_D[0..63] FBD_CMD[0..24] 43
FBC_D0 F7 B5 FBC_CMD0 FBD_D0 AR4 AU1 FBD_CMD0
FBC_D1 H5 FBC_D0 FBC_CMD0 A5 FBC_CMD1 FBD_D1 AP8 FBD_D0 FBD_CMD0 AU4 FBD_CMD1
FBC_D2 F8 FBC_D1 FBC_CMD1 C5 FBC_CMD2 FBD_D2 AP6 FBD_D1 FBD_CMD1 AT1 FBD_CMD2
FBC_D3 G5 FBC_D2 FBC_CMD2 A6 FBC_CMD3 FBD_D3 AR6 FBD_D2 FBD_CMD2 AR2 FBD_CMD3
FBC_D4 H8 FBC_D3 FBC_CMD3 B7 FBC_CMD4 FBD_D4 AM6 FBD_D3 FBD_CMD3 AR1 FBD_CMD4
D D
FBC_D5 E8 FBC_D4 FBC_CMD4 A7 FBC_CMD5 FBD_D5 AP3 FBD_D4 FBD_CMD4 AP1 FBD_CMD5
FBC_D6 C8 FBC_D5 FBC_CMD5 A8 FBC_CMD6 FBD_D6 AP5 FBD_D5 FBD_CMD5 AP4 FBD_CMD6
FBC_D7 D10 FBC_D6 FBC_CMD6 D8 FBC_CMD7 FBD_D7 AM9 FBD_D6 FBD_CMD6 AN1 FBD_CMD7
FBC_D8 D2 FBC_D7 FBC_CMD7 A9 FBC_CMD8 FBD_D8 AU5 FBD_D7 FBD_CMD7 AM2 FBD_CMD8
FBC_D9 E1 FBC_D8 FBC_CMD8 B10 FBC_CMD9 FBD_D9 AV6 FBD_D8 FBD_CMD8 AM1 FBD_CMD9
FBC_D10 C2 FBC_D9 FBC_CMD9 A10 FBC_CMD10 FBD_D10 AV9 FBD_D9 FBD_CMD9 AL1 FBD_CMD10
FBC_D11 D3 FBC_D10 FBC_CMD10 A11 FBC_CMD11 FBD_D11 AU3 FBD_D10 FBD_CMD10 AL4 FBD_CMD11
FBC_D12 C3 FBC_D11 FBC_CMD11 D11 FBC_CMD12 GA1XX GDDR6 CMD Mapping FBD_D12 AU6 FBD_D11 FBD_CMD11 AK1 FBD_CMD12
x16 Mode
FBC_D13 B4 FBC_D12 FBC_CMD12 A12 FBC_CMD13 FBD_D13 AU8 FBD_D12 FBD_CMD12 AJ2 FBD_CMD13
Lower 0..31 Upper 32..63
FBC_D14 E4 FBC_D13 FBC_CMD13 B13 FBC_CMD14 FBD_D14 AU10 FBD_D13 FBD_CMD13 AJ1 FBD_CMD14

T
DRAM1 DRAM2
FBC_D15 D5 FBC_D14 FBC_CMD14 A13 FBC_CMD15 FBD_D15 AR7 FBD_D14 FBD_CMD14 AH1 FBD_CMD15
CHA-Byte 0,1 CHA-Byte 4,5
FBC_D16 F17 FBC_D15 FBC_CMD15 A14 FBC_CMD16 FBD_D16 AF6 FBD_D15 FBD_CMD15 AH4 FBD_CMD16
FBC_D17 E14 FBC_D16 FBC_CMD16 D14 FBC_CMD17 FBD_D17 AH5 FBD_D16 FBD_CMD16 AG1 FBD_CMD17
CA0_A CMD1 CMD33
FBC_D18 C14 FBC_D17 FBC_CMD17 A15 FBC_CMD18 FBD_D18 AH3 FBD_D17 FBD_CMD17 AF2 FBD_CMD18
CA1_A CMD13 CMD45
FBC_D19 FBC_D18 FBC_CMD18 FBC_CMD19 FBD_D19 FBD_D18 FBD_CMD18 FBD_CMD19

M
H14 B16 CA2_A CMD12 CMD35 AF9 AF1
FBC_D20 E17 FBC_D19 FBC_CMD19 A16 FBC_CMD20 FBD_D20 AE6 FBD_D19 FBD_CMD19 AE1 FBD_CMD20
CA3_A CMD24 CMD46
FBC_D21 F16 FBC_D20 FBC_CMD20 A17 FBC_CMD21 FBD_D21 AE8 FBD_D20 FBD_CMD20 AE4 FBD_CMD21
CA4_A CMD11 CMD36
FBC_D22 C17 FBC_D21 FBC_CMD21 D17 FBC_CMD22 FBD_D22 AE5 FBD_D21 FBD_CMD21 AD1 FBD_CMD22
CA5_A CMD15 CMD43
FBC_D23 H17 FBC_D22 FBC_CMD22 A18 FBC_CMD23 FBD_D23 AE10 FBD_D22 FBD_CMD22 AC2 FBD_CMD23
CA6_A CMD22 CMD48
FBC_D24 F10 FBC_D23 FBC_CMD23 B19 FBC_CMD24 FBD_D24 AL6 FBD_D23 FBD_CMD23 AC1 FBD_CMD24
CA7_A CMD23 CMD47
FBC_D25 G10 FBC_D24 FBC_CMD24 A19 FBC_CMD25 FBD_D25 AL3 FBD_D24 FBD_CMD24 AB1 FBD_CMD25

rS
CA8_A CMD0 CMD34
FBC_D26 C11 FBC_D25 FBC_CMD25_NC A20 FBC_CMD26 FBD_D26 AL5 FBD_D25 FBD_CMD25_NC AB4 FBD_CMD26
CA9_A CMD2 CMD32
FBC_D27 FBC_D26 FBC_CMD26_NC FBC_CMD[28..52] 42 FBD_D27 FBD_D26 FBD_CMD26_NC FBD_CMD[28..52] 44
E11 B20 CABI_A CMD10 CMD37 AL8 AB2
FBC_D28 F11 FBC_D27 FBC_CMD27 A36 FBC_CMD28 FBD_D28 AJ6 FBD_D27 FBD_CMD27 G2 FBD_CMD28
CKE_A CMD14 CMD44
FBC_D29 F13 FBC_D28 FBC_CMD28 D35 FBC_CMD29 FBD_D29 AL10 FBD_D28 FBD_CMD28 G1 FBD_CMD29
FBC_D30 F14 FBC_D29 FBC_CMD29 A35 FBC_CMD30 FBD_D30 AH6 FBD_D29 FBD_CMD29 G3 FBD_CMD30
CHB-Byte 2,3 CHB-Byte 6,7
FBC_D31 H11 FBC_D30 FBC_CMD30 A34 FBC_CMD31 FBD_D31 AH8 FBD_D30 FBD_CMD30 H1 FBD_CMD31
CA0_B CMD5 CMD29
FBC_D32 F26 FBC_D31 FBC_CMD31 B34 FBC_CMD32 FBD_D32 T5 FBD_D31 FBD_CMD31 H2 FBD_CMD32
CA1_B CMD18 CMD52
FBC_D33 E26 FBC_D32 FBC_CMD32 A33 FBC_CMD33 FBD_D33 T6 FBD_D32 FBD_CMD32 J1 FBD_CMD33
CA2_B CMD7 CMD40
FBC_D34 H26 FBC_D33 FBC_CMD33 D32 FBC_CMD34 FBD_D34 P6 FBD_D33 FBD_CMD33 K4 FBD_CMD34
CA3_B CMD20 CMD50
FBC_D35 D28 FBC_D34 FBC_CMD34 A32 FBC_CMD35 FBD_D35 T8 FBD_D34 FBD_CMD34 K1 FBD_CMD35

fo
CA4_B CMD8 CMD39
FBC_D36 C26 FBC_D35 FBC_CMD35 A31 FBC_CMD36 FBD_D36 T3 FBD_D35 FBD_CMD35 K2 FBD_CMD36
CA5_B CMD16 CMD42
FBC_D37 E29 FBC_D36 FBC_CMD36 B31 FBC_CMD37 FBD_D37 N5 FBD_D36 FBD_CMD36 L1 FBD_CMD37
CA6_B CMD21 CMD49
FBC_D38 F28 FBC_D37 FBC_CMD37 A30 FBC_CMD38 FBD_D38 N3 FBD_D37 FBD_CMD37 L2 FBD_CMD38
CA7_B CMD19 CMD51
FBC_D39 G28 FBC_D38 FBC_CMD38 D29 FBC_CMD39 FBD_D39 N6 FBD_D38 FBD_CMD38 M1 FBD_CMD39
CA8_B CMD6 CMD28
FBC_D40 F31 FBC_D39 FBC_CMD39 A29 FBC_CMD40 FBD_D40 L6 FBD_D39 FBD_CMD39 N4 FBD_CMD40
CA9_B CMD4 CMD30
FBC_D41 K29 FBC_D40 FBC_CMD40 A28 FBC_CMD41 FBD_D41 N8 FBD_D40 FBD_CMD40 N1 FBD_CMD41
CABI_B CMD9 CMD38
FBC_D42 H29 FBC_D41 FBC_CMD41 B28 FBC_CMD42 FBD_D42 K6 FBD_D41 FBD_CMD41 P1 FBD_CMD42
CKE_B CMD17 CMD41
FBC_D43 J28 FBC_D42 FBC_CMD42 A27 FBC_CMD43 FBD_D43 L9 FBD_D42 FBD_CMD42 P2 FBD_CMD43

C
FBC_D44
FBC_D45
FBC_D46
D31
G31
E32
FBC_D43
FBC_D44
FBC_D45
FBC_CMD43
FBC_CMD44
FBC_CMD45
D26
A26
A25
FBC_CMD44
FBC_CMD45
FBC_CMD46
RESET* CMD3
y
CMD31
FBD_D44
FBD_D45
FBD_D46
K3
K5
J2
FBD_D43
FBD_D44
FBD_D45
FBD_CMD43
FBD_CMD44
FBD_CMD45
R1
T4
T1
FBD_CMD44
FBD_CMD45
FBD_CMD46
C

FBC_D47 H31 FBC_D46 FBC_CMD46 B25 FBC_CMD47 FBD_D47 K8 FBD_D46 FBD_CMD46 U1 FBD_CMD47
nl
FBC_D48 F19 FBC_D47 FBC_CMD47 A24 FBC_CMD48 FBD_D48 AC7 FBD_D47 FBD_CMD47 U2 FBD_CMD48
FBC_D49 K17 FBC_D48 FBC_CMD48 D23 FBC_CMD49 FBD_D49 AE3 FBD_D48 FBD_CMD48 V1 FBD_CMD49
FBC_D50 C20 FBC_D49 FBC_CMD49 A23 FBC_CMD50 FBD_D50 AC6 FBD_D49 FBD_CMD49 W4 FBD_CMD50
FBC_D51 J19 FBC_D50 FBC_CMD50 A22 FBC_CMD51 FBD_D51 AC4 FBD_D50 FBD_CMD50 W1 FBD_CMD51
FBC_D52 E20 FBC_D51 FBC_CMD51 B22 FBC_CMD52 FBD_D52 AB3 FBD_D51 FBD_CMD51 Y1 FBD_CMD52
FBC_D53 F20 FBC_D52 FBC_CMD52 A21 FBC_CMD53 FBD_D53 AB5 FBD_D52 FBD_CMD52 Y2 FBD_CMD53
lO

FBC_D54 K20 FBC_D53 FBC_CMD53_NC D20 FBC_CMD54 FBD_D54 AB6 FBD_D53 FBD_CMD53_NC AA1 FBD_CMD54
FBC_D55 H20 FBC_D54 FBC_CMD54_NC B23 FBD_D55 AB8 FBD_D54 FBD_CMD54_NC W2
FBC_D56 G22 FBC_D55 FBC_CMD55 FBD_D56 W6 FBD_D55 FBD_CMD55
FBC_D57 F22 FBC_D56 FBD_D57 W8 FBD_D56
FBC_D58 C23 FBC_D57 FBD_D58 W5 FBD_D57
FBC_D59 D22 FBC_D58 FBD_D59 Y6 FBD_D58
FBC_D60 E23 FBC_D59 FBD_D60 W3 FBD_D59
FBC_D61 F23 FBC_D60 FBD_D61 U9 FBD_D60
FBC_D62 F25 FBC_D61 K22 FBC_CLK0_P FBD_D62 U6 FBD_D61 AC10 FBD_CLK0_P
FBC_D63 H23 FBC_D62 FBC_CLK0 J22 FBC_CLK0_N FBC_CLK0_P 41 FBD_D63 T10 FBD_D62 FBD_CLK0 AC9 FBD_CLK0_N FBD_CLK0_P 43
tia

FBC_D63 FBC_CLK0* K23 FBC_CLK1_P FBC_CLK0_N 41 FBD_D63 FBD_CLK0* AB10 FBD_CLK1_P FBD_CLK0_N 43
FBC_CLK1 J23 FBC_CLK1_N FBC_CLK1_P 42 FBD_CLK1 AB9 FBD_CLK1_N FBD_CLK1_P 44
FBC_DBI0_N G7 FBC_CLK1* FBC_CLK1_N 42 FBD_DBI0_N AM7 FBD_CLK1* FBD_CLK1_N 44
41 FBC_DBI0_N FBC_DBI1_N E3 FBC_DQM0 43 FBD_DBI0_N FBD_DBI1_N AV7 FBD_DQM0
41 FBC_DBI1_N FBC_DBI2_N G16 FBC_DQM1 K13 FBC_WCK01_P 43 FBD_DBI1_N FBD_DBI2_N AF7 FBD_DQM1 AP9 FBD_WCK01_P
41 FBC_DBI2_N FBC_DBI3_N G13 FBC_DQM2 FBC_WCK01 J13 FBC_WCK01_N FBC_WCK01_P 41 43 FBD_DBI2_N FBD_DBI3_N AJ7 FBD_DQM2 FBD_WCK01 AP10 FBD_WCK01_N FBD_WCK01_P 43
41 FBC_DBI3_N FBC_DBI4_N F29 FBC_DQM3 FBC_WCK01* K11 FBC_WCKB01_P FBC_WCK01_N 41 43 FBD_DBI3_N FBD_DBI4_N P7 FBD_DQM3 FBD_WCK01* AR9 FBD_WCKB01_P FBD_WCK01_N 43
42 FBC_DBI4_N FBC_DBI5_N F32 FBC_DQM4 FBC_WCKB01 J11 FBC_WCKB01_N FBC_WCKB01_P 41 44 FBD_DBI4_N FBD_DBI5_N L7 FBD_DQM4 FBD_WCKB01 AR10 FBD_WCKB01_N FBD_WCKB01_P 43
en

42 FBC_DBI5_N FBC_DBI6_N G19 FBC_DQM5 FBC_WCKB01* J16 FBC_WCK23_P FBC_WCKB01_N 41 44 FBD_DBI5_N FBD_DBI6_N Y7 FBD_DQM5 FBD_WCKB01* AH10 FBD_WCK23_P FBD_WCKB01_N 43
42 FBC_DBI6_N FBC_DBI7_N G25 FBC_DQM6 FBC_WCK23 K16 FBC_WCK23_N FBC_WCK23_P 41 44 FBD_DBI6_N FBD_DBI7_N U7 FBD_DQM6 FBD_WCK23 AH9 FBD_WCK23_N FBD_WCK23_P 43
42 FBC_DBI7_N FBC_DQM7 FBC_WCK23* J14 FBC_WCKB23_P FBC_WCK23_N 41 44 FBD_DBI7_N FBD_DQM7 FBD_WCK23* AJ10 FBD_WCKB23_P FBD_WCK23_N 43
FBC_WCKB23 K14 FBC_WCKB23_N FBC_WCKB23_P 41 FBD_WCKB23 AJ9 FBD_WCKB23_N FBD_WCKB23_P 43
FBC_EDC0 D7 FBC_WCKB23* K31 FBC_WCK45_P FBC_WCKB23_N 41 FBD_EDC0 AM4 FBD_WCKB23* P10 FBD_WCK45_P FBD_WCKB23_N 43
41 FBC_EDC0 FBC_EDC1 B3 FBC_DQS_WP0 FBC_WCK45 J31 FBC_WCK45_N FBC_WCK45_P 42 43 FBD_EDC0 FBD_EDC1 AV4 FBD_DQS_WP0 FBD_WCK45 P9 FBD_WCK45_N FBD_WCK45_P 44
41 FBC_EDC1 FBC_EDC2 D16 FBC_DQS_WP1 FBC_WCK45* K32 FBC_WCKB45_P FBC_WCK45_N 42 43 FBD_EDC1 FBD_EDC2 AF4 FBD_DQS_WP1 FBD_WCK45* N10 FBD_WCKB45_P FBD_WCK45_N 44
41 FBC_EDC2 FBC_EDC3 D13 FBC_DQS_WP2 FBC_WCKB45 J32 FBC_WCKB45_N FBC_WCKB45_P 42 43 FBD_EDC2 FBD_EDC3 AJ4 FBD_DQS_WP2 FBD_WCKB45 N9 FBD_WCKB45_N FBD_WCKB45_P 44
fid

41 FBC_EDC3 FBC_EDC4 C29 FBC_DQS_WP3 FBC_WCKB45* K25 FBC_WCK67_P FBC_WCKB45_N 42 43 FBD_EDC3 FBD_EDC4 P4 FBD_DQS_WP3 FBD_WCKB45* Y10 FBD_WCK67_P FBD_WCKB45_N 44
42 FBC_EDC4 FBC_EDC5 C32 FBC_DQS_WP4 FBC_WCK67 J25 FBC_WCK67_N FBC_WCK67_P 42 44 FBD_EDC4 FBD_EDC5 L4 FBD_DQS_WP4 FBD_WCK67 Y9 FBD_WCK67_N FBD_WCK67_P 44
42 FBC_EDC5 FBC_EDC6 D19 FBC_DQS_WP5 FBC_WCK67* J26 FBC_WCKB67_P FBC_WCK67_N 42 44 FBD_EDC5 FBD_EDC6 Y4 FBD_DQS_WP5 FBD_WCK67* W9 FBD_WCKB67_P FBD_WCK67_N 44
42 FBC_EDC6 FBC_EDC7 D25 FBC_DQS_WP6 FBC_WCKB67 K26 FBC_WCKB67_N FBC_WCKB67_P 42 44 FBD_EDC6 FBD_EDC7 U4 FBD_DQS_WP6 FBD_WCKB67 W10 FBD_WCKB67_N FBD_WCKB67_P 44
42 FBC_EDC7 FBC_DQS_WP7 FBC_WCKB67* FBC_WCKB67_N 42 44 FBD_EDC7 FBD_DQS_WP7 FBD_WCKB67* FBD_WCKB67_N 44

B BP32 BP48 B
BP34 GND_710 BR1 GND_0718
GND_711 GND_0719
on

BP36 BR12
BP38 GND_712 BR15 GND_0720
BP40 GND_713 +FB_PLLAVDD BR18 GND_0721 +FB_PLLAVDD
BP42 GND_714 BR2 GND_0722
BP44 GND_715 BR21 GND_0723
BP46 GND_716 L35 BR24 GND_0724 T46
GND_717 FB_PLLVDD_5 GND_0725 FB_PLLVDD_6 1U_6.3V_K_X6S_0402
OPT@

OPT@
C
1U_6.3V_K_X6S_0402

1 1
CG154

CG1735

2 2
@ GN20E-FCBGA2714_BGA2714 @ GN20E-FCBGA2714_BGA2714
FC

Under GPU
Under GPU

FBVDDQ
FBVDDQ
1

CKE_A
1

1
LC

RG206 RG207 CKE_B

10K_0402_1% 10K_0402_1% RG241 RG242
FBVDDQ FBVDDQ NON_E3@ NON_E3@ 10K_0402_1% 10K_0402_1%
NON_E3@ NON_E3@
2

FBD_CMD14
2

FBD_CMD44 FBD_CMD17
1

CKE_A CKE_B FBD_CMD41

RG71 RG72 RG239 RG240 FBD_CMD3
10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% FBD_CMD31
OPT@ OPT@ OPT@ OPT@
2

FBC_CMD14 FBC_CMD17
1

FBC_CMD44 FBC_CMD41
A A
RESET RG208 RG209
FBC_CMD3 10K_0402_1% 10K_0402_1% FBD_CMD25
FBC_CMD31 NON_E3@ NON_E3@ FBD_CMD26
FBD_CMD53
2

FBD_CMD54
1

RESET RG75 RG76

10K_0402_1% 10K_0402_1%
OPT@ OPT@ FBC_CMD25
FBC_CMD26
2

FBC_CMD53
FBC_CMD54 Security Classification LCFC Highly Confidential Information Title
Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_VRAM C/D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A2
Y550 A0

Date: Monday, November 29, 2021 Sheet 31 of 110

5 4 3 2 1
 5 4 3 2 1

Power on/off sequence

+1.8VS_AON
MVVDD_EN
2

RG94 GPIO
10K_0402_5% OPT@ +1.8VS_AON +3VS
OPT@ UG1Q
OVERT_N_NVEN 1 2 RB751V-40_SOD323-2
12/24 MISC 1 DG7
1

28 OVERT_N_NVEN
Internal Thermal Sensor

1
OVERT_N BK7 BL8 VGA_SMB_CK2
RG90 RG88
28 OVERT_N OVERT I2CS_SCL
I2CS_SDA
BL7 VGA_SMB_DA2 EC 0_0201_5% 10K_0402_5%
@ OPT@
1 TS_VREF BG8
TG5 @ I2CC_SCL PXS_PWREN_R NVVDD_EN_CNTH DG5

2
TS_VREF BM7 RG37 1 @ 2 0_0201_5% 2
I2CC_SCL BN7 I2CC_SDA 1 NVVDD_EN
D I2CC_SDA NVVDD control GPIO4_GC6_MSVDD_EN_R
RG91 1 @ 2 0_0201_5% GPIO4_GC6_MSVDD_EN_RR 3 NVVDD_EN 102 D

I2CB_SCL

1
BN8 LBAT54AWT1G_SOT323-3
I2CB_SCL BM8 I2CB_SDA I2CB_SCL 46
OPT@ RG89
I2CB_SDA I2CB_SDA 46 DDS panel +1.8VS_AON 100K_0402_1%
@
BR8 I2CB_SCL
RG13 1 OPT@ 2 2.2K_0402_5%

2
THERMDN I2CB_SDA
GPIO29_NVVDD_EN RG16 1 OPT@ 2 2.2K_0402_5%
BP8 RG691 1 @ 2 100K_0201_5%
THERMDP GPIO4_GC6_MSVDD_EN
NVVDD_PSI RG243 1 OPT@ 2 10K_0201_5%
RG20 1 @ 2 10K_0201_5%
VGA_ALERT_N
RG14 1 OPT@ 2 10K_0201_5%
BP2 NVVDD_PWM_VID VGA_AC_DET_R
FB_GC6_EN ADC_MUX_SEL RG686 1 OPT@ 2 10K_0201_5%
GPIO0 BN3 NVVDD_PWM_VID 102
GPU_EVENT_N_R FBVDDQ_SEL RG125 1 OPT@ 2 2.2K_0402_5%
GPIO1 BN2 RG26 1 @ 2 10K_0201_5%
ADC_IN_P 1 2 0_0201_5% ADC_IN_P_GPU BP10 GPIO2 BM4 GPU_MUX_CNTL_RC
RG689 @
105 ADC_IN_P ADC_IN_N 1 2 0_0201_5% ADC_IN_N_GPU BR10 ADC_IN GPIO3 BM3 GPIO4_GC6_MSVDD_EN
RG690 @
105 ADC_IN_N ADC_IN* GPIO4 BM2
GPIO5 BM1 NVVDD_PSI
GPIO6 BL1 NVVDD_PSI 102
GPIO7 BK6 FBVDDQ_SEL GPU_EDP_PWM 45 GPU_MUX_CNTL_RC 1 OPT@ 2 10K_0201_5%
RG200
GPIO8 BK5 VGA_ALERT_N FBVDDQ_SEL 107
GPIO9 BK4 MEM_VREF_CTL VGA_ALERT_N 12 FBVDDQ_SEL
RG27 1 OPT@ 2 10K_0201_5% 0.95V_MAIN_EN

T
1 PAD JTAG_TCK BP25 GPIO10 BK3 MEM_VREF_CTL 37,39,41,43,50
TG1 @ JTAG_TMS VGA_AC_DET_R MEM_VREF_CTL
1 PAD BN25 JTAG_TCK GPIO11 BK2 GPU_EDP_ENVDD 45 1 OPT@ 2 100K_0201_5%
TG6 @ JTAG_TDI iGPU_EDP_ENBKL RG122
TG7 @ 1 PAD BT25 JTAG_TMS GPIO12 BK1 +1.8VS_AON +3VS
1 PAD JTAG_TDO BR25 JTAG_TDI GPIO13 BJ6 IFPA_HPD iGPU_EDP_ENBKL 46 GPU_EDP_ENBKL 1 OPT@ 2 100K_0201_5%
TG8 @ RG197
JTAG_TRST BM25 JTAG_TDO GPIO14 BJ5 IFPB_HPD IFPA_HPD 55
PWM_SW_SELECT_R GPU_EDP_PWM PXS_PWREN_R DG18
JTAG_TRST* GPIO15 BJ4 IFPB_HPD 61
GPU_EDP_HPD RG204 1 @ 2 0_0402_5% RG195 1 OPT@ 2 100K_0201_5% 1 2
GPIO16 BJ3 PWM_SW_SELECT 46
GPU_EDP_HPD 45 GPU_EDP_ENVDD
2

2
GPIO17 BJ2 RG196 1 OPT@ 2 10K_0201_5% RB751V-40_SOD323-2
NVJTAG_SEL BL25 GPIO18 BJ1
RG24 OPT@ RG667 RG668
NVJTAG_SEL GPIO19 BH1 iGPU_EDP_ENBKL 1 @ 2 100K_0201_5%

M
10K_0201_5% RG199 10K_0402_5% 1/16W_8.2K_1%_0402
GPIO20 BG7 @ OPT@
GPIO21 BG6 ADC_MUX_SEL_R GPU_EDP_ENBKL 45 PWM_SW_SELECT NVVDD_EN
OPT@ RG49 1 @ 2 0_0402_5% RG201 1 OPT@ 2 10K_0201_5% RG1200 1 @ 2 0_0402_5%
1

1
ADC_MUX_SEL 105
2

GPIO22 BG5 DG19

GPIO23 BG4 GPIO4_GC6_MSVDD_EN_R 1 GC6_MSVDD_EN_RR
RG119 RG666 OPT@2 0_0402_5% 2
GPIO24 BG3 FBVDDQ_PSI 1 0.95V_MAIN_EN_R 1 2 0_0402_5%
10K_0201_5% GPIO26_ROM_WP_R NVVDD_PWRGD NVVDD_PWRGD_R RG669 @
GPIO25 BG2 FBVDDQ_PSI 107 1 2 0_0402_5% 3 0.95V_MAIN_EN 32,103
IFPC_HPD RG670 @
50,102 NVVDD_PWRGD

1
OPT@ GPIO26 BG1
1

GPIO27 BF1 IFPC_HPD 50

LBAT54AWT1G_SOT323-3 RG671
GPIO28 BF2 GPIO29_NVVDD_EN 1 OPT@ 2 10K_0402_5%
+3VS RG672 OPT@ 10K_0402_5%
GPIO29 BF3 @
GPIO30 BF4

2
JTAG_SEL GPIO31 BF5
GPIO32 BF6 GPIO26_ROM_WP_R GPIO26_ROM_WP
RG1327 1 OPT@2 0_0402_5%

rS
PD No JTAG Dongle
GPIO33 BF7 GPIO26_ROM_WP 33
PU JTAG Dongle
GPIO34 BF8 RG1328 1 @ 2 0_0402_5% GPIO26_FP_FUSE
GPIO35 GPIO26_FP_FUSE 35

@ GN20E-FCBGA2714_BGA2714

GPU_MUX_CNTL_RC
RG1357 1 @ 2 0_0402_5%
GPU_MUX_CNTL 46
1
FBVDDQ_PWR_EN
@
CG1782
0.1U_25V_K_X5R_0201
2 UG12
FB_GC6_EN_R 1 2 0_0402_5% FB_GC6_EN_RR 1 4 FBVDDQ_PWR_EN
0.95VGS_PG RG35 @ 0.95VGS_PG_R
1 IN B OUT Y FBVDDQ_PWR_EN 107
NVVDD_PWRGDRG153 OPT@2 0_0402_5% 2
RG198 1 @ 2 0_0402_5% IN A
3 5

fo
GND Vcc +3VALW_SYS
Modify for fine tune sequence

1U_6.3V_K_X6S_0402
1 MC74VHC1G32DFT2G_SC70-5 1
CG156 OPT@
CG543
@ 0.1u_0201_10V6K
2 2 OPT@

C +1.8VS_AON C
y
2

RG188 +3VS

2
0_0402_5% +1.8VS_AON
PLT_RST_VGA_N VGA_PWRGD
1

RG30
nl
10K_0402_5%
OPT@
+1.8VS_AON +1.8VS_AON FBVDDQ_PWROK_R DG6

1
1 2 0_0402_5% 2
EC_SMB_CK2_PWR

+1.8VS_AON +3VS RG154 @

107 FBVDDQ_PWROK 1
1 2 0_0402_5% 0.95VGS_PG_RR 3 VGA_PWRGD 12,28
RG155 @
103 0.95VGS_PG
2

RG192 RG191 10K_0402_5%

2 1 1 LBAT54AWT1G_SOT323-3
@ @ CG2147 OPT@
OPT@
2

0_0402_5% 0.01U_25V_K_X5R_0201
1

RG4 RG5 RG189 RG184 2

lO

2.2K_0402_5% 2.2K_0402_5% 10K_0402_5% RG185 2.2K_0402_5% RG186 RG187

OPT@ OPT@ @ 2.2K_0402_5% OPT@ 2.2K_0402_5% 2.2K_0402_5%
5

V0.3 OPT@ OPT@ OPT@

1

1
G2

G2
1

VGA_SMB_CK2 4 3 I2CC_SCL 4 3
S2 D2 EC_SMB_CK2 45,76,79,90,102 S2 D2 NVDD_SCL 102,105

EC_SMB_DA2_PWR
QG3B QG35B
PJT7838_SOT363-6 PJT7838_SOT363-6
OPT@ OPT@
2

2
G1

G1

VGA_SMB_DA2 1 6 I2CC_SDA 1 6
S1 D1 EC_SMB_DA2 45,76,79,90,102 S1 D1 NVDD_SDA 102,105

Vgs(th)≤1.0V Vgs(th)≤1.0V
QG3A QG35A
tia

PJT7838_SOT363-6 PJT7838_SOT363-6 NOTE：

OPT@ OPT@
For AMD平平平平平MS，需需DG14/RG1366, 不需需RG1365, 平平平平pull up

+3VALW_SYS

RG1366 1 @ 2 0_0402_5%

2
VGA_ALERT_N @
DG3 2 1 RB751V-40_SOD323-2 +3VALW_SYS RG1367
en

DG14
10K_0402_5%
PXS_PWREN 2 @
10 PXS_PWREN 1 PXS_PWREN_R
VGA_AC_DET_R EC_PXS_PWREN
1

PXS_PWREN_R 35
2

DG1 2 1 RB751V-40_SOD323-2 3
VGA_AC_DET 79 +3VALW_SYS 79 EC_PXS_PWREN
RG39
OPT@ 10K_0402_5%
BAT54AW_SOT323-3
1

OPT@ @
1
2

RG1368
RG38 FB_GC6_EN_R 100K_0402_5%
10K_0402_5% RG40 1 @ 2 0_0402_5%
PCH_FB_GC6_EN 11 @
2

OPT@
1

D
FB_GC6_EN_N 5 QG7B
G LBSS138DW1T1G_SOT363-6
6

D OPT@
S
4

FB_GC6_EN 2
fid

QG7A
G LBSS138DW1T1G_SOT363-6
S OPT@
1
2

RG41
+3VS +3VALW_SYS 10K_0402_5%
OPT@
B B
1
1

RG23 RG1358
@ 0_0402_5%
0_0402_5% OPT@
+3VS
2

on
VGA_RST_PWR

1 +1.8VS_AON
2

CG51
RG95 0.1u_0201_10V6K
Discharge
2

10K_0402_5% 2 OPT@
@ RG36 +3VS
10K_0402_5%
1

OPT@
5

PLT_RST_N UG3
1

1
P

17,52,63,71,73,76,79 PLT_RST_N B VGA_RST_N PLT_RST_VGA_N +3VS

4 RG1261 @ 2 0_0402_5% RG1329
2 Y PLT_RST_VGA_N 28
10K_0402_5%
G

12 PXS_RST_N A OPT@
MC74VHC1G09DFT2G_SC70-5
3

1
2

OPT@
1

RG1330
C

RG127 10K_0402_5%
GPIO4_GC6_MSVDD_EN_R NVVDD Discharge
RG96 100K_0402_5% OPT@ FBVDDQ Discharge +0.95VGS Discharge +0.95VGS
100K_0402_5% OPT@
1

OPT@ D
2

GPIO29_NVVDD_EN 1 2 0_0402_5% GPIO4_GC6_MSVDD_EN_N 5

RG244 @ QG124B
G LBSS138DW1T1G_SOT363-6 NVVDD
6

D OPT@ FBVDDQ
GPIO4_GC6_MSVDD_EN S
2 0_0402_5% GPIO4_GC6_MSVDD_R_EN 2
4

1
RG1336 1 @ QG124A
G LBSS138DW1T1G_SOT363-6 RG81 RG85
S OPT@ 1/8W_5.11_1%_0805 1/8W_5.11_1%_0805
1
2

OPT@ OPT@
RG1332 RG29
2

2
1

10K_0402_5% 470_0603_5%
@ RG84 RG59 @ +5VALW
1/8W_5.11_1%_0805 1/8W_5.11_1%_0805
1

FBVDDQ_DIS 2

+0.95VGS_DIS
FC

@ @ +5VALW
1
2

RG80
2

+5VALW 47K_0402_5%
1

RG34 OPT@
NVVDD_DIS
47K_0402_5%
D
2
2

@ 0.95V_MAIN_EN_N
RG60 2 QG15
1

47K_0402_5% D G AO3402_SOT-23-3
FBVDDQ_PWR_EN_N
1

@ 5 QG6B OPT@
S

G LBSS138DW1T1G_SOT363-6
D
1

D @ D
NOTE： NVVDD_EN_N FBVDDQ_PWR_EN S
4

2 2 2
AMD platform and support MS:PCH_GPU_EVENT_N pull up with always power---GPU_EVENT function reserved G
QG8 QG6A
32,103 0.95V_MAIN_EN
QG14 Vgs(th)≤1.5V
AO3402_SOT-23-3 G LBSS138DW1T1G_SOT363-6 G LBSS139WT1G_SC70-3
1

@ S @ S OPT@
1

3
1

D RG82
NVVDD_EN 2 QG9
Reserve 100K_0402_5% Vgs(th)≤1.5V
3

G LBSS139WT1G_SC70-3 @
+1.8VS_AON S @
3

+3VALW_SYS +3VALW_SYS
1
LC

RG43
10K_0402_5%
Reserve
@
2
1

RG156 RG1365 GPU_EVENT_N_R

10K_0402_5% 10K_0402_5%
@ @
2

QG13B
D2

GPU_EVENT_N 5 PJT7838_SOT363-6
G2
S2
6

QG13A @
D1

A PCH_GPU_EVENT_N 2 A
12 PCH_GPU_EVENT_N G1 PJT7838_SOT363-6
S1
1

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GPIO I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A0 A0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, November 29, 2021 Sheet 32 of 110
5 4 3 2 1
 5 4 3 2 1

+1.8VS_AON +1.8VS_AON

EEPROM

10U_6.3V_M_X6S_0603
2

2
2 1
RG245 RG141
UG1W 10K_0402_5% 10K_0402_5% CG145
14/24 MISC 2 @ OPT@ 0.1u_0201_10V6K
1 2

@
OPT@

1
UG10

CG146
D D
STRAP0 BM5 BP7 ROM_CS_N ROM_CS_N RG138 2 OPT@ 1 33_0402_5% ROM_CS_N_R 1 8
STRAP1 BN5 STRAP0 ROM_CS* /CS VCC
STRAP2 BP4 STRAP1 ROM_SI BR7 ROM_SI ROM_SO RG137 1 @ 2 0_0402_5% ROM_SO_R 2 7
STRAP3 BP3 STRAP2 ROM_SO BT8 ROM_SO DO(IO1) /HOLD(IO3)
STRAP4 BR3 STRAP3 ROM_SCLK BT7 ROM_SCLK RG1199 1 @ 2 0_0402_5% ROM_WP 3 6 ROM_SCLK_R RG139 2 OPT@ 1 33_0402_5% ROM_SCLK
STRAP4 32 GPIO26_ROM_WP /WP(IO2) CLK
STRAP5 BR4
STRAP5

2
4 5 ROM_SI_R RG140 2 OPT@ 1 33_0402_5% ROM_SI
GND DI(IO0)

OPT@
RG249
10K_0402_5%
W25Q16JWSNIQ_SOIC8

T
OPT@

M
@ GN20E-FCBGA2714_BGA2714
VRAMCFG

rS
GPU VRAM FB Memory (GDDR6) RAMCFG[2:0] STRAP0 STRAP1 STRAP2

+1.8VS_AON
Samsung 8Gb K4Z80325BC-HC14 0(0x0000) L L L
GN20x-E7
RAMCFG Samsung 16Gb K4ZAF325BM-HC 14 9(0x0009) L M L

fo
1

GPU VRAM FB Memory (GDDR6) RAMCFG[2:0] STRAP0 STRAP1 STRAP2

RG104 RG101 RG106
1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201
@ @ @ Samsung 8Gb K4Z80325BC-HC14 0(0x0000) L L L
2

STRAP0 GN20x-E5
STRAP1 Micron 8Gb MT61K256M32JE-14:A 1(0x0001) H L L
GN20x-E3
C
STRAP2

Hynix 8Gb
y
H56C8H24AIR-S2C 2(0x0002) L H L
C
1

nl
RG102 RG100 RG105
1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201
@ @ @
2

GPU VRAM FB Memory (GDDR6) RAMCFG[2:0] STRAP0 STRAP1 STRAP2

lO

Hynix 16Gb H56G42AS4DX014 8(0x0008) M L L

GN20x-E6 Samsung 16Gb K4ZAF325BM-HC16 6(0x0006) L H H

Hynix 8Gb H56G32CS4DX005 5(0x0005) H L H

tia

+1.8VS_AON

VGA_DEVICE
en

1:SMB_ALT_ADDR ENABLE
0:SMB_ALT_ADDR DISABLE
VGA_DEVICE E3/E5/E7
1

1:DEVID_SEL REBRAND
RG110 RG108 RG112 0:DEVID_SEL ORIGNAL
1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201 STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE
OPT@ @ OPT@
1:PCIE_CFG LOW POWER
fid
2

STRAP3 H L H 0 1 0 1 0:PCIE_CFG HIGH POWER

STRAP4
STRAP5
1:VGA_DEVICE ENABLE
0:VGA_DEVICE DISABLE
1

B B
RG109 RG107 RG111
on

1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201

@ OPT@ @
2

C
FC

+1.8VS_AON

FS_OVERT
1

1
LC

RG115 RG114 RG118

1/20W_100K_1%_0201 10K_0201_1% 1/20W_100K_1%_0201
@ @ OPT@
2

ROM_SI
ROM_SO
ROM_SCLK FS_OVERT
GPU ROM_SO ROM_SI ROM_SCLK FS_OVERT
1

RG116 RG113 RG117

1/20W_100K_1%_0201 10K_0201_1% 1/20W_100K_1%_0201 GN20x L L H ENABLE
OPT@ OPT@ @
A A
2

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_NVHS I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A2
Y550 A0

Date: Monday, November 29, 2021 Sheet 33 of 110

5 4 3 2 1
 5 4 3 2 1

NVVDD
Under GPU
122A place 4x330uF(POSCAP)
PCB CO-LAYOUT
*

330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M
1.330uF x 1 + 47uF x 8 + 1uF x 4;
1 1 1 1
2.330uF(NV POSCAP) x 1 + 47uF x 8 + 1uF x 4;
+ + + + 3.330uF x 1 + 10uF x 3 + 4.7uF x 3 + 1uF x 4;
4.330uF x 1 + 47uF x 4 + 10uF x 4;
2 2 2 2

@
CG71

CG675
CG5

CG6
NVVDD
CRB place 27x47uF(0805)
LCFC place 58x22uF(0603)

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603
D D
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@ @ @ @ @ @

CG1580

CG1581

CG1582

CG1584

CG1585

CG1586

CG1587

CG1588

CG1589

CG1590

CG1591

CG1593

CG1594

CG1596

CG1597

CG1598

CG1599
T
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

UG1K
11/24 XVDD
NVVDD UG1M NVVDD
17/24 VDD_1/2 CONFIGURABLE NVVDD

M
122A AB14 VDD_001 VDD_076
AF29 NVVDD
POWER CHANNELS
NVVDD NVVDD UG1L NVVDD
AB15 AF30 (NC on substrate) 22/24 VDDMS
AB16 VDD_002 VDD_077 AF31

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603
AB17 VDD_003 VDD_078 AF32 AY27 AB13
AB18 VDD_004 VDD_079 AF33 AY1 BT52 AY28 VDDMS_97 VDDMS_1 AB44 NVVDD UG1N NVVDD
AB19 VDD_005 VDD_080 AF34 AY2 XVDD_1 XVDD_88 BR52 AY29 VDDMS_98 VDDMS_2 AD13
VDD_006 VDD_081 XVDD_2 XVDD_89 VDDMS_99 VDDMS_3 18/24 VDD_2/2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AB20 AF35 AY3 BN50 AY30 AD44
AB21 VDD_007 VDD_082 AF36 AY4 XVDD_3 XVDD_90 BM49 AY31 VDDMS_100 VDDMS_4 AF13 AK38 AP39 @ @ @ @ @
VDD_008 VDD_083 XVDD_4 XVDD_91 VDDMS_101 VDDMS_5 VDD_145 VDD_206

CG1600

CG1601

CG1602

CG1603

CG1604

CG1605

CG1607

CG1608

CG1609

CG1611

CG1612

CG1613

CG1614

CG1615

CG1616

CG1617

CG1618

CG1619
AB22 AF37 AY5 BL48 AY32 AF44 AK39 AP40

rS
AB23 VDD_009 VDD_084 AF38 AY6 XVDD_5 XVDD_92 BK47 AY33 VDDMS_102 VDDMS_6 AH13 AK40 VDD_146 VDD_207 AP41 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AB24 VDD_010 VDD_085 AF39 AY7 XVDD_6 XVDD_93 BJ46 AY34 VDDMS_103 VDDMS_7 AH44 AK41 VDD_147 VDD_208 AP42
AB25 VDD_011 VDD_086 AF40 AY8 XVDD_7 XVDD_94 AY35 VDDMS_104 VDDMS_8 AK13 AK42 VDD_148 VDD_209 AP43
AB26 VDD_012 VDD_087 AF41 AY9 XVDD_8 AY36 VDDMS_105 VDDMS_9 AK44 AK43 VDD_149 VDD_210 P14
AB27 VDD_013 VDD_088 AF42 AY10 XVDD_9 BT54 AY37 VDDMS_106 VDDMS_10 AM13 AM14 VDD_150 VDD_211 P15
AB28 VDD_014 VDD_089 AF43 AY11 XVDD_10 XVDD_95 BR53 AY38 VDDMS_107 VDDMS_11 AM44 AM15 VDD_151 VDD_212 P16
AB29 VDD_015 VDD_090 AH14 XVDD_11 XVDD_96 BP52 AY39 VDDMS_108 VDDMS_12 AP13 AM16 VDD_152 VDD_213 P17
AB30 VDD_016 VDD_091 AH15 XVDD_97 BN51 AY40 VDDMS_109 VDDMS_13 AP44 AM17 VDD_153 VDD_214 P18 NVVDD
AB31 VDD_017 VDD_092 AH16 BA1 XVDD_98 BM50 AY41 VDDMS_110 VDDMS_14 AT13 AM18 VDD_154 VDD_215 P19
AB32 VDD_018 VDD_093 AH17 BA2 XVDD_12 XVDD_99 BL49 AY42 VDDMS_111 VDDMS_15 AT14 AM19 VDD_155 VDD_216 P20
AB33 VDD_019 VDD_094 AH18 BA3 XVDD_13 XVDD_100 BJ47 AY43 VDDMS_112 VDDMS_16 AT15 AM20 VDD_156 VDD_217 P21
AB34 VDD_020 VDD_095 AH19 BA4 XVDD_14 XVDD_101 BH46 AY44 VDDMS_113 VDDMS_17 AT16 AM21 VDD_157 VDD_218 P22

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603
AB35 VDD_021 VDD_096 AH20 BA5 XVDD_15 XVDD_102 BG45 BA13 VDDMS_114 VDDMS_18 AT17 AM22 VDD_158 VDD_219 P23

fo
AB36 VDD_022 VDD_097 AH21 BA6 XVDD_16 XVDD_103 BF44 BA44 VDDMS_115 VDDMS_19 AT18 AM23 VDD_159 VDD_220 P24
AB37 VDD_023 VDD_098 AH22 BA7 XVDD_17 XVDD_104 BB13 VDDMS_116 VDDMS_20 AT19 AM24 VDD_160 VDD_221 P25
VDD_024 VDD_099 XVDD_18 VDDMS_117 VDDMS_21 VDD_161 VDD_222 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AB38 AH23 BA8 BB14 AT20 AM25 P26
AB39 VDD_025 VDD_100 AH24 BA9 XVDD_19 BT55 BB15 VDDMS_118 VDDMS_22 AT21 AM26 VDD_162 VDD_223 P27 @ @ @ @ @ @
VDD_026 VDD_101 XVDD_20 XVDD_105 VDDMS_119 VDDMS_23 VDD_163 VDD_224

CG1620

CG1621

CG1622

CG1623

CG1624

CG1625

CG1626

CG1627

CG1628

CG1629

CG1630

CG1631

CG1632

CG1633

CG1635

CG1636

CG1637
AB40 AH25 BA10 BR54 BB16 AT22 AM27 P28
AB41 VDD_027 VDD_102 AH26 BA11 XVDD_21 XVDD_106 BP53 BB17 VDDMS_120 VDDMS_24 AT23 AM28 VDD_164 VDD_225 P29 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AB42 VDD_028 VDD_103 AH27 XVDD_22 XVDD_107 BN52 BB18 VDDMS_121 VDDMS_25 AT24 AM29 VDD_165 VDD_226 P30
AB43 VDD_029 VDD_104 AH28 XVDD_108 BL50 BB19 VDDMS_122 VDDMS_26 AT25 AM30 VDD_166 VDD_227 P31
AD14 VDD_030 VDD_105 AH29 BB2 XVDD_109 BK49 BB20 VDDMS_123 VDDMS_27 AT26 AM31 VDD_167 VDD_228 P32
AD15 VDD_031 VDD_106 AH30 BB4 XVDD_23 XVDD_110 BJ48 BB21 VDDMS_124 VDDMS_28 AT27 AM32 VDD_168 VDD_229 P33
AD16 VDD_032 VDD_107 AH31 BB6 XVDD_24 XVDD_111 BH47 BB22 VDDMS_125 VDDMS_29 AT28 AM33 VDD_169 VDD_230 P34
AD17 VDD_033 VDD_108 AH32 BB8 XVDD_25 XVDD_112 BG46 BB23 VDDMS_126 VDDMS_30 AT29 AM34 VDD_170 VDD_231 P35

C
AD18
AD19
AD20
AD21
AD22
VDD_034
VDD_035
VDD_036
VDD_037
VDD_038
VDD_109
VDD_110
VDD_111
VDD_112
VDD_113
AH33
AH34
AH35
AH36
AH37
BB10

BC1
BC2
XVDD_26
XVDD_27

XVDD_28
XVDD_113

XVDD_114
XVDD_115
BR55
BP54
BN53
BB24
BB25
BB26
BB27
BB28
VDDMS_127
VDDMS_128
VDDMS_129
VDDMS_130
VDDMS_131
VDDMS_31
VDDMS_32
VDDMS_33
VDDMS_34
VDDMS_35
AT30
AT31
AT32
AT33
AT34
AM35
AM36
AM37
AM38
AM39
y
VDD_171
VDD_172
VDD_173
VDD_174
VDD_175
VDD_232
VDD_233
VDD_234
VDD_235
VDD_236
P36
P37
P38
P39
P40
NVVDD
place 30x10uF(0603)
C

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603
VDD_039 VDD_114 XVDD_29 XVDD_116 VDDMS_132 VDDMS_36 VDD_176 VDD_237
nl
AD23 AH38 BC3 BM52 BB29 AT35 AM40 P41 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AD24 VDD_040 VDD_115 AH39 BC4 XVDD_30 XVDD_117 BL51 BB30 VDDMS_133 VDDMS_37 AT36 AM41 VDD_177 VDD_238 P42
AD25 VDD_041 VDD_116 AH40 BC5 XVDD_31 XVDD_118 BK50 BB31 VDDMS_134 VDDMS_38 AT37 AM42 VDD_178 VDD_239 P43
AD26 VDD_042 VDD_117 AH41 BC6 XVDD_32 XVDD_119 BJ49 BB32 VDDMS_135 VDDMS_39 AT38 AM43 VDD_179 VDD_240 T14
AD27 VDD_043 VDD_118 AH42 BC7 XVDD_33 XVDD_120 BG47 BB33 VDDMS_136 VDDMS_40 AT39 AP14 VDD_180 VDD_241 T15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VDD_044 VDD_119 XVDD_34 XVDD_121 VDDMS_137 VDDMS_41 VDD_181 VDD_242

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG28

CG79

CG82

CG420

CG416

CG417

CG421

CG415

CG419

CG418

CG29

CG37

CG65

CG66

CG67
@

@
AD28 AH43 BC8 BF46 BB34 AT40 AP15 T16
AD29 VDD_045 VDD_120 AK14 BC9 XVDD_35 XVDD_122 BB35 VDDMS_138 VDDMS_42 AT41 AP16 VDD_182 VDD_243 T17
AD30 VDD_046 VDD_121 AK15 BC10 XVDD_36 BB36 VDDMS_139 VDDMS_43 AT42 AP17 VDD_183 VDD_244 T18
AD31 VDD_047 VDD_122 AK16 BC11 XVDD_37 BR56 BB37 VDDMS_140 VDDMS_44 AT43 AP18 VDD_184 VDD_245 T19
lO

AD32 VDD_048 VDD_123 AK17 XVDD_38 XVDD_123 BP55 BB38 VDDMS_141 VDDMS_45 AT44 AP19 VDD_185 VDD_246 T20
AD33 VDD_049 VDD_124 AK18 XVDD_124 BN54 BB39 VDDMS_142 VDDMS_46 AU13 AP20 VDD_186 VDD_247 T21
AD34 VDD_050 VDD_125 AK19 BD1 XVDD_125 BM53 BB40 VDDMS_143 VDDMS_47 AU44 AP21 VDD_187 VDD_248 T22
AD35 VDD_051 VDD_126 AK20 BD2 XVDD_39 XVDD_126 BK51 BB41 VDDMS_144 VDDMS_48 AV13 AP22 VDD_188 VDD_249 T23 NVVDD
AD36 VDD_052 VDD_127 AK21 BD3 XVDD_40 XVDD_127 BJ50 BB42 VDDMS_145 VDDMS_49 AV14 AP23 VDD_189 VDD_250 T24
AD37 VDD_053 VDD_128 AK22 BD4 XVDD_41 XVDD_128 BH49 BB43 VDDMS_146 VDDMS_50 AV15 AP24 VDD_190 VDD_251 T25
AD38 VDD_054 VDD_129 AK23 BD5 XVDD_42 XVDD_129 BG48 BB44 VDDMS_147 VDDMS_51 AV16 AP25 VDD_191 VDD_252 T26

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603
AD39 VDD_055 VDD_130 AK24 BD6 XVDD_43 XVDD_130 BF47 BC13 VDDMS_148 VDDMS_52 AV17 AP26 VDD_192 VDD_253 T27
VDD_056 VDD_131 XVDD_44 XVDD_131 VDDMS_149 VDDMS_53 VDD_193 VDD_254 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AD40 AK25 BD7 BC44 AV18 AP27 T28
AD41 VDD_057 VDD_132 AK26 BD8 XVDD_45 BD13 VDDMS_150 VDDMS_54 AV19 AP28 VDD_194 VDD_255 Y34
AD42 VDD_058 VDD_133 AK27 BD9 XVDD_46 BP56 BD14 VDDMS_151 VDDMS_55 AV20 AP29 VDD_195 VDD_321 Y35
AD43 VDD_059 VDD_134 AK28 BD10 XVDD_47 XVDD_132 BN55 BD17 VDDMS_152 VDDMS_56 AV21 AP30 VDD_196 VDD_322 Y36 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VDD_060 VDD_135 XVDD_48 XVDD_133 VDDMS_153 VDDMS_57 VDD_197 VDD_323

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG69

CG70

CG676

CG677

CG678

CG679

CG680

CG681

CG682

CG683

CG684

CG685

CG686

CG687

CG688
@

@
AF14 AK29 BD11 BM54 BD18 AV22 AP31 Y37
VDD_061 VDD_136 XVDD_49 XVDD_134 VDDMS_154 VDDMS_58 VDD_198 VDD_324
tia

AF15 AK30 BL53 BD21 AV23 AP32 Y38

AF16 VDD_062 VDD_137 AK31 +0.95VGS XVDD_135 BK52 BD22 VDDMS_155 VDDMS_59 AV24 AP33 VDD_199 VDD_325 Y39
AF17 VDD_063 VDD_138 AK32 XVDD_136 BJ51 BD25 VDDMS_156 VDDMS_60 AV25 AP34 VDD_200 VDD_326 Y40
AF18 VDD_064 VDD_139 AK33 XVDD_137 BF48 BD26 VDDMS_157 VDDMS_61 AV26 AP35 VDD_201 VDD_327 Y41
AF19 VDD_065
VDD_066
VDD_140
VDD_141
AK34 2.9A BT26 XVDD_50
XVDD_138
XVDD_139
BE47 BD28 VDDMS_158
VDDMS_159
VDDMS_62
VDDMS_63
AV27 AP36 VDD_202
VDD_203
VDD_328
VDD_329
Y42
AF20 AK35 BR26 BD46 BD29 AV28 AP37 Y43
AF21 VDD_067 VDD_142 AK36 BP26 XVDD_51 XVDD_140 BD31 VDDMS_160 VDDMS_64 AV29 AP38 VDD_204 VDD_330
AF22 VDD_068 VDD_143 AK37 BN26 XVDD_52 BD32 VDDMS_161 VDDMS_65 AV30 VDD_205 NVVDD
AF23 VDD_069 VDD_144 V29 BM26 XVDD_53 BD35 VDDMS_162 VDDMS_66 AV31
VDD_070 VDD_286 XVDD_54 VDDMS_163 VDDMS_67 place 5x4.7uF(0603)
AF24 V30 BL26 BD36 AV32
AF25 VDD_071 VDD_287 V31 BK26 XVDD_55 BD39 VDDMS_164 VDDMS_68 AV33 BT48
4.7U_6.3V_K_X6S_0603

4.7U_6.3V_K_X6S_0603

4.7U_6.3V_K_X6S_0603

4.7U_6.3V_K_X6S_0603

4.7U_6.3V_K_X6S_0603
AF26 VDD_072 VDD_288 V32 BJ26 XVDD_56 BD40 VDDMS_165 VDDMS_69 AV34 VDD_SENSE BR48 NVVDD_VDD_SENSE 102
en

AF27 VDD_073 VDD_289 V33 BH26 XVDD_57 BD43 VDDMS_166 VDDMS_70 AV35 GND_SENSE NVVDD_VSS_SENSE 102
AF28 VDD_074 VDD_290 V34 BG26 XVDD_58 BD44 VDDMS_167 VDDMS_71 AV36
VDD_075 VDD_291 XVDD_59 VDDMS_168 VDDMS_72 trace width: 8-10mils 1 1 1 1 1
T29 V35 BF26 N13 AV37 @ GN20E-FCBGA2714_BGA2714
T30 VDD_256 VDD_292 V36 XVDD_60 N15 VDDMS_169 VDDMS_73 AV38
T31 VDD_257 VDD_293 V37 N17 VDDMS_170 VDDMS_74 AV39
VDD_258 VDD_294 VDDMS_171 VDDMS_75 2 2 2 2 2
OPT@

OPT@
@

T32 V38 BR27 N19 AV40 @

VDD_259 VDD_295 XVDD_61 VDDMS_172 VDDMS_76
CG719

CG720

CG721

CG722

CG723

T33 V39 BN27 N21 AV41

T34 VDD_260 VDD_296 V40 BL27 XVDD_62 N23 VDDMS_173 VDDMS_77 AV42
T35 VDD_261 VDD_297 V41 BJ27 XVDD_63 N25 VDDMS_174 VDDMS_78 AV43
T36 VDD_262 VDD_298 V42 BG27 XVDD_64 N27 VDDMS_175 VDDMS_79 AV44
T37 VDD_263 VDD_299 V43 XVDD_65 N30 VDDMS_176 VDDMS_80 AW13
T38 VDD_264 VDD_300 Y14 N32 VDDMS_177 VDDMS_81 AW44
fid

T39 VDD_265 VDD_301 Y15 BT28 N34 VDDMS_178 VDDMS_82 AY13

T40 VDD_266 VDD_302 Y16 BR28 XVDD_66 N36 VDDMS_179 VDDMS_83 AY14 NVVDD
T41 VDD_267 VDD_303 Y17 BP28 XVDD_67 N38 VDDMS_180 VDDMS_84 AY15
VDD_268 VDD_304 XVDD_68 VDDMS_181 VDDMS_85 place 80x1uF(0402)
B T42 Y18 BN28 N40 AY16 B
T43 VDD_269 VDD_305 Y19 BM28 XVDD_69 N42 VDDMS_182 VDDMS_86 AY17
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
V14 VDD_270 VDD_306 Y20 BL28 XVDD_70 N44 VDDMS_183 VDDMS_87 AY18
V15 VDD_271 VDD_307 Y21 BK28 XVDD_71 P13 VDDMS_184 VDDMS_88 AY19
V16 VDD_272 VDD_308 Y22 BJ28 XVDD_72 P44 VDDMS_185 VDDMS_89 AY20
VDD_273 VDD_309 XVDD_73 VDDMS_186 VDDMS_90 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG457 @

V17 Y23 BH28 T13 AY21

VDD_274 VDD_310 XVDD_74 VDDMS_187 VDDMS_91
CG528 @

CG458 @

CG454 @

CG452 @

CG456 @

CG455 @

CG475 @
V18 Y24 BG28 T44 AY22
VDD_275 VDD_311 XVDD_75 VDDMS_188 VDDMS_92
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG471

CG465

CG466

CG467

CG476

CG478

CG496

CG451

CG450

CG453

CG732

CG733
@

V19 Y25 BF28 V13 AY23

on

V20 VDD_276 VDD_312 Y26 XVDD_76 V44 VDDMS_189 VDDMS_93 AY24 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

V21 VDD_277 VDD_313 Y27 Y13 VDDMS_190 VDDMS_94 AY25
V22 VDD_278 VDD_314 Y28 BT29 Y44 VDDMS_191 VDDMS_95 AY26
V23 VDD_279 VDD_315 Y29 BR29 XVDD_77 VDDMS_192 VDDMS_96
V24 VDD_280 VDD_316 Y30 BP29 XVDD_78
V25 VDD_281 VDD_317 Y31 BN29 XVDD_79 NVVDD
V26 VDD_282 VDD_318 Y32 BM29 XVDD_80
V27 VDD_283 VDD_319 Y33 BL29 XVDD_81 BP49
V28 VDD_284 VDD_320 BK29 XVDD_82 VDDMS_SENSE BR49 MSVDD_VDD_SENSE 102
VDD_285 BJ29 XVDD_83 GNDMS_SENSE MSVDD_VSS_SENSE 102
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
BH29 XVDD_84
XVDD_85 trace width: 8-10mils
BG29 @ GN20E-FCBGA2714_BGA2714
C

@ GN20E-FCBGA2714_BGA2714 BF29 XVDD_86

XVDD_87 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

@
CG460 @

CG461 @

CG462 @

CG463 @

CG521 @

CG522 @

CG523 @

CG464 @

CG728 @

CG729 @

CG731 @

CG734 @
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG495

CG468

CG724

CG725

CG726

CG727

CG730

CG735
@

@ GN20E-FCBGA2714_BGA2714 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
FC

NVVDD
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG1740 @
CG1745@

CG1746@

CG1752@

CG1753@

CG1758@

CG1759@
CG1744

CG1747

CG1748

CG1749

CG1750

CG1751

CG1754

CG1755

CG1756

CG1757

CG1741

CG1742

CG1743
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
@

@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
LC

NVVDD

A A
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG1763@

CG1771@

CG1772@

CG1777@

CG1779@
CG1760

CG1761

CG1762

CG1764

CG1765

CG1766

CG1767

CG1768

CG1769

CG1770

CG1773

CG1774

CG1775

CG1776

CG1778
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_POWER GPU CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y550 A0

Date: Monday, November 29, 2021 Sheet 34 of 110

5 4 3 2 1
 5 4 3 2 1

FBVDDQ FBVDDQ

UG1P
36A 19/24 FBVDDQ

AB11 L19
AB46 FBVDDQ_01 FBVDDQ_30 L20
AC11 FBVDDQ_02 FBVDDQ_31 L22
AE46 FBVDDQ_03 FBVDDQ_32 L23
AF11 FBVDDQ_04 FBVDDQ_33 L25
AF46 FBVDDQ_05 FBVDDQ_34 L26
AH11 FBVDDQ_06 FBVDDQ_35 L28
AH46 FBVDDQ_07 FBVDDQ_36 L29
AJ11 FBVDDQ_08 FBVDDQ_37 L31
AJ46 FBVDDQ_09 FBVDDQ_38 L32 UG1O +1.8VS_AON
AL11 FBVDDQ_10 FBVDDQ_39 L34 20/24 NC/1V8
D AL46 FBVDDQ_11 FBVDDQ_40 L37 D
AM11 FBVDDQ_12 FBVDDQ_41 L38 AV1 BF10

1U_6.3V_M_X6S_0201

1U_6.3V_M_X6S_0201
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

4.7U_6.3V_K_X6S_0603

4.7U_6.3V_K_X6S_0603
AM46 FBVDDQ_13 FBVDDQ_42 L40 AV2 NC_1 1V8_1 BF11
FBVDDQ_14 FBVDDQ_43 NC_2 1V8_2

CG672

CG673

CG669
AP11 L41 BG9 BG10
AR11 FBVDDQ_15 FBVDDQ_44 L43 BH10 NC_3 1V8_3 BG11 1 1 1 1 1 1 1

T
AR46 FBVDDQ_16 FBVDDQ_45 L44 BH11 NC_4 1V8_4
AU11 FBVDDQ_17 FBVDDQ_46 L46 BH14 NC_5
FBVDDQ_18 FBVDDQ_47 NC_6

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
AU46 N11 BJ16
AV11 FBVDDQ_19 FBVDDQ_48 N46 BJ7 NC_7 2 2 2 2 2 2 2
FBVDDQ_20 FBVDDQ_49 NC_8

CG667

CG668

CG670

CG671
AV46 P11 RG1360 BJ8 A4
AY46 FBVDDQ_21 FBVDDQ_50 P46 100_0402_1% BK16 NC_9 RSVD_1 A53
BA46 FBVDDQ_22 FBVDDQ_51 T11 FBVDDQ_VCC_SENSE 1 2 BN49 NC_10 RSVD_2 BN1

M
@ FBVDDQ
BC46 FBVDDQ_23 FBVDDQ_52 U11 BP50 NC_11 RSVD_3 BN56
K10 FBVDDQ_24 FBVDDQ_53 U46 BR50 NC_12 RSVD_4 BT4 Under GPU Near GPU
L11 FBVDDQ_25 FBVDDQ_54 W11 BR51 NC_13 RSVD_5 BT53
L13 FBVDDQ_26 FBVDDQ_55 W46 RG1359 1 @ 2 100_0402_1% BT51 NC_14 RSVD_6 D1
L14 FBVDDQ_27 FBVDDQ_56 Y11 D50 NC_15 RSVD_7 D56
L16 FBVDDQ_28 FBVDDQ_57 Y46 E50 NC_16 RSVD_8
FBVDDQ_29 FBVDDQ_58 F50 NC_17
PLACE WEST EDGE G50 NC_18
G6 NC_19

rS
RG25 1 OPT@2 0_0402_5% FBVDDQ_VSS_SENSE N49 NC_20 BH25 +FUSE_1V8
FBVDDQ_VSS_SENSE 107 NC_21 FUSE_SRC

1U_6.3V_M_X6S_0201

10K_0402_1%
PLACE NEAR GPU LOCAL SENSE +1.8VS_AON +FUSE_1V8

1
RG1335
GN20E-FCBGA2714_BGA2714
E54 FBVDDQ_SENSE_GPU FBVDDQ_VCC_SENSE

OPT@
RG61 1 @ 2 0_0402_5% @ 1
FBVDDQ_SENSE FBVDDQ_VCC_SENSE 107

OPT@
RG1326 1 @ 2 0_5%_0603
OPT@

2
W49 FB_VREF_PROBE RG174 1 2 2.49K_0402_1% 2
FB_VREF

CG674
CG72 1 2 3.9P_50V_B_NPO_0402 UG11

fo
OPT@ CG1103 1 2 @ A2 A1 +FUSE_1V8
2.2U_0402_6.3V6M VIN Vout
B1 B2
W47 FB_CAL_PD_VDDQ GND ON GPIO26_FP_FUSE 32
RG33 1 OPT@ 2 40.2_0402_1%
FBVDDQ Under GPU
FB_CAL_PD_VDDQ

1
Y47 FB_CAL_PU_GND RG73 1 OPT@ 2 40.2_0402_1% AP22913CN4-7_X1-WLB0909-4
FB_CAL_PU_GND RG1198
@
W48 FB_CAL_TERM_GND RG74 1 OPT@ 2 40.2_0402_1% 10K_0402_5%
FB_CAL_TERM_GND @
Place near balls

2
@ GN20E-FCBGA2714_BGA2714

C
y C
nl
lO

+1.8VALW +1.8VS_AON
tia

FBVDDQ

+1.8VALW to +1.8VS_AON
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
56P_50V_J_NPO_0201

56P_50V_J_NPO_0201

56P_50V_J_NPO_0201

56P_50V_J_NPO_0201

FBVDDQ
36A 1 1 1 1 1 1 1 1
QG123
CG7279

CG7280

CG7281

CG7282

CG7283

CG7284

CG7285

CG7286

Place close to GPU AON7380_DFN8-5

9 x 0603 22uF 3.5A
B+
0.1U_25V_K_X5R_0201
+5VALW 1
22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

2 2 2 2 2 2 2 2 2
1 5 3

10U_6.3V_M_X6S_0603
1

CG1783
en

1 1 1 1 1 1 1 1 1

1
+ RG678 1@ 1
1

@ @ @ @ @ 100K_0402_1% OPT@ CG611 RG680 2

4
CG1638

CG1639

CG1640

CG1641

CG1642

CG1643

CG1644

CG1645

CG1725

CG12
RG677 OPT@ @ 1/10W_47_5%_0603
2 2 2 2 2 2 2 2 2 2 220U_2.5V_Y_D_ESR6M _R_H1 47K_0402_5% 0.01U_50V_K_X7R_0402 OPT@
EMC Suggested reserved
2

FBVDDQ OPT@ 2 2

2
+1.8VS_VGA_GATE_EN RG682 2 OPT@ +1.8VS_VGA_GATE 1

@
1
2

CG902
0.047U_0402_25V_X7R_0402
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
56P_50V_J_NPO_0201

56P_50V_J_NPO_0201

56P_50V_J_NPO_0201

56P_50V_J_NPO_0201

1K_0402_1%
3

+1.8VS_VGA_DIS
1 1 1 1 1 1 1 1 QG4B D
+1.8VS_VGA_EN_N
CG7287

CG7288

CG7289

CG7290

CG7291

CG7292

CG7293

CG7294

5 1

OPT@
CG610
@ @ @ @ @ @ @ @ G
1
fid

2N7002KDWH_SOT363-6
6

2 2 2 2 2 2 2 2 QG4A D S RG683
4

RG679 1 @ 2 0_0402_5% PXS_PWREN_GATE 2 430K_0402_1% 2

32 PXS_PWREN_R G OPT@
B FBVDDQ 2N7002KDWH_SOT363-6 B
2

under GPU Place close to GPU 2 S

1

FBVDDQ 3PXS_PWREN_DELAY RG684 1 OPT@ 2 0_0402_5% CG901

1
8 x 0603 10uF 5 x 0603 10uF 0.1U_6.3V_K_X5R_0201RG681 QG5 D
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
56P_50V_J_NPO_0201

56P_50V_J_NPO_0201

1 OPT@ 100K_0402_5% +1.8VS_VGA_EN_N 2

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

1 @ G
2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1
2PXS_PWREN_DIS_DELAYRG685 1 OPT@
CG7295

CG7296

CG7297

CG7298

DG111 2 59K_0402_1%
2

@ @ @ @ S 2N7002KW_SOT323-3
on

3
LBAT54SWT1G_SOT323-3
1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2
OPT@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG88

CG89

CG741

CG742

CG76

CG77

CG739

CG740

CG87

CG743

CG736

CG737

CG738
@

+1.8VS_VGA Discharge
C

FBVDDQ
under GPU
24 x 0402 1uF
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
CG410 OPT@

CG412 OPT@

CG407 OPT@

CG404 OPT@

CG408 OPT@

CG399 OPT@

CG396 OPT@

CG744 OPT@

CG745 OPT@

CG746 OPT@

CG747 OPT@

CG748 OPT@

CG749 OPT@

CG750 OPT@

CG751 OPT@

CG752 OPT@

CG753 OPT@

CG754 OPT@

CG755 OPT@

CG756 OPT@

CG1563 OPT@

CG1564 OPT@

CG1565 OPT@

CG1566 OPT@
FC

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_POWER VDDQ

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y550 A0

Date: Monday, November 29, 2021 Sheet 35 of 110

5 4 3 2 1
 5 4 3 2 1

UG1F UG1G
15/24 GND_1/5 16/24 GND_2/5
UG1H
A2 AE35 AK8 AR42 21/24 GND_3/5 UG1I UG1J
A3 GND_001 GND_122 AE36 AL13 GND_238 GND_361 AR43 24/24 GND_5/5 23/24 GND_4/5
A54 GND_002 GND_123 AE37 AL14 GND_239 GND_362 AR44 B39 BE6
A55 GND_003 GND_124 AE38 AL15 GND_240 GND_363 AR5 B41 GND_481 GND_588 BE8 H7 R41 BR6 F30
D AA10 GND_004 GND_125 AE39 AL16 GND_241 GND_364 AR50 B42 GND_482 GND_589 BF52 H9 GND_854 GND_961 R42 BR9 GND_727 GND_791 F33 D
AA13 GND_005 GND_126 AE40 AL17 GND_242 GND_365 AR8 B44 GND_483 GND_590 BF54 J10 GND_855 GND_962 R43 BT2 GND_728 GND_792 F36
AA14 GND_006 GND_127 AE41 AL18 GND_243 GND_366 AT10 B45 GND_484 GND_591 BG12 J17 GND_856 GND_963 R44 BT3 GND_729 GND_793 F39
AA15 GND_007 GND_128 AE42 AL19 GND_244 GND_367 AT2 B47 GND_485 GND_592 BG15 J20 GND_857 GND_964 R47 C1 GND_730 GND_794 F4
AA16 GND_008 GND_129 AE43 AL2 GND_245 GND_368 AT4 B48 GND_486 GND_593 BG18 J29 GND_858 GND_965 R49 C10 GND_731 GND_795 F42

T
AA17 GND_009 GND_130 AE44 AL20 GND_246 GND_369 AT47 B51 GND_487 GND_594 BG21 J35 GND_859 GND_966 R51 C13 GND_732 GND_796 F45
AA18 GND_010 GND_131 AE49 AL21 GND_247 GND_370 AT49 B55 GND_488 GND_595 BG24 J4 GND_860 GND_967 R53 C16 GND_733 GND_797 F47
AA19 GND_011 GND_132 AE52 AL22 GND_248 GND_371 AT51 B56 GND_489 GND_596 BG30 J49 GND_861 GND_968 R55 C19 GND_734 GND_798 F48
AA2 GND_012 GND_133 AE54 AL23 GND_249 GND_372 AT53 B6 GND_490 GND_597 BG33 J51 GND_862 GND_969 R6 C22 GND_735 GND_799 F51
AA20 GND_013 GND_134 AE7 AL24 GND_250 GND_373 AT55 B8 GND_491 GND_598 BG36 J53 GND_863 GND_970 R8 C25 GND_736 GND_800 F53
AA21 GND_014 GND_135 AE9 AL25 GND_251 GND_374 AT6 B9 GND_492 GND_599 BG39 J55 GND_864 GND_971 T2 C28 GND_737 GND_801 F55
AA22 GND_015 GND_136 AF10 AL26 GND_252 GND_375 AT8 BA14 GND_493 GND_600 BG42 J6 GND_865 GND_972 T49 C31 GND_738 GND_802 F6

M
AA23 GND_016 GND_137 AF3 AL27 GND_253 GND_376 AU14 BA15 GND_494 GND_601 BG49 J8 GND_866 GND_973 T52 C34 GND_739 GND_803 F9
AA24 GND_017 GND_138 AF48 AL28 GND_254 GND_377 AU15 BA16 GND_495 GND_602 BG55 K12 GND_867 GND_974 T54 C37 GND_740 GND_804 G11
AA25 GND_018 GND_139 AF5 AL29 GND_255 GND_378 AU16 BA17 GND_496 GND_603 BH2 K15 GND_868 GND_975 T7 C4 GND_741 GND_805 G14
AA26 GND_019 GND_140 AF50 AL30 GND_256 GND_379 AU17 BA18 GND_497 GND_604 BH4 K18 GND_869 GND_976 T9 C40 GND_742 GND_806 G17
AA27 GND_020 GND_141 AF55 AL31 GND_257 GND_380 AU18 BA19 GND_498 GND_605 BH51 K19 GND_870 GND_977 U10 C43 GND_743 GND_807 G20
AA28 GND_021 GND_142 AF8 AL32 GND_258 GND_381 AU19 BA20 GND_499 GND_606 BH53 K21 GND_871 GND_978 U13 C46 GND_744 GND_808 G23
AA29 GND_022 GND_143 AG10 AL33 GND_259 GND_382 AU2 BA21 GND_500 GND_607 BH55 K24 GND_872 GND_979 U14 C56 GND_745 GND_809 G26
AA30 GND_023 GND_144 AG13 AL34 GND_260 GND_383 AU20 BA22 GND_501 GND_608 BH6 K27 GND_873 GND_980 U15 C7 GND_746 GND_810 G29
AA31 GND_024 GND_145 AG14 AL35 GND_261 GND_384 AU21 BA23 GND_502 GND_609 BH8 K28 GND_874 GND_981 U16 D12 GND_747 GND_811 G32

rS
AA32 GND_025 GND_146 AG15 AL36 GND_262 GND_385 AU22 BA24 GND_503 GND_610 BJ12 K30 GND_875 GND_982 U17 D15 GND_748 GND_812 G35
AA33 GND_026 GND_147 AG16 AL37 GND_263 GND_386 AU23 BA25 GND_504 GND_611 BJ14 K33 GND_876 GND_983 U18 D18 GND_749 GND_813 G38
AA34 GND_027 GND_148 AG17 AL38 GND_264 GND_387 AU24 BA26 GND_505 GND_612 BJ15 K36 GND_877 GND_984 U19 D21 GND_750 GND_814 G4
AA35 GND_028 GND_149 AG18 AL39 GND_265 GND_388 AU25 BA27 GND_506 GND_613 BJ17 K37 GND_878 GND_985 U20 D24 GND_751 GND_815 G41
AA36 GND_029 GND_150 AG19 AL40 GND_266 GND_389 AU26 BA28 GND_507 GND_614 BJ18 K39 GND_879 GND_986 U21 D27 GND_752 GND_816 G44
AA37 GND_030 GND_151 AG2 AL41 GND_267 GND_390 AU27 BA29 GND_508 GND_615 BJ20 K42 GND_880 GND_987 U22 D30 GND_753 GND_817 G49
AA38 GND_031 GND_152 AG20 AL42 GND_268 GND_391 AU28 BA30 GND_509 GND_616 BJ21 K45 GND_881 GND_988 U23 D33 GND_754 GND_818 G52
AA39 GND_032 GND_153 AG21 AL43 GND_269 GND_392 AU29 BA31 GND_510 GND_617 BJ23 K49 GND_882 GND_989 U24 D36 GND_755 GND_819 G54
AA4 GND_033 GND_154 AG22 AL44 GND_270 GND_393 AU30 BA32 GND_511 GND_618 BJ24 K52 GND_883 GND_990 U25 D39 GND_756 GND_820 G8
AA40 GND_034 GND_155 AG23 AL49 GND_271 GND_394 AU31 BA33 GND_512 GND_619 BJ31 K54 GND_884 GND_991 U26 D4 GND_757 GND_821 H10
AA41 GND_035 GND_156 AG24 AL52 GND_272 GND_395 AU32 BA34 GND_513 GND_620 BJ33 K7 GND_885 GND_992 U27 D42 GND_758 GND_822 H12
AA42 GND_036 GND_157 AG25 AL54 GND_273 GND_396 AU33 BA35 GND_514 GND_621 BJ35 K9 GND_886 GND_993 U28 D45 GND_759 GND_823 H13
AA43 GND_037 GND_158 AG26 AL7 GND_274 GND_397 AU34 BA36 GND_515 GND_622 BJ37 L10 GND_887 GND_994 U29 D48 GND_760 GND_824 H15

fo
AA44 GND_038 GND_159 AG27 AL9 GND_275 GND_398 AU35 BA37 GND_516 GND_623 BJ39 L3 GND_888 GND_995 U3 D49 GND_761 GND_825 H16
AA47 GND_039 GND_160 AG28 AM10 GND_276 GND_399 AU36 BA38 GND_517 GND_624 BJ41 L5 GND_889 GND_996 U30 D51 GND_762 GND_826 H18
AA49 GND_040 GND_161 AG29 AM3 GND_277 GND_400 AU37 BA39 GND_518 GND_625 BJ43 L50 GND_890 GND_997 U31 D53 GND_763 GND_827 H19
AA51 GND_041 GND_162 AG30 AM48 GND_278 GND_401 AU38 BA40 GND_519 GND_626 BJ45 L55 GND_891 GND_998 U32 D6 GND_764 GND_828 H21
AA53 GND_042 GND_163 AG31 AM5 GND_279 GND_402 AU39 BA41 GND_520 GND_627 BJ53 L8 GND_892 GND_999 U33 D9 GND_765 GND_829 H22
AA55 GND_043 GND_164 AG32 AM50 GND_280 GND_403 AU40 BA42 GND_521 GND_628 BJ9 M10 GND_893 GND_1000 U34 E10 GND_766 GND_830 H24
AA6 GND_044 GND_165 AG33 AM55 GND_281 GND_404 AU41 BA43 GND_522 GND_629 BK31 M2 GND_894 GND_1001 U35 E13 GND_767 GND_831 H25
AA8 GND_045 GND_166 AG34 AM8 GND_282 GND_405 AU42 BA50 GND_523 GND_630 BK33 M4 GND_895 GND_1002 U36 E16 GND_768 GND_832 H27
AB47 GND_046 GND_167 AG35 AN10 GND_283 GND_406 AU43 BA55 GND_524 GND_631 BK35 M47 GND_896 GND_1003 U37 E19 GND_769 GND_833 H28
AB49 GND_047 GND_168 AG36 AN13 GND_284 GND_407 AU49 BB47 GND_525 GND_632 BK37 M49 GND_897 GND_1004 U38 E2 GND_770 GND_834 H3
AB52 GND_048 GND_169 AG37 AN14 GND_285 GND_408 AU52 BB49 GND_526 GND_633 BK39 M51 GND_898 GND_1005 U39 E22 GND_771 GND_835 H30
AB54 GND_049 GND_170 AG38 AN15 GND_286 GND_409 AU54 BB51 GND_527 GND_634 BK41 M53 GND_899 GND_1006 U40 E25 GND_772 GND_836 H32

C
AB7
AC13
AC14
AC15
AC16
GND_050
GND_051
GND_052
GND_053
GND_054
GND_171
GND_172
GND_173
GND_174
GND_175
AG39
AG4
AG40
AG41
AG42
AN16
AN17
AN18
AN19
AN2
GND_287
GND_288
GND_289
GND_290
GND_291
GND_410
GND_411
GND_412
GND_413
GND_414
AU7
AU9
AV10
AV3
AV5
BB53
BB55
BC14
BC15
BC16
GND_528
GND_529
GND_530
GND_531
GND_532
GND_635
GND_636
GND_637
GND_638
GND_639
BK43
BK45
BK54
BL12
BL15
y M55
M6
M8
N14
N16
GND_900
GND_901
GND_902
GND_903
GND_904
GND_1007
GND_1008
GND_1009
GND_1010
GND_1011
U41
U42
U43
U44
U48
E28
E31
E34
E37
E40
GND_773
GND_774
GND_775
GND_776
GND_777
GND_837
GND_838
GND_839
GND_840
GND_841
H33
H34
H36
H37
H39 C
GND_055 GND_176 GND_292 GND_415 GND_533 GND_640 GND_905 GND_1012 GND_778 GND_842
nl
AC17 AG43 AN20 AV50 BC17 BL18 N18 U5 E43 H4
AC18 GND_056 GND_177 AG44 AN21 GND_293 GND_416 AV8 BC18 GND_534 GND_641 BL2 N2 GND_906 GND_1013 U50 E5 GND_779 GND_843 H40
AC19 GND_057 GND_178 AG47 AN22 GND_294 GND_417 AW10 BC19 GND_535 GND_642 BL21 N20 GND_907 GND_1014 U55 E52 GND_780 GND_844 H42
AC20 GND_058 GND_179 AG49 AN23 GND_295 GND_418 AW14 BC20 GND_536 GND_643 BL24 N22 GND_908 GND_1015 U8 E7 GND_781 GND_845 H43
AC21 GND_059 GND_180 AG51 AN24 GND_296 GND_419 AW15 BC21 GND_537 GND_644 BL30 N24 GND_909 GND_1016 V10 F1 GND_782 GND_846 H45
AC22 GND_060 GND_181 AG53 AN25 GND_297 GND_420 AW16 BC22 GND_538 GND_645 BL32 N26 GND_910 GND_1017 V2 F12 GND_783 GND_847 H46
AC23 GND_061 GND_182 AG55 AN26 GND_298 GND_421 AW17 BC23 GND_539 GND_646 BL34 N28 GND_911 GND_1018 V4 F15 GND_784 GND_848 H47
AC24 GND_062 GND_183 AG6 AN27 GND_299 GND_422 AW18 BC24 GND_540 GND_647 BL36 N29 GND_912 GND_1019 V47 F18 GND_785 GND_849 H48
AC25 GND_063 GND_184 AG8 AN28 GND_300 GND_423 AW19 BC25 GND_541 GND_648 BL38 N31 GND_913 GND_1020 V49 F2 GND_786 GND_850 H50
lO

AC26 GND_064 GND_185 AH2 AN29 GND_301 GND_424 AW2 BC26 GND_542 GND_649 BL4 N33 GND_914 GND_1021 V51 F21 GND_787 GND_851 H55
AC27 GND_065 GND_186 AH47 AN30 GND_302 GND_425 AW20 BC27 GND_543 GND_650 BL40 N35 GND_915 GND_1022 V53 F24 GND_788 GND_852 H6
AC28 GND_066 GND_187 AH49 AN31 GND_303 GND_426 AW21 BC28 GND_544 GND_651 BL42 N37 GND_916 GND_1023 V55 F27 GND_789 GND_853
AC29 GND_067 GND_188 AH52 AN32 GND_304 GND_427 AW22 BC29 GND_545 GND_652 BL44 N39 GND_917 GND_1024 V6 GND_790
AC3 GND_068 GND_189 AH54 AN33 GND_305 GND_428 AW23 BC30 GND_546 GND_653 BL46 N41 GND_918 GND_1025 V8
AC30 GND_069 GND_190 AH7 AN34 GND_306 GND_429 AW24 BC31 GND_547 GND_654 BL55 N43 GND_919 GND_1026 W13 @ GN20E-FCBGA2714_BGA2714
AC31 GND_070 GND_191 AJ13 AN35 GND_307 GND_430 AW25 BC32 GND_548 GND_655 BL6 N48 GND_920 GND_1027 W14
AC32 GND_071 GND_192 AJ14 AN36 GND_308 GND_431 AW26 BC33 GND_549 GND_656 BL9 N52 GND_921 GND_1028 W15
AC33 GND_072 GND_193 AJ15 AN37 GND_309 GND_432 AW27 BC34 GND_550 GND_657 BM14 N54 GND_922 GND_1029 W16
AC34 GND_073 GND_194 AJ16 AN38 GND_310 GND_433 AW28 BC35 GND_551 GND_658 BM17 N7 GND_923 GND_1030 W17
AC35 GND_074 GND_195 AJ17 AN39 GND_311 GND_434 AW29 BC36 GND_552 GND_659 BM20 P3 GND_924 GND_1031 W18
AC36 GND_075 GND_196 AJ18 AN4 GND_312 GND_435 AW30 BC37 GND_553 GND_660 BM23 P5 GND_925 GND_1032 W19
AC37 GND_076 GND_197 AJ19 AN40 GND_313 GND_436 AW31 BC38 GND_554 GND_661 BM30 P50 GND_926 GND_1033 W20
GND_077 GND_198 GND_314 GND_437 GND_555 GND_662 GND_927 GND_1034
tia

AC38 AJ20 AN41 AW32 BC39 BM32 P55 W21

AC39 GND_078 GND_199 AJ21 AN42 GND_315 GND_438 AW33 BC40 GND_556 GND_663 BM34 P8 GND_928 GND_1035 W22
AC40 GND_079 GND_200 AJ22 AN43 GND_316 GND_439 AW34 BC41 GND_557 GND_664 BM36 R10 GND_929 GND_1036 W23
AC41 GND_080 GND_201 AJ23 AN44 GND_317 GND_440 AW35 BC42 GND_558 GND_665 BM38 R13 GND_930 GND_1037 W24
AC42 GND_081 GND_202 AJ24 AN47 GND_318 GND_441 AW36 BC43 GND_559 GND_666 BM40 R14 GND_931 GND_1038 W25
AC43 GND_082 GND_203 AJ25 AN49 GND_319 GND_442 AW37 BC49 GND_560 GND_667 BM42 R15 GND_932 GND_1039 W26
AC44 GND_083 GND_204 AJ26 AN51 GND_320 GND_443 AW38 BC52 GND_561 GND_668 BM44 R16 GND_933 GND_1040 W27
AC5 GND_084 GND_205 AJ27 AN53 GND_321 GND_444 AW39 BC54 GND_562 GND_669 BM46 R17 GND_934 GND_1041 W28
AC50 GND_085 GND_206 AJ28 AN55 GND_322 GND_445 AW4 BD15 GND_563 GND_670 BM48 R18 GND_935 GND_1042 W29
AC55 GND_086 GND_207 AJ29 AN6 GND_323 GND_446 AW40 BD16 GND_564 GND_671 BN10 R19 GND_936 GND_1043 W30
AC8 GND_087 GND_208 AJ3 AN8 GND_324 GND_447 AW41 BD19 GND_565 GND_672 BN11 R2 GND_937 GND_1044 W31
AD10 GND_088 GND_209 AJ30 AP2 GND_325 GND_448 AW42 BD20 GND_566 GND_673 BN12 R20 GND_938 GND_1045 W32
en

AD2 GND_089 GND_210 AJ31 AP49 GND_326 GND_449 AW43 BD23 GND_567 GND_674 BN13 R21 GND_939 GND_1046 W33
AD4 GND_090 GND_211 AJ32 AP52 GND_327 GND_450 AW47 BD24 GND_568 GND_675 BN14 R22 GND_940 GND_1047 W34
AD47 GND_091 GND_212 AJ33 AP54 GND_328 GND_451 AW49 BD27 GND_569 GND_676 BN15 R23 GND_941 GND_1048 W35
AD49 GND_092 GND_213 AJ34 AP7 GND_329 GND_452 AW51 BD30 GND_570 GND_677 BN16 R24 GND_942 GND_1049 W36
AD51 GND_093 GND_214 AJ35 AR13 GND_330 GND_453 AW53 BD33 GND_571 GND_678 BN17 R25 GND_943 GND_1050 W37
AD53 GND_094 GND_215 AJ36 AR14 GND_331 GND_454 AW55 BD34 GND_572 GND_679 BN18 R26 GND_944 GND_1051 W38
AD55 GND_095 GND_216 AJ37 AR15 GND_332 GND_455 AW6 BD37 GND_573 GND_680 BN19 R27 GND_945 GND_1052 W39
AD6 GND_096 GND_217 AJ38 AR16 GND_333 GND_456 AW8 BD38 GND_574 GND_681 BN20 R28 GND_946 GND_1053 W40
AD8 GND_097 GND_218 AJ39 AR17 GND_334 GND_457 AY47 BD41 GND_575 GND_682 BN21 R29 GND_947 GND_1054 W41
AE13 GND_098 GND_219 AJ40 AR18 GND_335 GND_458 AY49 BD42 GND_576 GND_683 BN22 R30 GND_948 GND_1055 W42
AE14 GND_099 GND_220 AJ41 AR19 GND_336 GND_459 AY52 BD48 GND_577 GND_684 BN23 R31 GND_949 GND_1056 W43
AE15 GND_100 GND_221 AJ42 AR20 GND_337 GND_460 AY54 BD50 GND_578 GND_685 BN24 R32 GND_950 GND_1057 W44
fid

AE16 GND_101 GND_222 AJ43 AR21 GND_338 GND_461 B1 BD55 GND_579 GND_686 BN30 R33 GND_951 GND_1058 W52
AE17 GND_102 GND_223 AJ44 AR22 GND_339 GND_462 B11 BE10 GND_580 GND_687 BN31 R34 GND_952 GND_1059 W54
AE18 GND_103 GND_224 AJ5 AR23 GND_340 GND_463 B12 BE2 GND_581 GND_688 BN32 R35 GND_953 GND_1060 W7
B AE19 GND_104 GND_225 AJ50 AR24 GND_341 GND_464 B14 BE4 GND_582 GND_689 BN33 R36 GND_954 GND_1061 Y3 B
AE2 GND_105 GND_226 AJ55 AR25 GND_342 GND_465 B15 BE49 GND_583 GND_690 BN34 R37 GND_955 GND_1062 Y48
AE20 GND_106 GND_227 AJ8 AR26 GND_343 GND_466 B17 BE51 GND_584 GND_691 BN35 R38 GND_956 GND_1063 Y5
AE21 GND_107 GND_228 AK10 AR27 GND_344 GND_467 B18 BE53 GND_585 GND_692 BN36 R39 GND_957 GND_1064 Y50
AE22 GND_108 GND_229 AK2 AR28 GND_345 GND_468 B2 BE55 GND_586 GND_693 BR30 R4 GND_958 GND_1065 Y55
AE23 GND_109 GND_230 AK4 AR29 GND_346 GND_469 B21 GND_587 GND_726 R40 GND_959 GND_1066 Y8
AE24 GND_110 GND_231 AK47 AR3 GND_347 GND_470 B24 GND_960 GND_1067
AE25 GND_111 GND_232 AK49 AR30 GND_348 GND_471 B26 @ GN20E-FCBGA2714_BGA2714
on

AE26 GND_112 GND_233 AK51 AR31 GND_349 GND_472 B27 @ GN20E-FCBGA2714_BGA2714

AE27 GND_113 GND_234 AK53 AR32 GND_350 GND_473 B29
AE28 GND_114 GND_235 AK55 AR33 GND_351 GND_474 B30
AE29 GND_115 GND_236 AK6 AR34 GND_352 GND_475 B32
AE30 GND_116 GND_237 B38 AR35 GND_353 GND_476 B33
AE31 GND_117 GND_480 BH13 AR36 GND_354 GND_477 B35
AE32 GND_118 GND_F AR37 GND_355 GND_478 B36
AE33 GND_119 AR38 GND_356 GND_479 AR40
AE34 GND_120 AR39 GND_357 GND_359 AR41
GND_121 GND_358 GND_360

@ GN20E-FCBGA2714_BGA2714 @ GN20E-FCBGA2714_BGA2714
C
FC
LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y550 A0

Date: Monday, November 29, 2021 Sheet 36 of 110

5 4 3 2 1
 5 4 3 2 1

UG4D
?
? UG4C
COMMON ?
?
FBVDDQ COMMON

30 FBA_CMD[0..24]
RG1341
A11 A1 UG4B FBA_CMD1 H3 K1 +FBA_A_VREFC 1 2 +FBA_VREFC
A13 VSS_1 VDD_1 A14 UG4A FBA_CMD13 G11 CA0_A VREFC 0_0201_5%
A2 VSS_2 VDD_2 E10 NORMAL FBA_CMD12 G4 CA1_A @
VSS_3 VDD_3 CA2_A

1
A4 E5 FBA_CMD24 H12
VSS_4 VDD_4 30 FBA_D[8..15] NORMAL 30 FBA_D[0..7] CA3_A
B1 H13 x16 x8 FBA_CMD11 H5 RG1342
B14 VSS_5 VDD_5 H2 FBA_D12 G2 FBA_D3 N2 FBA_CMD15 H10 CA4_A 1K_0402_1%
C10 VSS_6 VDD_6 L13 FBA_D13 B3 DQ7_A FBA_D7 P3 DQ6_B FBA_CMD22 J12 CA5_A OPT@
C12 VSS_7 VDD_7 L2 FBA_D15 F2 DQ2_A FBA_D1 M2 DQ4_B FBA_CMD23 J11 CA6_A
BYTE1 BYTE0

2
D
C3 VSS_8 VDD_8 P10 FBA_D14 E3 DQ6_A FBA_D0 P2 DQ7_B FBA_CMD0 J4 CA7_A D
C5 VSS_9 VDD_9 P5 FBA_D9 B4 DQ4_A FBA_D6 U3 DQ5_B FBA_CMD2 J3 CA8_A
D1 VSS_10 VDD_10 V1 FBA_D10 B2 DQ0_A FBA_D2 V3 DQ2_B FBA_CMD10 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBA_D11 E2 DQ3_A FBA_D4 U4 DQ1_B FBA_CMD14 G10 CABI_n_A
D14 VSS_12 VDD_12 FBA_D8 A3 DQ5_A FBA_D5 U2 DQ0_B CKE_n_A
D3 VSS_13 DQ1_A DQ3_B N5
E11 VSS_14 FBA_EDC1 C2 FBA_EDC0 T2 TCK
VSS_15 FBVDDQ 30 FBA_EDC1 FBA_DBI1_N EDC0_A 30 FBA_EDC0 FBA_DBI0_N EDC0_B
E4 D2 R2 F10
VSS_16 30 FBA_DBI1_N DBI0_n_A 30 FBA_DBI0_N DBI0_n_B TDI
F1 N10
F12 VSS_17 FBA_WCKB01_P D4 FBA_WCK01_P R4 TDO
VSS_18 30 FBA_WCKB01_P FBA_WCKB01_N WCK_t_A 30 FBA_WCK01_P FBA_WCK01_N NC3
F14 B10 D5 R5 F5
VSS_19 VDDQ_1 30 FBA_WCKB01_N WCK_c_A 30 FBA_WCK01_N NC4 FBA_CMD5 TMS
F3 B5 L3
VSS_20 VDDQ_2 30 FBA_D[16..23] FBA_D20 FBA_CMD18 CA0_B

T
G1 C1 P13 M11
VSS_21 VDDQ_3 30 FBA_D[24..31] FBA_D18 DQ13_B FBA_CMD7 CA1_B
G12 C11 x16 x8 U13 M4
G14 VSS_22 VDDQ_4 C14 FBA_D24 B11 FBA_D23 M13 DQ11_B FBA_CMD20 L12 CA2_B
VSS_23 VDDQ_5 FBA_D29 DQ8_A NC BYTE2 FBA_D22 DQ15_B FBA_CMD8 CA3_B
G3 C4 G13 NC N13 L5
H11 VSS_24 VDDQ_6 E1 FBA_D31 E13 DQ15_A FBA_D16 U12 DQ14_B FBA_CMD16 L10 CA4_B
BYTE3

M
NC
H4 VSS_25 VDDQ_7 E14 FBA_D28 F13 DQ13_A FBA_D19 P12 DQ10_B FBA_CMD21 K12 CA5_B
NC
L11 VSS_26 VDDQ_8 F11 FBA_D26 E12 DQ14_A FBA_D21 V12 DQ12_B FBA_CMD19 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 FBA_D25 B12 DQ12_A FBA_D17 U11 DQ9_B FBA_CMD6 K4 CA7_B
NC
M1 VSS_28 VDDQ_10 H1 FBA_D30 B13 DQ10_A DQ8_B FBA_CMD4 K3 CA8_B
NC
M12 VSS_29 VDDQ_11 H14 FBA_D27 A12 DQ11_A FBA_EDC2 T13 FBA_CMD9 K5 CA9_B J14FBA_ZQ_1_A RG146 1 OPT@ 2 121_0402_1%
NC
30 FBA_EDC2

rS
M14 VSS_30 VDDQ_12 J13 DQ9_A FBA_DBI2_N R13 EDC1_B FBA_CMD17 M10 CABI_n_B ZQ_A
VSS_31 VDDQ_13 FBA_EDC3 30 FBA_DBI2_N DBI1_n_B CKE_n_B
M3 J2 C13 GND K14FBA_ZQ_1_B RG145 1 OPT@ 2 121_0402_1%
VSS_32 VDDQ_14 30 FBA_EDC3 FBA_DBI3_N EDC1_A FBA_WCK23_P ZQ_B
N1 K13 D13 R11
VSS_33 VDDQ_15 30 FBA_DBI3_N DBI1_n_A NC 30 FBA_WCK23_P FBA_WCK23_N WCK_t_B
N12 K2 R10
VSS_34 VDDQ_16 FBA_WCKB23_P D11 30 FBA_WCK23_N WCK_c_B
N14 L1 NC
VSS_35 VDDQ_17 30 FBA_WCKB23_P FBA_WCKB23_N D10 NC1
N3 L14 NC
VSS_36 VDDQ_18 30 FBA_WCKB23_N NC2 FBA_CMD3
P11 N11 J1
VSS_37 VDDQ_19 RESET_n
P4 N4 MT61K256M32JE-14-A_FBGA180
R1 VSS_38 VDDQ_20 P1 MT61K256M32JE-14-A_FBGA180

fo
VSS_39 VDDQ_21 @
R12 P14 @
R14 VSS_40 VDDQ_22 T1 FBA_CLK0_N K10
VSS_41 VDDQ_23 30 FBA_CLK0_N CK_c
R3 T11 FBA_CLK0_P J10
T10
T12
T3
T5
VSS_42
VSS_43
VSS_44
VSS_45
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
T14
T4
U10
U5
follow CRB bit swap 30 FBA_CLK0_P CK_t
NC5

NC6
G5

M5
C C
U1
U14
V11
VSS_46
VSS_47
VSS_48
VDDQ_28
y
VSS_49
nl
V13 +1.8VS_AON
V2 VSS_50 +1.8VS_AON
V4 VSS_51 4 x 0402 1 uF
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

VPP_1 @
A5
lO

VPP_2 V10
VPP_3 1 1 1 1
V5
VPP_4
OPT@

OPT@

OPT@

OPT@
CG201

CG202

CG203

CG204

MT61K256M32JE-14-A_FBGA180
2 2 2 2
@
tia

FBVDDQ

1
en

RG77
1/16W_549_1%_0402
@

2
FBVDDQ 4 x 0603 10 uF +FBA_VREFC_R 1 2 +FBA_VREFC
6 x 0603 22 uF +FBA_VREFC 38
AROUND DRAM CLOSE TO DRAM FBVDDQ RG78 16 mil
1
2 x 0603 10 uF 18 x 0402 1 uF
CLOSE TO DRAM 931_0402_1% 1
@ RG79 CG148
fid

1K_0402_1% 820P_0402_25V7
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

@ @
2
1 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
2

2 QG1
B 32,50 MEM_VREF_CTL B
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

LSI1012XT1G_SC-89-3
CG162

CG163

CG164

CG121

CG122

CG123

CG124

CG125

CG126

CG128

CG129

CG130

2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

@
on

3
CG111

CG115

CG160

CG161
CG1646

CG1647

CG1648

CG1649

CG1650

CG1651

CG1716

CG1717

Vgs(th)≤0.9V VREFC IS NOT USED IN

x16 CONFIGURATION
1K OHM PULL-DOWN IS
IN PLACE OF THE 1.33K
C

CLOSE TO DRAM FBVDDQ FOR RV99

CLOSE TO DRAM
FBVDDQ
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1 1 1 1 1 1
330U_B2_2.5VM_R9M

1
FC

+
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG194

CG195

CG196

CG197

CG198

CG199

2 2 2 2 2 2

2
@
CG1567

LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GDDR6_A_[31_0]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y550
Date: Monday, November 29, 2021 Sheet 37 of 110
5 4 3 2 1
 5 4 3 2 1

UG5D
? UG5C
? ?
COMMON ?
COMMON
FBVDDQ
30 FBA_CMD[28..52]
UG5A RG1343
UG5B FBA_CMD33 H3 K1 +FBA_B_VREFC 1 2 +FBA_VREFC
FBA_CMD45 CA0_A VREFC +FBA_VREFC 37
A11 A1 NORMAL G11 0_0201_5%
VSS_1 VDD_1 30 FBA_D[40..47] FBA_CMD35 CA1_A
A13 A14 NORMAL G4 @ 1
VSS_2 VDD_2 CA2_A

1
A2 E10 FBA_D45 G2 FBA_CMD46 H12 CG83
VSS_3 VDD_3 FBA_D42 DQ7_A 30 FBA_D[32..39] FBA_CMD36 CA3_A
A4 E5 B3 x16 x8 H5 RG1344 820P_0402_25V7
B1 VSS_4 VDD_4 H13 FBA_D43 F2 DQ2_A FBA_D35 N2 FBA_CMD43 H10 CA4_A
VSS_5 VDD_5 BYTE5 FBA_D47 DQ6_A FBA_D34 DQ6_B FBA_CMD48 CA5_A
1K_0402_1%
2
@
B14 H2 E3 P3 J12 OPT@
C10 VSS_6 VDD_6 L13 FBA_D41 B4 DQ4_A FBA_D37 M2 DQ4_B FBA_CMD47 J11 CA6_A
BYTE4

2
C12 VSS_7 VDD_7 L2 FBA_D44 B2 DQ0_A FBA_D38 P2 DQ7_B FBA_CMD34 J4 CA7_A
D
C3 VSS_8 VDD_8 P10 FBA_D46 E2 DQ3_A FBA_D36 U3 DQ5_B FBA_CMD32 J3 CA8_A D
C5 VSS_9 VDD_9 P5 FBA_D40 A3 DQ5_A FBA_D33 V3 DQ2_B FBA_CMD37 J5 CA9_A
D1 VSS_10 VDD_10 V1 DQ1_A FBA_D32 U4 DQ1_B FBA_CMD44 G10 CABI_n_A
D12 VSS_11 VDD_11 V14 FBA_EDC5 C2 FBA_D39 U2 DQ0_B CKE_n_A
VSS_12 VDD_12 30 FBA_EDC5 FBA_DBI5_N EDC0_A DQ3_B
D14 D2 N5
VSS_13 30 FBA_DBI5_N DBI0_n_A FBA_EDC4 TCK
D3 T2
VSS_14 FBA_WCKB45_P 30 FBA_EDC4 FBA_DBI4_N EDC0_B
E11 D4 R2 F10
VSS_15 FBVDDQ 30 FBA_WCKB45_P FBA_WCKB45_N WCK_t_A 30 FBA_DBI4_N DBI0_n_B TDI
E4 D5 N10
VSS_16 30 FBA_WCKB45_N WCK_c_A FBA_WCK45_P TDO
F1 R4
VSS_17 30 FBA_WCK45_P FBA_WCK45_N NC3
F12 R5 F5
VSS_18 30 FBA_D[56..63] 30 FBA_WCK45_N NC4 FBA_CMD29 TMS
F14 B10 x16 x8 L3
VSS_19 VDDQ_1 FBA_D60 30 FBA_D[48..55] FBA_D51 FBA_CMD52 CA0_B
F3 B5 B11 NC P13 M11
VSS_20 VDDQ_2 FBA_D56 DQ8_A FBA_D49 DQ13_B FBA_CMD40 CA1_B

T
G1 C1 G13 NC U13 M4
G12 VSS_21 VDDQ_3 C11 FBA_D59 E13 DQ15_A FBA_D50 M13 DQ11_B FBA_CMD50 L12 CA2_B
VSS_22 VDDQ_4 BYTE7 FBA_D57 DQ13_A NC BYTE6 FBA_D52 DQ15_B FBA_CMD39 CA3_B
G14 C14 F13 NC N13 L5
G3 VSS_23 VDDQ_5 C4 FBA_D63 E12 DQ14_A FBA_D53 U12 DQ14_B FBA_CMD42 L10 CA4_B
NC
H11 VSS_24 VDDQ_6 E1 FBA_D62 B12 DQ12_A FBA_D54 P12 DQ10_B FBA_CMD49 K12 CA5_B

M
NC
H4 VSS_25 VDDQ_7 E14 FBA_D58 B13 DQ10_A FBA_D48 V12 DQ12_B FBA_CMD51 K11 CA6_B
NC
L11 VSS_26 VDDQ_8 F11 FBA_D61 A12 DQ11_A FBA_D55 U11 DQ9_B FBA_CMD28 K4 CA7_B
NC
L4 VSS_27 VDDQ_9 F4 DQ9_A DQ8_B FBA_CMD30 K3 CA8_B
M1 VSS_28 VDDQ_10 H1 FBA_EDC7 C13 FBA_EDC6 T13 FBA_CMD38 K5 CA9_B J14FBA_ZQ_2_A RG158 1 OPT@ 2 121_0402_1%
GND
VSS_29 VDDQ_11 30 FBA_EDC7 FBA_DBI7_N EDC1_A 30 FBA_EDC6 FBA_DBI6_N EDC1_B FBA_CMD41 CABI_n_B ZQ_A
M12 H14 D13 R13 M10
30 FBA_DBI7_N 30 FBA_DBI6_N

rS
M14 VSS_30 VDDQ_12 J13 DBI1_n_A NC DBI1_n_B CKE_n_B K14FBA_ZQ_2_B RG159 1 OPT@ 2 121_0402_1%
M3 VSS_31 VDDQ_13 J2 FBA_WCKB67_P D11 FBA_WCK67_P R11 ZQ_B
NC
VSS_32 VDDQ_14 30 FBA_WCKB67_P FBA_WCKB67_N D10 NC1 30 FBA_WCK67_P FBA_WCK67_N WCK_t_B
N1 K13 NC R10
VSS_33 VDDQ_15 30 FBA_WCKB67_N NC2 30 FBA_WCK67_N WCK_c_B
N12 K2
N14 VSS_34 VDDQ_16 L1
N3 VSS_35 VDDQ_17 L14 MT61K256M32JE-14-A_FBGA180 FBA_CMD31 J1
VSS_36 VDDQ_18 RESET_n
P11 N11 @ MT61K256M32JE-14-A_FBGA180
P4 VSS_37 VDDQ_19 N4
VSS_38 VDDQ_20 @
R1 P1

fo
R12 VSS_39 VDDQ_21 P14 FBA_CLK1_N K10 CK_c
R14
R3
T10
T12
VSS_40
VSS_41
VSS_42
VSS_43
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
T1
T11
T14
T4
follow CRB bit swap 30
30
FBA_CLK1_N
FBA_CLK1_P
FBA_CLK1_P J10
CK_t
NC5
G5

M5
T3 VSS_44 VDDQ_26 U10 NC6
C T5 VSS_45 VDDQ_27 U5 C
U1
U14
V11
VSS_46
VSS_47
VSS_48
VDDQ_28
y
VSS_49
nl
V13 +1.8VS_AON
V2 VSS_50 +1.8VS_AON
V4 VSS_51 4 x 0402 1 uF
VSS_52 CLOSE TO DRAM MT61K256M32JE-14-A_FBGA180
@
A10
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

VPP_1 A5
lO

VPP_2 V10
VPP_3 1 1 1 1
V5
VPP_4
OPT@

OPT@

OPT@

OPT@
CG209

CG210

CG211

CG212

MT61K256M32JE-14-A_FBGA180
2 2 2 2
@
tia
en

FBVDDQ 4 x 0603 10 uF FBVDDQ

AROUND DRAM 6 x 0603 22 uF CLOSE TO DRAM CLOSE TO DRAM 18 x 0402 1 uF
2 x 0603 10 uF
fid
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 2 2 2 2 2 2
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG207

CG232

CG231

CG233

CG236

CG235

CG234

CG237

CG205

CG239

CG238

CG206

B 2 2 2 2 2 2 2 2 2 2 2 2 B
2 2 2 2 2 2 1 1 1 1 1 1
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

on
CG221

CG220

CG219

CG218
CG1652

CG1653

CG1654

CG1655

CG1656

CG1657

CG1699

CG1700

FBVDDQ
CLOSE TO DRAM CLOSE TO DRAM
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

FBVDDQ
1 1 1 1 1 1
FC
330U_B2_2.5VM_R9M

1
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG228

CG213

CG217

CG214

CG215

CG216

+ 2 2 2 2 2 2

2
CG1568

LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GDDR6_A_[63_32]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y550
Date: Monday, November 29, 2021 Sheet 38 of 110
5 4 3 2 1
 5 4 3 2 1

UG6D
?
? UG6C
COMMON ?
?
FBVDDQ COMMON

30 FBB_CMD[0..24]
RG1345
A11 A1 UG6B FBB_CMD1 H3 K1 +FBB_A_VREFC 1 2+FBB_VREFC
A13 VSS_1 VDD_1 A14 UG6A FBB_CMD13 G11 CA0_A VREFC 0_0201_5%
A2 VSS_2 VDD_2 E10 NORMAL FBB_CMD12 G4 CA1_A @
VSS_3 VDD_3 CA2_A

1
A4 E5 FBB_CMD24 H12
VSS_4 VDD_4 30 FBB_D[8..15] NORMAL 30 FBB_D[0..7] CA3_A
B1 H13 x16 x8 FBB_CMD11 H5 RG1346
B14 VSS_5 VDD_5 H2 FBB_D12 G2 FBB_D3 N2 FBB_CMD15 H10 CA4_A 1K_0402_1%
C10 VSS_6 VDD_6 L13 FBB_D10 B3 DQ7_A FBB_D4 P3 DQ6_B FBB_CMD22 J12 CA5_A OPT@
D
C12 VSS_7 VDD_7 L2 FBB_D14 F2 DQ2_A FBB_D2 M2 DQ4_B FBB_CMD23 J11 CA6_A D
BYTE0

2
C3 VSS_8 VDD_8 P10 FBB_D13 E3 DQ6_A FBB_D0 P2 DQ7_B FBB_CMD0 J4 CA7_A
VSS_9 VDD_9 BYTE1 FBB_D15 DQ4_A FBB_D6 DQ5_B FBB_CMD2 CA8_A
C5 P5 B4 U3 J3
D1 VSS_10 VDD_10 V1 FBB_D11 B2 DQ0_A FBB_D7 V3 DQ2_B FBB_CMD10 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBB_D8 E2 DQ3_A FBB_D1 U4 DQ1_B FBB_CMD14 G10 CABI_n_A
D14 VSS_12 VDD_12 FBB_D9 A3 DQ5_A FBB_D5 U2 DQ0_B CKE_n_A
D3 VSS_13 DQ1_A DQ3_B N5
E11 VSS_14 FBB_EDC1 C2 FBB_EDC0 T2 TCK
VSS_15 FBVDDQ 30 FBB_EDC1 FBB_DBI1_N EDC0_A 30 FBB_EDC0 FBB_DBI0_N EDC0_B
E4 D2 R2 F10
VSS_16 30 FBB_DBI1_N DBI0_n_A 30 FBB_DBI0_N DBI0_n_B TDI
F1 N10
F12 VSS_17 FBB_WCKB01_P D4 FBB_WCK01_P R4 TDO
VSS_18 30 FBB_WCKB01_P FBB_WCKB01_N WCK_t_A 30 FBB_WCK01_P FBB_WCK01_N NC3
F14 B10 D5 R5 F5
VSS_19 VDDQ_1 30 FBB_WCKB01_N WCK_c_A 30 FBB_WCK01_N NC4 FBB_CMD5 TMS

T
F3 B5 L3
VSS_20 VDDQ_2 30 FBB_D[16..23] FBB_D23 FBB_CMD18 CA0_B
G1 C1 P13 M11
VSS_21 VDDQ_3 30 FBB_D[24..31] FBB_D22 DQ13_B FBB_CMD7 CA1_B
G12 C11 x16 x8 U13 M4
G14 VSS_22 VDDQ_4 C14 FBB_D25 B11 FBB_D16 M13 DQ11_B FBB_CMD20 L12 CA2_B
NC
G3 VSS_23 VDDQ_5 C4 FBB_D30 G13 DQ8_A FBB_D17 N13 DQ15_B FBB_CMD8 L5 CA3_B

M
NC
H11 VSS_24 VDDQ_6 E1 FBB_D31 E13 DQ15_A FBB_D20 U12 DQ14_B FBB_CMD16 L10 CA4_B
VSS_25 VDDQ_7 FBB_D28 DQ13_A NC BYTE2 FBB_D19 DQ10_B FBB_CMD21 CA5_B
H4 E14 F13 NC P12 K12
L11 VSS_26 VDDQ_8 F11 FBB_D29 E12 DQ14_A FBB_D21 V12 DQ12_B FBB_CMD19 K11 CA6_B
VSS_27 VDDQ_9 BYTE3 FBB_D27 DQ12_A
NC
FBB_D18 DQ9_B FBB_CMD6 CA7_B
L4 F4 B12 NC U11 K4
M1 VSS_28 VDDQ_10 H1 FBB_D24 B13 DQ10_A DQ8_B FBB_CMD4 K3 CA8_B
NC

rS
M12 VSS_29 VDDQ_11 H14 FBB_D26 A12 DQ11_A FBB_EDC2 T13 FBB_CMD9 K5 CA9_B J14FBB_ZQ_1_A RG160 1 OPT@ 2 121_0402_1%
NC
VSS_30 VDDQ_12 DQ9_A 30 FBB_EDC2 FBB_DBI2_N EDC1_B FBB_CMD17 CABI_n_B ZQ_A
M14 J13 R13 M10
VSS_31 VDDQ_13 FBB_EDC3 30 FBB_DBI2_N DBI1_n_B CKE_n_B
M3 J2 C13 GND K14FBB_ZQ_1_B RG161 1 OPT@ 2 121_0402_1%
VSS_32 VDDQ_14 30 FBB_EDC3 FBB_DBI3_N EDC1_A FBB_WCK23_P ZQ_B
N1 K13 D13 R11
VSS_33 VDDQ_15 30 FBB_DBI3_N DBI1_n_A NC 30 FBB_WCK23_P FBB_WCK23_N WCK_t_B
N12 K2 R10
VSS_34 VDDQ_16 FBB_WCKB23_P D11 30 FBB_WCK23_N WCK_c_B
N14 L1 NC
VSS_35 VDDQ_17 30 FBB_WCKB23_P FBB_WCKB23_N D10 NC1
N3 L14 NC
VSS_36 VDDQ_18 30 FBB_WCKB23_N NC2 FBB_CMD3
P11 N11 J1
VSS_37 VDDQ_19 RESET_n
P4 N4 MT61K256M32JE-14-A_FBGA180

fo
R1 VSS_38 VDDQ_20 P1 MT61K256M32JE-14-A_FBGA180
VSS_39 VDDQ_21 @
R12 P14 @
R14 VSS_40 VDDQ_22 T1 FBB_CLK0_N K10
VSS_41 VDDQ_23 30 FBB_CLK0_N CK_c
R3 T11 FBB_CLK0_P J10

C
T10
T12
T3
T5
VSS_42
VSS_43
VSS_44
VSS_45
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
T14
T4
U10
U5
follow CRB bit swap y 30 FBB_CLK0_P CK_t
NC5

NC6
G5

M5 C

U1 VSS_46 VDDQ_28
U14 VSS_47
VSS_48
nl
V11
V13 VSS_49 +1.8VS_AON
V2 VSS_50 +1.8VS_AON
V4 VSS_51 4 x 0402 1 uF
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
lO
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

VPP_1 @
A5
VPP_2 V10
VPP_3 1 1 1 1
V5
VPP_4
OPT@

OPT@

OPT@

OPT@
CG244

CG246

CG245

CG247

2 2 2 2
MT61K256M32JE-14-A_FBGA180
@
tia

FBVDDQ

1
en

RG162
1/16W_549_1%_0402
@

2
FBVDDQ 4 x 0603 10 uF FBVDDQ +FBB_VREFC_R 1 2 +FBB_VREFC
6 x 0603 22 uF +FBB_VREFC 40
AROUND DRAM 2 x 0603 10 uF
CLOSE TO DRAM CLOSE TO DRAM RG163
1 16 mil
18 x 0402 1 uF 931_0402_1%
fid

1
@ RG164 CG264
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1K_0402_1% 820P_0402_25V7
22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

1 1 1 1 1 1 1 1 1 1 1 1 @ @
2
1 1 1 1 1 1 2 2 2 2 2 2
2

B B
2
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

QG33
CG242

CG268

CG269

CG270

CG274

CG271

CG272

CG273

CG240

CG275

CG276

CG241

2 2 2 2 2 2 2 2 2 2 2 2 32,50 MEM_VREF_CTL
LSI1012XT1G_SC-89-3
on

2 2 2 2 2 2 1 1 1 1 1 1
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

@
3
CG256

CG257

CG254

CG255
CG1658

CG1659

CG1660

CG1661

CG1662

CG1663

CG1701

CG1702

Vgs(th)≤0.9V VREFC IS NOT USED IN

x16 CONFIGURATION
1K OHM PULL-DOWN IS
IN PLACE OF THE 1.33K
C

FBVDDQ
CLOSE TO DRAM CLOSE TO DRAM FOR RV1183
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

FBVDDQ
1 1 1 1 1 1
FC
330U_B2_2.5VM_R9M

1
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG265

CG248

CG253

CG251

CG250

CG252

+ 2 2 2 2 2 2

2
CG1569

LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GDDR6_B_[31_0]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y550
Date: Monday, November 29, 2021 Sheet 39 of 110
5 4 3 2 1
 5 4 3 2 1

UG7D UG7C
? ?
? ?
COMMON COMMON

FBVDDQ 30 FBB_CMD[28..52]
RG1347
UG7A FBB_CMD33 H3 K1 +FBB_B_VREFC 1 2 +FBB_VREFC
FBB_CMD45 CA0_A VREFC +FBB_VREFC 39
UG7B G11 0_0201_5%
A11 A1 FBB_CMD35 G4 CA1_A @
VSS_1 VDD_1 30 FBB_D[40..47] NORMAL CA2_A 1

1
A13 A14 NORMAL FBB_CMD46 H12 CG303
A2 VSS_2 VDD_2 E10 FBB_D47 G2 FBB_CMD36 H5 CA3_A RG1348 820P_0402_25V7
VSS_3 VDD_3 FBB_D40 DQ7_A 30 FBB_D[32..39] FBB_CMD43 CA4_A
A4 E5 B3 x16 x8 H10 1K_0402_1% @
B1 VSS_4 VDD_4 H13 FBB_D43 F2 DQ2_A FBB_D34 N2 FBB_CMD48 J12 CA5_A OPT@ 2
B14 VSS_5 VDD_5 H2 FBB_D46 E3 DQ6_A FBB_D36 P3 DQ6_B FBB_CMD47 J11 CA6_A

2
C10 VSS_6 VDD_6 L13 FBB_D42 B4 DQ4_A FBB_D37 M2 DQ4_B FBB_CMD34 J4 CA7_A
D VSS_7 VDD_7 BYTE5 FBB_D45 DQ0_A FBB_D38 DQ7_B FBB_CMD32 CA8_A D
C12 L2 B2 BYTE4 P2 J3
C3 VSS_8 VDD_8 P10 FBB_D44 E2 DQ3_A FBB_D33 U3 DQ5_B FBB_CMD37 J5 CA9_A
C5 VSS_9 VDD_9 P5 FBB_D41 A3 DQ5_A FBB_D35 V3 DQ2_B FBB_CMD44 G10 CABI_n_A
D1 VSS_10 VDD_10 V1 DQ1_A FBB_D32 U4 DQ1_B CKE_n_A
D12 VSS_11 VDD_11 V14 FBB_EDC5 C2 FBB_D39 U2 DQ0_B N5
VSS_12 VDD_12 30 FBB_EDC5 FBB_DBI5_N EDC0_A DQ3_B TCK
D14 D2
VSS_13 30 FBB_DBI5_N DBI0_n_A FBB_EDC4
D3 T2 F10
VSS_14 FBB_WCKB45_P 30 FBB_EDC4 FBB_DBI4_N EDC0_B TDI
E11 D4 R2 N10
VSS_15 FBVDDQ 30 FBB_WCKB45_P FBB_WCKB45_N WCK_t_A 30 FBB_DBI4_N DBI0_n_B TDO
E4 D5
VSS_16 30 FBB_WCKB45_N WCK_c_A FBB_WCK45_P
F1 R4 F5
VSS_17 30 FBB_WCK45_P FBB_WCK45_N NC3 FBB_CMD29 TMS
F12 R5 L3
VSS_18 30 FBB_D[56..63] 30 FBB_WCK45_N NC4 FBB_CMD52 CA0_B
F14 B10 x16 x8 M11
VSS_19 VDDQ_1 FBB_D63 30 FBB_D[48..55] FBB_D51 FBB_CMD40 CA1_B

T
F3 B5 B11 NC P13 M4
G1 VSS_20 VDDQ_2 C1 FBB_D59 G13 DQ8_A FBB_D48 U13 DQ13_B FBB_CMD50 L12 CA2_B
NC
G12 VSS_21 VDDQ_3 C11 FBB_D56 E13 DQ15_A FBB_D50 M13 DQ11_B FBB_CMD39 L5 CA3_B
VSS_22 VDDQ_4 FBB_D57 DQ13_A
NC BYTE6 FBB_D53 DQ15_B FBB_CMD42 CA4_B
G14 C14 BYTE7 F13 NC N13 L10
G3 VSS_23 VDDQ_5 C4 FBB_D62 E12 DQ14_A FBB_D54 U12 DQ14_B FBB_CMD49 K12 CA5_B

M
NC
H11 VSS_24 VDDQ_6 E1 FBB_D58 B12 DQ12_A FBB_D52 P12 DQ10_B FBB_CMD51 K11 CA6_B
NC
H4 VSS_25 VDDQ_7 E14 FBB_D60 B13 DQ10_A FBB_D49 V12 DQ12_B FBB_CMD28 K4 CA7_B
NC
L11 VSS_26 VDDQ_8 F11 FBB_D61 A12 DQ11_A FBB_D55 U11 DQ9_B FBB_CMD30 K3 CA8_B
NC
L4 VSS_27 VDDQ_9 F4 DQ9_A DQ8_B FBB_CMD38 K5 CA9_B J14FBB_ZQ_2_A RG165 1 OPT@ 2 121_0402_1%
M1 VSS_28 VDDQ_10 H1 FBB_EDC7 C13 FBB_EDC6 T13 FBB_CMD41 M10 CABI_n_B ZQ_A
GND
30 FBB_EDC7 30 FBB_EDC6

rS
M12 VSS_29 VDDQ_11 H14 FBB_DBI7_N D13 EDC1_A FBB_DBI6_N R13 EDC1_B CKE_n_B K14FBB_ZQ_2_B RG166 1 OPT@ 2 121_0402_1%
VSS_30 VDDQ_12 30 FBB_DBI7_N DBI1_n_A NC 30 FBB_DBI6_N DBI1_n_B ZQ_B
M14 J13
M3 VSS_31 VDDQ_13 J2 FBB_WCKB67_P D11 FBB_WCK67_P R11
NC
VSS_32 VDDQ_14 30 FBB_WCKB67_P FBB_WCKB67_N D10 NC1 30 FBB_WCK67_P FBB_WCK67_N WCK_t_B
N1 K13 NC R10
VSS_33 VDDQ_15 30 FBB_WCKB67_N NC2 30 FBB_WCK67_N WCK_c_B
N12 K2
N14 VSS_34 VDDQ_16 L1 FBB_CMD31 J1
VSS_35 VDDQ_17 RESET_n
N3 L14 MT61K256M32JE-14-A_FBGA180
P11 VSS_36 VDDQ_18 N11 MT61K256M32JE-14-A_FBGA180
VSS_37 VDDQ_19 @
P4 N4

fo
VSS_38 VDDQ_20 @
R1 P1 FBB_CLK1_N K10
VSS_39 VDDQ_21 30 FBB_CLK1_N CK_c
R12 P14 FBB_CLK1_P J10
R14
R3
T10
T12
VSS_40
VSS_41
VSS_42
VSS_43
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
T1
T11
T14
T4
follow CRB bit swap 30 FBB_CLK1_P CK_t
NC5

NC6
G5

M5

C T3 VSS_44 VDDQ_26 U10 C

T5
U1
U14
VSS_45
VSS_46
VSS_47
VDDQ_27
VDDQ_28
U5
y
VSS_48
nl
V11
V13 VSS_49 +1.8VS_AON
V2 VSS_50 +1.8VS_AON
VSS_51 MT61K256M32JE-14-A_FBGA180
V4 CLOSE TO DRAM 4 x 0402 1 uF
VSS_52 @
A10
lO
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

VPP_1 A5
VPP_2 V10
VPP_3 1 1 1 1
V5
VPP_4
OPT@

OPT@

OPT@

OPT@
CG309

CG308

CG310

CG311

2 2 2 2
MT61K256M32JE-14-A_FBGA180
@
tia
en

FBVDDQ 4 x 0603 10 uF
AROUND DRAM 6 x 0603 22 uF CLOSE TO DRAM FBVDDQ
2 x 0603 10 uF 18 x 0402 1 uF
CLOSE TO DRAM
fid
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

1 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
B B
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG306

CG296

CG294

CG295

CG299

CG298

CG297

CG300

CG304

CG302

CG301

CG305
on

2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG284

CG283

CG282

CG281
CG1664

CG1665

CG1666

CG1667

CG1668

CG1669

CG1703

CG1704

CLOSE TO DRAM FBVDDQ

CLOSE TO DRAM
FBVDDQ
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
FC

1 1 1 1 1 1
330U_B2_2.5VM_R9M

1
+
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG291

CG312

CG280

CG277

CG278

CG279

2 2 2 2 2 2

2
CG1570

LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GDDR6_B_[63_32]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y550
Date: Monday, November 29, 2021 Sheet 40 of 110
5 4 3 2 1
 5 4 3 2 1

UG8D
?
? UG8C
COMMON ?
?
FBVDDQ COMMON

31 FBC_CMD[0..24]
RG1349
A11 A1 UG8B FBC_CMD1 H3 K1 +FBC_A_VREFC 1 2+FBC_VREFC
A13 VSS_1 VDD_1 A14 UG8A FBC_CMD13 G11 CA0_A VREFC 0_0201_5%
A2 VSS_2 VDD_2 E10 NORMAL FBC_CMD12 G4 CA1_A @
VSS_3 VDD_3 CA2_A

1
A4 E5 FBC_CMD24 H12
VSS_4 VDD_4 31 FBC_D[8..15] NORMAL 31 FBC_D[0..7] CA3_A
B1 H13 x16 x8 FBC_CMD11 H5 RG1350
B14 VSS_5 VDD_5 H2 FBC_D11 G2 FBC_D3 N2 FBC_CMD15 H10 CA4_A 1K_0402_1%
C10 VSS_6 VDD_6 L13 FBC_D15 B3 DQ7_A FBC_D4 P3 DQ6_B FBC_CMD22 J12 CA5_A OPT@
C12 VSS_7 VDD_7 L2 FBC_D14 F2 DQ2_A FBC_D1 M2 DQ4_B FBC_CMD23 J11 CA6_A

2
D
C3 VSS_8 VDD_8 P10 FBC_D13 E3 DQ6_A FBC_D7 P2 DQ7_B FBC_CMD0 J4 CA7_A D
VSS_9 VDD_9 BYTE1 FBC_D9 DQ4_A FBC_D2 DQ5_B FBC_CMD2 CA8_A
C5 P5 B4 BYTE0 U3 J3
D1 VSS_10 VDD_10 V1 FBC_D10 B2 DQ0_A FBC_D6 V3 DQ2_B FBC_CMD10 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBC_D12 E2 DQ3_A FBC_D5 U4 DQ1_B FBC_CMD14 G10 CABI_n_A
D14 VSS_12 VDD_12 FBC_D8 A3 DQ5_A FBC_D0 U2 DQ0_B CKE_n_A
D3 VSS_13 DQ1_A DQ3_B N5
E11 VSS_14 FBC_EDC1 C2 FBC_EDC0 T2 TCK
VSS_15 FBVDDQ 31 FBC_EDC1 FBC_DBI1_N EDC0_A 31 FBC_EDC0 FBC_DBI0_N EDC0_B
E4 D2 R2 F10
VSS_16 31 FBC_DBI1_N DBI0_n_A 31 FBC_DBI0_N DBI0_n_B TDI
F1 N10
F12 VSS_17 FBC_WCKB01_P D4 FBC_WCK01_P R4 TDO
VSS_18 31 FBC_WCKB01_P FBC_WCKB01_N WCK_t_A 31 FBC_WCK01_P FBC_WCK01_N NC3
F14 B10 D5 R5 F5
VSS_19 VDDQ_1 31 FBC_WCKB01_N WCK_c_A 31 FBC_WCK01_N NC4 FBC_CMD5 TMS
F3 B5 L3
VSS_20 VDDQ_2 31 FBC_D[16..23] FBC_D20 FBC_CMD18 CA0_B

T
G1 C1 P13 M11
VSS_21 VDDQ_3 31 FBC_D[24..31] FBC_D21 DQ13_B FBC_CMD7 CA1_B
G12 C11 x16 x8 U13 M4
G14 VSS_22 VDDQ_4 C14 FBC_D25 B11 FBC_D23 M13 DQ11_B FBC_CMD20 L12 CA2_B
VSS_23 VDDQ_5 FBC_D28 DQ8_A NC BYTE2 FBC_D16 DQ15_B FBC_CMD8 CA3_B
G3 C4 G13 NC N13 L5
H11 VSS_24 VDDQ_6 E1 FBC_D29 E13 DQ15_A FBC_D17 U12 DQ14_B FBC_CMD16 L10 CA4_B
BYTE3

M
NC
H4 VSS_25 VDDQ_7 E14 FBC_D26 F13 DQ13_A FBC_D22 P12 DQ10_B FBC_CMD21 K12 CA5_B
NC
L11 VSS_26 VDDQ_8 F11 FBC_D27 E12 DQ14_A FBC_D18 V12 DQ12_B FBC_CMD19 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 FBC_D24 B12 DQ12_A FBC_D19 U11 DQ9_B FBC_CMD6 K4 CA7_B
NC
M1 VSS_28 VDDQ_10 H1 FBC_D30 B13 DQ10_A DQ8_B FBC_CMD4 K3 CA8_B
NC
M12 VSS_29 VDDQ_11 H14 FBC_D31 A12 DQ11_A FBC_EDC2 T13 FBC_CMD9 K5 CA9_B J14FBC_ZQ_1_A RG167 1 OPT@ 2 121_0402_1%
NC
31 FBC_EDC2

rS
M14 VSS_30 VDDQ_12 J13 DQ9_A FBC_DBI2_N R13 EDC1_B FBC_CMD17 M10 CABI_n_B ZQ_A
VSS_31 VDDQ_13 FBC_EDC3 31 FBC_DBI2_N DBI1_n_B CKE_n_B
M3 J2 C13 GND K14FBC_ZQ_1_B RG168 1 OPT@ 2 121_0402_1%
VSS_32 VDDQ_14 31 FBC_EDC3 FBC_DBI3_N EDC1_A FBC_WCK23_P ZQ_B
N1 K13 D13 R11
VSS_33 VDDQ_15 31 FBC_DBI3_N DBI1_n_A NC 31 FBC_WCK23_P FBC_WCK23_N WCK_t_B
N12 K2 R10
VSS_34 VDDQ_16 FBC_WCKB23_P D11 31 FBC_WCK23_N WCK_c_B
N14 L1 NC
VSS_35 VDDQ_17 31 FBC_WCKB23_P FBC_WCKB23_N D10 NC1
N3 L14 NC
VSS_36 VDDQ_18 31 FBC_WCKB23_N NC2 FBC_CMD3
P11 N11 J1
VSS_37 VDDQ_19 RESET_n
P4 N4 MT61K256M32JE-14-A_FBGA180
R1 VSS_38 VDDQ_20 P1 MT61K256M32JE-14-A_FBGA180

fo
VSS_39 VDDQ_21 @
R12 P14 @
R14 VSS_40 VDDQ_22 T1 FBC_CLK0_N K10
VSS_41 VDDQ_23 31 FBC_CLK0_N CK_c
R3 T11 FBC_CLK0_P J10
T10
T12
T3
T5
VSS_42
VSS_43
VSS_44
VSS_45
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
T14
T4
U10
U5
follow CRB bit swap 31 FBC_CLK0_P CK_t
NC5

NC6
G5

M5
C C
U1
U14
V11
VSS_46
VSS_47
VSS_48
VDDQ_28
y
VSS_49
nl
V13 +1.8VS_AON
V2 VSS_50 +1.8VS_AON
V4 VSS_51 4 x 0402 1 uF
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

VPP_1 @
A5
lO

VPP_2 V10
VPP_3 1 1 1 1
V5
VPP_4
OPT@

OPT@

OPT@

OPT@
CG317

CG318

CG319

CG320

MT61K256M32JE-14-A_FBGA180
2 2 2 2
@
tia

FBVDDQ

1
en

RG169
1/16W_549_1%_0402
@

2
FBVDDQ 4 x 0603 10 uF +FBC_VREFC_R 1 2 +FBC_VREFC
6 x 0603 22 uF +FBC_VREFC 42
AROUND DRAM CLOSE TO DRAM FBVDDQ RG171 16 mil
1
2 x 0603 10 uF
CLOSE TO DRAM 931_0402_1% 1
18 x 0402 1 uF @ RG170 CG336
fid

1K_0402_1% 820P_0402_25V7
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

@ @
2
1 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
2

2 QG34
B 32,50 MEM_VREF_CTL B
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

LSI1012XT1G_SC-89-3
CG315

CG340

CG341

CG342

CG345

CG344

CG343

CG346

CG313

CG347

CG348

CG314

2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

@
on

3
CG327

CG329

CG326

CG328
CG1670

CG1671

CG1672

CG1673

CG1674

CG1675

CG1705

CG1706

Vgs(th)≤0.9V VREFC IS NOT USED IN

x16 CONFIGURATION
1K OHM PULL-DOWN IS
IN PLACE OF THE 1.33K
C

CLOSE TO DRAM FOR RV1189

FBVDDQ
FBVDDQ CLOSE TO DRAM
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
330U_B2_2.5VM_R9M

1
FC

1 1 1 1 1 1
+
CG325
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG337

CG321

CG323

CG322

CG324

2 2 2 2 2 2 2
CG1571

LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GDDR6_C_[31_0]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y550
Date: Monday, November 29, 2021 Sheet 41 of 110
5 4 3 2 1
 5 4 3 2 1

UG9D UG9C
? ?
? ?
COMMON COMMON

FBVDDQ 31 FBC_CMD[28..52]
RG1351
UG9A FBC_CMD33 H3 K1 +FBC_B_VREFC 1 2+FBC_VREFC
FBC_CMD45 CA0_A VREFC +FBC_VREFC 41
UG9B G11 0_0201_5%
A11 A1 FBC_CMD35 G4 CA1_A @
VSS_1 VDD_1 31 FBC_D[40..47] NORMAL CA2_A 1

1
A13 A14 NORMAL FBC_CMD46 H12 CG376
A2 VSS_2 VDD_2 E10 FBC_D47 G2 FBC_CMD36 H5 CA3_A RG1352 820P_0402_25V7
VSS_3 VDD_3 FBC_D40 DQ7_A 31 FBC_D[32..39] FBC_CMD43 CA4_A
A4 E5 B3 x16 x8 H10 1K_0402_1% @
B1 VSS_4 VDD_4 H13 FBC_D43 F2 DQ2_A FBC_D35 N2 FBC_CMD48 J12 CA5_A 2
VSS_5 VDD_5 BYTE5 FBC_D42 DQ6_A FBC_D39 DQ6_B FBC_CMD47 CA6_A
OPT@
B14 H2 E3 P3 J11

2
D
C10 VSS_6 VDD_6 L13 FBC_D45 B4 DQ4_A FBC_D38 M2 DQ4_B FBC_CMD34 J4 CA7_A D
VSS_7 VDD_7 FBC_D46 DQ0_A BYTE4 FBC_D37 DQ7_B FBC_CMD32 CA8_A
C12 L2 B2 P2 J3
C3 VSS_8 VDD_8 P10 FBC_D41 E2 DQ3_A FBC_D36 U3 DQ5_B FBC_CMD37 J5 CA9_A
C5 VSS_9 VDD_9 P5 FBC_D44 A3 DQ5_A FBC_D32 V3 DQ2_B FBC_CMD44 G10 CABI_n_A
D1 VSS_10 VDD_10 V1 DQ1_A FBC_D33 U4 DQ1_B CKE_n_A
D12 VSS_11 VDD_11 V14 FBC_EDC5 C2 FBC_D34 U2 DQ0_B N5
VSS_12 VDD_12 31 FBC_EDC5 FBC_DBI5_N EDC0_A DQ3_B TCK
D14 D2
VSS_13 31 FBC_DBI5_N DBI0_n_A FBC_EDC4
D3 T2 F10
VSS_14 FBC_WCKB45_P 31 FBC_EDC4 FBC_DBI4_N EDC0_B TDI
E11 D4 R2 N10
VSS_15 FBVDDQ 31 FBC_WCKB45_P FBC_WCKB45_N WCK_t_A 31 FBC_DBI4_N DBI0_n_B TDO
E4 D5
VSS_16 31 FBC_WCKB45_N WCK_c_A FBC_WCK45_P
F1 R4 F5
VSS_17 31 FBC_WCK45_P FBC_WCK45_N NC3 FBC_CMD29 TMS
F12 R5 L3
VSS_18 31 FBC_D[56..63] 31 FBC_WCK45_N NC4 FBC_CMD52 CA0_B

T
F14 B10 x16 x8 M11
VSS_19 VDDQ_1 FBC_D62 31 FBC_D[48..55] FBC_D52 FBC_CMD40 CA1_B
F3 B5 B11 NC P13 M4
G1 VSS_20 VDDQ_2 C1 FBC_D56 G13 DQ8_A FBC_D54 U13 DQ13_B FBC_CMD50 L12 CA2_B
NC
G12 VSS_21 VDDQ_3 C11 FBC_D57 E13 DQ15_A FBC_D50 M13 DQ11_B FBC_CMD39 L5 CA3_B
VSS_22 VDDQ_4 FBC_D59 DQ13_A
NC BYTE6 FBC_D53 DQ15_B FBC_CMD42 CA4_B
G14 C14 BYTE7 F13 N13 L10

M
NC
G3 VSS_23 VDDQ_5 C4 FBC_D63 E12 DQ14_A FBC_D48 U12 DQ14_B FBC_CMD49 K12 CA5_B
NC
H11 VSS_24 VDDQ_6 E1 FBC_D61 B12 DQ12_A FBC_D55 P12 DQ10_B FBC_CMD51 K11 CA6_B
NC
H4 VSS_25 VDDQ_7 E14 FBC_D58 B13 DQ10_A FBC_D51 V12 DQ12_B FBC_CMD28 K4 CA7_B
NC
L11 VSS_26 VDDQ_8 F11 FBC_D60 A12 DQ11_A FBC_D49 U11 DQ9_B FBC_CMD30 K3 CA8_B
NC
L4 VSS_27 VDDQ_9 F4 DQ9_A DQ8_B FBC_CMD38 K5 CA9_B J14FBC_ZQ_2_A RG172 1 OPT@ 2 121_0402_1%

rS
M1 VSS_28 VDDQ_10 H1 FBC_EDC7 C13 FBC_EDC6 T13 FBC_CMD41 M10 CABI_n_B ZQ_A
GND
VSS_29 VDDQ_11 31 FBC_EDC7 FBC_DBI7_N EDC1_A 31 FBC_EDC6 FBC_DBI6_N EDC1_B CKE_n_B
M12 H14 D13 R13 K14FBC_ZQ_2_B RG173 1 OPT@ 2 121_0402_1%
VSS_30 VDDQ_12 31 FBC_DBI7_N DBI1_n_A NC 31 FBC_DBI6_N DBI1_n_B ZQ_B
M14 J13
M3 VSS_31 VDDQ_13 J2 FBC_WCKB67_P D11 FBC_WCK67_P R11
NC
VSS_32 VDDQ_14 31 FBC_WCKB67_P FBC_WCKB67_N D10 NC1 31 FBC_WCK67_P FBC_WCK67_N WCK_t_B
N1 K13 NC R10
VSS_33 VDDQ_15 31 FBC_WCKB67_N NC2 31 FBC_WCK67_N WCK_c_B
N12 K2
N14 VSS_34 VDDQ_16 L1 FBC_CMD31 J1
VSS_35 VDDQ_17 RESET_n
N3 L14 MT61K256M32JE-14-A_FBGA180
P11 VSS_36 VDDQ_18 N11 MT61K256M32JE-14-A_FBGA180

fo
VSS_37 VDDQ_19 @
P4 N4 @
R1 VSS_38 VDDQ_20 P1 FBC_CLK1_N K10 CK_c
R12
R14
R3
T10
VSS_39
VSS_40
VSS_41
VSS_42
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
P14
T1
T11
T14
follow CRB bit swap 31
31
FBC_CLK1_N
FBC_CLK1_P
FBC_CLK1_P J10
CK_t
NC5
G5

M5
C T12 VSS_43 VDDQ_25 T4 NC6 C
T3
T5
U1
VSS_44
VSS_45
VSS_46
VDDQ_26
VDDQ_27
VDDQ_28
U10
U5
y
VSS_47
nl
U14
V11 VSS_48
V13 VSS_49 +1.8VS_AON
V2 VSS_50 +1.8VS_AON
VSS_51 MT61K256M32JE-14-A_FBGA180
V4 CLOSE TO DRAM 4 x 0402 1 uF
VSS_52 @
lO

A10
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

VPP_1 A5
VPP_2 V10
VPP_3 1 1 1 1
V5
VPP_4
OPT@

OPT@

OPT@

OPT@
CG381

CG382

CG383

CG384

2 2 2 2
MT61K256M32JE-14-A_FBGA180
@
tia
en

FBVDDQ 4 x 0603 10 uF
AROUND DRAM 6 x 0603 22 uF CLOSE TO DRAM FBVDDQ
fid

2 x 0603 10 uF 18 x 0402 1 uF
CLOSE TO DRAM
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

B 1 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 B
on
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG379

CG370

CG367

CG368

CG372

CG371

CG369

CG373

CG377

CG374

CG375

CG378

2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG392

CG393

CG391

CG390
CG1676

CG1677

CG1678

CG1679

CG1680

CG1681

CG1707

CG1708

CLOSE TO DRAM
FBVDDQ
CLOSE TO DRAM
FBVDDQ
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
FC
330U_B2_2.5VM_R9M

1 1 1 1 1 1 1
+
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CG364

CG385

CG389

CG386

CG387

CG388

2 2 2 2 2 2
2
@
CG1572

LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GDDR6_C_[63_32]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y550
Date: Monday, November 29, 2021 Sheet 42 of 110
5 4 3 2 1
 5 4 3 2 1

UG13D
?
? UG13C
COMMON ?
?
FBVDDQ COMMON

31 FBD_CMD[0..24]
RG1353
A11 A1 UG13B FBD_CMD1 H3 K1 +FBD_A_VREFC 1 2 +FBD_VREFC
A13 VSS_1 VDD_1 A14 UG13A FBD_CMD13 G11 CA0_A VREFC 0_0201_5%
A2 VSS_2 VDD_2 E10 NORMAL FBD_CMD12 G4 CA1_A @
VSS_3 VDD_3 CA2_A

1
A4 E5 FBD_CMD24 H12
VSS_4 VDD_4 31 FBD_D[8..15] NORMAL 31 FBD_D[0..7] CA3_A
B1 H13 x16 x8 FBD_CMD11 H5 RG1354
B14 VSS_5 VDD_5 H2 FBD_D11 G2 FBD_D2 N2 FBD_CMD15 H10 CA4_A 1K_0402_1%
C10 VSS_6 VDD_6 L13 FBD_D15 B3 DQ7_A FBD_D3 P3 DQ6_B FBD_CMD22 J12 CA5_A NON_E3@
C12 VSS_7 VDD_7 L2 FBD_D12 F2 DQ2_A FBD_D1 M2 DQ4_B FBD_CMD23 J11 CA6_A
BYTE0

2
D
C3 VSS_8 VDD_8 P10 FBD_D13 E3 DQ6_A FBD_D0 P2 DQ7_B FBD_CMD0 J4 CA7_A D
VSS_9 VDD_9 BYTE1 FBD_D14 DQ4_A FBD_D4 DQ5_B FBD_CMD2 CA8_A
C5 P5 B4 U3 J3
D1 VSS_10 VDD_10 V1 FBD_D9 B2 DQ0_A FBD_D6 V3 DQ2_B FBD_CMD10 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBD_D8 E2 DQ3_A FBD_D7 U4 DQ1_B FBD_CMD14 G10 CABI_n_A
D14 VSS_12 VDD_12 FBD_D10 A3 DQ5_A FBD_D5 U2 DQ0_B CKE_n_A
D3 VSS_13 DQ1_A DQ3_B N5
E11 VSS_14 FBD_EDC1 C2 FBD_EDC0 T2 TCK
VSS_15 FBVDDQ 31 FBD_EDC1 FBD_DBI1_N EDC0_A 31 FBD_EDC0 FBD_DBI0_N EDC0_B
E4 D2 R2 F10
VSS_16 31 FBD_DBI1_N DBI0_n_A 31 FBD_DBI0_N DBI0_n_B TDI
F1 N10
F12 VSS_17 FBD_WCKB01_P D4 FBD_WCK01_P R4 TDO
VSS_18 31 FBD_WCKB01_P FBD_WCKB01_N WCK_t_A 31 FBD_WCK01_P FBD_WCK01_N NC3
F14 B10 D5 R5 F5
VSS_19 VDDQ_1 31 FBD_WCKB01_N WCK_c_A 31 FBD_WCK01_N NC4 FBD_CMD5 TMS
F3 B5 L3
VSS_20 VDDQ_2 31 FBD_D[16..23] FBD_D23 FBD_CMD18 CA0_B

T
G1 C1 P13 M11
VSS_21 VDDQ_3 31 FBD_D[24..31] FBD_D21 DQ13_B FBD_CMD7 CA1_B
G12 C11 x16 x8 U13 M4
G14 VSS_22 VDDQ_4 C14 FBD_D26 B11 FBD_D19 M13 DQ11_B FBD_CMD20 L12 CA2_B
NC
G3 VSS_23 VDDQ_5 C4 FBD_D29 G13 DQ8_A FBD_D17 N13 DQ15_B FBD_CMD8 L5 CA3_B
VSS_24 VDDQ_6 FBD_D31 DQ15_A NC BYTE2 FBD_D20 DQ14_B FBD_CMD16 CA4_B
H11 E1 BYTE3 E13 U12 L10

M
NC
H4 VSS_25 VDDQ_7 E14 FBD_D30 F13 DQ13_A FBD_D18 P12 DQ10_B FBD_CMD21 K12 CA5_B
NC
L11 VSS_26 VDDQ_8 F11 FBD_D28 E12 DQ14_A FBD_D22 V12 DQ12_B FBD_CMD19 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 FBD_D24 B12 DQ12_A FBD_D16 U11 DQ9_B FBD_CMD6 K4 CA7_B
NC
M1 VSS_28 VDDQ_10 H1 FBD_D27 B13 DQ10_A DQ8_B FBD_CMD4 K3 CA8_B
NC
M12 VSS_29 VDDQ_11 H14 FBD_D25 A12 DQ11_A FBD_EDC2 T13 FBD_CMD9 K5 CA9_B J14FBD_ZQ_1_A RG213 1 NON_E3@
2 121_0402_1%
NC
31 FBD_EDC2

rS
M14 VSS_30 VDDQ_12 J13 DQ9_A FBD_DBI2_N R13 EDC1_B FBD_CMD17 M10 CABI_n_B ZQ_A
VSS_31 VDDQ_13 FBD_EDC3 31 FBD_DBI2_N DBI1_n_B CKE_n_B
M3 J2 C13 GND K14FBD_ZQ_1_B RG214 1 NON_E3@
2 121_0402_1%
VSS_32 VDDQ_14 31 FBD_EDC3 FBD_DBI3_N EDC1_A FBD_WCK23_P ZQ_B
N1 K13 D13 R11
VSS_33 VDDQ_15 31 FBD_DBI3_N DBI1_n_A NC 31 FBD_WCK23_P FBD_WCK23_N WCK_t_B
N12 K2 R10
VSS_34 VDDQ_16 FBD_WCKB23_P D11 31 FBD_WCK23_N WCK_c_B
N14 L1 NC
VSS_35 VDDQ_17 31 FBD_WCKB23_P FBD_WCKB23_N D10 NC1
N3 L14 NC
VSS_36 VDDQ_18 31 FBD_WCKB23_N NC2 FBD_CMD3
P11 N11 J1
VSS_37 VDDQ_19 RESET_n
P4 N4 MT61K256M32JE-14-A_FBGA180
R1 VSS_38 VDDQ_20 P1 MT61K256M32JE-14-A_FBGA180

fo
VSS_39 VDDQ_21 @
R12 P14 @
R14 VSS_40 VDDQ_22 T1 FBD_CLK0_N K10
VSS_41 VDDQ_23 31 FBD_CLK0_N CK_c
R3 T11 FBD_CLK0_P J10
T10
T12
T3
T5
VSS_42
VSS_43
VSS_44
VSS_45
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
T14
T4
U10
U5
follow CRB bit swap 31 FBD_CLK0_P CK_t
NC5

NC6
G5

M5
C C
U1
U14
V11
VSS_46
VSS_47
VSS_48
VDDQ_28
y
VSS_49
nl
V13 +1.8VS_AON
V2 VSS_50 +1.8VS_AON
V4 VSS_51 4 x 0402 1 uF
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
VPP_1 @
A5
lO
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

VPP_2 V10
VPP_3 1 1 1 1
V5
VPP_4
NON_E3@

NON_E3@

NON_E3@

NON_E3@

MT61K256M32JE-14-A_FBGA180
2 2 2 2
CG551

CG552

CG553

CG554

@
tia

FBVDDQ

1
en

RG210
1/16W_549_1%_0402
@

2
+FBD_VREFC_R 1 2 +FBD_VREFC
4 x 0603 10 uF +FBD_VREFC 44
FBVDDQ RG211 16 mil

1
AROUND DRAM 6 x 0603 22 uF CLOSE TO DRAM FBVDDQ 931_0402_1% 1
2 x 0603 10 uF 18 x 0402 1 uF
CLOSE TO DRAM @ RG212 CG555
fid

1K_0402_1% 820P_0402_25V7
1

@ @
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

2
2

1 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
2 QG36
B 32,50 MEM_VREF_CTL B
LSI1012XT1G_SC-89-3
@
CG769

CG770

CG771

CG772

CG773

CG774

CG775

CG776

CG777

CG778

CG779

CG780
NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@
on

2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

Vgs(th)≤0.9V VREFC IS NOT USED IN

CG765

CG766

CG767

CG768
CG1682

CG1683

CG1684

CG1685

CG1686

CG1687

CG1709

CG1710

x16 CONFIGURATION
1K OHM PULL-DOWN IS
IN PLACE OF THE 1.33K
C

FOR RV1189
CLOSE TO DRAM
FBVDDQ
CLOSE TO DRAM
FBVDDQ
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
FC
330U_B2_2.5VM_R9M

1 1 1 1 1 1 1
+
CG781

CG782

CG783

CG784

CG785

CG786
NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

2 2 2 2 2 2
2
@
CG1573

LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GDDR6_C_[31_0]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y550
Date: Monday, November 29, 2021 Sheet 43 of 110
5 4 3 2 1
 5 4 3 2 1

UG14D
? UG14C
? ?
COMMON ?
COMMON
FBVDDQ
31 FBD_CMD[28..52]
UG14A RG1355
UG14B FBD_CMD33 H3 K1 +FBD_B_VREFC 1 2 +FBD_VREFC
FBD_CMD45 CA0_A VREFC +FBD_VREFC 43
A11 A1 NORMAL G11 0_0201_5%
VSS_1 VDD_1 31 FBD_D[40..47] FBD_CMD35 CA1_A
A13 A14 NORMAL G4 @ 1
VSS_2 VDD_2 CA2_A

1
A2 E10 FBD_D47 G2 FBD_CMD46 H12 CG657
VSS_3 VDD_3 FBD_D40 DQ7_A 31 FBD_D[32..39] FBD_CMD36 CA3_A
A4 E5 B3 x16 x8 H5 RG1356 820P_0402_25V7
B1 VSS_4 VDD_4 H13 FBD_D41 F2 DQ2_A FBD_D38 N2 FBD_CMD43 H10 CA4_A 1K_0402_1% @
B14 VSS_5 VDD_5 H2 FBD_D43 E3 DQ6_A FBD_D34 P3 DQ6_B FBD_CMD48 J12 CA5_A NON_E3@ 2
D
C10 VSS_6 VDD_6 L13 FBD_D42 B4 DQ4_A FBD_D37 M2 DQ4_B FBD_CMD47 J11 CA6_A D
BYTE5

2
C12 VSS_7 VDD_7 L2 FBD_D44 B2 DQ0_A FBD_D39 P2 DQ7_B FBD_CMD34 J4 CA7_A
VSS_8 VDD_8 FBD_D46 DQ3_A BYTE4 FBD_D35 DQ5_B FBD_CMD32 CA8_A
C3 P10 E2 U3 J3
C5 VSS_9 VDD_9 P5 FBD_D45 A3 DQ5_A FBD_D33 V3 DQ2_B FBD_CMD37 J5 CA9_A
D1 VSS_10 VDD_10 V1 DQ1_A FBD_D36 U4 DQ1_B FBD_CMD44 G10 CABI_n_A
D12 VSS_11 VDD_11 V14 FBD_EDC5 C2 FBD_D32 U2 DQ0_B CKE_n_A
VSS_12 VDD_12 31 FBD_EDC5 FBD_DBI5_N EDC0_A DQ3_B
D14 D2 N5
VSS_13 31 FBD_DBI5_N DBI0_n_A FBD_EDC4 TCK
D3 T2
VSS_14 FBD_WCKB45_P 31 FBD_EDC4 FBD_DBI4_N EDC0_B
E11 D4 R2 F10
VSS_15 FBVDDQ 31 FBD_WCKB45_P FBD_WCKB45_N WCK_t_A 31 FBD_DBI4_N DBI0_n_B TDI
E4 D5 N10
VSS_16 31 FBD_WCKB45_N WCK_c_A FBD_WCK45_P TDO
F1 R4
VSS_17 31 FBD_WCK45_P FBD_WCK45_N NC3
F12 R5 F5
VSS_18 31 FBD_D[56..63] 31 FBD_WCK45_N NC4 FBD_CMD29 TMS

T
F14 B10 x16 x8 L3
VSS_19 VDDQ_1 FBD_D61 31 FBD_D[48..55] FBD_D52 FBD_CMD52 CA0_B
F3 B5 B11 NC P13 M11
G1 VSS_20 VDDQ_2 C1 FBD_D57 G13 DQ8_A FBD_D51 U13 DQ13_B FBD_CMD40 M4 CA1_B
NC
G12 VSS_21 VDDQ_3 C11 FBD_D60 E13 DQ15_A FBD_D53 M13 DQ11_B FBD_CMD50 L12 CA2_B
VSS_22 VDDQ_4 FBD_D59 DQ13_A
NC BYTE6 FBD_D54 DQ15_B FBD_CMD39 CA3_B
G14 C14 F13 N13 L5

M
NC
G3 VSS_23 VDDQ_5 C4 FBD_D63 E12 DQ14_A FBD_D50 U12 DQ14_B FBD_CMD42 L10 CA4_B
VSS_24 VDDQ_6 BYTE7 FBD_D62 DQ12_A
NC
FBD_D55 DQ10_B FBD_CMD49 CA5_B
H11 E1 B12 NC P12 K12
H4 VSS_25 VDDQ_7 E14 FBD_D58 B13 DQ10_A FBD_D48 V12 DQ12_B FBD_CMD51 K11 CA6_B
NC
L11 VSS_26 VDDQ_8 F11 FBD_D56 A12 DQ11_A FBD_D49 U11 DQ9_B FBD_CMD28 K4 CA7_B
NC
L4 VSS_27 VDDQ_9 F4 DQ9_A DQ8_B FBD_CMD30 K3 CA8_B

rS
M1 VSS_28 VDDQ_10 H1 FBD_EDC7 C13 FBD_EDC6 T13 FBD_CMD38 K5 CA9_B J14FBD_ZQ_2_A RG215 1 NON_E3@
2 121_0402_1%
GND
VSS_29 VDDQ_11 31 FBD_EDC7 FBD_DBI7_N EDC1_A 31 FBD_EDC6 FBD_DBI6_N EDC1_B FBD_CMD41 CABI_n_B ZQ_A
M12 H14 D13 R13 M10
VSS_30 VDDQ_12 31 FBD_DBI7_N DBI1_n_A 31 FBD_DBI6_N DBI1_n_B CKE_n_B
M14 J13 NC K14FBD_ZQ_2_B RG216 1 NON_E3@
2 121_0402_1%
M3 VSS_31 VDDQ_13 J2 FBD_WCKB67_P D11 FBD_WCK67_P R11 ZQ_B
NC
VSS_32 VDDQ_14 31 FBD_WCKB67_P FBD_WCKB67_N D10 NC1 31 FBD_WCK67_P FBD_WCK67_N WCK_t_B
N1 K13 NC R10
VSS_33 VDDQ_15 31 FBD_WCKB67_N NC2 31 FBD_WCK67_N WCK_c_B
N12 K2
N14 VSS_34 VDDQ_16 L1
N3 VSS_35 VDDQ_17 L14 MT61K256M32JE-14-A_FBGA180 FBD_CMD31 J1
VSS_36 VDDQ_18 RESET_n
P11 N11 MT61K256M32JE-14-A_FBGA180

fo
VSS_37 VDDQ_19 @
P4 N4 @
R1 VSS_38 VDDQ_20 P1
R12 VSS_39 VDDQ_21 P14 FBD_CLK1_N K10 CK_c
R14
R3
T10
T12
VSS_40
VSS_41
VSS_42
VSS_43
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
T1
T11
T14
T4
follow CRB bit swap 31
31
FBD_CLK1_N
FBD_CLK1_P
FBD_CLK1_P J10
CK_t
NC5
G5

M5
C C
T3
T5
U1
VSS_44
VSS_45
VSS_46
VDDQ_26
VDDQ_27
VDDQ_28
U10
U5
y NC6

VSS_47
nl
U14
V11 VSS_48 +1.8VS_AON
V13 VSS_49
V2 VSS_50 +1.8VS_AON 4 x 0402 1 uF
VSS_51 CLOSE TO DRAM
V4 MT61K256M32JE-14-A_FBGA180
VSS_52
lO

@
A10
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

VPP_1 A5
VPP_2 1 1 1 1
V10
VPP_3 V5
VPP_4
NON_E3@

NON_E3@

NON_E3@

NON_E3@

2 2 2 2
CG1721

CG1722

CG1723

CG1780

MT61K256M32JE-14-A_FBGA180
@
tia
en
fid

B 4 x 0603 10 uF B
FBVDDQ
AROUND DRAM 6 x 0603 22 uF CLOSE TO DRAM FBVDDQ
on

2 x 0603 10 uF 18 x 0402 1 uF
CLOSE TO DRAM
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402
22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

22U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

10U_6.3V_M_X6S_0603

1 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
C
CG799

CG800

CG801

CG802

CG803

CG804

CG805

CG806

CG807

CG808

CG809

CG810
NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
CG1689
NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@
CG795

CG796

CG797

CG798
CG1688

CG1690

CG1691

CG1692

CG1693

CG1711

CG1712

FC

FBVDDQ
CLOSE TO DRAM CLOSE TO DRAM
1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

1U_6.3V_K_X6S_0402

FBVDDQ
1 1 1 1 1 1
LC
330U_B2_2.5VM_R9M

1
CG811

CG812

CG813

CG814

CG815

CG816
NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

NON_E3@

+ 2 2 2 2 2 2

2
@
CG1574

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GDDR6_C_[63_32]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y550
Date: Monday, November 29, 2021 Sheet 44 of 110
5 4 3 2 1
 5 4 3 2 1

1.2V_MUX VDD12 VDD33

VDD33
CPU_EDP_TX0_P CV47 1 2 0.1u_0201_10V6K CPU_EDP_TX0_C_P VDD33 LV111 1 2 HCB1005PF-800T23_2P

0.01U_10V_K_X5R_0201

0.01U_10V_K_X5R_0201

0.1u_0201_10V6K
7 CPU_EDP_TX0_P

CV67

CV72

CV68

CV71
0.1u_0201_10V6K
CPU_EDP_TX0_N CV48 1 2 0.1u_0201_10V6K CPU_EDP_TX0_C_N VDD33 +3VS
7 CPU_EDP_TX0_N VDD12 2 1 1 2

0.01U_10V_K_X5R_0201

0.01U_10V_K_X5R_0201

0.1u_0201_10V6K
CPU_EDP_TX1_P CPU_EDP_TX1_C_P

CV200

CV201

CV202

CV203
CV52 1 2 0.1u_0201_10V6K VDD33 eDP MUX

0.1u_0201_10V6K
7 CPU_EDP_TX1_P
2

VDD12 RV852 RV121 1 @ 2 0_5%_0603

CPU_EDP_TX1_N 1 2 0.1u_0201_10V6K CPU_EDP_TX1_C_N Y570:SA0000BCH00 (PS8361QFN66GTR)
CV50 2 1 1 2
7 CPU_EDP_TX1_N
@
Y570P/Y770:SA0000AQK10 (PS8461EQFN66GTR) 1 2 2 1
CPU_EDP_TX2_P CV55 1 2 0.1u_0201_10V6K CPU_EDP_TX2_C_P 0_0201_5%
7 CPU_EDP_TX2_P 会会会A3 8461E
1

CPU_EDP_TX2_N CV56 1 2 0.1u_0201_10V6K CPU_EDP_TX2_C_N 1 2 2 1 Place near to PIN 60,21,49,26

7 CPU_EDP_TX2_N
CPU_EDP_TX3_P CV53 1 2 0.1u_0201_10V6K CPU_EDP_TX3_C_P
32
56
42
55
43

29

24

7 CPU_EDP_TX3_P
2

UV12 Place near to PIN 60,21,49,26

D CPU_EDP_TX3_N CV54 1 2 0.1u_0201_10V6K CPU_EDP_TX3_C_N D
VDD_DDC
VDD12_1
VDD12_2
VDDTX12_1
VDDTX12_2
VDDA12
VDD33_1
VDD33_2
VDDRX12_1
VDDRX12_2

7 CPU_EDP_TX3_N

CPU_EDP_AUXP CV49 1 2 0.1u_0201_10V6K CPU_EDP_AUX_C_P

7 CPU_EDP_AUXP CPU_EDP_TX0_C_P 4 54 MUX_EDP_TX0_P

T
CPU_EDP_AUXN CV51 1 2 0.1u_0201_10V6K CPU_EDP_AUX_C_N CPU_EDP_TX0_C_N 5 IN1_D0p OUT_D0p 53 MUX_EDP_TX0_N
7 CPU_EDP_AUXN CPU_EDP_TX1_C_P 7 IN1_D0n OUT_D0n 51 MUX_EDP_TX1_P

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201
CPU_EDP_TX1_C_N 8 IN1_D1p OUT_D1p 50 MUX_EDP_TX1_N VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33

1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201
CPU_EDP_TX2_C_P 10 IN1_D1n OUT_D1n 48 MUX_EDP_TX2_P

1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201
CPU_EDP_TX2_C_N IN1_D2p OUT_D2p MUX_EDP_TX2_N

RV853

RV116

RV105

RV107

RV109

RV113

RV134
11 47

1
CPU_EDP_TX3_C_P 12 IN1_D2n OUT_D2n 45 MUX_EDP_TX3_P

1
CPU_EDP_TX3_C_N 13 IN1_D3p OUT_D3p 44 MUX_EDP_TX3_N

M
CPU_EDP_AUX_C_P IN1_D3n OUT_D3n MUX_EDP_AUXN

RV830

RV103
62 57 @
GPU_EDP_TX0_P CV57 1 2 0.1u_0201_10V6K GPU_EDP_TX0_C_P CPU_EDP_AUX_C_N 61 IN1_AUXp DP_AUXn_SDA 58 MUX_EDP_AUXP @ @ @ @ @ @ @
29 GPU_EDP_TX0_P 65 IN1_AUXn DP_AUXp_SCL 49 EDP_HPD
EDP_HPD 47,79

2
GPU_EDP_TX0_N CV58 1 2 0.1u_0201_10V6K GPU_EDP_TX0_C_N 66 IN1_SDA OUT_HPD 9 EDP_MUX_SW
29 GPU_EDP_TX0_N EDP_MUX_SW 46

2
PCH_EDP_HPD
RV102 1 @ 2 0_0201_5% IN1_HPD 16 IN1_SCL SW 28 MUX_CFG0 RSV0 I2C_CTL_EN MUX_CFG0 MUX_CFG2 MUX_CFG4 IN1_EQ0 IN1_EQ1 IN2_EQ0 IN2_EQ1
GPU_EDP_TX1_P GPU_EDP_TX1_C_P 7 PCH_EDP_HPD GPU_EDP_TX0_C_P IN1_HPD CFG0 MUX_CFG1

RV343

RV108
CV59 1 2 0.1u_0201_10V6K 14 27

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201
29 GPU_EDP_TX1_P GPU_EDP_TX0_C_N IN2_D0p CFG1 MUX_CFG2

RV110

RV133

RV135
15 26

1
GPU_EDP_TX1_N CV60 1 2 0.1u_0201_10V6K GPU_EDP_TX1_C_N GPU_EDP_TX1_C_P 17 IN2_D0n CFG2 25 MUX_CFG3
29 GPU_EDP_TX1_N GPU_EDP_TX1_C_N IN2_D1p CFG3 MUX_CFG4

RV831

RV117
18 46

rS
RV115
GPU_EDP_TX2_P GPU_EDP_TX2_C_P GPU_EDP_TX2_C_P IN2_D1n CFG4 IN1_EQ1

RV104
CV61 1 2 0.1u_0201_10V6K 20 41 0_0201_5% @ @ @ @ @ @ @
29 GPU_EDP_TX2_P GPU_EDP_TX2_C_N 21 IN2_D2p IN1_EQ1 40 IN1_EQ0 MUX_PDCV3454
1 2 1U_0402_10V6K
GPU_EDP_TX2_N CV62 1 2 0.1u_0201_10V6K GPU_EDP_TX2_C_N GPU_EDP_TX3_C_P 22 IN2_D2n IN1_EQ0 39 IN2_EQ1
29 GPU_EDP_TX2_N

2
GPU_EDP_TX3_C_N 23 IN2_D3p IN2_EQ1 38 IN2_EQ0
GPU_EDP_TX3_P CV63 1 2 0.1u_0201_10V6K GPU_EDP_TX3_C_P GPU_EDP_AUX_C_P 60 IN2_D3n IN2_EQ0 6 I2C_CTL_EN
29 GPU_EDP_TX3_P GPU_EDP_AUX_C_N 59 IN2_AUXp I2C_ADDR 52 CA_DET RV1191 2 1M_0402_5%
GPU_EDP_TX3_N CV64 1 2 0.1u_0201_10V6K GPU_EDP_TX3_C_N 63 IN2_AUXn DP_CADET 31 MUX_REXT RV1322 1 1/20W_4.99K_1%_0201
29 GPU_EDP_TX3_N 64 IN2_SDA REXT 30 MUX_PD RV96 1 2 1/20W_20K_5%_0201
VDD33
IN2_HPD 19 IN2_SCL PD# 37 RSV0
GPU_EDP_AUXP CV66 1 2 0.1u_0201_10V6K GPU_EDP_AUX_C_P TV1 33 IN2_HPD RSV0 36
29 GPU_EDP_AUXP TV2 34 CSDA RSV1 35 1 2 1/20W_4.7K_5%_0201
RV3487 @ VDD33
GPU_EDP_AUXN GPU_EDP_AUX_C_N CSCL AUX_CFG
EPAD

CV65 1 2 0.1u_0201_10V6K
29 GPU_EDP_AUXN L: eDP application(default)

fo
TV1 1 TV1 H: Standard DP application +1.8VS_AON
TV2 1 TV2 @ PS8461EQFN66GTR-A3_QFN66_5X10
67

1
RV118
10K_0201_5%
PCH_EDP_HPD RV5601 2 100K_0402_5%

2
MUX_EDP_TX0_P
MUX_EDP_TX0_P 47 1 2 0_0201_5% TV1 GPU_EDP_HPD
32,76,79,90,102 EC_SMB_DA2 RV867 @
MUX_EDP_TX0_N

MUX_EDP_TX1_P
MUX_EDP_TX0_N

MUX_EDP_TX1_P
47

47
32,76,79,90,102 EC_SMB_CK2
RV868

Hunk 10/9 : Reserved I2C control EDP MUX

1 @ 2 0_0201_5% TV2
y 32 GPU_EDP_HPD

QV11
MMBT3904WH_SOT323-3

1
C MUX_EDP_TX1_N C C
MUX_EDP_TX1_N 47 IN2_HPD
nl
2 RV123 1 2 100K_0201_5% RV124 1 @ 2 0_0201_5%
MUX_EDP_TX2_P B
MUX_EDP_TX2_P 47 E

2
MUX_EDP_TX2_N
MUX_EDP_TX2_N 47 1 1
RV125
MUX_EDP_TX3_P CV74 @ CV75
MUX_EDP_TX3_P 47 100K_0201_5%
220P_25V_K_X7R_0201 220P_25V_K_X7R_0201
MUX_EDP_TX3_N 2 2
MUX_EDP_TX3_N 47

1
lO

MUX_EDP_AUXN
MUX_EDP_AUXN 47
MUX_EDP_AUXP
MUX_EDP_AUXP 47
MUX_EDP_AUXN RV120 1 A2@ 2 100K_0201_5% VDD33
MUX_EDP_AUXP RV122 1 A2@ 2 100K_0201_5%
MUX_CFG1 RV112 1 @ 21/20W_4.7K_5%_0201
VDD33
MUX_CFG3 RV111 1 @ 21/20W_4.7K_5%_0201
VDD33
GPU_EDP_AUX_C_N RV126 1 @ 2 100K_0201_5%
VDD33
tia

GPU_EDP_AUX_C_P RV127 1 @ 2 100K_0201_5%

en

+3VS

UV15
1 5
OE Vcc
GPU_EDP_PWM 2
32 GPU_EDP_PWM IN_A
3 4 GPU_EDP_PWM_B
GND OUT_Y GPU_EDP_PWM_B 46
fid

M74VHC1GT125DF2G_SC70-5

B B

+3VS
UV16
1 5
OE Vcc
GPU_EDP_ENBKL 2
on

32 GPU_EDP_ENBKL IN_A
3 4 GPU_EDP_ENBKL_B
GND OUT_Y GPU_EDP_ENBKL_B 46

M74VHC1GT125DF2G_SC70-5

+3VS

UV17
1 5
C

OE Vcc
GPU_EDP_ENVDD 2
32 GPU_EDP_ENVDD IN_A
3 4 GPU_EDP_ENVDD_B
GND OUT_Y GPU_EDP_ENVDD_B 46

M74VHC1GT125DF2G_SC70-5
FC
LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 EDP MUX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y540 A0

Date: Monday, November 29, 2021 Sheet 45 of 110

5 4 3 2 1
 A B C D E

EDP PWM LOGIC CONTROL need fine tune RG107 RG108 RG88 BOM structure
08/08
+3VS

+3VS
1
new add +3VS CV2
08/12 1 DDS@ 1U_0402_10V6K
UV7 DDS@ UV8 DDS@ CV1
1 5 1 4 PWM_SEL DDS@ 1U_0402_10V6K UV2 DDS@ 2
OE Vcc 12,46 CPU_EDP_SW PWM_SW_SELECT_B 2 IN B OUT Y EC_EDP_PWM 1 5
PWM_SW_SELECT IN A 2 79 EC_EDP_PWM EDP_PWM_M Y1 Vcc
2 UV1 DDS@ 3
32 PWM_SW_SELECT IN_A 3 5 +3VS_UV8 Y0 MUX_INVT_PWM_R RV90 2
RV92 2 @ 1 0_0402_5%
+3VS 45 GPU_EDP_PWM_B
1 5 4 @ 1 0_0402_5%
3 4 PWM_SW_SELECT_B GND Vcc 3 Y1 Vcc Z MUX_INVT_PWM 47
GND OUT_Y 7 PCH_EDP_PWM Y0 EDP_PWM_M
4 2 6
Z GND S EC_PWM_OUT_EN 79
MC74VHC1G32DFT2G_SC70-5 1
M74VHC1GT125DF2G_SC70-5 Discrete mode: EDP_SW 1 DDS@ 2 6 PWM_SEL
MSHybrid mode: EDP_SW 0 GND S
08/12
CV41
0.1u_0201_10V6K
74LVC1G3157GW_SOT363-6 VCC: 3V VIH:2V
1
Or gate 2 default high 1
74LVC1G3157GW_SOT363-6
08/06

T
S z
H Y1 DGPU
L Y0

M
iGPU

rS
+3VS

Co-lay EDP ENVDD LOGIC CONTROL

new add +3VS 1
08/12 CV43 new add
UV19 DDS@ @ 1U_0402_10V6K 08/08
1 5 UV11 @ +3VS
OE Vcc GPU_EDP_ENVDD_B 1 5 2
GPU_MUX_CNTL 2 PCH_EDP_ENVDD 3 Y1 Vcc
32 GPU_MUX_CNTL IN_A Y0 4 EDP_ENVDD
3 4 GPU_MUX_CNTL_B Z

fo
2
GND OUT_Y 2 6 EDP_MUX_SW RV84
GND S 1
M74VHC1GT125DF2G_SC70-5 CV45 @
74LVC1G3157GW_SOT363-6 0.1u_0201_10V6K +3VS
2 0_0402_5%
@

1
+3VS

+3VS_UV5
1
DDS@

2
CV1542
0.1u_0201_10V6K

2
DDS@ RV85 2
EDP ENVDD LOGIC CONTROL
y 10K_0402_5%
DDS@ RV86

1
VIH: 2.1V Vil: 0.9V 10K_0402_5%

5
Voh: 2.9V Vol: 0.1V(Io 50uA) UV5

1
2 UV10 DDS@ EDP_ENVDD 1 2

P
EDP_MUX_SW B MUX_EDP_ENVDD_R RV87 2
nl
1 4 UV3 DDS@ 4 @ 1 0_0402_5%
12,46 CPU_EDP_SW GPU_MUX_CNTL_B 2 IN B OUT Y EDP_MUX_SW 45 PCH_EDP_ENVDD 1 4 EDP_ENVDD 2 Y MUX_EDP_ENVDD 47

G
IN A 7 PCH_EDP_ENVDD GPU_EDP_ENVDD_B 2 IN B OUT Y 79 EC_EDP_ENVDD A
3 5 +3VS_UV10RV93 2 1 0_0402_5% 45 GPU_EDP_ENVDD_B IN A
@ +3VS DDS@ MC74VHC1G09DFT2G_SC70-5

3
GND Vcc 3 5 +3VS_UV3 RV76 2 @ 1 0_0402_5%
GND Vcc +3VS
MC74VHC1G32DFT2G_SC70-5 1
DDS@ MC74VHC1G32DFT2G_SC70-5 1
CV42 DDS@
lO

0.1u_0201_10V6K CV3
2 0.1u_0201_10V6K
2
tia
en
fid

level shift for I2C

3 EDP backlight LOGIC CONTROL 3

VIH: 2.1V Vil: 0.9V

Voh: 2.9V Vol: 0.1V(Io 50uA)
UV4 DDS@ +1.8VS_AON +1.8VS_AON +LCD_VDD
PCH_EDP_ENBKL1 4 EDP_ENBKL RV3462 @ 1 0_0402_5%
7 PCH_EDP_ENBKL 2 IN B OUT Y MUX_EDP_ENBKL 79
45 GPU_EDP_ENBKL_B IN A
on

3 5 +3VS_UV4 RV3492 @ 1 0_0402_5%

GND Vcc +3VS

MC74VHC1G32DFT2G_SC70-5 1
2

DDS@
CV4 RV347 RV348
0.1u_0201_10V6K 2.2K_0402_5% 2.2K_0402_5%
5

2 DDS@ @ @ DDS@
G2

G1
1

I2CB_SCL 4 3 I2CB_SCLA_L 6 1
32 I2CB_SCL S2 D2 D1 S1 GPU_I2CB_SCL 47
C

For AMD MS solution :Stuff QV509 ,unstuff RV350 QV37B

RV80 Only reserved. PJT7838_SOT363-6 QV38A
PJT7838_SOT363-6
+1.8VS_AON +1.8VS_AON +3VS +3VS
2

DDS@ DDS@
G1

G2
1

I2CB_SDA 1 6 I2CB_SDA_L 3 4
2

32 I2CB_SDA S1 D1 D2 S2 GPU_I2CB_SDA 47
FC

1 @ RV80
RV79 DDS@ 10K_0402_5% Vgs(th)≤1.0V
DDS@ 100K_0402_5% CV5 QV37A
2

0.1u_0201_10V6K PJT7838_SOT363-6 QV38B

2 PJT7838_SOT363-6
1

3 1PCH_ENBKL_R 1 3 PCH_EDP_ENBKL RV94 1 @ 2 0_0402_5%

32 iGPU_EDP_ENBKL

QV9 QV509
LSI1012XT1G_SC-89-3 LSI1012XT1G_SC-89-3
DDS@ RV95 1 @ 2 0_0402_5%
Vgs(th)≤0.9V
LC

RV3502 @ 1 0_0402_5%

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 DC V TO VS INTERFACE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y550 A0

Date: Monday, November 29, 2021 Sheet 46 of 110

A B C D E
 5 4 3 2 1

LCD POWER CIRCUIT B+

+LED_VDD
@
FV3 2A 80 mil
2A 80 mil JV1 2 1 JUMP_43X79 1 2 JEDP1
+LCD_VDD 2 1 1
+LED_VDD 1
需需 SA00008S600 4A_32V_ 0497004PKRHF 1 1 2
+3VALW CV14 RV826 1 @ 2 0_0402_5% 3 2
UV9 W=80mils 4 3
W=80mils FV3 need changed to SP04000A200 4.7U_0805_25V6K CV15
RV3 2 @ 1 0_0805_5% LCD_VDD_OUT 1 5 AO3401A_SOT23-3 @ 0.1U_25V_K_X5R_0201 For EMI 5 4
OUT IN QV513 2 2 6 5
EMC@ 6
0.1u_0201_10V6K

2 3 1 EXC24CH900U_4P 7
S

GND USB20_6_N 4 3 USB20_6_N_EDP +LCD_VDD 1A Inrush 2A 8 7

1 1 LCD_VDD_OCB 3 14 USB20_6_N 4 3 8
CV7 1 @ 2 4 @ AO3401A 9
OCB EN 9
CV8

VDS:-30V
EMI Request 10
G
2

4.7U_0402_6.3V6M RV6 SY6288E1AAC_SOT23-5 CV3456 1000P_0402_50V_X7R_0402 VGS: /-12V USB20_6_P 1 2 USB20_6_P_EDP EDP_HPD 11 10
2 2 1 2 Vth: -0.5~-1.3V 14 USB20_6_P 1 2 45,79 EDP_HPD BKOFF_N 12 11
10K_0402_5% ID:-4A LV1 79 BKOFF_N MUX_INVT_PWM 13 12
RDson: <50mohm, Vgs -10V
1

46 MUX_INVT_PWM LCD_OD_N 14 13
@ EMC@
7 LCD_OD_N 15 14
RV3501
1/20W_150K_1%_0201 RV827 1 @ 2 0_0402_5% 16 15
D @ DMIC 66 CODEC_DMIC_DAT 17 16 D
66 CODEC_DMIC_CLK 18 17
RV3499 100K_0201_5%
2

1 2 USB20_6_N_EDP 19 18
MUX_EDP_ENVDD @ USB20_6_P_EDP 20 19
46 MUX_EDP_ENVDD
1

21 20

T
RV3500 IT8258_YLOGO_LED_PWM RV3493 1 Y7@ 2 0_0402_5% Y_LOGO 22 21
80 IT8258_YLOGO_LED_PWM
1

+3VS_DMIC 22
100K_0402_5%

1 @ 100K_0201_5% 0.5A 23
+3VS_DMIC +3VS_CMOS 23
@ 24
+3VS_CMOS 24
RV1

CV22 25
+5VALW_LOGO
2

0.1u_0201_10V6K YLOGO_LED_PWM_B_OUT RV3492 2 @ 1 0_0402_5% Y_LOGO 26 25

2 YLOGO_LED_PWM_G_OUT 27 26
2

YLOGO_LED_PWM_R_OUT 28 27

M
1

RV3503 0_0402_5% QV511 D RV8502 @ 1 0_0402_5% 29 28

1 2 PM_SLP_S5_N_R 2 +3VL LID_SW_N 30 29
@ 79,83 LID_SW_N
17 PM_SLP_S5_N G 31 30
32 31
@ S 2N7002KW_SOT323-3 33 32
1
3

46 GPU_I2CB_SDA 34 33
46 GPU_I2CB_SCL 35 34
@ CV3499
MUX_INVT_PWM 100K_0201_5% 1 2 RV2 2N7002KW 0.1U_6.3V_K_X5R_0201 MUX_EDP_AUXN CV1553 1 2 0.1u_0201_10V6K MUX_EDP_AUX_CON_N 36 35
2 45 MUX_EDP_AUXN MUX_EDP_AUXP MUX_EDP_AUX_CON_P 36
VDS:60V CV1554 1 2 0.1u_0201_10V6K 37

rS
VGS: /-20V 45 MUX_EDP_AUXP 38 37
EDP_HPD 100K_0201_5% 1 2 RV5 Vth: 1.0~2.5V MUX_EDP_TX0_P CV1555 1 2 0.22U_25V_K_X5R_0201MUX_EDP_TX0_CON_P 39 38
ID:115mA 45 MUX_EDP_TX0_P MUX_EDP_TX0_N 39
RDson: 4ohm, Vgs 4.5V CV1556 1 2 0.22U_25V_K_X5R_0201MUX_EDP_TX0_CON_N 40
45 MUX_EDP_TX0_N 41 40
MUX_EDP_TX1_P CV1557 1 2 0.22U_25V_K_X5R_0201MUX_EDP_TX1_CON_P 42 41
45 MUX_EDP_TX1_P MUX_EDP_TX1_N 2 0.22U_25V_K_X5R_0201MUX_EDP_TX1_CON_N 42
CV1558 1 43
45 MUX_EDP_TX1_N 44 43
MUX_EDP_TX2_P CV1559 1 2 0.22U_25V_K_X5R_0201MUX_EDP_TX2_CON_P 45 44
45 MUX_EDP_TX2_P MUX_EDP_TX2_N 2 0.22U_25V_K_X5R_0201MUX_EDP_TX2_CON_N 45
CV1560 1 46
45 MUX_EDP_TX2_N 47 46
EMI request MUX_EDP_TX3_P CV1561 1 2 0.22U_25V_K_X5R_0201MUX_EDP_TX3_CON_P 48 47
45 MUX_EDP_TX3_P MUX_EDP_TX3_N 2 0.22U_25V_K_X5R_0201MUX_EDP_TX3_CON_N 48
CV1562 1 49 52
45 MUX_EDP_TX3_N 50 49 GND2 51

fo
@ 50 GND1
MUX_INVT_PWM 470P_0201_25V_X7R_0201 2 1 CV13
CVILUX_CF69502D0R0-05-NH
@ ME@
BKOFF_N 470P_0201_25V_X7R_0201 1 2 CV12

EMC_NS@
CODEC_DMIC_DAT 10P_50V_D_NPO_0201 1 2 CV28

EMC_NS@
CODEC_DMIC_CLK 100P_50V_J_NPO_0201 1 2 CV11

C
y C
nl
+5VALW
lO

1
CV251
1U_0402_10V6K
2@

UV5412
16
Vcc 4 YLOGO_LED_PWM_B_MUX
select for LOGO_led PWR +5VALW_LOGO 2 1A 7 YLOGO_LED_PWM_G_MUX
82 YLOGO_LED_PWM_B 1B1 2A YLOGO_LED_PWM_R_MUX
06/12 yong 3 9
5 1B2 3A 12
82 YLOGO_LED_PWM_G 2B1 4A
6
2B2
tia

RV47 1 Y7@ 2 0_0402_5% 11 15

+5VALW_S3 82 YLOGO_LED_PWM_R 3B1 OE
10 1
79 EC_YLOGO_LED_PWM 3B2 S YLOGO_LED_SEL 79
RV48 1 Y570P@ 2 1/10W_0_5%_0603 14
+5VALW

2
13 4B1 8
4B2 GND 17 RV1063
T-PAD S State
RV48 使使使使使使使直Y560_15,Y560P 需需 100K_0402_5%
L nA to nB1
CBT3257ABQ_DHVQFN16_2P5X3P5 @
H nA to nB2
@

1
en

+3VS +3VS_DMIC

EC_YLOGO_LED_PWM RV3504 1 Y570P@ 2 0_0402_5% YLOGO_LED_PWM_B_MUX

RV81 1 @ 2 0_5%_0603

+5VALW +5VALW +5VALW

fid

2
RV70 RV75 RV71
+3VS +3VS_CMOS
@ @ @
B B
10K_0402_5% 10K_0402_5% 10K_0402_5%
1

1
YLOGO_LED_PWM_B_OUT YLOGO_LED_PWM_G_OUT YLOGO_LED_PWM_R_OUT
RV3497 1 @ 2 1/10W_0_5%_0603
QV8 1 QV7 1 QV101
2 D Y570P@ D @ D @
YLOGO_LED_PWM_B_MUX 2 YLOGO_LED_PWM_G_MUX 2 YLOGO_LED_PWM_R_MUX 2
2

@ CV543 G G G
on

RV789 0.047U_0402_16V_X7R_0402 S S S
2

2
1 PJA138K_SOT23-3 PJA138K_SOT23-3 PJA138K_SOT23-3
100K_0402_5% UV25 RV72 3 RV73 3 RV74 3
5 1 Y570P@ 100K_0402_5% @ 100K_0402_5% @ 100K_0402_5%
1

IN OUT
2
1

1
GND
4 3
78,79 IO_Camera_EN ENB OCB

SY6288D20AAC_SOT23-5
C

YLOGO_LED_PWM_B_OUT YLOGO_LED_PWM_G_OUT YLOGO_LED_PWM_R_OUT

1

1
1

1
EMC_NS@ 2 DV1 EMC_NS@ 2 DV2 EMC_NS@ 2 DV3
FC

AZ5725-01F.R7GR_DFN1006P2X2 AZ5725-01F.R7GR_DFN1006P2X2 AZ5725-01F.R7GR_DFN1006P2X2

CV102 CV103 CV104
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J
1 1 1
2

2
2

@ @ @
LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 eDP/ CMOS/Touch screen

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y540 A0

Date: Monday, November 29, 2021 Sheet 47 of 110

5 4 3 2 1
 5 4 3 2 1

D D

T
M
rS
fo
C
y C
nl
lO
tia
en
fid

B B
on
C
FC
LC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 eDP/ CMOS/Touch screen

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y550 A0

Date: Monday, November 29, 2021 Sheet 48 of 110

5 4 3 2 1
 5 4 3 2 1

D D

T
M
rS
fo
C
y C
nl
lO
tia
en
fid
on

B B
C
FC
LC

A A

Title
<Title>

Size Document Number Rev

A <Doc> A0

Date: Monday, November 29, 2021 Sheet 49 of 110

5 4 3 2 1
 5 4 3 2 1

HDMI Power
+5VS +5VS_HDMI_F +5VS_HDMI
QV501
LP2301ALT1G_SOT-23-3
FV501
1 3 1 2
D

D 1 D
1.1A_8V_1206L110THYR +1.8VS_AON
CV501 +5VS_HDMI
Ihold:1.1A,Itrip:2.2A,
G
2

0.1u_0201_10V6K
84 SUSP Rmax:0.21ohm 2 +5VS_HDMI

2
1

1
RV60
10K_0402_5%
T
RPV501
2.2K_0404_4P2R_5%
update by bing
3
4

2
JHDMI2 20180316

M
HDMI_DET 19
18 Hot_Plug_Detect IFPC_HPD
+5V_Power 32 IFPC_HPD
17
DDPB_DATA_U 16 DDC/CEC_GND
DDPB_CLK_U 15 SDA QV4
14 SCL MMBT3904WH_SOT323-3
Utility

1
GPU_HDMI_TX0_P CV502 1 2 0.1u_0201_10V6K HDMI_TX0_CON_P 13 20

rS
C
29 GPU_HDMI_TX0_P HDMI_CLK_CON_N CEC GND1
RV859 1 2 6.8_0201_1% HDMI_CLK_R_CON_N 12 2 RV58 1 2 100K_0402_5% HDMI_DET
GPU_HDMI_TX0_N CV503 1 2 0.1u_0201_10V6K HDMI_TX0_CON_N 11 TMDS_Clock- 21 B
29 GPU_HDMI_TX0_N HDMI_CLK_CON_P 1 2 6.8_0201_1% HDMI_CLK_R_CON_P 10 TMDS_Clock_Shield GND2
RV860 E

3
GPU_HDMI_TX1_P CV504 1 2 0.1u_0201_10V6K HDMI_TX1_CON_P HDMI_TX0_CON_N RV861 1 2 6.8_0201_1% HDMI_TX0_R_CON_N 9 TMDS_Clock+ 22
29 GPU_HDMI_TX1_P TMDS_Data0- GND3 1

1
8 CV29
GPU_HDMI_TX1_N CV505 1 2 0.1u_0201_10V6K HDMI_TX1_CON_N HDMI_TX0_CON_P RV862 1 2 6.8_0201_1% HDMI_TX0_R_CON_P 7 TMDS_Data0_Shield 23 RV57 220P_0402_50V7K
29 GPU_HDMI_TX1_N HDMI_TX1_CON_N TMDS_Data0+ GND4
RV863 1 2 6.8_0201_1% HDMI_TX1_R_CON_N 6 100K_0402_5%
GPU_HDMI_TX2_P CV506 1 2 0.1u_0201_10V6K HDMI_TX2_CON_P 5 TMDS_Data1- 2
29 GPU_HDMI_TX2_P HDMI_TX1_CON_P TMDS_Data1_Shield
RV864 1 2 6.8_0201_1% HDMI_TX1_R_CON_P 4

2
GPU_HDMI_TX2_N CV507 1 2 0.1u_0201_10V6K HDMI_TX2_CON_N HDMI_TX2_CON_N RV865 1 2 6.8_0201_1% HDMI_TX2_R_CON_N 3 TMDS_Data1+
29 GPU_HDMI_TX2_N TMDS_Data2-

fo
2
GPU_HDMI_CLK_P CV508 1 2 0.1u_0201_10V6K HDMI_CLK_CON_P HDMI_TX2_CON_P RV866 1 2 6.8_0201_1% HDMI_TX2_R_CON_P 1 TMDS_Data2_Shield
29 GPU_HDMI_CLK_P TMDS_Data2+
GPU_HDMI_CLK_N CV509 1 2 0.1u_0201_10V6K HDMI_CLK_CON_N ALLTOP_C12919-11939-L
29 GPU_HDMI_CLK_N
ME@

HDMI_TX0_CON_P 1 2 1/20W_499_1%_0201 HDMI_TX0_DP_R LV840 1 2 FCM1005KF-601T03_2P

C
HDMI_TX0_CON_N
RV504

RV505 1 2 1/20W_499_1%_0201 HDMI_TX0_DN_R LV841 1 2 FCM1005KF-601T03_2P

y +3VS C
HDMI_TX1_CON_P RV506 1 2 1/20W_499_1%_0201 HDMI_TX1_DP_R LV842 1 2 FCM1005KF-601T03_2P
nl
HDMI_TX1_CON_N RV507 1 2 1/20W_499_1%_0201 HDMI_TX1_DN_R LV843 1 2 FCM1005KF-601T03_2P
HDMI_TX2_CON_P RV508 1 2 1/20W_499_1%_0201 HDMI_TX2_DP_R LV844 1 2 FCM1005KF-601T03_2P

1
HDMI_TX2_CON_N RV509 1 2 1/20W_499_1%_0201 HDMI_TX2_DN_R LV845 1 2 FCM1005KF-601T03_2P RV666
lO

1M_0402_5%
HDMI_CLK_CON_P RV510 1 2 1/20W_499_1%_0201 HDMI_CLK_DP_R LV846 1 2 FCM1005KF-601T03_2P

2
HDMI_CLK_CON_N RV511 1 2 1/20W_499_1%_0201 HDMI_CLK_DN_R LV847 1 2 FCM1005KF-601T03_2P

G
1

3
CPU_HDMI_HPD HDMI_DET

1
QV504
LSI1012XT1G_SC-89-3 7 CPU_HDMI_HPD

D
RV849 1 @ 2 0_0402_5% 2
32,102 NVVDD_PWRGD
RV848 1 @ 2 0_0402_5% QV6
Vgs(th)≤0.9V
tia

32,37,39,41,43 MEM_VREF_CTL
3

1
RV512 1 @ 2 PJA138K_SOT23-3
100K_0402_5% RV503
100K_0402_5%
NV Suggestion

2
en

EMC
Del RV513,RV514,RV516,RV517,RV519,RV520,RV522,RV523,LV501,LV502,LV503,LV504 ----arthur.chen 12/25

+5VS_HDMI +1.8VS_AON +1.8VS_AON

fid

2
RV42 RV40
1

B B
RV3496 @ @
@ 0_0402_5%
0_0402_5% 0_0402_5%
AUX
1

1
on

1
NV suggestion
RV56 RV55
10K_0402_5% 10K_0402_5%
2

@
G1

G1

DDPB_DATA_U 2
1 6 6 1
HDMI1_DAT 29
C

S1 D1 D1 S1
DV501 DV502
HDMI_TX1_CON_N 1 10 HDMI_TX1_CON_N HDMI_DET 1 1 10 9 HDMI_DET PJT7838_SOT363-6 PJT7838_SOT363-6
Line-1 NC1
QV512A QV3A
HDMI_TX1_CON_P 2 9 HDMI_TX1_CON_P DDPB_CLK_U 2 2 9 8 DDPB_CLK_U
Line-2 NC2
5

3 8 DDPB_DATA_U 4 4 7 7 DDPB_DATA_U @
G2

G2

GND1 GND2
HDMI_TX2_CON_N 4 7 HDMI_TX2_CON_N +5VS_HDMI 5 5 6 6 +5VS_HDMI DDPB_CLK_U 4 3 3 4
FC

Line-3 NC3 S2 D2 D2 S2 HDMI1_CLK 29

HDMI_TX2_CON_P 5 6 HDMI_TX2_CON_P 3 3
Line-4 NC4 PJT7838_SOT363-6 PJT7838_SOT363-6
Vgs(th)≤1V
EMC_NS@ AZ1023-04F.R7G_DFN2510P10E10 8 QV512B QV3B

EMC_NS@ AZ1045-04F_DFN2510P10E-10-9

DV501 & DV503 Change to SC300005R00

RV3488 2 @ 1 0_0402_5%
DV503
HDMI_CLK_CON_P 1 10 HDMI_CLK_CON_P
LC

Line-1 NC1
HDMI_CLK_CON_N 2 9 HDMI_CLK_CON_N
Line-2 NC2 RV3489 2 @ 1 0_0402_5%
3 8
GND1 GND2
HDMI_TX0_CON_P 4 7 HDMI_TX0_CON_P
Line-3 NC3
A HDMI_TX0_CON_N 5 6 HDMI_TX0_CON_N A
Line-4 NC4
EMC_NS@ AZ1023-04F.R7G_DFN2510P10E10

Security Classification
Security Classification LCFC Highly Confidential Information Title
Issued Date 2019/07/02 Deciphered Date 2020/02/24 HDMI_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y540 A0

Date: Monday, November 29, 2021 Sheet 50 of 110

5 4 3 2 1
 5 4 3 2 1

TBT portA/rear side

D D

T
VBUS_TBTA

M
+3VALW VINA_3V3
NSR20F30NXT5G_DSN2-2

RU2 1 @ 2 0_5%_0603
1

2
1

DU614

rS
VINA_3V3 VCC3_LDO_PDA CU4
4.7U_25V_M_X5R_0402
1
2
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

VCC1V5_LDO_PDA

1 1 1
CU1

CU2

CU3

2 2 2 VBUS_TBTB
NSR20F30NXT5G_DSN2-2

VCC3_LDO_PDA
4.7U_25V_M_X5R_0402

1/20W_12.1K_1%_02011/20W_52.3K_+-1%_0201
1

2 VCC3_LDO_PDA
DU618

CU881

+5VALW
1

fo
1

EC_I2C_INT4_PDA_N RU10 1 @ 2 10K_0201_5%

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

1
G2

G8
H4

H1

H3

H8

C8

RU3
A3

A8
B8
F8

UU5411
TBT_I2C2_SCL
2

1 1 1 1 1 1 RPU7 1 4 2.2K_0404_4P2R_5%
VSYS

VIN_3V3

LDO_1V5_1
LDO_1V5_2

LDO_3V3

PA_VBUS_1
PA_VBUS_2
PA_VBUS_3

PB_VBUS_1
PB_VBUS_2
PB_VBUS_3

TBT_I2C2_SDA
CU121

CU122

2 3
2
CU6

CU7

CU8

CU9

A7 PDA_ADCIN2
2 2 2 2 2 2 B7 PP5V_1 PCH_PMC_ALERT_PD_N
RU11 1 @ 2 10K_0201_5%
C7 PP5V_2
1

D7 PP5V_3
E7 PP5V_4 G4
VCC3_LDO_PDA
F7 PP5V_5 ADCIN1
y TBTA_I2C_SCL 1 4 2.2K_0404_4P2R_5%
RU5

RPU2
G7 PP5V_6 TBTA_I2C_SDA 2 3
H7 PP5V_7 G3 PDA_ADCIN2 Address : 7/4
2

PP5V_8 ADCIN2
C C
nl
A4
E8 PA_GATE_VSYS G5
PA_GATE_VBUS PA_CC1 H5 TBTA_CC1 53
PA_CC2 TBTA_CC2 53
B5 TBTA_CC1 CU10 1 2 330P_25V_K_X7R_0201
PB_CC1 USBC2_CC1_CONN 56
B4 A5
PB_GATE_VSYS PB_CC2 USBC2_CC2_CONN 56 TBTA_CC2
D8 CU11 1 2 330P_25V_K_X7R_0201
PB_GATE_VBUS
lO

USBC2_CC1_CONN CU876 1 2 330P_25V_K_X7R_0201

USBC2_CC2_CONN CU877 1 2 330P_25V_K_X7R_0201
C1 D1 EC_I2C_INT4_N_PDA_R
RU15 1 @ 2 0_0201_5% EC_I2C_INT4_PDA_N
55 TYPE-C_DP_RE_HPD2 GPIO0 I2C_EC_IRQ# EC_I2C_INT4_PDA_N 79
TBTA_RESET_N RU202 1 @ 2 0_0201_5% PD_TBTA_RESET_N G1 E1 EC_SMB_CK4_TBT RU1100 1 @ 2 0_0201_5% EC_SMB_CK4_PD EC
52 TBTA_RESET_N GPIO1 I2C_EC_SCL EC_SMB_DA4_TBT EC_SMB_DA4_PD EC_SMB_CK4_PD 60,79 Slave
F1 RU1101 1 @ 2 0_0201_5%
TBTA_PWR_EN 1 2 0_0201_5% PD_TBTA_PWR_EN A6 I2C_EC_SDA EC_SMB_DA4_PD 60,79
RU204 @
52 TBTA_PWR_EN GPIO2
H6 VCC3_LDO_PDA
55 PS8812_DP_MODE_C2 GPIO3 F2 PMC_ALERT_PDA_N RU21 1 2 0_0201_5% PCH_PMC_ALERT_PD_N
@
USB_OC2_N 1 2 0_0201_5% USB_OC2_R_N B3 I2C2S_IRQ# PCH_PMC_ALERT_PD_N 17
RU26 @
7,14 USB_OC2_N GPIO4 E2 TBT_I2C2_SCL 1 2 0_0201_5% SML1_CLK_TBT PCH SML1
RU22 @ Slave
I2C2S_SCL TBT_I2C2_SDA SML1_DATA_TBT SML1_CLK_TBT 11,60
tia

C2 D2 RU1046 1 @ 2 0_0201_5%
GPIO5 I2C2S_SDA SML1_DATA_TBT 11,60
10K_0201_5%

10K_0201_5%

10K_0201_5%
2

F6 1
55 PS8812_FLIP_C2 GPIO6
RU2477

RU2479

RU2478

G6 B1 CU300
55 PS8812_USB_MODE_C2 GPIO7 I2C3M_IRQ# TBT_I2C_INT_N 52 0.1U_6.3V_K_X5R_0201
@
B6 A2 TBTA_I2C_SCL RU3525 1 @ 2 0_0201_5% BB Re-timer UU9 @ 2
TBTA_I2C_R_SCL 52,55 Master
1

GPIO8 I2C3M_SCL A1 TBTA_I2C_SDA RU3526 1 @ 2 0_0201_5% A0_TBT 1 8

1 2 0_0201_5% TBT_FORCE_PWR_R C6 I2C3M_SDA_1 B2 TBTA_I2C_R_SDA 52,55 A0 VCC
RU208 @ @ @ @
10,52 CPU_TBT_FORCE_PWR_R GPIO9 I2C3M_SDA_2 A1_TBT 2 7 MPROM_WP RU2483 2 1 10K_0201_5%
@
GND

A1 WP
A2_TBT 3 6 TBTA_I2C_SCL_ROM 1 @ 2 TBTA_I2C_SCL
en

SN2011060YBGR_DSBGA50 A2 SCL RU1104 0_0201_5%

H2

EC_I2C_INT4_N_PDA_R PAD 1 @ 4 5 TBTA_I2C_SDA_ROM 1 @ 2 TBTA_I2C_SDA

10K_0201_5%

10K_0201_5%

10K_0201_5%

ITE11
2

VSS SDA RU1105 0_0201_5%

EC_SMB_CK4_TBT
RU2480

RU2481

RU2482

PAD 1 @
ITE12
@ @ @ CAT24C256WI-GT3_SO8
EC_SMB_DA4_TBT PAD 1 @
ITE13 Address 1010 A2 A1 A0 R/W
1

For E14-intel:1010 000 R/W

fid

B B
on
C
FC
LC

A A

Security Classification LCFC Highly Confidential Information Title

S540-TGL
Issued Date 2012/07/01 Deciphered Date 2014/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
TYPEC_Controller_PortA A0

Date: Monday, November 29, 2021 Sheet 51 of 110

5 4 3 2 1
 5 4 3 2 1

Burnside Bridge Re-Timer UU202D Y

TCP0_CTX_DRX0_P 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CTX_C_DRX0_P J1

TBT PORTS J12 TBTA_RX0_P +3VALW
7
7
TCP0_CTX_DRX0_P
TCP0_CTX_DRX0_N
TCP0_CTX_DRX0_N
CU216
CU217 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CTX_C_DRX0_N J2 ASSRXp1 BSSRXp1 J11 TBTA_RX0_N TBTA_RX0_P
TBTA_RX0_N
53
53
TBT retime：SA00009QD30
ASSRXn1 BSSRXn1 TBTA_FLASH_BUSY_N RU244 1 2 10K_0201_5%
TCP0_CRX_DTX0_P
FLASH_BUSY# should be shared between BBR#1 and
2 0.22U_6.3V_K_X5R_0201 TCP0_CRX_C_DTX0_P TBTA_TX0_P
Port B - TypeC Side

CU218 1 G1 G12 RU245 1 @ 2 10K_0201_5% BBR#2 with PU to PW_VCC3v3_SX_SYS

7 TCP0_CRX_DTX0_P TCP0_CRX_DTX0_N 2 0.22U_6.3V_K_X5R_0201 TCP0_CRX_C_DTX0_N ASSTXp1 BSSTXp1 TBTA_TX0_N TBTA_TX0_P 53
Port A - Host Side

CU219 1 G2 G11
7 TCP0_CRX_DTX0_N ASSTXn1 BSSTXn1 TBTA_TX0_N 53
TCP0_CTX_DRX1_P CU220 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CTX_C_DRX1_P C1 C12 TBTA_RX1_P
7 TCP0_CTX_DRX1_P TCP0_CTX_DRX1_N 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CTX_C_DRX1_N C2 ASSRXp2 BSSRXp2 C11 TBTA_RX1_N TBTA_RX1_P 53
CU221
7 TCP0_CTX_DRX1_N ASSRXn2 BSSRXn2 TBTA_RX1_N 53 +3VS
TCP0_CRX_DTX1_P CU222 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CRX_C_DTX1_P E1 E12 TBTA_TX1_P
7 TCP0_CRX_DTX1_P TCP0_CRX_DTX1_N ASSTXp2 BSSTXp2 TBTA_TX1_P 53 POC_GPIO6:
CU223 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CRX_C_DTX1_N E2 E11 TBTA_TX1_N BB_TBTA_GPIO_6 RU246 1 2 10K_0201_5% Indication to S0 state for Re-timer
7 TCP0_CRX_DTX1_N ASSTXn2 BSSTXn2 TBTA_TX1_N 53 1 @ 2 10K_0201_5%
RU247
CPU_TBT_LSX0_TXDRU468 1 @ 2 0_0201_5% CPU_TBT_LSX0_TXD_R
M7 M10 TBTA_SBU1
7 CPU_TBT_LSX0_TXD CPU_TBT_LSX0_RXD 1 2 0_0201_5% CPU_TBT_LSX0_RXD_R L7 PA_LSTX_SBU1 B_SBU1 L10 TBTA_SBU2 TBTA_SBU1 53
RU469 @
7 CPU_TBT_LSX0_RXD PA_LSRX_SBU2 B_SBU2 TBTA_SBU2 53
TCP0_AUX_P RU223 1 @ 2 0_0201_5% TCP0_AUX_R_P L8
7 TCP0_AUX_P TCP0_AUX_N 1 2 0_0201_5% TCP0_AUX_R_N M8 PA_AUX_P 3VALW_TBTA
RU224 @
7 TCP0_AUX_N PA_AUX_N
TBTA_FORCE_PWR
BB_FORCE_PWR:
AC coupling caps and PU/PD on AUX lines RU248 1 @ 2 10K_0201_5% Connect to EC/PCH for FW update
are implemented inside Burnside Bridge. RU249 1 2 10K_0201_5% '0' - by default
D D
'1' - for debug only/FW update

3VALW_TBTA

T
+VCC3V3_LC_TBTA RPU204
BB_TBTA_FLSH_SHARE_EN RU250 1 2 10K_0201_5%
TBTA_TCK
FLSH_SHARE_EN (iPU):
1 8 RU251 1 @ 2 10K_0201_5% '0' - Flash isn't shared, 1 Flash per Re-timer.
2 7 TBTA_TDI JHL8040RSLMNx
TBTA_TMS '1' - Flash is shared between 2 Re-timers
3 6
TBTA_TDO @
4 5

M
VCC3_BB_SPI
10K_0804_8P4R_5% 3VALW_TBTA FLSH_MSTR_SLV (iPU):
TBT_SPI_MISO BB_TBTA_FLSH_MSTR_SLV RU252 Should be used only when DG_FLSH_SHARE_EN is High.
RU237 1 2 1/20W_2.2K_5%_0201 1 2 10K_0201_5% '0' - Set Re-timer to be Slave on shared flash SPI I/F.
UU202A TBT_SPI_CS_N RU238 1 2 1/20W_2.2K_5%_0201 RU253 1 @ 2 10K_0201_5%
TBTA_SPI_WP_N '1' - Set Re-timer to be Master on shared flash SPI I/F
RU239 1 2 1/20W_3.3K_5%_0201
TBT_SPI_MOSI 1 2 0_0201_5% BBA_SPI_DI C6 C9 BB_I2C_SCL 1 2 0_0201_5% TBTA_SPI_HOLD_N 1 2 1/20W_3.3K_5%_0201
FLSH_MSTR_SLV of BBR#1 (set as Master) should be PU
RU227 @ RU231 @ RU240
TBT_SPI_MISO 1 2 0_0201_5% BBA_SPI_DO B4 EE_DI I2C_SCL E7 BB_I2C_SDA 1 2 0_0201_5% TBTA_I2C_R_SCL 51,55 and PD for BBR#2 (set as Slave)
RU228 @ RU232 @
FLASH

TBT_SPI_CS_N 1 2 0_0201_5% BBA_SPI_CS_N B6 EE_DO I2C_SDA A10 TBTA_I2C_INT_N 1 2 0_0201_5% TBTA_I2C_R_SDA 51,55
RU229 @ RU233 @
TBT_SPI_CLK BBA_SPI_CLK EE_CS_N I2C_INT TBTA_FORCE_PWR TBT_I2C_INT_N 51

rS
RU230 1 @ 2 0_0201_5% C7 B10 RU234 1 @ 2 0_0201_5%
EE_CLK FORCE_PWR A9 TBTA_FLASH_BUSY_N CPU_TBT_FORCE_PWR_R 51
POC GPIO

FLASH_BUSY_N B9 BB_TBTA_GPIO_5
DEBUG

RESET# should be output from PD.

MISC &

POC_GPIO_5 A8 BB_TBTA_GPIO_6 3VALW_TBTA

TBTA_TDI POC_GPIO_6 BB_TBTA_PERST_N Pull up or Pull down based on USB PD Controller GPIO design.
A3 B8 Note: If the USB PD Controller has a weak pull up present during its
TBTA_TMS C3 TDI PERST_N A7 TBTA_SMBUS_SCL TBTA_RESET_N RU254 1 @ 2 100K_0201_5%
TBTA_TCK TMS SMBUS_SCL TBTA_SMBUS_SDA boot, a 10K to 100K Ohm pull down resistor is required to keep the
B5 B7 RU255 1 @ 2 100K_0201_5%
Burnside Bridge RESET_N low during the VCC_3P3_SX power supply
JTAG

TBTA_TDO C5 TCK SMBUS_SDA A4 BB_TBTA_FLSH_SHARE_EN +3VALW VCC3_BB_SPI

TDO POC_GPIO_10 A5 BB_TBTA_FLSH_MSTR_SLV ramp. The USB PD controller must drive RESET_N meeting the Burnside
POC_GPIO_11 A6 BB_TBTA_POC_GPIO12 CU224
Bridge datasheet timing requirements to take it out of reset. If the USB
POC_GPIO_12 L3 RU241 1 @ 2 0_0402_5% 1 2 PD Controller can hold RESET_N low during the Burnside Bridge
TBTA_THERMDA NC_L3
POC_GPIO_12 have iPU VCC_3P3_SX power supply ramp, a 10K to 100K Ohm pull up and
@ TP93 1 M11
THERMDA 0.1U_6.3V_K_X5R_0201 push/pull GPIO on the USB PD controller is recommended.
M12

fo
B2 TEST_EDM
Main power reset signal

8
FUSE_VQPS_64 L11 TBTA_RESET_N UU204
A11 RESET_N TBTA_RESET_N 51

VCC
A12 MONDC L9 TBTA_XTAL_25M_IN
DEBUG

Main

L12 NC_A12 XTAL_25_IN M9 TBTA_XTAL_25M_OUT

MONDC_SVR XTAL_25_OUT TBT_SPI_CS_N 1 5 TBT_SPI_MOSI
TBTA_TEST_PWRGD B3 L5 TBTA_RSENSE /CS DI(IO0)
B11 TEST_PWR_GOOD RSENSE L4 TBTA_RBIAS RU236 1 2 1/20W_4.75K_0.5%_0201
TEST_EN RBIAS TBT_SPI_MISO 2 6 TBT_SPI_CLK
A1 DO(IO1) CLK
ATEST_P
Place as close as
A2 possible to pins
ATEST_N TBTA_SPI_WP_N 3 7 TBTA_SPI_HOLD_N

C
JHL8040RSLMNx
@
Y
y /WP(IO2)
GND
/HOLD(IO3)

BB_TBTA_PERST_N
RU256
RU257
1 @
1 @
3VALW_TBTA

2 10K_0201_5%
2 10K_0201_5%
C
nl
W25Q80DVSSIG_SO8
4

RU258 1 @ 2 0_0201_5%
PLT_RST_N 17,32,63,71,73,76,79

BB_TBTA_PERST_N RU259 1 2 0_0201_5%

CPU_TBT_PERST_N 17
@

UU202B
lO

3.3V@ 230mA
L2 E6 IN
+VCC3V3_ANA_TBTA VCC3P3_ANA VCC3P3_SX 3VALW_TBTA
E5 M4
+VCC3V3_LC_TBTA VCC3P3_LC VCC3P3_SVR_1 M5
F6 VCC3P3_SVR_2
+VCC0V9_SVR_TBTA VCC0P9_SVR_ANA_1
3.3V@ 50mA
G6 J7 IN
3VA_TBTA
Power

VCC0P9_SVR_ANA_2 VCC3P3A
0.1U_6.3V_K_X5R_0201

E3 L1 3VALW_TBTA 3VALW_TBTA +3VALW_PCH 3VALW_TBTA

VCC0P9_SVR_1 SVR_IND_1 +VCC0V9_SVR_TBTA_IND
G3 M1 OUT
2.2K_0404_4P2R_5%

VCC0P9_SVR_2 SVR_IND_2 BB_TBTA_POC_GPIO12 RU260 1 @ 2 10K_0201_5%

E9 M2 1
4
3

VCC0P9_SVR_PB_ANA_1 SVR_VSS_1
CU225

G9 M3 RU261 1 @ 2 10K_0201_5%
VCC0P9_SVR_PB_ANA_2 SVR_VSS_2
tia
RPU205

J3 BB_TBTA_GPIO_5 RU262 1 2 100K_0201_5%

+VCC0V9_LC_TBTA VCC0P9_LC 2 TBTA_TEST_PWRGD RU263 1 2 1/20W_100_1%_0201
L6 J5 TBTA_NC_J5 RU464 1 @ 2 0_0201_5% UU205
+VCC0V9_LVR_TBTA 3VALW_TBTA
1
2

M6 VCC0P9_LVR NC_J5 J6 TBTA_NC_J6 RU465 1 @ 2 0_0201_5% 8 1

VCC0P9_LVR_SENSE NC_J6 VCCB VCCA
TBTA_SMBUS_SCL 7 2 CPU_SML0_CLK
JHL8040RSLMNx Y B0 A0
+3VALW_PCH TBTA_SMBUS_SDA 6 3 CPU_SML0_DATA
@ Pin J5 should be connected to
B1 A1
PW_VCC3v3_SX for DBR
1 2 0_0201_5% TBTA_SMBUS_OE 5 4
compatibility. for BBR this pin is NC in RU359 @
OE GND
the package.
en

3VALW_TBTA
FXMA2102UMX_U-MLP8_1P2X1P4
1

RU360 @
100K_0201_5% RPU206 1 4 2.2K_0404_4P2R_5% BB_I2C_SCL
2 3 BB_I2C_SDA
2

UU202C Y
RU264 1 @ 2 10K_0201_5% TBTA_I2C_INT_N
B1 F12
B12 VSS_ANA_1 VSS_ANA_12 G7
D1 VSS_ANA_2 VSS_ANA_13 H1
fid

D2 VSS_ANA_3 VSS_ANA_14 H2
D11 VSS_ANA_4 VSS_ANA_15 H11

B
D12
F1
VSS_ANA_5
VSS_ANA_6 GND VSS_ANA_16
VSS_ANA_17
H12
J9 B
F2 VSS_ANA_7 VSS_ANA_18 K1
F7 VSS_ANA_8 VSS_ANA_19 K2 TBTA_SMBUS_SCL RU242 1 @ 2 0_0201_5% CPU_SML0_CLK
F9 VSS_ANA_9 VSS_ANA_20 K11 CPU_SML0_CLK 11
F11 VSS_ANA_10 VSS_ANA_21 K12 TBTA_SMBUS_SDA RU243 1 @ 2 0_0201_5% CPU_SML0_DATA
VSS_1
VSS_2
VSS_3

VSS_ANA_11 VSS_ANA_22 CPU_SML0_DATA 11

on
F3
F5
G5

JHL8040RSLMNx
@
C

XTAL
TBTA_XTAL_25M_IN_R RU265 1 @ 2 0_0402_5% TBTA_XTAL_25M_IN

LU202 EMC_NS@
4 3
4 3
FC

0.9v @850mA 1 2
1 2
+3VALW For BBR,
3VALW_TBTA C3718 +VCC0V9_SVR_TBTA_IND +VCC0V9_SVR_TBTA EXC24CH500U_4P
3VALW_TBTA LU201
1 can be
1 2 TBTA_XTAL_25M_OUT_R 1 2 0_0402_5% TBTA_XTAL_25M_OUT
removed. RU266 @
CU166
UU203
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_0402_6.3V6K 1 1 1 1 1 1 0.68UH_DFE201610E-R68M-P2_3.1A_20% 1 1 1 1 1 1 1 1 1 1
2
10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201

CU242
2.2U_6.3V_M_X5R_0201

CU243
2.2U_6.3V_M_X5R_0201

CU248
2.2U_6.3V_M_X5R_0201

CU249
2.2U_6.3V_M_X5R_0201

CU250
2.2U_6.3V_M_X5R_0201

CU251
2.2U_6.3V_M_X5R_0201

CU252
2.2U_6.3V_M_X5R_0201

CU253
2.2U_6.3V_M_X5R_0201

1 14 +3VTBTA RU680 2 @ 1 0_5%_0603

Pin J5

Pin E6

Inductor must be placed on the

Pin M4

Pin M5

VIN1_1 VOUT1_2 1 1 TBTA_XTAL_25M_IN_R

CU238

CU239

CU240

CU241

CU244

CU245

CU246

CU247

2 13 same side as BB. No vias allowed

VIN1_2 VOUT1_1
CU7296

CU7297

CU7298
Pin E3

Pin E9

Pin G6

Pin G3

Pin G9
Pin F6

TBTA_PWR_EN 2 2 2 2 2 2
on VCC0v9_SVR_IND 2 2 2 2 2 2 2 2 2 2 YU1
3 12 1 2 1000P_50V_K_X7R_0201
51 TBTA_PWR_EN ON1 CT1 2 2
4 11 2 3 TBTA_XTAL_25M_OUT_R
LC

+3VALW VBIAS GND NC1 OSC2

0.01U_0402_25V7K
CU999

1 CU7299
1

5 10 1 2 1000P_50V_K_X7R_0201 1 4
@ RU95 ON2 CT2 OSC1 NC2
10K_0201_5% 6 9 +3VTBTA 1 1
2 +3VALW VIN2_1 VOUT2_2
7 8 Share Same GND plane and connect to M2 & M3 pins (SVR_VSS) of BB
A VIN2_2 VOUT2_1 CU226 25MHZ_10PF_7R25000006 CU227 A
2

1 15 10P_0201_25V8G 10P_0201_25V8G
GPAD 2 2
CU169 TPS22976DPUR_WSON_2X3
1U_0402_6.3V6K
2

3VALW_TBTA 3VA_TBTA +VCC3V3_ANA_TBTA +VCC3V3_LC_TBTA +VCC0V9_LC_TBTA +VCC0V9_LVR_TBTA

RU269 1 @ 2 0_0402_5%
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

RU270 1 @ 2 0_0402_5% 1 1 1 1 1 1 1 1
CU254

CU255
2.2U_6.3V_M_X5R_0201

CU347
18P_50V_J_NPO_0201

CU256
2.2U_6.3V_M_X5R_0201

CU257
2.2U_6.3V_M_X5R_0201

CU258
2.2U_6.3V_M_X5R_0201

CU259

CU260
2.2U_6.3V_M_X5R_0201
Pin L2

Pin E5

Pin L6
Pin J7

Pin J7

Pin J3

2 2 2 2 2 2 2 2
@ Title
Security Classification LCFC Highly Confidential Information
Place holder for RC filter to reduce Yoga C970-ADL
Issued Date 2021/01/19 Deciphered Date 2022/01/19
ripple to VCC3v3A pin
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
TYPEC_MUX_PortA A0

Date: Monday, November 29, 2021 Sheet 52 of 110

5 4 3 2 1
 5 4 3 2 1

Reduce current surge in a

VBUS-short event. If not AC coupling is recommended for
needed, place 0Ohm VBUS-short protection on SSRX lines. If +3VALW
resistor instead. not needed, place 0Ohm resistor instead.
TBTA_RX0_P RU271 1 2 1/20W_2.2_1%_0201 TBTA_RX0_R_P CU261 1 2 0.33U_25V_K_X5R_0201 TBTA_RX0_C_P
52 TBTA_RX0_P

2
TBTA_RX0_N RU272 1 2 1/20W_2.2_1%_0201 TBTA_RX0_R_N CU262 1 2 0.33U_25V_K_X5R_0201 TBTA_RX0_C_N
52 TBTA_RX0_N
RU290
TBTA_TX0_P RU273 1 2 1/20W_2.2_1%_0201 TBTA_TX0_R_P CU263 1 2 0.22U_25V_K_X5R_0201 TBTA_TX0_C_P 100K_0201_5%
52 TBTA_TX0_P TBTA_TX0_N RU274 1 2 1/20W_2.2_1%_0201 TBTA_TX0_R_N CU264 1 2 0.22U_25V_K_X5R_0201 TBTA_TX0_C_N
52 TBTA_TX0_N

1
TBTA_RX1_P RU275 1 2 1/20W_2.2_1%_0201 TBTA_RX1_R_P CU265 1 2 0.33U_25V_K_X5R_0201 TBTA_RX1_C_P TBT_USB2_ON_N
52 TBTA_RX1_P TBTA_RX1_N @ TBT_USB2_ON_N 56,62
RU276 1 2 1/20W_2.2_1%_0201 TBTA_RX1_R_N CU266 1 2 0.33U_25V_K_X5R_0201 TBTA_RX1_C_N
52 TBTA_RX1_N
TBTA_TX1_P RU277 1 2 1/20W_2.2_1%_0201 TBTA_TX1_R_P CU267 1 2 0.22U_25V_K_X5R_0201 TBTA_TX1_C_P
52 TBTA_TX1_P

3
TBTA_TX1_N RU278 1 2 1/20W_2.2_1%_0201 TBTA_TX1_R_N CU268 1 2 0.22U_25V_K_X5R_0201 TBTA_TX1_C_N D
52 TBTA_TX1_N TBT_USB2_ON
RU287 1 2 0_0201_5% 1
D 79 EC_ON_PCH G L2N7002KN3T5G_SOT883-3 D

@ QU201

1
S

2
RU289
@ @
100K_0201_5%
Signal:TBT_USB2_ON_N
Bleeding SSTX/SSRX resistors Voltage Level:3.3V

2
L2N7002KN3T5G_SOT883-3
must be placed near USBC connector if 330nF cap 0113,change from module Vds max=60V
DU202 DU203 is being used. Otherwise de-populate. Vgs max=+/- 20V
@ @
Vgs(th)=1.0V/2.5V(min/max)
TBTA_RX0_R_P 1 2 2 1 TBTA_RX0_R_N 1 2 1/20W_220K_1%_0201 TBTA_RX0_C_P Rds(ON)=2.7ohm(max,Vgs=5 V)
RU279 Id=320mA(TA =25 C )
1 2 2 1

T
Ton Delay=9.9ns
RU280 1 2 1/20W_220K_1%_0201 TBTA_RX0_C_N Rise time=5ns
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 RU281 1 2 1/20W_220K_1%_0201 TBTA_TX0_C_P
DU204 DU205 +3VALW_PCH

M
@ @
RU282 1 2 1/20W_220K_1%_0201 TBTA_TX0_C_N
TBTA_TX0_R_P 1 2 2 1 TBTA_TX0_R_N
1 2 2 1 RU283 1 2 1/20W_220K_1%_0201 TBTA_RX1_C_P 1U_6.3V_M_X5R_0201 1 2 CU269
UU206
RU284 1 2 1/20W_220K_1%_0201 TBTA_RX1_C_N @

rS
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 0.1U_6.3V_K_X5R_0201 1 2 CU270 8 7
DU206 DU207 TBTA_TX1_C_P VCC NC
@ @ RU285 1 2 1/20W_220K_1%_0201
@
TBTA_RX1_R_P 1 2 2 1 TBTA_RX1_R_N RU286 1 2 1/20W_220K_1%_0201 TBTA_TX1_C_N USB20_7_P 2 3 USB20_7_U_P
1 2 2 1 14 USB20_7_P HSD+ D+
USB20_7_N 6 5 USB20_7_U_N
14 USB20_7_N HSD- D-
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
DU208 DU209 TBT_USB2_ON_N
@ @ 1 4

fo
OE# GND
TBTA_TX1_R_P 1 2 2 1 TBTA_TX1_R_N
1 2 2 1 TS3USB31ERSER_UQFN8_1P5X1P5
@
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
PCH
C C

ESD Diodes should be located as close as possible to USBC.

y USB20_7_P

USB20_7_N
RU291

RU292
1

1
@

@
2 0_0201_5%

2 0_0201_5%
USB20_7_U_P

USB20_7_U_N
nl
lO

RU293 1 @ 2 0_0402_5%

EMC@
EXC24CH900U_4P
tia

USB20_7_U_N 3 4 TBTA_USB2_CON_N
3 4

USB20_7_U_P 2 1 TBTA_USB2_CON_P
2 1
LU203
TBTA_SBU1 RU1108 1 @ 2 0_0201_5% TBTA_SBU1_CON
52 TBTA_SBU1
en

TBTA_SBU2 RU1109 1 @ 2 0_0201_5% TBTA_SBU2_CON RU294 1 @ 2 0_0402_5%

52 TBTA_SBU2
TBTA_CC1 RU1110 1 @ 2 0_0201_5% TBTA_CC1_CON
51 TBTA_CC1 TBTA_CC2 TBTA_CC2_CON
RU1111 1 @ 2 0_0201_5%
51 TBTA_CC2

TBTA_SBU1_CON RU652 2 @ 1 1/20W_1M_1%_0201

TBTA_SBU2_CON RU653 2 @ 1 1/20W_1M_1%_0201
fid

VBUS_TBTA VBUS_TBTA
B B
JUSBC1
on

B12 A1
GND4 GND1
TBTA_RX0_C_P B11 A2 TBTA_TX0_C_P
SSRXP1 SSTXP1
TBTA_RX0_C_N B10 A3 TBTA_TX0_C_N
SSRXN1 SSTXN1
C

B9 A4
VBUS4 VBUS1
TBTA_SBU2_CON B8 A5 TBTA_CC1_CON
SBU2 CC1
VBUS_TBTA TBTA_USB2_CON_N B7 A6 TBTA_USB2_CON_P
DN2 DP1
TBTA_USB2_CON_P B6 A7 TBTA_USB2_CON_N
FC

DP2 DN1
DU210 EMC_NS@ DU211 EMC_NS@ Near Near Near Near TBTA_CC2_CON B5 A8 TBTA_SBU1_CON
PinB9 PinB4 CC2 SBU1
0.01U_25V_K_X5R_0201

0.01U_25V_K_X5R_0201

0.01U_25V_K_X5R_0201

0.01U_25V_K_X5R_0201

TBTA_USB2_CON_N 1 2 2 1 TBTA_USB2_CON_P PinA9 PinA4 B4 A9

1 2 2 1 1 1 1 1 VBUS3 VBUS2
CU273

CU274

CU275

CU276

TBTA_TX1_C_N B3 A10 TBTA_RX1_C_N

SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2 SSTXN2 SSRXN2
2 2 2 2 TBTA_TX1_C_P B2 A11 TBTA_RX1_C_P
SSTXP2 SSRXP2
LC

DU212 EMC_NS@ DU213 EMC_NS@ B1 A12

GND3 GND2
TBTA_SBU1_CON 1 2 2 1 TBTA_SBU2_CON
1 2 2 1 25 28
26 GND5 GND8 29
SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2 27 GND6 GND9 30
GND7 GND10
DU214 EMC_NS@ DU215 EMC_NS@
1124x HIGHSTAR_UB11249-23003-1H
TBTA_CC1_CON 1 2 2 1 TBTA_CC2_CON
1 2 2 1 5=5" gold plating ME@
9=30" gold plating
SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2
B200x
A A
W:镀镀镀
DU216 H: 镀镀镀
EMC_NS@

VBUS_TBTA 1 2
1 2

SPHV24-01ETG-C_SOD882-2

FOR ESD Security Classification LCFC Highly Confidential Information Title

Yoga C970-ADL
Issued Date 2021/01/19 Deciphered Date 2022/01/19
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TYPEC_CONN_PortA
Date: Monday, November 29, 2021 Sheet 53 of 110
5 4 3 2 1
 5 4 3 2 1

D D

T
M
rS
fo
C
y C
nl
lO
tia
en
fid

B B
on
C
FC
LC

A A

Title
<Title>

Size Document Number Rev

D <Doc> A0

Date: Monday, November 29, 2021 Sheet 54 of 110

5 4 3 2 1
 5 4 3 2 1

+3VALW_SYS
VCC3_PS8812_B VCC3_PS8812_B VCC1R2M_B

RU666 1 @ 2 0_5%_0603
0.01U_25V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1
CU1027

CU1032
4.7U_0402_6.3V6M

CU457

CU458

CU459

CU793

CU916

CU794

CU917
CU1026

CU480

@ @

2 2 2 2 2 2 2 2 2 2 2

VCC3_PS8812_B VDD_DCI_B

+3VALW_SYS
RU667 1 @ 2 0_5%_0603
D D
RU454 1 2 100K_0201_5% GPU_IFPA_AUXN_C

RU457 1 2 100K_0201_5% GPU_IFPA_AUXP_C

100P 25V J NPO 0201

100P 25V J NPO 0201

1 1

M
@ @

2 2

CU478

CU479
rS
VCC3_PS8812_B VDD_DCI_B

VCC1R2M_B SA00009F910 做BOM

DP3_AUXP_R RU1003 1 @ 2 0_0201_5% USBC2_DPAUX1_CONN
DP3_AUXN_R RU1004 1 @ 2 0_0201_5% USBC2_DPAUX2_CONN USBC2_DPAUX1_CONN 56
USBC2_DPAUX2_CONN 56
UU6
1 52
2 VDD_DM_1 VDD33_2 51

fo
56 PS8812_USBC4_RX1_P 3 RX1p DCI_DATA 50
56 PS8812_USBC4_RX1_N 4 RX1n DCI_CLK 49
5 TEST VDD_DCI 48 PS8812_CEQ_2
6 RSV CEQ 47
7 VDD_R1 VDD_A2 46 PS8812_SSEQ_2
56 PS8812_USBC4_RX2_N 8 VDD_R2 SSEQ 45
RX2n TX2p PS8812_USBC4_TX2_P 56
56 PS8812_USBC4_RX2_P 9 44
10 RX2p TX2n 43 PS8812_RESET_N_2 PS8812_USBC4_TX2_N 56
CU460 1 2 0.33U_25V_K_X5R_0201 USB30_RX1_MUX_N 11 VDD_DM_2 RESET# 42
14 USB30_RX1_N USB30_RX1_MUX_P SSRXn TX1n PS8812_USBC4_TX1_N 56
CU461 1 2 0.33U_25V_K_X5R_0201 12 41
14 USB30_RX1_P 13 SSRXp TX1p 40 TYPE-C_DP_RE_HPD2 PS8812_USBC4_TX1_P 56
1 2 0.22U_6.3V_K_X5R_0201 USB30_TX1_MUX_N 14 VDD_A1 IN_HPD 39 TYPE-C_DP_RE_HPD2 51
CU462

C
29
29
14
14
USB30_TX1_N
USB30_TX1_P

GPU_IFPA_TX0_P
GPU_IFPA_TX0_N
CU463

CU464
CU465
1

1
1
2 0.22U_6.3V_K_X5R_0201 USB30_TX1_MUX_P

2 0.1U_6.3V_K_X5R_0201
2 0.1U_6.3V_K_X5R_0201
TYPE-C2_DP_RE_TXP0
TYPE-C2_DP_RE_TXN0
PS8812_ADDR_2
15
16
17
18
19
SSTXn
SSTXp
VDD_DM_3
ML0p
ML0n
REXT
VDD_DM_4
FLIP
CE_USB
CE_DP
38
37
36
35
34
MUX_REXT2

DP3_AUXN_R
PS8812_FLIP_C2
PS8812_USB_MODE_C2
PS8812_DP_MODE_C2
y
PS8812_FLIP_C2 51
PS8812_USB_MODE_C2
PS8812_DP_MODE_C2
51
51
VCC3_PS8812_B

1
RU463
2
VCC3_PS8812_B

1
RU1026
2
UU2
C
@ @ TPS74801DRCR_SON-10_3X3
TYPE-C2_DP_RE_TXP1 ADDR SBU2 DP3_AUXP_R VCC3_PS8812_B_PG
nl
CU466 1 2 0.1U_6.3V_K_X5R_0201 20 33 3 6
29 GPU_IFPA_TX1_P 1 2 0.1U_6.3V_K_X5R_0201 TYPE-C2_DP_RE_TXN1 21 ML1p SBU1 32 GPU_IFPA_AUXN_C CU468 1 2 4 PG GND1 7
CU467 0.1U_6.3V_K_X5R_0201 RU1027 1/20W_100K_1%_0201 1/20W_100K_1%_0201 RU435
29 GPU_IFPA_TX1_N PS8812_DPEQ2 22 ML1n AUXn 31 GPU_IFPA_AUXP_C CU469 1 2 GPU_IFPA_AUXN 29 1 2 VCC1R2M_B_EN 5 BIAS SS 8 VCC1R2M_B_FB 1 2 VCC1R2M_B
0.1U_6.3V_K_X5R_0201
CU470 1 2 0.1U_6.3V_K_X5R_0201 TYPE-C2_DP_RE_TXP2 23 DPEQ AUXp 30 GPU_IFPA_AUXP 29 EN FB
29 GPU_IFPA_TX2_P 1 2 0.1U_6.3V_K_X5R_0201 TYPE-C2_DP_RE_TXN2 24 ML2p VDD_D1 29 PDC_SDA2_R 1 2 0_0201_5%
CU471 RU445 @ 1/20W_100K_1%_0201 2.49K_0402_1%
29 GPU_IFPA_TX2_N 1 2 0.1U_6.3V_K_X5R_0201 TYPE-C2_DP_RE_TXP3 25 ML2n CSDA 28 PDC_SCL2_R 1 2 0_0201_5% TBTA_I2C_R_SDA 51,52 2 9
CU472 RU446 @
GND

29 GPU_IFPA_TX3_P 1 2 0.1U_6.3V_K_X5R_0201 TYPE-C2_DP_RE_TXN3 26 ML3p CSCL 27 TBTA_I2C_R_SCL 51,52 IN2 OUT1

CU473
29 GPU_IFPA_TX3_N ML3n VDD33_1

GND2
@ PS8812QFN52GTRA2_QFN52_6P5X4P5 1 10
lO
53

IN1 OUT2

UU2_SS
2

11
RU437

1/20W_4.99K_1%_0201
1
4.99K_0402_1% 1

22P_0201_258J

RU438
CU474 1
1

10U 6.3V M X5R 0402

EMC_NS@
@ 1 CU475

CU455

10U 6.3V M X5R 0402

2

2
2
2
tia
en

VCC3_PS8812_B
fid

RU439 2 1 1/20W_4.7K_5%_0201 PS8812_DP_MODE_C2

B RU440 2 1 1/20W_4.7K_5%_0201 PS8812_FLIP_C2 VCC3_PS8812_B +1.8VS_AON B

RU441 2 1 1/20W_4.7K_5%_0201 PS8812_USB_MODE_C2

HPD
1

RU447

pin control mode, connect to PDC

1

follow yoga740 change to stuff

on

07/01 YONG RU436 10K_0201_5%

2

100K_0201_5% IFPA_HPD
to NV GPU 32 IFPA_HPD
2

PS8812_RESET_N_2 QU101
MMBT3904WH_SOT323-3
1

C RU448 RU449
1 2TYPE-C_DP_RE_HPD2_Q1 2 TYPE-C_DP_RE_HPD2_R1 @ 2 0_0201_5% TYPE-C_DP_RE_HPD2
CU476 B
0.1U_6.3V_K_X5R_0201

VCC3_PS8812_B E 100K_0201_5%
3

RU450
C

2
2 1 PS8812_DPEQ2 RU453 1 2 1/20W_4.7K_5%_0201 2
@ 1 CU477 RU451
RU452 1/20W_4.7K_5%_0201
100K_0201_5%
2 1 PS8812_CEQ_2 RU456 1 2 1/20W_4.7K_5%_0201 220P_50V_K_X7R_0201
1

RU455 1/20W_4.7K_5%_0201 2 100K_0201_5%

1
2 1 PS8812_ADDR_2 RU459 1 2 1/20W_4.7K_5%_0201
@
RU458 1/20W_4.7K_5%_0201
Automatic DCI mode ent 2 1 PS8812_SSEQ_2 RU461 2 1 1/20W_4.7K_5%_0201
ering enabled @ @
FC

RU460 1/20W_4.7K_5%_0201

TYPE-C_DP_HPD2 1 2 0_0201_5% TYPE-C_DP_RE_HPD2

to APU 12 TYPE-C_DP_HPD2
RU668 @
LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 DC V TO VS INTERFACE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y540 A0

Date: Monday, November 29, 2021 Sheet 55 of 110

5 4 3 2 1
 5 4 3 2 1

VBUS_TBTB

USB20_8_CONN_P
USB20_8_CONN_N

AZ5725-01F.R7GR_DFN1006P2X2

0.01U_25V_K_X5R_0201

0.01U_25V_K_X5R_0201

0.01U_25V_K_X5R_0201

0.01U_25V_K_X5R_0201
1U_0603_25V6K
1
AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
JUSBC2 1 1 1 1 1

CU59

CU60

CU61

CU62

CU63
1
2

EMC_NS@

DU28
B12 A1 DU23 DU24 @
GND4 GND1

2
USBC4_RX1_CON_P B11 A2 USBC4_TX1_CON_P 2 2 2 2 2
SSRXP1 SSTXP1
USBC4_RX1_CON_N USBC4_TX1_CON_N

2
B10 A3
SSRXN1 SSTXN1

2
1

1
B9 A4
RU669 1 @ 2 0_0402_5% VBUS_TBTB VBUS4 VBUS1 VBUS_TBTB EMC_NS@ EMC_NS@

1
D USBC2_DPAUX2_CONN B8 A5 USBC2_CC1_CONN D
55 USBC2_DPAUX2_CONN SBU2 CC1 USBC2_CC1_CONN 51
USB20_8_CONN_N B7 A6 USB20_8_CONN_P
LU24 @ DN2 DP1
PS8812_USBC4_TX1_P 1 2 PS8812_USBC4_TX1_R_P CU52 1 2 0.22U_25V_K_X5R_0201 USBC4_TX1_CON_P USB20_8_CONN_P B6 A7 USB20_8_CONN_N

T
55 PS8812_USBC4_TX1_P 1 2 DP2 DN1
USBC2_CC2_CONN B5 A8 USBC2_DPAUX1_CONN
PS8812_USBC4_TX1_N PS8812_USBC4_TX1_R_N USBC4_TX1_CON_N 51 USBC2_CC2_CONN CC2 SBU1 USBC2_DPAUX1_CONN 55
4 3 CU51 1 2 0.22U_25V_K_X5R_0201
55 PS8812_USBC4_TX1_N 4 3 B4 A9
EXC24CH500U_4P VBUS_TBTB USBC4_TX2_CON_N
VBUS3 VBUS2
USBC4_RX2_CON_N
VBUS_TBTB
B3 A10
SSTXN2 SSRXN2

M
USBC4_TX2_CON_P B2 A11 USBC4_RX2_CON_P
RU710 1 @ 2 0_0402_5% SSTXP2 SSRXP2
B1 A12
GND3 GND2 USBC2_DPAUX1_CONN RU801 1 2 2M_0402_5%

RU670 1 @ 2 0_0402_5% 25 28
26 GND5 GND8 29 USBC2_DPAUX2_CONN RU802 1 2 2M_0402_5%
27 GND6 GND9 30
GND7 GND10

rS
DU25
LU25 EMC_NS@ USBC2_DPAUX1_CONN 9 10 1 USBC2_DPAUX1_CONN
1
PS8812_USBC4_TX2_N 1 2 PS8812_USBC4_TX2_R_N CU54 1 2 0.22U_25V_K_X5R_0201 USBC4_TX2_CON_N HIGHSTAR_UB11249-23003-1H
55 PS8812_USBC4_TX2_N 1 2 USBC2_DPAUX2_CONN 8 2 USBC2_DPAUX2_CONN
ME@ 9 2
PS8812_USBC4_TX2_P 4 3 PS8812_USBC4_TX2_R_P CU53 1 2 0.22U_25V_K_X5R_0201 USBC4_TX2_CON_P USBC2_CC1_CONN 7 4 USBC2_CC1_CONN
7 4
55 PS8812_USBC4_TX2_P 4 3
EXC24CH500U_4P USBC2_CC2_CONN 6 5 USBC2_CC2_CONN
6 5

3 3

RU671 1 @ 2 0_0402_5% 8
USBC4_RX1_CON_N RU726 1 2 220K_0201_5% AZ1045-04F_DFN2510P10E-10-9

fo
USBC4_RX1_CON_P RU727 1 2 220K_0201_5% EMC_NS@
USBC4_RX2_CON_P RU903 1 2 220K_0201_5%
USBC4_RX2_CON_N RU902 1 2 220K_0201_5%

RU672 1 @ 2 0_0402_5%

EMC_NS@
EXC24CH500U_4P
PS8812_USBC4_RX1_N 4 3 PS8812_USBC4_RX1_R_N CU55 1 2 0.33U_25V_K_X5R_0201 USBC4_RX1_CON_N

C
55

55
PS8812_USBC4_RX1_N

PS8812_USBC4_RX1_P
PS8812_USBC4_RX1_P 1
4

1
3

2
2 PS8812_USBC4_RX1_R_P CU56 1 2 0.33U_25V_K_X5R_0201 USBC4_RX1_CON_P
y DU26
AZ174S-04FPR7G_DFN2510P10E10
C
LU26
nl
USBC4_TX2_CON_P 10 5 USBC4_RX2_CON_N
USBC4_TX2_CON_N 9 NC4 Line-4 4 USBC4_RX2_CON_P
USBC4_RX2_CON_P 7 NC3 Line-3 2 USBC4_TX2_CON_N
RU673 1 @ 2 0_0402_5% USBC4_RX2_CON_N NC2 Line-2 USBC4_TX2_CON_P

GND2
GND1
6 1
NC1 Line-1

EMC_NS@

8
3
lO

RU674 1 @ 2 0_0402_5%

LU27
EMC_NS@
PS8812_USBC4_RX2_N 1 2 PS8812_USBC4_RX2_R_N CU58 1 2 0.33U_25V_K_X5R_0201 USBC4_RX2_CON_N
55 PS8812_USBC4_RX2_N 1 2

PS8812_USBC4_RX2_P PS8812_USBC4_RX2_R_P USBC4_RX2_CON_P

DU26 & DU27 Change to SC300007A00 使用使使做BOM
4 3 CU57 1 2 0.33U_25V_K_X5R_0201
55 PS8812_USBC4_RX2_P 4 3
EXC24CH500U_4P
tia

RU675 1 @ 2 0_0402_5% DU27

AZ174S-04FPR7G_DFN2510P10E10

USBC4_TX1_CON_P 10 5 USBC4_RX1_CON_N
USBC4_TX1_CON_N 9 NC4 Line-4 4 USBC4_RX1_CON_P
USBC4_RX1_CON_P 7 NC3 Line-3 2 USBC4_TX1_CON_N
USBC4_RX1_CON_N NC2 Line-2 USBC4_TX1_CON_P
GND2
GND1
6 1
NC1 Line-1
en

EMC_NS@
8
3
fid

+3VALW_PCH
UU140

B CU930 1 @ 2 0.1U_6.3V_K_X5R_02018 7 B
VCC NC
CU931 1 @ 2 1U_6.3V_M_X5R_0201
2 3 USB20_8_R_P
14 USB20_8_P HSD+ D+
6 5 USB20_8_R_N
14 USB20_8_N HSD- D-
on

TBT_USB2_ON_N 1 4
53 TBT_USB2_ON_N OE# GND

TS3USB31ERSER_UQFN8_1P5X1P5
@

USB20_8_R_P RU1021 1 @ 2 0_0201_5% USB20_8_P

USB20_8_R_N RU1022 1 @ 2 0_0201_5% USB20_8_N

C

1 2 0_0402_5%
FC

RU912 @

EMC@
EXC24CH900U_4P
USB20_8_R_N 1 2 USB20_8_CONN_N
1 2

USB20_8_R_P 4 3 USB20_8_CONN_P
4 3
LU23

RU911 1 @ 2 0_0402_5%
LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 DC V TO VS INTERFACE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y540 A0

Date: Monday, November 29, 2021 Sheet 56 of 110

5 4 3 2 1
 5 4 3 2 1

USB3.1 PORT x2
+USB_VCCB
+5VALW
Low Active 2.2A
UU134 CU73 1 2 100U_1206_6.3V6M +USB_VCCB
5 1
IN OUT
2 2
CU76 GND
4 3 USB_OC0_N @
D
1U_6.3V_M_X5R_0201 ENB OCB USB_OC0_N 14,59 CU74 1 2 D
1 SY6288D20AAC_SOT23-5 1U_0603_25V6M
1
@
@ CU77 CU75 1 2 470P_50V_K_X7R_0201
1000P_0402_50V_X7R_0402
2
USB_ON_N
78,79 USB_ON_N
JUA1
1
USB20_2_CON_N 2 VBUS
USB20_2_CON_P 3 D-
D+

T
4
USB30_RX1_CON_N 5 GND1
USB30_RX1_CON_P 6 SSRX- 10
RU133 1 @ 2 0_0402_5% UARTA_P80_EN 7 SSRX+ GND3 11
USB30_TX1_CON_N 8 GND2 GND4 12

M
USB30_TX1_CON_P 9 SSTX- GND5 13
SSTX+ GND6

USB@ 2

1
0_0402_5%
LU101 EMC@
USBP3-_S 1 2 USB20_2_CON_N RU1033

RU1028
1 2 100K_0402_5% ALLTO_C107MJ-10939-L
Debug@ ME@

rS
USBP3+_S 4 3 USB20_2_CON_P

2
4 3
EXC24CH900U_4P

RU134 1 @ 2 0_0402_5%

RU136 1 @ 2 0_0402_5%

fo
LU99 EMC_NS@
1 2 USB30_RX1_CON_N
58 USB30_HUB2_RX_N 1 2

C 4 3 USB30_RX1_CON_P C
58 USB30_HUB2_RX_P 4
EXC24CH900U_4P
3
y
nl
RU135 1 @ 2 0_0402_5%

RU132 1 @ 2 0_0402_5%
For USB Debug Function
lO

LU100 EMC_NS@
1 2 USB30_TX1_R_N CU80 1 USB30_TX1_CON_N
2 0.1u_0201_10V6K
58 USB30_HUB2_TX_N 1 2

USB30_TX1_R_P CU79 1 USB30_TX1_CON_P UI129

4 3 2 0.1u_0201_10V6K
58 USB30_HUB2_TX_P 4 3
EXC24CH900U_4P
tia

RU600 2 Debug@ 1 0_0402_5% EC_TX_C 1 10 RU602 2 Debug@ 1 0_0402_5% +3VALW

71,79 EC_TX 1D+ VCC
RU131 1 @ 2 0_0402_5%
RU601 2 Debug@ 1 0_0402_5% EC_RX_C 2 9 USB_UART_SEL
71,79 EC_RX 1D- S
3 8 USBP3+_S
58 USB20_HUB2_P 2D+ D+
NCY3958Y USBP3-_S
4 7
58 USB20_HUB2_N 2D- D-
en

5 6
GND1 OE# +3VALW
11
EMC close to USB Conn GND2

USBDEBUG Kernel debug

1
fid

NCT3958Y_DFN10_3X3 RU605
DU106 Set input Set input Debug@ 10K_0402_5%
USB30_RX1_CON_N 10 1 USB30_RX1_CON_N Debug@
NC1 Line-1 Set output Low ENABLE

2
USB30_RX1_CON_P 9 2 USB30_RX1_CON_P USB_UART_SEL
B NC2 Line-2 B
USB30_TX1_CON_N 7 4 USB30_TX1_CON_N
on

NC3 Line-3

1
USB30_TX1_CON_P 6 5 USB30_TX1_CON_P USB20_HUB2_P 2 USB@1 USBP3+_S QU13 D
NC4 Line-4 RU603 0_0402_5% UARTA_P80_EN 2
3
UARTA_P80_EN POST 80 G
GND1 USB20_HUB2_N 2 USB@1 USBP3-_S
8 Set input DISABLE RU604 0_0402_5% 2N7002KW_SOT323-3 S

3
GND2
Debug@
C

AZ1143-04F-R7G_DFN2510P10E10 Set output Low ENABLE

EMC@

USB20_2_CON_P 新新USB Debug 线线

FC

+USB_VCCB
USB20_2_CON_N OE# S FUNCTION
H X DISABLE
1

DU108 L L D(+/-) to 1D(+/-)

1

EMC@ DU107 L H D(+/-) to 2D(+/-)

AZC199-02S.R7G_SOT23-3
LC

EMC@
2
2

AZ5725-01F.R7GR_DFN1006P2X2
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 USB2.0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, November 29, 2021 Sheet 57 of 110
5 4 3 2 1
 5 4 3 2 1

+3V_HUB +3V_HUB
+DVDD12_HUB +AVDD12_HUB
LU97 LU98

0.1U_6.3V_K_X5R_0201
USB_HUB_1V2_SW 1 2 USB_HUB_1V2_FB 1 2
1
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
10U_0603_6.3V6M

10U_0603_6.3V6M
2.2UH_EP-22AM05B02_2A_20% HCB1608KF-181T20_2P

CU816
1 1 1 1 1 1 1 1 1 1 1 1 1
2
CU904

CU905

CU906

CU907

CU808

CU809

CU810

CU926

CU811

CU812

CU813

CU814

CU815
+3V_HUB
D 2 2 2 2 2 2 2 2 2 2 2 2 2 D

UU36

0.1U_6.3V_K_X5R_0201
8
1

VCC
SPI_HUB_CS# RU324 1 2 10K_0201_5%
SPI_HUB_CLK 6 1 SPI_HUB_CS# SPI_HUB_MISO RU325 1 2 10K_0201_5%

CU817
SPI_HUB_MOSI 5 CLK CS# 3 SPI_HUB_WP# SPI_HUB_WP# RU1064 1 2 10K_0201_5%
SPI_HUB_MISO 2 DI WP# 7 SPI_HUB_HD# SPI_HUB_MOSI RU1065 1 2 10K_0201_5% 2
DO HOLD# SPI_HUB_CLK RU1066 1 2 10K_0201_5%

GND
SPI_HUB_HD# RU1070 1 2 10K_0201_5%

+3V_HUB W25X05CLSNIG_SO8

T
+AVDD12_HUB +DVDD12_HUB

M
12
45

29

37
27
1
7

UU138 +5VALW_HUB +5VALW_HUB

AVDD12
VP12_P3
VP12_P2
VP12_P0

DVDD12

DVDD33
V33

rS

1/20W_4.7K_5%_0201
15K_0201_1%
3 41

RU1068

RU1069
59 USB20_HUB3_P DP_P3 DP_P0 USB20_2_P 14
4 42
59 USB20_HUB3_N DM_P3 DM_P0 USB20_2_N 14
59 USB30_HUB3_TX_N
5 43 CU923 1 2 0.1U_6.3V_K_X5R_0201
TXN1_P3 TXN1_P0 USB30_RX3_N 14
6 44 CU924 1 2 0.1U_6.3V_K_X5R_0201
59 USB30_HUB3_TX_P USB30_RX3_P 14

2
8 TXP1_P3 TXP1_P0 46 CU821 1 2 0.1U_6.3V_K_X5R_0201
59 USB30_HUB3_RX_N RXN1_P3 RXN1_P0 USB30_TX3_N 14 USB_HUB_RESET# USB_HUB_VBUSIN
9 47 CU922 1 2 0.1U_6.3V_K_X5R_0201

fo
59 USB30_HUB3_RX_P RXP1_P3 RXP1_P0 USB30_TX3_P 14

1/20W_30K_1%_0201
10 31 SPI_HUB_MOSI
57 USB30_HUB2_TX_N TXN1_P2 GL3523 P_SPI_DO

1
11 32 SPI_HUB_CLK
1

10K_0201_5%
1U_0402_6.3V6K
57 USB30_HUB2_TX_P TXP1_P2 P_SPI_CK

2
13 33 SPI_HUB_MISO
QFN-48

RU334

RU335
57 USB30_HUB2_RX_N RXN1_P2 P_SPI_DI SPI_HUB_CS#
14 34

CU818
57 USB30_HUB2_RX_P RXP1_P2 P_SPI_CZ
15
57 USB20_HUB2_P DP_P2 2
C 16 C
57 USB20_HUB2_N
y

2
DM_P2 35 USB_HUB_PGANG RU336 1 2 100K_0201_5%

1
18 PGANG 28 USB_HUB_RTERM RU337 1 2
USB_OC_R 19 PWREN3J RTERM 30 USB_HUB_RESET# 1/20W_20K_1%_0201
USB_OC0_R_N OVCUR3J RESETJ USB_HUB_X1
nl
20 39
21 OVCUR2J X1 38 USB_HUB_X2
PWREN2J X2
USB_HUB_1V2_FB 22 23 GND_CHIP
USB_HUB_1V2_SW 24 FB VSSP 49
SW GND
AVDD33_1
AVDD33_2
AVDD33_3

+3V_HUB
lO
AVDD33

26 VDDP

USB_OC_R USB_HUB_X2
VBUS

RU349 1 2 10K_0201_5% GL3523-ONY30_QFN48_6X6

36 V5

RU331 1 2 10K_0201_5% USB_OC0_R_N USB_HUB_X1

USB_HUB_VBUSIN

RU340 1 2 1M_0402_5%
48
40
2
17

25

+3V_HUB

2
tia

RU341
1K_0201_5%
YU2

+5VALW_HUB

1
+5VALW_HUB
1 4
OSC1 NC2
USB_HUB_X2_R 2 3 USB_HUB_X2_R
0.1U_6.3V_K_X5R_0201

NC1 OSC2
en
10U_0603_6.3V6M

USB_HUB_X1
2 1 1
25MHZ_10PF_7R25000006
CU925
CU901

CU820
GND_CHIP

22U_0603_6.3V6-M
1 2 2
1 1
CU902 CU802
fid

12P_0402_50V8 18P_0402_50V8
2 2

B B
+5VALW +5VALW_HUB
on

MAX 0.2A
@
RU839 1 2 1/10W_0_5%_0603

UU136
C

5 1
IN OUT
2
GND
DB_USB_HUB_PWR_EN 4 3
79 DB_USB_HUB_PWR_EN EN OCB
FC
1

SY6288C20AAC_SOT23-5
RU842
100K_0201_5%
2

LC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 USB2.0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, November 29, 2021 Sheet 58 of 110
5 4 3 2 1
 A B C D E

+USB_VCCA
RU169 1 @ 2 0_0402_5%

LU95 EMC@ CU788 1 2 100U_1206_6.3V6M

USB20_3_U_N 1 2 USB20_3_R_N
1 2 @
CU113 1 2
USB20_3_U_P 4 3 USB20_3_R_P 1U_0603_25V6M
4 3 @
EXC24CH900U_4P CU114 1 2
470P_0402_50V7K
RU170 1 @ 2 0_0402_5%
1 1

JUA3
RU172 1 @ 2 0_0402_5% 1
USB20_3_R_N 2 VBUS
USB20_3_R_P 3 D-
LU93 EMC_NS@ 4 D+
1 2 USB30_RX3_CON_N USB30_RX3_CON_N 5 GND1
58 USB30_HUB3_RX_N 1 2 USB30_RX3_CON_P SSRX-
6 10
7 SSRX+ GND3 11
4 3 USB30_RX3_CON_P USB30_TX3_CON_N 8 GND2 GND4 12
58 USB30_HUB3_RX_P 4 3 USB30_TX3_CON_P SSTX- GND5
9 13
SSTX+ GND6

T
EXC24CH900U_4P

RU171 1 @ 2 0_0402_5% ALLTO_C107MJ-10939-L

ME@

M
RU168 1 @ 2 0_0402_5%

LU94 EMC_NS@
USB charger

rS
1 2 USB30_TX3_C_N 1 2 USB30_TX3_CON_N
58 USB30_HUB3_TX_N 1 2 CU116 0.1U_6.3V_K_X5R_0201

58 USB30_HUB3_TX_P
4
4 3
3 USB30_TX3_C_P
CU115
1 2 USB30_TX3_CON_P
0.1U_6.3V_K_X5R_0201 +5VALW
2.5A
EXC24CH900U_4P
UU133
RU161 1 @ 2 0_0402_5% @
CU117 2 1 .1U_0402_16V7K 1 16 ILIM_HI RU162 1 2 18.2K_0402_1%

fo
IN ILIM_HI
2 15 ILIM_LO RU163 1 @ 2 20K_0402_1%
58 USB20_HUB3_N DM_OUT ILIM_LO
3 14
58 USB20_HUB3_P DP_OUT GND
ILIM_SEL 4 13
ILIM_SEL FAULT USB_OC0_N 14,57
2 2
y 79 USB_CHG_EN
CHG_MOD1
5

6
EN OUT
12

11 USB20_3_U_N
+USB_VCCA

79 CHG_MOD1 CLT1 DM_IN

nl
CHG_MOD2 7 10 USB20_3_U_P
DU4 USB20_3_R_P CLT2 DP_IN

E_PAD
USB30_RX3_CON_N 10 1 USB30_RX3_CON_N +USB_VCCA CHG_MOD3 8 9 STATUS_N
NC1 Line-1 USB20_3_R_N 79 CHG_MOD3 CLT3 STATUS STATUS_N 79
USB30_RX3_CON_P 9 2 USB30_RX3_CON_P
lO

NC2 Line-2
3

SN1702001RTER_WQFN16_3X3

17
1

USB30_TX3_CON_N 7 4 USB30_TX3_CON_N DU3

NC3 Line-3 AZC199-02S.R7G_SOT23-3 DU242
1

USB30_TX3_CON_P 6 5 USB30_TX3_CON_P EMC@ AZ5725-01F.R7GR_DFN1006P2X2

NC4 Line-4 EMC@
3
GND1
2

8
GND2
tia
2

AZ1143-04F-R7G_DFN2510P10E10 +5VALW
EMC@
1

en

STATUS_N RU164 2 1 10K_0402_5%

for placement optimization

[close to EC side] *
+5VALW *
RU160 *
fid

ILIM_SEL 2 3
CHG_MOD2 1 4

10K_0404_4P2R_5%
*
3 3
ILIM_SEL RU165 2 @ 1 10K_0402_5%
on

CHG_MOD2 RU166 2 @ 1 10K_0402_5%

USB_CHG_EN RU167 2 1 10K_0402_5%

*
C

CLT1 CLT2 CLT3 ILIM_SEL MOD

FC

0 0 0 X DCH OUT held low

1 1 1 1 CDP Data Connected and Port Power Mgt. Function Active

1 1 1 0 SDP2 Data Connected

LC

1 1 0 X SDP1 Data Connected

0 1 0 X SDP1 Data Connected

1 0 0 X DCP_Short Device Forced to stay in DCP BC 1.2 charging mode

1 0 1 X DCP_Divider Device Forced to stay in DCP Divider 1 Charging Mode

4 4

0 1 1 X DCP_Auto Data Disconnected and Port Power Mgt. Function Active

0 0 1 X DCP_Auto Data Disconnected and Power Wake Function Active

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 USB2.0/USB3.0 PORT (LEFT)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, November 29, 2021 Sheet 59 of 110
A B C D E
 5 4 3 2 1

D D

T
M
VCC3_LDO_PD

rS
+USB_VBUS
1/20W_52.3K_+-1%_0201
1
NSR20F30NXT5G_DSN2-2

RU1059

Type-C/rear side
1

2
1

2
DU616

VIN_PD_3V3 VCC3_LDO_PD CU856

USB_VSYS 4.7U_25V_M_X5R_0402
1 PDB_ADCIN1
+3VALW VIN_PD_3V3
1/20W_12.1K_1%_0201
2
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

VCC1V5_LDO_PDB

1
2

1 1 1 RU1061 1 @ 2 0_5%_0603

fo
1

RU1060
CU857

CU858

CU859
1

@ 2 2 2
2

AZ4520-01F.R7G_DFN1610P2E2
2

DU619
2

+5VALW Address: 4/7

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

G2

G8
H4

H1

H3

H8

C8
A3

A8
B8
F8

UU5410
1 1 1 1 1 1
y VCC3_LDO_PD
VSYS

VIN_3V3

LDO_1V5_1
LDO_1V5_2

LDO_3V3

PA_VBUS_1
PA_VBUS_2
PA_VBUS_3

GND1
GND2
GND3
CU864

CU865
CU860

CU861

CU862

CU863

A7
C 2 2 2 2 2 2 B7 PP5V_1 C
PP5V_2 EC_I2C_INT4_PDB_N RU1062 1
nl
C7 @ 2 10K_0201_5%
D7 PP5V_3 USBC1_CC1 62
E7 PP5V_4 G4 PDB_ADCIN1 USBC1_CC2 62
220P_25V_K_X7R_0201

220P_25V_K_X7R_0201

F7 PP5V_5 ADCIN1 @
G7 PP5V_6 PD_I2C2_SCL RPU8 1 4 2.2K_0404_4P2R_5%
H7 PP5V_7 G3 PD_I2C2_SDA 2 3
PP5V_8 ADCIN2 VCC3_LDO_PD 1 1
CU866

CU867

@
lO

A4 2 2 PD_I2C_SCL RPU207 1 4 2.2K_0404_4P2R_5%

88 TYPE_C_GATE_VSYS 2 0_0201_5% Type-C_GATE_VBUS_R PA_GATE_VSYS TYPEC_CC1 PD_I2C_SDA
RU1087 1 @ E8 G5 2 3
88 TYPE_C_GATE_VBUS PA_GATE_VBUS PA_CC1 H5 TYPEC_CC2
PA_CC2
B5
B4 NC2 A5
D8 NC1 NC3
GND4

RU3516 1 @ 2 0_0201_5% EC_I2C_INT4_PDA_N

EC_I2C_INT4_PDA_N 79
C1 D1 EC_I2C_INT4_PDB_R_N RU1067 1 @ 2 0_0201_5% EC_I2C_INT4_PDB_N
GPIO0 I2C_EC_IRQ# EC_I2C_INT4_PDB_N 79
EC_SMB_CK4_PD_R EC_SMB_CK4_PD
tia

G1 E1 RU367 1 @ 2 0_0201_5%
61 TYPE-C_DP_RE_HPD1 GPIO1 I2C_EC_SCL F1 EC_SMB_DA4_PD_R 1 2 0_0201_5% EC_SMB_DA4_PD EC_SMB_CK4_PD 51,79 EC
RU368 @ Slave
A6 I2C_EC_SDA EC_SMB_DA4_PD 51,79
GPIO2
H6 VCC3_LDO_PD
61 PS8812_DP_MODE_C1 GPIO3 F2 PD2_I2C_INT_R_N 2 0_0201_5% PCH_PMC_ALERT_PD_N
RU1092 1 @
USB_OC2_N PD2_USB_OC2_N_R I2C2S_IRQ# PCH_PMC_ALERT_PD_N 17
RU1088 1 @ 2 0_0201_5% B3
7,14 USB_OC2_N GPIO4 E2 PD_I2C2_SCL RU3527 1 @ 2 0_0201_5% Slave PCH SML1
PD2_GPPC_B2_VRALERT_N_R C2 I2C2S_SCL PD_I2C2_SDA SML1_CLK_TBT 11,51
RU1089 1 @ 2 0_0201_5% D2 RU3528 1 @ 2 0_0201_5%
19 PD_GPPC_B2_VRALERT_N GPIO5 I2C2S_SDA SML1_DATA_TBT 11,51
10K_0201_5%

10K_0201_5%

10K_0201_5%
2

F6 1
61 PS8812_FLIP_C1 GPIO6
RU2484

RU2485

RU2486
en

G6 B1 @CU7274
61 PS8812_USB_MODE_C1 GPIO7 I2C3M_IRQ# 0.1U_6.3V_K_X5R_0201
B6 A2 PD_I2C_SCL UU11 2
PD_I2C_SCL 61
1

GPIO8 I2C3M_SCL A1 PD_I2C_SDA A0_PD 1 8

I2C3M_SDA_1 PD_I2C_SDA 61 A0 VCC
RU1103 1 @ 2 0_0201_5% C6 B2 @ @ @
88 PD_GPIO GPIO9 I2C3M_SDA_2 A1_PD 2 PD_ROM_WPRU2487 2
GND5

7 @ 1 10K_0201_5%
A1 WP
A2_PD 3 6 PD_I2C_SCL_ROM 1 @ 2 PD_I2C_SCL
SN2011062YBGR_DSBGA50 A2 SCL RU1106 0_0201_5%
H2

4 5 PD_I2C_SDA_ROM 1 @ 2 PD_I2C_SDA
10K_0201_5%

10K_0201_5%

10K_0201_5%
2

VSS SDA RU1107 0_0201_5%

RU2488

RU2489

RU2490
fid

CAT24C256WI-GT3_SO8
@
Address 1010 A2 A1 A0 R/W
1

B For E14-intel:1010 000 R/W B

@ @ @
on
C
FC
LC

A A

Security Classification LCFC Highly Confidential Information Title

Common Module
Issued Date 2012/07/01 Deciphered Date 2014/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
TYPEC_MUX_PortA A0

Date: Monday, November 29, 2021 Sheet 60 of 110

5 4 3 2 1
 5 4 3 2 1

+3VALW_SYS VCC3_PS8812_A VCC3_PS8812_A VCC1R2M_A

RU416 1 @ 2 0_5%_0603
1 1 1 1 1 1 1 1 1 1 1
0.01U_25V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
4.7U_0402_6.3V6M
CU919

CU918

CU791

CU792

CU920

CU921

CU425

CU401

CU414

CU415

CU413

@ @

2 2 2 2 2 2 2 2 2 2 2

VCC3_PS8812_A VDD_DCI_A

D RU427 1 @ 2 0_5%_0603 D

T
+3VALW_SYS

RU413 1 2 100K_0201_5% GPU_IFPB_AUXN_C

RU414 1 2 100K_0201_5% GPU_IFPB_AUXP_C

100P 25V J NPO 0201

100P 25V J NPO 0201

1 1

@ @

rS
2 2
VCC3_PS8812_A VDD_DCI_A

CU403

CU402
SA00009F910 做BOM
VCC1R2M_A

UU3
1 52
62 PS8812_USBC0_RX1_P 2 VDD_DM_1 VDD33_2 51
3 RX1p DCI_DATA 50

fo
62 PS8812_USBC0_RX1_N 4 RX1n DCI_CLK 49
5 TEST VDD_DCI 48 PS8812_CEQ_1
6 RSV CEQ 47
7 VDD_R1 VDD_A2 46 PS8812_SSEQ_1
8 VDD_R2 SSEQ 45
RX2n TX2p PS8812_USBC0_TX2_P 62
62 PS8812_USBC0_RX2_N 9 44
62 PS8812_USBC0_RX2_P 10 RX2p TX2n 43 PS8812_RESET_N_1 PS8812_USBC0_TX2_N 62
CU406 1 2 0.33U_25V_K_X5R_0201 USB30_RX4_MUX_N 11 VDD_DM_2 RESET# 42
14 USB30_RX4_N USB30_RX4_MUX_P SSRXn TX1n PS8812_USBC0_TX1_N 62
CU407 1 2 0.33U_25V_K_X5R_0201 12 41
14 USB30_RX4_P 13 SSRXp TX1p 40 TYPE-C_DP_RE_HPD1 PS8812_USBC0_TX1_P 62
1 2 0.22U_6.3V_K_X5R_0201 USB30_TX4_MUX_N 14 VDD_A1 IN_HPD 39 TYPE-C_DP_RE_HPD1 60
CU405
14 USB30_TX4_N CU404 1 2 0.22U_6.3V_K_X5R_0201 USB30_TX4_MUX_P 15 SSTXn REXT 38 MUX_REXT1 VCC3_PS8812_A

C
14

29
29
USB30_TX4_P

GPU_IFPB_TX0_P
GPU_IFPB_TX0_N
CU417
CU418
1
1

1
2 0.1U_6.3V_K_X5R_0201
2 0.1U_6.3V_K_X5R_0201

2 0.1U_6.3V_K_X5R_0201
TYPE-C1_DP_RE_TXP0
TYPE-C1_DP_RE_TXN0
PS8812_ADDR_1
TYPE-C1_DP_RE_TXP1
16
17
18
19
20
SSTXp
VDD_DM_3
ML0p
ML0n
ADDR
VDD_DM_4
FLIP
CE_USB
CE_DP
SBU2
37
36
35
34
33
DP2_AUXN_R
DP2_AUXP_R
PS8812_FLIP_C1
PS8812_USB_MODE_C1
PS8812_DP_MODE_C1
y
PS8812_FLIP_C1

PS8812_DP_MODE_C1
DP2_AUXN_R 62
60
PS8812_USB_MODE_C1 60
60
VCC3_PS8812_A

1
RU432
@ 2 1
RU433
@ 2 VCC3_PS8812_A_PG
3
UU5
TPS74801DRCR_SON-10_3X3
6 C
CU419 1/20W_100K_1%_0201
29 GPU_IFPB_TX1_P TYPE-C1_DP_RE_TXN1 ML1p SBU1 GPU_IFPB_AUXN_C PG GND1 7
nl
CU420 1 2 0.1U_6.3V_K_X5R_0201 21 32 CU408 1 2 0.1U_6.3V_K_X5R_0201 DP2_AUXP_R 62 RU431 1/20W_100K_1%_0201 4 RU400
29 GPU_IFPB_TX1_N PS8812_DPEQ1 22 ML1n AUXn 31 GPU_IFPB_AUXP_C 1 2 0.1U_6.3V_K_X5R_0201 GPU_IFPB_AUXN 29 1 2 VCC1R2M_A_EN 5 BIAS SS 8 VCC1R2M_A_FB 1 2 VCC1R2M_A
CU409
CU421 1 2 0.1U_6.3V_K_X5R_0201 TYPE-C1_DP_RE_TXP2 23 DPEQ AUXp 30 GPU_IFPB_AUXP 29 EN FB
29 GPU_IFPB_TX2_P 1 2 0.1U_6.3V_K_X5R_0201 TYPE-C1_DP_RE_TXN2 24 ML2p VDD_D1 29 PDC_SDA1_R 1 2 0_0201_5%
CU422 RU415 @ 1/20W_100K_1%_0201 2.49K_0402_1%
29 GPU_IFPB_TX2_N 1 2 0.1U_6.3V_K_X5R_0201 TYPE-C1_DP_RE_TXP3 25 ML2n CSDA 28 PDC_SCL1_R 1 2 0_0201_5% PD_I2C_SDA 60 2 9
CU423 RU425 @
GND

29 GPU_IFPB_TX3_P 1 2 0.1U_6.3V_K_X5R_0201 TYPE-C1_DP_RE_TXN3 26 ML3p CSCL 27 PD_I2C_SCL 60 IN2 OUT1

CU424
29 GPU_IFPB_TX3_N ML3n VDD33_1

GND2

UU5_SS
@ PS8812QFN52GTRA2_QFN52_6P5X4P5 1 10
53

IN1 OUT2
lO
2

11
RU402

1/20W_4.99K_1%_0201
1
4.99K_0402_1% 1

22P_0201_258J

RU430
CU411 1
1

10U 6.3V M X5R 0402

EMC_NS@
@ 1 CU412

CU386

10U 6.3V M X5R 0402

2

2
2
2
tia
en

VCC3_PS8812_A +1.8VS_AON

HPD

1
RU423
1

10K_0201_5%
RU401

2
100K_0201_5% IFPB_HPD
VCC3_PS8812_A 32 IFPB_HPD
to NV GPU
fid

PS8812_RESET_N_1 QU8
1 MMBT3904WH_SOT323-3
B C RU422 B
RU417 2 1 1/20W_4.7K_5%_0201 PS8812_DP_MODE_C1 2TYPE-C_DP_RE_HPD1_Q1 2 1 2 0_0201_5% TYPE-C_DP_RE_HPD1
1 CU416 RU419 @
B 100K_0201_5%
E
3

2
RU418 2 1 1/20W_4.7K_5%_0201 PS8812_FLIP_C1 0.1U_6.3V_K_X5R_0201 RU421

2
2
1 CU410 RU420

RU408 2 1 PS8812_USB_MODE_C1
on

1/20W_4.7K_5%_0201 100K_0201_5% 220P_50V_K_X7R_0201

1

2 100K_0201_5%

1
pin control mode, connect to PDC
follow yoga740 change to stuff
07/01 YONG

VCC3_PS8812_A TYPE-C_DP_HPD1 1 2 0_0201_5% TYPE-C_DP_RE_HPD1

to APU 12 TYPE-C_DP_HPD1
RU424 @

2 1 PS8812_DPEQ1 RU410 1 2 1/20W_4.7K_5%_0201

@
C

RU403 1/20W_4.7K_5%_0201

2 1 PS8812_CEQ_1 RU411 1 2 1/20W_4.7K_5%_0201

RU404 1/20W_4.7K_5%_0201

2 1 PS8812_ADDR_1 RU412 1 @ 2 1/20W_4.7K_5%_0201

RU405 1/20W_4.7K_5%_0201
Automatic DCI mode ent 2 1 PS8812_SSEQ_1 RU409 2 1 1/20W_4.7K_5%_0201
ering enabled @ @
RU406 1/20W_4.7K_5%_0201
FC
LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2019/07/02 Deciphered Date 2020/05/16 DDI Redriver PS8330

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y550 A0

Date: Monday, November 29, 2021 Sheet 61 of 110

5 4 3 2 1
 4 3 2 1

USB20_4_CONN_P +USB_VBUS
USB20_4_CONN_N

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

0.01U_25V_K_X5R_0201

0.01U_25V_K_X5R_0201

0.01U_25V_K_X5R_0201

0.01U_25V_K_X5R_0201
1U_0603_25V6K
2

2
DU18 DU22 1 1 1 1 1

CU1028
CU14

CU26

CU13

CU12
2

2
GND4
GND3
GND2
GND1

4
3
2
1
@

SP1224-01UTG_UDFN-6

Vbus
NC3
NC2
NC1
JUSBC3 2 2 2 2 2
1 2 0_0402_5%

DU1
RU35 @

GND8
GND7
GND6
GND5

1
B12 A1
GND4 GND1 EMC_NS@ EMC_NS@

1
D USBC0_RX1_CON_P B11 A2 USBC0_TX1_CON_P D
EXC24CH500U_4P SSRXp1 SSTXp1
PS8812_USBC0_TX1_N PS8812_USBC0_TX1_R_N USBC0_TX1_CON_N USBC0_RX1_CON_N USBC0_TX1_CON_N

GND1
GND2
GND3
GND4
4 3 CU22 1 2 0.22U_25V_K_X5R_0201 B10 A3
61 PS8812_USBC0_TX1_N 4 3 SSRXn1 SSTXn1
B9 A4
+USB_VBUS +USB_VBUS

T
PS8812_USBC0_TX1_P 1 2 PS8812_USBC0_TX1_R_P CU23 1 2 0.22U_25V_K_X5R_0201 USBC0_TX1_CON_P Vbus4 Vbus1
61 PS8812_USBC0_TX1_P

5
6
7
8
1 2 USBC1_DPAUX2_CONN B8 A5 USBC1_CC1_CONN
LU1 @ SBU2 CC1
USB20_4_CONN_N B7 A6 USB20_4_CONN_P
Dn2 Dp1
USB20_4_CONN_P B6 A7 USB20_4_CONN_N
1 2 0_0402_5% Dp2 Dn1

M
RU36 @
USBC1_CC2_CONN B5 A8 USBC1_DPAUX1_CONN
CC2 SBU1
B4 A9
+USB_VBUS USBC0_TX2_CON_N
Vbus3 Vbus2
USBC0_RX2_CON_N
+USB_VBUS
RU37 1 @ 2 0_0402_5% B3 A10
SSTXn2 SSRXn2
USBC0_TX2_CON_P B2 A11 USBC0_RX2_CON_P DU21
SSTXp2 SSRXp2 USBC1_DPAUX1_CONN 9 10 1 USBC1_DPAUX1_CONN
1
EXC24CH500U_4P

rS
B1 A12
GND10
PS8812_USBC0_TX2_P PS8812_USBC0_TX2_R_P USBC0_TX2_CON_P GND3 GND2 USBC1_DPAUX2_CONN 2 USBC1_DPAUX2_CONN
GND9

4 3 CU25 1 2 0.22U_25V_K_X5R_0201 8 9 2
61 PS8812_USBC0_TX2_P 4 3
USBC1_CC1_CONN 7 4 USBC1_CC1_CONN
7 4
PS8812_USBC0_TX2_N 1 2 PS8812_USBC0_TX2_R_N CU24 1 2 0.22U_25V_K_X5R_0201 USBC0_TX2_CON_N
61 PS8812_USBC0_TX2_N
GND5
GND6

1 2 HIGHSTAR-UB11249-B200W-1H USBC1_CC2_CONN 6 5 USBC1_CC2_CONN

6 5
LU22 EMC_NS@
3 3

8
RU38 1 @ 2 0_0402_5%
AZ1045-04F_DFN2510P10E-10-9
EMC_NS@

fo
RU39 1 @ 2 0_0402_5%

EMC_NS@
EXC24CH500U_4P
PS8812_USBC0_RX1_N 4 3 PS8812_USBC0_RX1_R_N CU19 1 2 0.33U_25V_K_X5R_0201 USBC0_RX1_CON_N
61 PS8812_USBC0_RX1_N 4 3

C
61 PS8812_USBC0_RX1_P
PS8812_USBC0_RX1_P 1

LU13
1 2
2 PS8812_USBC0_RX1_R_P CU18 1 2 0.33U_25V_K_X5R_0201 USBC0_RX1_CON_P
USBC0_RX1_CON_N
USBC0_RX1_CON_P
USBC0_RX2_CON_P
USBC0_RX2_CON_N
RU7241
RU7251
RU3881
y
2 220K_0201_5%
2 220K_0201_5%
2 220K_0201_5%
DU19
AZ174S-04FPR7G_DFN2510P10E10
C
RU3891 2 220K_0201_5%
USBC0_TX2_CON_N USBC0_RX2_CON_P
10 5
nl
USBC0_TX2_CON_P 9 NC4 Line-4 4 USBC0_RX2_CON_N
RU40 1 @ 2 0_0402_5%
USBC0_RX2_CON_N 7 NC3 Line-3 2 USBC0_TX2_CON_P
USBC0_RX2_CON_P NC2 Line-2 USBC0_TX2_CON_N

GND2
GND1
6 1
NC1 Line-1

EMC_NS@

8
3
lO

RU41 1 @ 2 0_0402_5%

EXC24CH500U_4P
PS8812_USBC0_RX2_P 4 3 PS8812_USBC0_RX2_R_P CU20 1 2 0.33U_25V_K_X5R_0201 USBC0_RX2_CON_P
61 PS8812_USBC0_RX2_P 4 3

61 PS8812_USBC0_RX2_N
PS8812_USBC0_RX2_N 1
1 2
2 PS8812_USBC0_RX2_R_N CU21 1 2 0.33U_25V_K_X5R_0201 USBC0_RX2_CON_N DU19 & DU20 Change to SC300007A00 使用使使做BOM
EMC_NS@
LU21
DU20
tia

AZ174S-04FPR7G_DFN2510P10E10
RU42 1 @ 2 0_0402_5%
USBC0_RX1_CON_P 10 5 USBC0_TX1_CON_N
USBC0_RX1_CON_N 9 NC4 Line-4 4 USBC0_TX1_CON_P
USBC0_TX1_CON_P 7 NC3 Line-3 2 USBC0_RX1_CON_N
USBC0_TX1_CON_N NC2 Line-2 USBC0_RX1_CON_P

GND2
GND1
6 1
NC1 Line-1

EMC_NS@

8
3
en

+3VALW_SYS
UU139

CU928 1 2 0.1U_6.3V_K_X5R_02018 7
VCC3_LDO_PD VCC NC
CU929 1 @ 2 1U_6.3V_M_X5R_0201
2 3 USB20_4_R_P
14 USB20_4_P HSD+ D+
UU10 @
6 5 USB20_4_R_N
1 2 CU1033 C4 B4 +LDO1_3V3_OVP RU901 1 2 100K_0201_5% 14 USB20_4_N HSD- D-
0.1u_0201_10V6K VCC3_LDO_PD
VPWR FLT
fid

D1 B1 USBC1_DPAUX1_CONN TBT_USB2_ON_N 1 4
61 DP2_AUXP_R SBU1 C_SBU1 USBC1_DPAUX2_CONN 53 TBT_USB2_ON_N OE# GND
D2 A1
61 DP2_AUXN_R SBU2 C_SBU2
B D3 A2 USBC1_CC1_CONN TS3USB31ERSER_UQFN8_1P5X1P5 B
60 USBC1_CC1 CC1 C_CC1
D4 B2
60 USBC1_CC2 CC2 RPD_G1 @
A3 USBC1_CC2_CONN
C_CC2 B3
RPD_G2 USB20_4_R_P RU1029 1 @ 2 0_0201_5% USB20_4_P
C1
GND1 C2 USB20_4_R_N RU1030 1 @ 2 0_0201_5% USB20_4_N
on

OVP_VBIAS A4 GND2 C3
VBIAS GND3
1
CU1029
SN1904020YBFR_DSBGA16 RU33 1 @ 2 0_0402_5%
0.1U_50V_K_X5R_0402
2

LU6
USB20_4_R_N 4 3 USB20_4_CONN_N
4 3
C

USB20_4_R_P 1 2 USB20_4_CONN_P
1 2
EXC24CH900U_4P
EMC@

RU34 1 @ 2 0_0402_5%
DP2_AUXP_R RU721 1 @ 2 0_0201_5% USBC1_DPAUX1_CONN
DP2_AUXN_R RU722 1 @ 2 0_0201_5% USBC1_DPAUX2_CONN

USBC1_CC1 RU24 1 @ 2 0_0201_5% USBC1_CC1_CONN

USBC1_CC2 1 2 0_0201_5% USBC1_CC2_CONN
FC

RU25 @

USBC1_DPAUX1_CONN RU30 1 2 2M_0402_5%

USBC1_DPAUX2_CONN RU43 1 2 2M_0402_5%
LC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 USB TYPE-C Port

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y540 A0

Date: Monday, November 29, 2021 Sheet 62 of 110

4 3 2 1
 A B C D E

M.2 SSD(PCIE GEN4 from CPU)

+3VS +3VS_SSD1
Need short
J6 @
2 1 Min 3A
2 1
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

12P_50V_J_NPO_0201

2.2P_25V_C_COG_0201

JUMP_43X79
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1 1 1 1 1 1 1
CK209

CK210

CK211

CK212

CK218

CK219

+ CK222
1 100U_6.3V_M_B2_ESR35M_TPE_H1.9 1
2 2 2 2 2 2
RF_NS@

RF_NS@

@ 2
@

JSSD1
NGFF1 +3VS_SSD1

1 2
3 GND_1 3.3V_1 4
PCIE4A_CRX_DTX3_N 5 GND_2 3.3V_2 6
14 PCIE4A_CRX_DTX3_N PCIE4A_CRX_DTX3_P PERN3 N/C_2
7 8
14 PCIE4A_CRX_DTX3_P PERP3 N/C_3
9 10
PCIE4A_CTX_DRX3_N CK17 2 1 0.22U_6.3V_K_X5R_0201 PCIE4A_CTX_C_DRX3_N 11 GND_3 DAS/DSS# 12
14 PCIE4A_CTX_DRX3_N PCIE4A_CTX_DRX3_P PCIE4A_CTX_C_DRX3_P PETN3 3.3V_3
CK18 2 1 0.22U_6.3V_K_X5R_0201 13 14
14 PCIE4A_CTX_DRX3_P PETP3 3.3V_4
15 16
PCIE4A_CRX_DTX2_N 17 GND_4 3.3V_5 18
14 PCIE4A_CRX_DTX2_N PCIE4A_CRX_DTX2_P PERN2 3.3V_6
19 20
14 PCIE4A_CRX_DTX2_P PERP2 N/C_4
21 22
PCIE4A_CTX_DRX2_N CK19 2 1 0.22U_6.3V_K_X5R_0201 PCIE4A_CTX_C_DRX2_N 23 GND_5 N/C_5 24
14 PCIE4A_CTX_DRX2_N PCIE4A_CTX_DRX2_P PCIE4A_CTX_C_DRX2_P PETN2 N/C_6
CK21 2 1 0.22U_6.3V_K_X5R_0201 25 26
14 PCIE4A_CTX_DRX2_P PETP2 N/C_7
27 28
PCIE4A_CRX_DTX1_N 29 GND_6 N/C_8 30
14 PCIE4A_CRX_DTX1_N PCIE4A_CRX_DTX1_P PERN1 N/C_9
31 32
14 PCIE4A_CRX_DTX1_P PERP1 N/C_10
33 34
PCIE4A_CTX_DRX1_N CK20 2 1 0.22U_6.3V_K_X5R_0201 PCIE4A_CTX_C_DRX1_N 35 GND_7 N/C_11 36

T
14 PCIE4A_CTX_DRX1_N PCIE4A_CTX_DRX1_P PCIE4A_CTX_C_DRX1_P PETN1 N/C_12
CK14 2 1 0.22U_6.3V_K_X5R_0201 37 38
14 PCIE4A_CTX_DRX1_P PETP1 DEVSLP
39 40
PCIE4A_CRX_DTX0_N 41 GND_8 N/C_13 42
14 PCIE4A_CRX_DTX0_N PCIE4A_CRX_DTX0_P PERN0/SATA-B+ N/C_14
43 44
14 PCIE4A_CRX_DTX0_P PERP0/SATA-B- N/C_15
45 46
GND_9 N/C_16

M
PCIE4A_CTX_DRX0_N CK15 2 1 0.22U_6.3V_K_X5R_0201 PCIE4A_CTX_C_DRX0_N 47 48
14 PCIE4A_CTX_DRX0_N PCIE4A_CTX_DRX0_P PCIE4A_CTX_C_DRX0_P PETN0/SATA-A- N/C_17 SSD1_RST_N SSD_RST_N PLT_RST_N
CK16 2 1 0.22U_6.3V_K_X5R_0201 49 50 RK460 1 @ 2 0_0201_5% RK462 1 @ 2 0_0201_5%
14 PCIE4A_CTX_DRX0_P PETP0/SATA-A+ PERST# SSD_CLKREQ_N PLT_RST_N 17,32,52,71,73,76,79
51 52 1
CLK_PCIE_SSD1_N GND_10 CLKREQ# SSD_CLKREQ_N 16
53 54 1
16 CLK_PCIE_SSD1_N CLK_PCIE_SSD1_P REFCLKN PEWAKE#
55 56 @ CK41
16 CLK_PCIE_SSD1_P REFCLKP N/C_18
57 58 TPK2 1000P_0402_50V_X7R_0402
GND_11 N/C_19 2
59 NC NC 60

rS
61 NC NC 62
63 NC NC 64
65 NC NC 66
67 68 SUSCLK_SSD1 RK22 1 @ 2 0_0201_5% SUSCLK
SUSCLK 16,63,71
69 N/C_1 SUSCLK 70
71 PEDET 3.3V_7 72 +3VS_SSD1
73 GND_12 3.3V_8 74
75 GND_13 3.3V_9
1 1 1
GND_14
@

@
77 76 CK42 CK36 CK143
PEG1 PEG2
2 2 2

fo
0.1u_0201_10V6K

22UC_6.3VC_MC_X5RC_0603
ME@
0.01U_10V_K_X5R_0201

DEREN_40-42329-067B3RHF-L

2 2

@
y
nl
lO
tia

M.2 SSD(SATA/PCIE Gen3 from PCH)

en

+3VS +3VS_SSD2
Need short
J7 @
2 1 Min 3A
2 1
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

12P_50V_J_NPO_0201

2.2P_25V_C_COG_0201

JUMP_43X79
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1 1 1 1 1 1 1 1
47U_6.3V_M_X5R_0603

47U_6.3V_M_X5R_0603
CK213

CK214

CK215