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Patrick Fay · Debdeep Jena · Paul Maki
Editors
High-
Frequency
GaN Electronic
Devices
High-Frequency GaN Electronic Devices
Patrick Fay • Debdeep Jena • Paul Maki
Editors
High-Frequency GaN
Electronic Devices
123
Editors
Patrick Fay Debdeep Jena
University of Notre Dame Cornell University
Notre Dame, IN, USA Ithaca, NY, USA
Paul Maki
Office of Naval Research
Arlington, VA, USA
This Springer imprint is published by the registered company Springer Nature Switzerland AG.
The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
Preface
GaN and related materials (AlGaN, InGaN) have established themselves as a key
material system for RF and microwave power electronics and are vying for the posi-
tion in low-frequency power electronics applications as well. Perhaps, surprisingly,
the material properties of the GaN material family are quite well-matched to the
needs of ultrahigh-frequency electronics as well, with high carrier mobilities in
polarization-induced 2D electron gases and comparatively high densities of states
that enable both large current density and aggressive device scaling for high-
frequency operation. However, scaling of conventional device architectures such
as the high electron mobility transistor widely used in GaN for RF and microwave
power applications is only one of the several possible routes to exceptional high-
frequency performance in III-N devices. By leveraging the unique properties of
the nitrides along with less conventional physical bases of operation, entirely new
classes of devices with significant potential for high-frequency performance are
possible. This volume brings together scientists and device engineers working
on both aggressively scaled conventional transistors and unconventional high-
frequency device concepts in the III-N material system. Device concepts for
mm-wave to THz operation based on deeply scaled HEMTs, as well as distributed
device designs based on plasma-wave propagation in polarization-induced 2DEG
channels, tunneling, and hot-carrier injection are discussed in detail. In addition,
advances in the underlying materials science that enable these demonstrations and
advancements in metrology that permit the accurate characterization and evaluation
of these emerging device concepts are also included. Targeting both academic and
industrial researchers looking to push the envelope in GaN-based electronics device
research, this book aims to provide readers with a current, comprehensive treatment
of device concepts and physical phenomenology suitable for applying GaN and
related materials to emerging ultrahigh-frequency applications.
v
Contents
vii
viii Contents
Epilogue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Chapter 1
Introduction and Overview
P. Fay ()
University of Notre Dame, Notre Dame, IN, USA
e-mail: [email protected]
D. Jena ()
Cornell University, Ithaca, NY, USA
e-mail: [email protected]
P. Maki
Office of Naval Research, Arlington, VA, USA
Robert L. Coffie
1 Introduction
Since the invention of the first transistor by Bell labs in 1947 [24], scientist and
engineers have pursued novel semiconductor materials for enhanced performance
for particular applications. For example, one of the initial motivations to pursue
the development of silicon transistors was the larger band gap of silicon compared
to germanium [22]. The larger band gap allows silicon transistors to operate at
higher temperatures than germanium transistors. Due to the large number of possible
semiconductor materials (>600 [22]) and limited resources, researchers began
trying to predict the potential improvement of a new semiconductor material system
for a specific application based on material properties alone. These predictions
are typically based on a single expression known as a figure of merit. Figures of
merit now exist for many applications [1, 2, 7, 10, 13, 14, 25, 34]. This chapter
will focus on Johnson’s figure of merit (JFoM) published by E. O. Johnson
in 1965 [10]. Johnson’s figure of merit is often used to predict the potential
power/frequency performance of a material system based solely on its material
properties. Care must be taken when predicting performance based on JFoM as
many parameters not considered by JFoM can significantly impact performance.
The additional considerations of doping, low field mobility, thermal constraints, and
heterojunctions will also be discussed.
R. L. Coffie ()
RLC Solutions, Plano, TX, USA
e-mail: [email protected]
In order to derive JFoM, a relationship between the transit time of mobile carriers
from the point of injection to point of collection and the maximum possible voltage
the region of transit can sustain must be established. All the nomenclature for JFoM
will be in terms of an n-channel field effect transistor (FET). Thus, the point of
injection is the source and the point of collection is the drain. The distance the
electron travels after it is injected is the drain-source length (Lds ). The time it takes
an electron to transverse this distance is
τ = Lds vavg (2.1)
where vavg is the average velocity of the electron as it travels across Lds . Transit
time τ is minimized when the electron travels at its saturation velocity (vs ) across
the entire drain-source distance giving
τmin = Lds vs (2.2)
In order for mobile charges to reach their saturation velocity, a sufficient electric
field must be present which is equivalent to assuming the depletion region in the
semiconductor extends from drain to source. The lack of a low electric field region
in the gate-source access region further implies that the gate is self-aligned with the
source. The drain-source length can then be approximated as
Lds = Lg + XD (2.3)
where Lg is the gate length and XD is the depletion extension past the gate towards
the drain. We can now re-write (2.2) as
τmin = Lg + XD vs (2.4)
Passivation
Source Drain
Gate
Channel
Buffer
Highly doped Substrate
Fig. 2.1 Schematic cross-section of a typical high frequency field effect transistor
where Ex is the electric field in the x-direction. For high power operation, a large
voltage swing is desired and Ex should be maximized. All semiconductors have
a maximum or critical electric field (Ec ) that can be sustained before breakdown
occurs. This leads to a maximum value for (2.6) of
Johnson’s figure of merit is defined as the product of the maximum transit frequency
and maximum voltage for a given drain-source distance
JFoM = fT Vdsmax = Ec vs (2π ) (2.8)
Several key items should be highlighted regarding JFoM. First, JFoM is only defined
in terms of material parameters. This was one of Johnson’s goals and the attractive
nature of JFoM for researchers searching for novel semiconductor materials for
high power high frequency operation. Second, real devices never reach the value
predicted by JFoM. This is due to the fact that mobile carriers do not travel at
their saturation velocity across the entire drain-source region and the electric field
along the channel is non-uniform (at best Ex reaches Ec for a very small portion
of the channel). Third, breakdown voltage and fT are inversely related to each
other. Therefore, high frequency devices have lower breakdown voltages compared
to devices designed for lower operating frequency. Last, JFoM completely ignores
the low electric field regions in the transistor where electrons do not travel at their
saturated velocity. These low field regions in real transistors may account for a large
portion of the performance of highly scaled devices and thus cannot be ignored [17].
Despite the limitations of JFoM, a comparison of different material systems for
high power high frequency applications is often performed using JFoM. Although
JFoM can be calculated using (2.8), JFoM of a material system is typically
normalized to JFoM of a material system that has a known power/frequency
performance. The normalized JFoM is then a measure of how much “better” the new
material system may be compared to the material system used for normalization. For
8 R. L. Coffie
example, Table 2.1 shows material parameters from several different semiconductor
material systems. Since GaN-based high electron mobility transistor (HEMT)
technology is now the semiconductor to displace for future high frequency high
power applications, we will use GaN’s JFoM for normalization. Figure 2.2 shows
the normalized JFoMs for the material systems in Table 2.1. Three important
observations should be made. First, JFoM for Si and GaAs are more than 10×
smaller than all of the wide band gap semiconductors JFoMs. Since GaAs was
the dominant material system for high power high frequency applications before
GaN, the development of GaN transistors promised a greater than 10× JFoM
improvement over GaAs. Second, Table 2.1 shows the reason for the greater
than 10× improvement in JFoM for wide band gap semiconductors over Si and
GaAs is due primarily to their high critical fields. Third, only AlN and diamond
from Table 2.1 have a larger JFoM than GaN and both have less than 3× JFoM
improvement compared to GaN. Thus, critical field engineering alone is running
out of room to increase power performance.
Fig. 2.2 Johnson’s figure of merit normalized to GaN for the materials listed in Table 2.1
The relationship between JFoM and output power can be obtained by determining
the maximum power possible at a specific frequency. Our first approach will
determine the maximum output power for a device with a given fT . We will
define this metric as the output power figure of merit 1 (Pout FoM1). To establish
the Pout FoM1, a large signal model for the transistor must be chosen. The ideal
linear device model shown in Fig. 2.3a will be used for this analysis. Although
more sophisticated models may be chosen [33], they complicate the analysis with
limited additional insight. The ideal linear model is assumed to have a maximum
current Imax , a knee voltage Vk , a voltage independent transconductance gm , and
breakdown voltage VBD as shown in Fig. 2.3b. The drain terminal of the transistor is
connected to the DC drain supply and load by an ideal bias-tee and the gate terminal
is connected to the DC gate supply and AC signal source by an ideal bias-tee as
well.
The gate voltage vGS [t] is given by the sum of the DC component and the AC
component
loadline
G + D
S
Drain Voltage
Fig. 2.3 (a) Circuit model for ideal linear device. (b) ID − VD family of curves for ideal linear
device. Diagonal line is the loadline for Class A bias and maximum output power
10 R. L. Coffie
Imax vDS Vk , vDS ≤ Vk
ID,max = (2.10)
Imax , vDS ≥ Vk
Within the Imax boundary, the drain current iDS [t] is related to the gate voltage as
gm vGS [t] − Vp , vGS − Vp > 0
iDS [t] = (2.11)
0, vGS − Vp < 0
where Vp is the pinch-off voltage. In order to fully define the boundary conditions
of the problem, the conduction angle, the type of load being used, and the amount of
compression need to be specified. The analysis can be performed for many different
bias conditions and compression levels [18], but we will choose an input power
just prior to any clipping of the drain current or voltage waveforms due to the IV
boundaries and Class A bias defined as a drain bias current of
IDD = gm VGG − Vp = ID,max 2 (2.12)
Output power at this input power level is often referred to as maximum linear output
power. Class A bias at maximum linear output power results in no harmonic content
in the drain voltage or current waveforms, greatly simplifying the analysis. The lack
of harmonic content results in a purely resistive load as the optimum load. Due to
the ideal bias-tee, the drain voltage vDS and load voltage vL are
vDS [t] = VDD + vL [t] , vL [t] = −gm vgs cos [ωt] RL (2.13)
In general, a parametric plot of iDS [t] vs. vDS [t] over one period is called a loadline
plot. For a resistive load, a parametric plot is not needed since iDS can be written in
terms of vDS as
We still need to determine the load resistor that maximizes the power delivered to
the load. For Class A bias and a resistive load, the loadline will pass through the bias
point. Assuming the loadline intersects the Imax boundary at point (V1 , ID,max ), the
load resistance and gm vgs can be written as
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