AND9820

Advance Information
AR0234 Developer Guide
1/2.6−Inch CMOS Digital Image Sensor

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APPLICATION NOTE

INTRODUCTION
This Developer Guide provides detailed descriptions and Registers y_addr_start, x_addr_start, y_addr_end, and
usage guidelines for various features of the AR0234 Global x_addr_end are used to specify the image window. The
Shutter Sensor. Also provided are guidelines for optimal minimum value for x_addr_start is 8 and the maximum
settings for various use cases. For detailed electrical and value for x_addr_end is 1927. The minimum y_addr_start
timing specifications or register descriptions, refer to the and maximum y_addr_end are 8 and 1207, respectively.
AR0234 Data Sheet and the AR0234 Register Reference
documents (AND9812/D). FRAME RATE
Achieving the desired frame rate at the proper resolution
OPTIMAL SETTING GUIDELINES is a balancing act between row timing and the number of
The AR0234 Global Shutter Sensor has many built-in rows in the image. Integration time and the pixel clock
features and is capable of many resolutions and frame rates. frequency are additional factors. The minimum line length
Guidelines for setting resolution and frame rate are provided is 612 pixel clocks which enables a frame rate of 120 fps.
in this section. Detailed settings for the many features are
provided throughout the remainder of this Developer Guide. BLANKING CONTROL
The AR0234 includes the ON Semiconductor Register Horizontal blanking and vertical blanking times are
Wizard tool which can be used to create appropriate settings. controlled by the LINE_LENGTH_PCK and
FRAME_LENGTH_LINES registers, respectively.
RESOLUTION The actual imager timing is described in the Frame Time
The ON Semiconductor AR0234 sensor is capable of a section of this Developer Guide.
maximum resolution of 1920 x 1200 at up to 120 fps.

This document contains information on a product under development.

ON Semiconductor reserves the right to change or discontinue this
product without notice.

This document, and the information contained herein, is CONFIDENTIAL AND

PROPRIETARY and the property of Semiconductor Components Industries,
LLC., dba ON Semiconductor. It shall not be used, published, disclosed or
disseminated outside of the Company, in whole or in part, without the written
permission of ON Semiconductor. Reverse engineering of any or all of the
information contained herein is strictly prohibited.

E 2019, SCILLC. All Rights Reserved.

© Semiconductor Components Industries, LLC, 2019 1 Publication Order Number:

June, 2019 − Rev. 0 AND9820/D
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PIXEL DATA FORMAT columns and active rows are included for use when
horizontal or vertical mirrored readout is enabled, to allow
Pixel Array Structure readout to start on the same pixel. The pixel adjustment is
The AR0234 pixel array is configured as 2110 columns by always performed for monochrome or color versions. The
1252 rows, (see Figure 1). The dark pixels are optically central 1928 x 1208 pixel active area is surrounded with
black and are used internally to monitor black level. Of the optically transparent dummy pixels and non−optically
left 172 columns, 148 are dark pixels used for row noise transparent barrier pixels to improve image uniformity
correction. Of the bottom 30 rows of pixels, 8 of the dark within the active area. Not all barrier pixels can be read out.
rows are used for black level correction. There are 1940 The optical center of the readable active pixels can be found
columns by 1220 rows of optically active pixels. While the between X_ADDR 969 and 970, and between Y_ADDR
sensor’s format is 1920 x 1200, the additional active 609 and 610.

2110

6 Light Dummy + 4 Barrier

1940 x 1220 Optically Transparent (1928 x 1208 Active)

5.82 x 3.66 mm2 (5.78 x 3.62 mm2)

2 Barrier + 6 Light Dummy +

1252

148 Dark + 4 Barrier

16 Barrier + 2 Light Dummy +
6 Light Dummy 16 Barrier +
8 Dark
4 Barrier

Light Dummy
Dark Pixel Barrier Pixel Active Pixel
Pixel

Figure 1. Pixel Array Description

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OUTPUT DATA FORMAT of vertical frame time (in rows) is programmable through
The AR0234 image data is read out in a progressive scan. R0x300A. Line_Valid (LV) is HIGH during the shaded
Valid image data is surrounded by horizontal and vertical region of Figure 2. Optional embedded register setup
blanking (see Figure 2). The amount of horizontal row time information and histogram statistic information are
(in clocks) is programmable through R0x300C. The amount available in the first two and the last two rows of image data.

P0,0 P0,1 P0,2.....................................P0,n−1 P0,n 00 00 00 .................. 00 00 00

P1,0 P1,1 P1,2.....................................P1,n−1 P1,n 00 00 00 .................. 00 00 00

VALID IMAGE HORIZONTAL

BLANKING

Pm−1,0 Pm−1,1.....................................Pm−1,n−1 Pm−1,n 00 00 00 .................. 00 00 00

Pm,0 Pm,1.....................................Pm,n−1 Pm,n 00 00 00 .................. 00 00 00

00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00

VERTICAL BLANKING VERTICAL/HORIZONTAL

BLANKING

00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00

Figure 2. Spatial Illustration of Image Readout

READOUT SEQUENCE data. One 10−bit pixel datum is launched on the DOUT pins
Typically, the readout window is set to a region including for each falling edge of PIXCLK. The launch edge of
only active pixels. The user has the option of reading out PIXCLK may be set in register R0x3028. When both FV and
dark regions of the array, but if this is done, consideration LV are asserted, the pixel is valid. PIXCLK cycles that occur
must be given to how the sensor reads the dark regions for when FV is deasserted are called vertical blanking. PIXCLK
its own purposes. cycles that occur when only LV is deasserted are called
horizontal blanking.
PARALLEL OUTPUT DATA TIMING
To enable the parallel output pins, set R0x301A[7] = 1,
The output images are divided into frames, which are and set R0x301A[12] = 1 to disable the MIPI serializer. The
further divided into lines. By default, the sensor produces parallel input pins (i.e. TRIGGER, STANDBY, etc) may be
1920 rows of 1200 columns each. The FV and LV signals enabled by setting R0x301A[8] = 1. Only one output
indicate the boundaries between frames and lines, interface should be enabled at a time.
respectively. PIXCLK can be used as a clock to latch the

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PIXCLK

FV
LV
DOUT[9:0] P0 P1 P2 P3 Pn

Vertical Blanking Horiz Blanking Valid Image Data Horiz Blanking Vertical Blanking

Figure 3. Default Pixel Output Timing

LV and FV LV Format Options

The timing of the FV and LV outputs is closely related to The default situation (R0x306E[1:0] = 0x0) is for LV to
the row time and the frame time. FV will be asserted for an be de−asserted when FV is de−asserted. By setting
integral number of row times, which will normally be equal R0x306E[1:0]= 0x1, a continuous LV signal will be output.
to the height of the output image. The formats for reading out three lines and two vertical
LV will be asserted during the valid pixels of each row. blanking lines are shown in Figure 4.
The leading edge of LV will be offset from the leading edge
of FV by 6 PIXCLKs. Normally, LV will only be asserted if
FV is asserted; this is configurable as described below.

FV
Default
LV

FV
Continuous LV LV

Figure 4. LV Format Options

The timing of an entire frame is shown below in Figure 5: the maximum rate of one pixel per PIXCLK. One row time
“Line Timing and FRAME_VALID/ LINE_VALID (tROW) is the period from the first pixel output in a row to the
Signals”. For detailed timing diagrams and switching first pixel output in the next row. The row time and frame
parameters, refer to the AR0234 data sheet. time are defined by equations in Table 1.

Frame Time
The pixel clock (PIXCLK) represents the time needed to
sample one pixel from the array. The sensor outputs data at
...
FRAME_VALID

...
LINE_VALID
...

Number of master clocks P1 A Q A Q A P2

Figure 5. Line Timing and FRAME_VALID/LINE_VALID Signals

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Table 1. FRAME TIME (EXAMPLE BASED ON 1920 X 1200, 120 FRAMES PER SECOND)
Default Timing at 90 MHz (CIT
Parameter Name Equation = 200 rows)
A Active data time Context A: (R0x3008 − R0x3004 + 1)/4 480 pixel clocks = 5.33 ms
Context B: (R0x308E − R0x308A + 1)/4

P1 Frame start blanking 6 (fixed) 6 pixel clocks = 0.07 ms

P2 Frame end blanking 6 (fixed) 6 pixel clocks = 0.07 ms
Q Horizontal blanking R0x300C − A 132 pixel clocks = 1.47 ms
A+Q Row Time (tROW) R0x300C 612 pixel clocks = 6.8 ms

V Vertical blanking Context A: [(R0x300A+5 − (R0x3006 − R0x3002 + 1)) * (A + Q)] 12,852 pixel clocks = 142.8 ms
Context B: [(R0x300A+5 − (R0x3090 − R0x308C + 1)) * (A + Q)]

Nrows * (A Frame valid time Context A: ((R0x3006-R0x3002+1)*(A+Q))-Q+P1+P2 734,280 pixel clocks = 8.16 ms
+ Q) Context B: ((R0x3090-R0x308C+1)*(A+Q))-Q+P1+P2
F Total frame time V + (Nrows * (A + Q)) 747,132 pixel clocks = 8.3 ms

NOTE: R0x3004 = R0x308A= 8

R0x3008 = R0x308E= 1927
R0x3002 = R0x308C= 8
R0x3006 = R0x3090= 1207
R0x300A = 1216
R0x3012 = 200
Sensor timing is shown in terms of pixel clock cycles (see control is programmed with 2000 rows and the fine shutter
Figure 3: “Default Pixel Output Timing,” on page 4). The width total is zero.
recommended maximum pixel clock frequency is 90 MHz. For Master mode, if the integration time registers exceed
The vertical blanking and the total frame time equations the total readout time, then the vertical blanking time is
assume that the integration time (coarse integration time) is internally extended automatically to adjust for the additional
less than the number of active lines plus the blanking lines: integration time required. This extended value is not written
(eq. 1) back to the frame_length_lines register. The
Coarse Integration Time t Window Height ) Vertical Blanking frame_length_lines register can be used to adjust
frame-to−frame readout time. This register does not affect
If this is not the case, the number of integration lines must
the exposure time but it may extend the readout time.
be used instead to determine the frame time, (see Table 2).
In this example, it is assumed that the coarse integration time

Table 2. FRAME TIME: LONG INTEGRATION TIME

Equation Default Timing at 90 MHz (CIT =
Parameter Name (Number of Pixel Clock Cycles) 2000 rows)

F’ Total frame time (long integration time) Context A: (R0x3012 * (A + Q)) + P1 + P2 1,224,012 pixel clocks = 13.6 ms
Context B: (R0x3016 * (A + Q)) + P1 + P2

EXPOSURE The actual total integration time is defined as:

Total integration time is the result of 1. For CIT = 0
coarse_integration_time and fine_integration_time t clk + (17 ) 2 * FIT) (eq. 2)
registers plus offset, and depends also on whether manual or
automatic exposure is selected. Constraint for FIT:
FIT > 79 and FIT < 150
Given:
T + t clkńPixelClkFreq (eq. 3)
• CIT = R0x3012, Coarse_integration_time (number of
lines of integration) R0x3268[14] must be set to 1.
• FIT = R0x3014, fine_integration_time (number of 2. CIT = 1
pixels of integration) t clk + (LLPCK ) 313 ) 2 * FIT) (eq. 4)
• LLPCK = R0x300C Constraint for FIT:
• tclk = Total Integration Time (unit in clocks) FIT > 39 and FIT < 80
• T= Total Integration Time (unit in seconds) T + t clkńPixelClkFreq (eq. 5)

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R0x3268[14] must be set to 1. includes vertical blanking lines), such that the frame rate is
3. CIT > 1 not affected by the integration time.
tclk + (CIT * LLPCK * 162 ) 3 * FIT) (eq. 6)
At different FPS, the sensor will have different PIXCLK
frequencies which will change exposure times.
Constraint for FIT:
FIT > 0 and FIT < 80 ROW−TIME DEFINITION
T + t clkńPixelClkFreq (eq. 7) One row−time is equal to the sum of the number of active
pixels (columns) and the number of horizontal blanking
R0x3268[14] = 0
pixels divided by the pixel readout rate:
Note: FIT must be an even number for all cases. (eq. 10)
With the restrictions that: active_pixel ) horizontal_blank_pixels
row_time +
1. When automatic exposure control (AEC) is PIXCLK_frequency
disabled:
(eq. 11)
A The number of lines of integration for Context
A equals the value in R0x3012, and for Context B line_length_pck(R0x300C)
row_time default_settings +
equals the value in R0x3016. PIXCLK_frequency
B The number of pixels of integration for Context
A equals the value in R0x3014, and for Context B line_length_pck(612)
+ + 6.8 ms
equals the value in R0x3018. 90 MHz
2. When automatic exposure control (AEC) is
enabled, the number of lines of integration may FRAME TIME DEFINITION
vary from frame to frame, with the limits When frame_length_lines > coarse_integration_time:
controlled by R0x311E (minimum auto exposure
time should be 2 rows) and R0x311C (maximum rows_per_frame = frame_length_lines + overhead =
auto exposure time). For a specific frame output, frame_length_lines + 5
the exposure time (in rows) can be read in When frame_length_lines <= coarse_integration_time:
R0x3164. Fine integration time is not used by the rows_per_frame = coarse_integration_time − 2 + overhead
auto exposure function. = coarse_integration_time + 3
If the exposure time is to be set to approximately 2 ms and Frame Time = rows_per_frame * row_time
default settings are being used (where one row−time equals
6.8 μs), a value of “294” is entered in R0x3012 (2 ms / 6.8 μs EXPOSURE INDICATOR
= 294). In this mode, only whole number row−time The AR0234 provides an output pin, FLASH, to indicate
increments are allowed−no fractional time increments can when the exposure takes place. When R0x3270[8] is set,
be achieved. It may be possible to adjust the number of FLASH is HIGH during exposure.
horizontal active or blanking pixels to bring the desired
exposure time to a whole number row−time increment. REAL−TIME CONTEXT SWITCHING
The exposure time using the default power up settings of In the AR0234, the user may switch between two full
the sensor can be determined as follows: register sets (listed in Table 3) by writing to a context switch
(eq. 8)
change bit in R0x30B0[13]. This context switch will change
all registers (no shadowing) at the frame start time and have
exposure_time + coarse_integration_time row_time the new values apply to the immediate next exposure and
exposure_time + (294 rows) (6.8 ms) + 2 ms (eq. 9) readout time.
Typically, the value of the coarse_integration_time
register is limited to the number of lines per frame (which

Table 3. REAL−TIME CONTEXT−SWITCHABLE REGISTERS

Register Number
Register Description Context A Context B
y_addr_start R0x3002 R0x308C
x_addr_start R0x3004 R0x308A
y_addr_end R0x3006 R0x3090
x_addr_end R0x3008 R0x308E
coarse_integration_time R0x3012 R0x3016

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Table 3. REAL−TIME CONTEXT−SWITCHABLE REGISTERS

Register Number
Register Description Context A Context B
fine_integration_time R0x3014 R0x3018
x_odd_inc R0x30A2 R0x30AE
y_odd_Inc R0x30A6 R0x30A8
green1_gain (GreenR) R0x3056 R0x30BC
blue_gain R0x3058 R0x30BE
red_gain R0x305A R0x30C0
green2_gain (GreenB) R0x305C R0x30C2
global_gain R0x305E R0x30C4
frame_length_lines R0x300A R0x30AA
coarse_analog_gain R0x3060[6:4] R0x3060[14:12]
fine_analog_gain R0x3060[3:0] R0x3060[11:8]
col_bin R0x3040[13] R0x3040[11]
row_bin R0x3040[12] R0x3040[10]
line_length_pck R0x300C R0x303E
operation_mode R0x3082[1:0] R0x3084[1:0]
col_sf_bin_en R0x3040[9] R0x3040[8]
col_sf_bin_mono_en R0x3040[7] R0x3040[6]

AR0234 has a highly configurable programmable context Table 6. SECOND CONTROL WORD
switching RAM of size 256 x 16. Within this context
R0x3066[15:11] R0x3066[10:0]
memory, changes to any register may be stored. The register
set for each context must be the same, but the number of Load count Bits [11:1] of stored register address
contexts and registers per context are limited only by the size
of the context memory. Two registers are required to use the CONTEXT SWITCHING EXAMPLE:
context switching RAM as described in Table 4. The following example will program three contexts for two
address values,
Table 4. CONTEXT SWITCHING RAM REGISTERS • X_addr_end = Address 0x3008
Register Address Register Name • Y_addr_end = Address 0x3006
0x3034 CTX_CONTROL_REG The three contexts are:
0x3066 CTX_WR_DATA_REG
• Context 1
− X_addr_end = 1080 (0x0438)
Register 0x3034 is used initially to reset the address − Y_addr_end = 810 (0x032A)
counter for programming the context RAM. It is later used
to determine when to load the new register set and which
• Context 2
− X_addr_end = 640 (0x0280)
register set to load. Register 0x3066 is used to set the number
− Y_addr_end = 480 (0x01E0)
of contexts, the register address with multiple contexts, and
the context values. The first two writes to register 0x3066 • Context 3
are control words as shown in Tables 5 and 6. − X_addr_end = 320 (0x0140)
− Y_addr_end = 240 (0x00F0)
Table 5. FIRST CONTROL WORD To configure the AR0234 context RAM:
1. Write 0x0000 to R0x3034. This will reset the
R0x3066[15:8] R0x3066[7:4] R0x3066[3:0]
context RAM address counter.
1111_1000 Number of MSB of stored register
(Fixed control word) Contexts address

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2. Write 0xF823 to R0x3066. This will write the first SWITCHING CONTEXTS
control word to the first address of the context Once the context RAM has been configured, register
RAM. The first 8 bits are a fixed control word. R0x3034 is then used to determine when to switch contexts,
Bits [7:4] are set to the number of contexts, where and to which context to switch. Table 7 describes how to
0 represents one context. In this example, it is control context switching.
0b0010, that is, 2+1=3 contexts to be programmed.
Bits [3:0] represent the MSB of the stored register Table 7. CONTEXT SWITCH CONTROL
address. Since we are switching registers R0x3006
CTX_CONTROL_REG Description
and R0x3008, we write 0x3 (or 0b0011).
3. Write 0x1003 to R0x3066. Bits [15:11], load R0x3034[15] = 0x1 Load the new context immediately
count, represents the number of sequential R0x3034[3:0] Determines which context to load
addresses to contain stored context values. In this
example, it is 0b00010, that is, two consecutive FEATURES
registers, R0x3006 and R0x3008 are to be NOTE: See the AR0234 Register Reference for
configured. Bits [10:0] represent bits [11:1] of the additional details.
address of the first register to be configured. Bit 0
is not needed because all address values are even. Auto Multiple Context RAMs Switching
In this case, we are writing bits [11:1] of R0x3006. 1. Two contexts auto switching
4. Program the register values for R0x3006 R0x3034[6:4] = 4, store
A Write 0x032A to R0x3066 first context at 1st and 2nd position and
B Write 0x01E0 to R0x3066 second context at 3rd position.
C Write 0x00F0 to R0x3066 2. Three contexts auto switching
5. Program the register values for R0x3008 R0x3034[6:4] = 6, store
A Write 0x0438 to R0x3066 first context at 1st and 2nd position,
B Write 0x0280 to R0x3066 second context at 3rd position and
C Write 0x0140 to R0x3066 third context at 4th position.
6. The load counter has now expired, so a new 3. Four contexts auto switching
command is expected. This may be a new set of R0x3034[6:4] = 7, store
context registers to be programmed. In this case, first context at 1st and 2nd position,
return to step 2. second context at 3rd position,
7. If all desired context registers have been third context at 4th position and
configured, write 0x0000 to R0x3066 to end the fourth context at 5th position.
programming sequence. Note: Four contexts is possible but need to
If the desired context switchable registers do not share the discard first 4 frames.
same MSB in address, the programming procedure will need
to skip back to step 2 to load the new MSB in R0x3066[3:0].

frm1 frm2 frm3 frm4 frm5 frm6 frm7 frm8 frm9 frm10 frm11 frm12 frm13

cxt1 (def*) cxt1 (def*) cxt2 cxt3 cxt4 cxt1 cxt2 cxt3 cxt4 cxt1 cxt2 cxt3 cxt4

Figure 6. Auto Multiple Context RAM Switching Sequence

OPERATIONAL MODES programmed through the two−wire serial interface for both
modes.
Master Mode
In master mode, the exposure period occurs
The AR0234 works in master (video) or trigger (single
simultaneously with the frame readout (see Figures 7
frame) modes. In master mode, the sensor generates the
and 8). This makes master mode the fastest mode of
integration and readout timing. In trigger mode, it accepts an
operation. When exposure time is greater than the frame
external trigger to start exposure, then generates the
length, the number of vertical blanking rows is increased
exposure and readout timing. The exposure time is
automatically to accommodate the exposure time.

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Readout Time > Exposure Time

FLASH
Exposure Time

FRAME_VALID Vertical Blanking

LINE_VALID

DOUT(9) xxx xxx xxx

Figure 7. Master Mode Synchronization Waveform #1

Exposure Time > Readout Time

FLASH
Exposure Time

Vertical Blanking
FRAME_VALID

LINE_VALID

DOUT[9] xxx xxx xxx

Figure 8. Master Mode Synchronization Waveform #2

Trigger Mode taken place. This triggering action can be the passing of an
In trigger mode, the exposure period and the frame object on a conveyor belt, the flash of a strobe light, or the
readout occur sequentially (see Figure 10 and Figure 11 on press of a button.
page 11). This makes trigger mode slower than master The AR0234 offers the ability to synchronize the start of
mode. Two options of triggering are made available. A the image sensor’s exposure with this triggering action. This
Pulsed Trigger mode where only a single frame is output, synchronization is controlled on the image sensor through
and an Automatic Trigger mode where a series of frames are the use of the TRIGGER input signal. Additionally, the
output. image sensor offers the flexibility to program the exposure
time remotely. This Developer Guide only addresses the
Triggered System Details
single image sensor (non−stereoscopic) mode of operation.
Many imaging applications commonly require the image
sensor to capture an image only after a triggering action has

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EXTCLK
TRIGGER

AR0234
CONTROLLER
PIXCLK
FRAME_VALID
LINE_VALID
FLASH
DOUT[9:0]

Figure 9. Block Diagram

When the image sensor is set to trigger mode, the It is important to note that in Automatic Trigger Mode, the
beginning and duration of the exposure time are controlled. Trigger input is an asynchronous interrupt to the sensor’s
The global shutter feature of the image sensor allows all exposure and readout control logic. The falling edge of the
pixels to be exposed in parallel−all pixels start exposing Trigger pulse will never affect the frame that is currently
(integrating charge) simultaneously and stop exposing being readout, but the timing of the trigger falling edge may
simultaneously. When exposure stops, the per-pixel interrupt the integration time and the FLASH output
integrated charges are digitized and read out of the chip. A duration for the following frame. Avoid processing any
new exposure begins only after the readout of all pixels is frame that starts readout after the falling edge of Trigger
complete. If the TRIGGER input is left in the asserted state, since its exposure time may have been interrupted, and to
the sensor will automatically initiate a new frame prevent from having a corrupted FLASH output pulse
acquisition sequence upon completion of the current frame. (perhaps causing and extended illumination control output),
In Automatic Trigger Mode, if the Trigger signal is the Trigger input should not fall within FLL − (ImageHeight
brought low to stop readout during integration time (during +16 ) + 16, with ImageHeight = R0x3006[9:0] −
the FLASH high period), then the FLASH output signal may R0x3002[9:0] + 1 line times of the start of integration time
not go low for the final frame. To avoid this, the Trigger (typically the FLASH rising edge). If it is difficult to ensure
signal should be brought low between integration periods that the Trigger falling edge does not occur within this
(when FLASH is low). window, then the FLASH signal can be safely disabled (by
R0x3270[8]=0) just before de−asserting the Trigger input.

TTT

TRIGGER TTPW

EXPOSURE
TIME
TTF
FLASH

TFFV

FRAME_VALID
(for Parallel mode only) TVB

LINE_VALID
FRAME TIME
(for Parallel mode only)

Notes: 1. Not drawn to scale.

2. Frame readout shortened for clarity.
3. Progressive scan readout mode shown.
Figure 10. Pulsed Trigger Mode

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TRIGGER

EXPOSURE EXPOSURE EXPOSURE

TIME TIME TIME
TTF FRAME A FRAME B FRAME C
FLASH

TFFV

FRAME_VALID FRAME A FRAME B

(for Parallel mode only)
TVB

LINE_VALID
(for Parallel mode only)
FRAME TIME

Figure 11. Automatic Trigger Mode

TABLE 8. TRIGGER TIMING

Symbol Description Value
Minimum TRIGGER signal period TTF + EXPOSURE TIME + TFFV + FRAME TIME (see Equation 16)
TTT

TTPW TRIGGER signal pulse width 3 clocks

TTF TRIGGER to FLASH Case 1: LED Delay = 0
Parallel: (7 + (530/LLPCK)) rows + 2.6 us
MIPI: (7+(530/LLPCK)) rows + MIPI Wake up Time + 2.6 us

Case 2: (LED Delay !=0) (Lag)

Parallel: (9 + (R0x3270[6:0])) rows + 2.6 us
MIPI: (9 + (R0x3270[6:0])) rows + MIPI Wake up Time + 2.6 us

Case 3: (LED Delay != 0) (Lead)

Parallel: 9 rows + 2.6 us
MIPI: 9 rows + MIPI Wake up Time + 2.6 us
TFFV FLASH to FRAME_VALID (15.16 + (567/LLPCK)) rows
TVB Minimum Vertical blanking time 1 row
1. Exposure Time must be less than TTT- (TTF+TFFV+Frame Time) in order to keep a constant frame rate with fixed TTT.
2. See “Exposure and Data Synchronization Outputs” on page 12 for the row−time unit definition.
3. To change exposure time, change the coarse integration time registers R0x3012 for Context A or R0x3016 for Context B.
4. To change frame rate, change the TTT value.
5. LED Delay is R0x3270[6:0]; Lag is R0x3270[7] = 0
6. Ideal LED Delay (unit row): R0x3270[6:0] < (R0x3012 – 3)
7. MIPI Wake up Time is about 1.4 ms.
8. Pulsed Trigger Mode Trigger pulse must fall before frame readout

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Example: TTF for MIPI 4−lane, LED Delay = 0, pixel clock Register Settings
= 90 MHz, The TRIGGER mode of operation requires that register
LLPCK = 612, R0x301A (Reset Register) bit 2 be set to “0”. Setting this
MIPI Wake Up Time ~ 1.4 ms register to “1” will switch the sensor back to the master mode
So, TTF ~ (7+ (530/612)) rows + 1.4 ms + 2.6 us ~ 11.87 ms of operation. The general purpose I/O (GPI) pins must also
be enabled as shown in Table 9.

Table 9. SNAPSHOT MODE REGISTER SETTINGS

Value in
Register Register Name Bit Bit Name Bit Description Dec (Hex)

R0x301A Reset Register 2 Stream 0 = Trigger mode 0

1 = master mode

R0x301A Reset Register 8 GPI_EN 0 = GPI input buffers disabled 1

1 = GPI input buffers enabled

R0x301A Reset Register 11 forced_pll_on 0 = PLL powered down in standby 1

1 = PLL always powered

Table 10. PULSE TRIGGER, AND MUTI−SENSOR SYNC MODE SETTING

R0x301A[2] R0x301A[8] R0x301A[11] R0x30CE[5] R0x30CE[8]
Pulse Trigger 0 1 1 0 0
Multi−sensor Sync Mode 1 1 1 1 1

Start of Exposure normally held in a LOW state. FLASH changes to a HIGH

The start of exposure is controlled by the TRIGGER input state when the image sensor is exposing (integrating
on the image sensor. Normally, TRIGGER is held in a LOW charge). FLASH returns to the normal LOW state once the
state. To start exposing, this signal is changed to a HIGH exposure (set by register R0x3012 (Context A), or register
state. This HIGH state is then sampled on the rising edge of R0x3016 (Context B)) has timed out. Refer to “Flash Mode”
the master clock (EXTCLK) of the image sensor. TRIGGER on page 23 for additional flash mode options.
must be held HIGH for greater than 3 TEXTCLK cycles time. To indicate a valid frame of video data is being output
from the image sensor, FRAME_VALID switches to a
Duration of Exposure
HIGH state. The change of state occurs slightly over 18
The duration of the exposure is set by the value stored in row−times after the exposure time ends. FRAME_VALID
R0x3012, which represents an equivalent number of returns to a LOW state after the active rows have been read
row−times (see “Exposure and Data Synchronization out. The number of active rows plus vertical blanking is
Outputs” on page 12) to the actual exposure time. stored in the FRAME_LENGTH_LINES register
The minimum exposure time supported by the AR0234 (R0x300A) (default value is 1216).
image sensor in trigger mode is 0 row−times (sub−row is During the valid video frame state, LINE_VALID
supported). switches to a HIGH state to indicate a valid row of video data
Exposure and Data Synchronization Outputs is being presented. LINE_VALID returns to a LOW state
The AR0234 image sensor offers an output after a set number of PIXCLK cycles corresponding to the
synchronization signal (FLASH) that can be used to control number of active pixels per line. The number of active pixels
the flash of a light source. The timing of this signal in trigger plus horizontal blanking is stored in the
mode is similar to the other master modes. The signal is LINE_LENGTH_PCK register (R0x300C).

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TRIGGER Input Restrictions

The minimum time between two successive TRIGGER input pulses (shown as TTT in Figure 10 on page 10) is calculated
from the exposure time and the frame time. The exposure time is described in “Exposure and Data Synchronization Outputs”
on page 12. The frame time may be calculated from two variables: the row−time, and the number of rows-per-frame. The
number of rows−per−frame is equal to the sum (R0x300A) of the number of active rows and the number of vertical blanking
rows:
rows_per_frame default_settings + frame_length_lines(R0300A ) 5) + 1221 (eq. 12)

The frame time is equal to the product of the number of rows−per-frame and the row− time.
frame_time + rows_per_frame (row_time) (eq. 13)

frame_time default_settings + (1221 rows) ǒ6.8rowmsǓ + 8.30 ms (eq. 14)

The minimum time between two successive TRIGGER pulses equals the sum of the frame time, the exposure time, TTF and
TFFV:
T TT + (frame_time) ) (exposure_time) ) ǒT TF ) T FFVǓ (eq. 15)
Further, the maximum allowable frame rate may be calculated from these same three variables. The maximum frame rate is
the reciprocal of the sum of the frame time, the exposure time, trigger to flash, and flash to frame valid times:.
1
frame_rate + (eq. 16)
frame_time ) exposure_time ) T TF ) T FFV
The TRIGGER pulse period should correspond to the desired frame rate. For individual (asynchronous) trigger pulses, the
TRIGGER signal should be asserted no sooner than FRAME_VALID is deasserted, and the minimum of 27 rows of vertical
blanking has elapsed.

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Example Frame Rate Calculations Step 2: Calculate the rows−per−frame read out.
Two examples follow on performing frame rate row_per_frame + frame_length_lines ) 5 (eq. 19)
calculations for the AR0234 image sensors, shown in
Table 11 below. row_per_frame + 1221 rows (eq. 20)
Example 1 shows maximum exposure time for keeping
Step 3: Calculate the frame time.
frame rate at 25 fps.
frame_time + (rows_per_frame) (row_time) (eq. 21)

Table 11. EXAMPLE 1 (WITH DEFAULT SETTING FOR

FULL RESOLUTION) frame_time + ǒ1221 rowsǓ ǒ6.8rowmsǓ + 8.30 ms (eq. 22)

Image Sensor Setting

Condition Description Register [Bits] = Value
Step 4: Calculate TTF + TFFV.
Operational mode Trigger R0x301A[2] = 0
R0x301A[8] = 1
T TF ) T FFV + ǒǒ7 ) ǒ530
612
ǓǓrows ) 1.4 ms ) 2.6 msǓ
R0x301A[11] = 1
PIXCLK frequency 90 MHz N/A
ǒ
) 15.16 ) ǒ567Ǔrows
612
row_time

Window height 1200 (Note 9) R0x3006 = 1207 + (11.86 ) 16.09)rows 6.8 ms

R0x3002 = 8 (eq. 23)
+ 190.13 ms
Window width 1920 R0x3008 = 1927
R0x3004 = 8
Step 5: Calculate the maximum exposure time
Frame Rate + 25 fps (eq. 24)
line_length_pck 612 R0x300C = 612
frame_length_line 1216 R0x300A = 1216 T TT + 10 6ń25 ms + 40, 000 ms (eq. 25)
s
(eq. 26)
Integration time 16 R0x3012 = 16 Flash width t T TT * ǒT TF ) T FFV ) Frame_timeǓ
MIPI Wake Up 1.4 ms
(eq. 27)
Time
Flash width t 40, 000 ms * 190.13 ms * 16.67 ms
9. Window height is 1208 rows with embedded stats and data + 23, 139.87 ms
enabled.
See actual flash width computation in Flash Mode section on
Step 1: Calculate the row−time. page 15.
line_length_pck Assume R0x3270[7 : 0] + 0 (eq. 28)
row_time + (eq. 17)
PIXCLK_frequency
Flash wdith + exposure_time ) 11 ms (eq. 29)
612
row_time + + 6.8 ms (eq. 18) (eq. 30)
90 MHz Exposure_time t 23, 139.87 ms * 11 ms + 23, 128.87 ms

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FLASH MODE 1. Master mode

AR0234 provides an output pin, FLASH, to indicate when A. For R0x3270[7]=1: the start of flash output is
the exposure takes place. leading the start of the integration, and the end of
Flash Mode: Set R0x3270[8] = 1 and R0x3046[8]=0 to the flash is the same as the end of integration:
enable LED flash mode output. The length of flash output is Rx0x3270[7:0] is an 8 bit two’s complement
controlled by R0x3270[7:0], unit in half row time. number.
Toverhead = 11 ms and is at the end of the flash pulse B. For R0x3270[7]=0: the start of flash output is
Length of flash output + T flash + TINT ) T overhead (eq. 31) lagging the start of the integration, and the end of
the flash is the same as the end of integration.
* (row_time) * ƪ(R0x3270[7 : 0])ń2ƫ

Start of End of
Integration Integration

Programmable Lead
Delay

Flash output
R0x3270[7]=1

Flash output
R0x3270[7]=0

Programmable Lag Delay

Start of End of
Integration Integration

Figure 12. Master Mode

NOTE: Inverted flash output is not supported.

2. Trigger Mode D. For R0x3270[7]=0, the start of the flash output

A. The sensor is in stand−by mode before trigger is lagging the start of the integration, but the end
pulse appearance. of the flash is the same as the end of integration.
B. When R0x3270[7:0] = 0 That is, the length of flash is shorter than that of
TFlash = Tint + 11 us (eq. 33) integration. Note: there will have flash output,
C. For R0x3270[7]=1, the start of the flash output only when trigger pulse width > (TTF + 1
is the same as the start of the integration, but the row_time).
end of the flash is lagging the end of the
integration. That is, the length of flash is longer
than that of integration.

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For R0x3270[7]=0

Trigger Pulse

Programmable leading
Flash output edge of Flash output
Solid Line: R0x3270[7:0]=0
Red Dash: R0x3270[7]=0

Start of Integration End of Integration

For R0x3270[7]=1

Trigger Pulse

Programmable end of
Flash output Flash output
Solid Line: R0x3270[7:0]=0
Red Dash: R0x3270[7]=1

Start of Integration End of Integration

Figure 13. Trigger Mode
NOTE: This for reference only. Please refer to Figure 10 for exact timing.

Constraints when using flash lead and lag adjustment: for simplicity. Registers written via the two−wire interface
will not be preserved following a hard reset.
For CIT=0,1,2: set R0x3270[7:0]=0. Soft Reset of Logic
Soft reset of logic is controlled by bit 0 of the R0x301A
For 2<CIT<67: Reset register. This bit is a self−resetting bit and also returns
When R0x3270[7]=0 (led lag): the usable range is from 1 to to “0” during two−wire serial interface reads. Registers
(2*CIT − 5) decimal. written via the two wire interface will not be preserved
following a soft reset.
When R0x3270[7]=1 (led lead): do not use it. OUTPUT ENABLE
RESET The AR0234’s outputs can be tri−stated with the
The AR0234 may be reset by using RESET_BAR or the OE_BAR pin. Before the external pin can be used to control
reset register. output enable, set register R0x301A[6] = 0 to disable the
output drivers. Then set R0x301A[8] = 1 to enable the input
Hard Reset of Logic pins (OE_BAR, TRIGGER, and STANDBY). Driving
The host system can reset the image sensor by bringing the OE_BAR low will enable the output drivers, while driving
RESET_BAR pin to a LOW state. Alternatively, the it high will tri−state the parallel output pins. The parallel
RESET_BAR pin can be connected to an external RC circuit outputs can also be tri−stated by setting R0x301A[7] = 0.

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CLOCKS

Note: mlane is number of MIPI lanes.

Figure 14. PLL for the Serial Interface

VCO FSERIAL_CLK, or OP_CLK when configured to use the

The sensor contains a phase−locked loop (PLL) that is parallel interface.
used for timing generation and control. The required VCO
clock frequency is attained through the use of a pre−PLL Table 12. PLL PARAMETERS FOR THE PARALLEL
clock divider followed by a multiplier. The PLL multiplier INTERFACE
should be an even integer. If an odd integer (M) is
Parameter Symbol Min Max Unit
programmed, the PLL will default to the lower (M−1) value
to maintain an even multiplier value. The multiplier is External Clock EXTCLK 6 54 MHz
followed by a set of dividers used to generate the output VCO Clock FVCO 384 768 MHz
clocks required for the sensor array, the pixel analog and
Readout Clock PIXCLK 90 Mpixel/s
digital readout paths, and the output parallel and serial
interfaces. Use of the PLL is required when using the MIPI
SERIAL PLL CONFIGURATION
interface. Fvco can be calculated using the following
equations: The PLL must be enabled when MIPI mode is selected.
The sensor will use op_sys_clk_div and op_pix_clk_div to
EXTCLK pll_multiplier
F VCO + (eq. 32) configure the output clock per lane (OP_CLK). The
pre_pll_clk_div configuration will depend on the number of active lanes (1
EXTCLK pll_multiplier (eq. 33) or 2) configured. To configure the sensor protocol and
PIXCLK + number of lanes, refer to “Serial Configuration” on page 17.
pre_pll_clk_div vt_sys_clk_div vt_pix_clk_div
mlanes
4 Table 13. PLL PARAMETERS FOR THE SERIAL
INTERFACE
EXTCLK pll_multiplier (eq. 34)
op_clk + Parameter Symbol Min Max Unit
pre_pll_clk_div vt_sys_clk_div vt_pix_clk_div
External Clock EXTCLK 6 54 MHz
Note: mlane is number of MIPI lanes.
VCO Clock FVCO 384 768 MHz
DUAL READOUT PATHS Readout Clock PIXCLK 90 Mpixel/s
There are two readout paths within the sensor digital
Output Clock (10−bit) OP_CLK 90 Mpixel/s
block. The sensor PLL should be configured such that the
total pixel rate across both readout paths is equal to the Output Serial Data Rate FSERIAL 360 900 Mbps
output pixel rate. Per Lane

PARALLEL PLL CONFIGURATION Configure the serial output so that it adheres to the following
The maximum output of the parallel interface is rules:
90 Mpixel/s. This will limit the readout clock (PIXCLK) to • The maximum data−rate per lane (FSERIAL) is
90 Mpixel/s. The sensor will not use the FSERIAL, 900 Mbps/lane

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• Configure the output pixel rate per lane (OP_CLK) so Example

that the sensor output pixel rate matches the peak pixel FLL = 1216
rate (2 x PIXCLK). LLPCK = 612
4−lane : 4*OP_CLK = 4*PIXCLK PIXCLK = 90 MHz
2−lane : 2*OP_CLK = 4*PIXCLK Frame Time = 8.30 ms
1−lane : 1*OP_CLK = 4*PIXCLK 3. Set R0x301A[12] = 1 if serial mode was used.
4. External clock can be turned off to further
minimize power consumption (Optional)
Table 14. EXAMPLE PLL CONFIGURATIONS FOR THE
SERIAL INTERFACE Exiting Soft Standby:
1. Enable external clock if it was turned off.
4−lane 2−lane 2. Set R0x301A[2] = 1 or drive the TRIGGER pin
Parameter 10−bit 8−bit 10−bit Unit HIGH.
FVCO 450 720 450 MHz
3. Intermediately following, set R0x301A[12] = 0 if
serial mode is used.
vt_sys_clk_div 1 1 1
vt_pix_clk_div 5 8 5 WINDOW CONTROL
Registers x_addr_start, x_addr_end, y_addr_start, and
op_sys_clk_div 1 2 1
y_addr_end control the size and starting coordinates of the
op_pix_clk_div 10 8 10 image window.
FSERIAL 450 720 450 MHz The exact window height and width out of the sensor is
FSERIAL_CLK 450 360 450 MHz
determined by the difference between the Y address start and
end registers or the X address start and end registers,
PIXCLK 90 90 45 MHz
respectively.
OP_CLK 90 90 90 MHz The AR0234 allows different window sizes for context A
Pixel Rate 900 720 900 Mpixel/s and context B.

BLANKING CONTROL
Spread−Spectrum Clocking
Horizontal blank and vertical blank times are controlled
To facilitate improved EMI performance, the external
by the line_length_pck and frame_length_lines registers,
clock input allows for spread spectrum sources, with no
respectively.
impact on image quality. Limits of the spread spectrum input
clock are: • Horizontal blanking is specified in terms of pixel
clocks. It is calculated by subtracting the X window
• 5% maximum clock modulation
size from the line_length_pck register. The minimum
• 35 kHz maximum modulation frequency horizontal blanking is 132 pixel clocks.
• Accepts triangle wave modulation, as well as sine or • Vertical blanking is specified in terms of numbers of
modified triangle modulations. lines. It is calculated by subtracting the Y window size
STREAM/STANDBY CONTROL from the frame_length_lines register. The minimum
The sensor supports a standby mode: Soft Standby. In this vertical blanking is 16 lines.
mode, external clock can be optionally disabled to further The actual imager timing can be calculated using Table 1
minimize power consumption. If this is done, then the on page 5 and Table 2 on page 5, which describe the Line
power−up sequence described in the AR0234 data sheet Timing and FV/LV signals.
must be followed. READOUT MODES
Soft Standby By default, the resolution of the output image is the full
Soft Standby is a low power state that is controlled width and height of the FOV as defined above. The output
through register R0x301A[2]. When the sensor comes back resolution can be reduced by digital binning.
from Soft Standby, previously written register settings are Binning
still maintained. Soft standby will not occur if the TRIGGER All of the pixels in the FOV contribute to the output
pin is held high. A specific sequence needs to be followed image in binning mode. This can result in a more pleasing
to enter and exit from Soft Standby. output image with reduced artifacts. It also improves
Entering Soft Standby: low−light performance for horizontal sum binning. For
1. Set R0x301A[2] = 0 or drive the TRIGGER pin monochrome operation, R0x30B0[7] must be set to
LOW. 1.Binning mode is enabled by setting read_mode
2. Delay (One Frame Time) (R0x3040), x_odd_inc(R0x30A2) and y_odd_inc
Frame Time = FLL * LLPCK/PIXCLK (R0x30A6) for context A, and x_odd_inc_cb (R0x30AE)
and y_odd_inc_cb (R0x30A8) for context B. The

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following tables show how to set these registers for digital Skipping
binning. Skipping reduces resolution by using only selected rows
Color binning is defined as Rx30B0[7]=0. In this mode, from the FOV in the output image. In skip mode, entire rows
2 pixels in the same color plane will be combined (binning) of pixels are not sampled, resulting in a lower resolution
as define by Rx3040[13:12]. output image. A skip 2X mode skips one Bayer pair of pixels
For mono chrome binning, Rx30B0[7]=1, this mode will for every pair output. Skipping is set by R0x30A6 (context
combine 2 adjacent pixels regardless of color planes. A) and R0x30A8 (context B). The maximum supported skip
Tables 15 and 16 demonstrate how to set these registers is 16 rows. Both Vertical and Horizontal Bayer and
for digital binning. monochrome skip modes are supported. Refer to Table 17
Note: For monochrome sensor, when not in binning mode on page 19 for supported skip factors.
and lens shading correction is enabled (R0x3780[15]=1),
R0x30B0[7] must be set to 0. Otherwise, the image will be Table 17. SKIP MODE SETTINGS
distorted.
Vertical Horizontal
Skip Factor R0x30A6 (R0x30A8) R0x30A2 (R0x30AE)
Table 15. DIGITAL HORIZONTAL BINNING
No Skip 0x0001 0x0001
Context A R0x3040[13] R0x30A2 R0x3040[5]
2 0x0003 0x0003
Context B R0x3040[11] R0x30AE
4 0x0007 0x0007
Sum 1 3 1
8 0x000F 0x000F
Average 1 3 0
16 0x001F 0x001F

Table 16. ANALOG VERTICAL BINNING

Context A R0x3040[12] R0x30A6
Context B R0x3040[10] R0x30A8
Average (Bayer Sensor) 1 3
Sum (Monochrome Sensor)

X incrementing
Y incrementing

Figure 15. Pixel Readout (no skipping)

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X incrementing

Y incrementing
Figure 16. Pixel Readout (Row Skip 2X Bayer)

X incrementing

Y incrementing

Figure 17. Pixel Readout (Row Skip 2X Monochrome)

MIRROR color, and therefore the Bayer pattern, is preserved when

mirroring the columns.
Column Mirror Image
By setting R0x3040[14] = 1, the readout order of the
columns is reversed, as shown in Figure 18. The starting

LV

Normal readout
G0[9:0] R0[9:0] G1[9:0] R1[9:0] G2[9:0] R2[9:0]
D OUT[9:0]

Reverse readout
D OUT[9:0] G3[9:0] R2[9:0] G2[9:0] R1[9:0] G1[9:0] R0[9:0]

Figure 18. Six Pixels in Normal and Column Mirror Readout Modes

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Row Mirror Image pixel is maintained in this mode by a 1−pixel shift in the
By setting R0x3040[15] = 1, the readout order of the rows imaging array.
is reversed as shown in Figure 19. The starting Bayer color

FV

Normal readout
Row0[9:0] Row1[9:0] Row2[9:0] Row3[9:0] Row4[9:0] Row5[9:0]
DOUT[9:0]

Reverse readout
DOUT[9:0] Row6[9:0] Row5[9:0] Row4[9:0] Row3[9:0] Row2[9:0] Row1[9:0]

Figure 19. Six Rows in Normal and Row Mirror Readout Modes

COMPRESSION The size of this bubble is (Integration_Time x tROW),

AR0234 sensor can optionally compress 10−bit data to calculating the row time according to the new settings.
8-bit using DPCM (differential pulse code modulation) The Coarse_Integration_Time and
compression. This compression is a lossy compression. The Fine_Integration_Time fields may be written to without
detailed DPCM compression algorithm can be found in causing a bubble in the output rate under certain
MIPI CSI−2 specification (MIPI Alliance Specification for circumstances. Because the shutter sequence for the next
Camera Serial Interface 2 (CSI−2)). The predictor for frame often is active during the output of the current frame,
AR0234 DPCM is Predictor1. The compression is applied this would not be possible without special provisions in the
after the data pedestal has been added to the data. The DPCM hardware. Writes to these registers take effect two frames
compression can be enabled by setting R0x31D0 and after the frame they are written, which allows the integration
R0x31AC. Setting R0x31D0 to ‘1’ enables compression, time to increase without interrupting the output or producing
and the bit depth (10bit or 8bit) is selected by R0x31AC. a corrupt frame (as long as the change in integration time
does not affect the frame time).
MAINTAINING A CONSTANT FRAME RATE
Maintaining a constant frame rate while continuing to SYNCHRONIZING REGISTER WRITES TO FRAME
have the ability to adjust certain parameters is the desired BOUNDARIES
scenario. This is not always possible, however, because Changes to most register fields that affect the size or
register updates are synchronized to the read pointer, and the brightness of an image take effect on the frame after the one
shutter pointer for a frame is usually active during the during which they are written. These fields are noted as
readout of the previous frame. Therefore, any register “synchronized to frame boundaries” in the AR0234 Register
changes that could affect the row time or the set of rows Reference. By default the new digital and analog gains will
sampled causes the shutter pointer to start over at the be effective for frame n+2 when changed during the readout
beginning of the next frame. of frame n as shown in Figure 21. If R0x3786[4]=1, the new
By default, the following register fields cause a “bubble” digital and analog gains will be effective for frame n+1 when
in the output rate (that is, the vertical blank increases for one changed during the readout of frame n i.e. they will be single
frame) if they are written in video mode, even if the new buffered as shown in Figure 22. To ensure that a register
value would not change the resulting frame rate. The update takes effect on the next frame, the write operation
following list shows only a few examples of such registers; must be completed after the leading edge of FV and before
a full listing can be seen in the AR0234 Register Reference. the trailing edge of FV.
• X_Addr_Start As a special case, in trigger mode, register writes that
• X_Addr_End occur after FV but before the next trigger will take effect
immediately on the next frame, as if there had been a Restart.
• Y_Addr_Start
However, if the trigger for the next frame occurs during FV,
• Y_Addr_End register writes take effect as with video mode.
• Frame_Length_Lines Fields not identified as being frame-synchronized are
• Line_Length_Pclk updated immediately after the register write is completed.
• Coarse_Integration_Time The effect of these registers on the next frame can be difficult
• Fine_Integration_Time to predict if they affect the shutter pointer.
• Read_Mode

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write new settings

(Exp “B”)
frame n frame n+1 frame n+2

Two−wire
serial Interface idle idle
(Input)
FLASH
Exp “A” Exp “A” Exp “B” Exp “B” Exp “B”
(Output)

FRAME_VALID
Readout Exp “A” Readout Exp “A” Readout Exp “B” Readout Exp “B” Readout Exp “B”
(Output)

frame−start frame−start new image available

activates new at output
settings (Exp “B”)

Figure 20. Latency For Single Buffered Registers - Coarse Integration Time Example

write new settings

(Col_Gain “A”)
frame n frame n+1 frame n+2

Two−wire
serial Interface idle idle
(Input)

FLASH Exp “A” Exp “A” Exp “A” Exp “A” Exp “A”
(Output)

FRAME_VALID
Readout Exp “A” Readout Exp “A” Readout Exp “A” Readout Exp “A” Readout Exp “A”
(Output)

Readout frame contains

frame−start new Col_Gain setting

Figure 21. Latency For Double Buffered Registers - Column Gain Example(R0x3786[4] = 0)

Figure 22. Latency For Single−Buffered Registers (if R0x3786[4] = 1) - Column Gain Example

RESTART between issuing the Restart and the beginning of the next
To restart the AR0234 at any time during the operation of frame is a maximum of tFRAME.
the sensor, write a “1” to the Restart register (R0x301A[1]
= 1). This has two effects: first, the current frame is read out TEMPERATURE SENSOR
and the sensor enters standby. Second, any writes to The AR0234 sensor has a built−in PTAT−based
frame-synchronized registers and the shutter width registers (Proportional To Absolute Temperature) temperature
take effect immediately, and a new frame starts. The current sensor, accessible through registers, that is capable of
frame completes before the new frame is started, so the time measuring die junction temperature. The temperature sensor

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can be enabled by writing R0x30B4[0]=1 and AUTO EXPOSURE

R0x30B4[4]=1. After this, the temperature sensor output The integrated automatic exposure control (AEC) is
value can be read from R0x30B2[9:0]. responsible for ensuring that optimal settings of exposure
The value read out from the temperature sensor register is and gain are computed and updated every other frame. AEC
an ADC output value that needs to be converted downstream can be enabled or disabled by R0x3100[0]. When AEC is
to a final temperature value in degrees Celsius. Since the disabled (R0x3100[0] = 0), the sensor uses the manual
PTAT device characteristic response is quite linear in the exposure value in the coarse and fine integration time
temperature range of operation required, a simple linear registers and the manual gain value in the gain registers.
function as in Equation 35 can be used to convert the ADC When AEC is enabled (R0x3100[0]=1), the target luma
output value to the final temperature in degrees Celsius. value is set by AE_LUMA_TARGET_REG (R0x3102). For
AR0234, this target luma has a default value of 0x5000. To
Temperature + slope R0x30B2ƪ 9:0ƫ ) T0 (eq. 35)
set to 1/2 saturation, register should be set to 0x8000. The
For this conversion, a the slope equals 0.7°C / LSB, and luma target maximum auto exposure value is limited by
y−intercept ”T0” can be calculated from a single known R0x311C; the minimum auto exposure is limited by
point calibration value. This calibration value can be read R0x311E. These values are in units of line−times. The
from register R0x30C6 which corresponds to the value read minimum value for register 0x311E is 2 rows. The exposure
at 55°C. Once read, the y− intercept value can be calculated control measures current scene luminosity by accumulating
and used in the above equation. a histogram of Gr pixel values while reading out a frame. It
Final equation: then compares the current luminosity to the desired output
(eq. 36) luminosity. Finally, the appropriate adjustments are made to
Temperature + 0.7 (R0x30B2[9:0] * R0x30C6[9:0]) ) 55 the exposure time and gain.
Example: Auto Exposure Implementation
R0x30C6[9:0]=0x1BD=445 The AR0234 Auto Exposure control is implemented as
R0x30B2[9:0]=0x1A2=418 three main blocks − AE Stats Calculation, AE Target
Temperature = 0.7x(418−445)+55=36.1 Selection, and an Exposure Control System. See Figure 23
For more information on the temperature sensor registers, for details.
refer to the AR0234 Register Reference.

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10-bit image (Gr pixels)

Sensor Digital Block

AE Target
AE STATS AE Statistics
Selection
Auto_AG_enable

Man_AG
TargetRatio
AG ae_enable
auto_ag_en
Current dark level auto_dg_en
Auto_DG_enable
Exposure Control min_ana_gain
Current exposure time
Man_DG System
ae_roi_x_start_offset
DG
ae_roi_x_size
ae_roi_y_start_offset
ae_roi_y_size
Auto_DG_gain

AE USER INTERFACE REGISTERS (R/W)

Auto_AG_gain
ae_mean_l

Integration time ae_ag_exposure_hi

ae_ag_exposure_lo

ae_luma_target_reg

ae_min_ev_step_reg
ae_max_ev_step_reg

ae_damp_offset_reg
ae_damp_gain_reg
ae_damp_max_reg

ae_max_exposure_reg
ae_min_exposure_reg
AE status monitor/debug Registers (R only)

AR0234 Output Image

ae_mean_l
ae_dark_cur_thresh_reg
AR0234 Output Image ae_dig_gain
ae_ana_gain

ae_coarse_integration_time
Footer:
Histogram
AE status monitoring \ debug registers

Figure 23. AE Block Diagram

AE Embedded Statistics and Data no ROI is specified, statistics are gathered from the full
The AE Stats Calculation block (Figure 24) takes the user output frame. From this histogram, all relevant auto
specified Region of Interest (ROI) and creates a histogram exposure statistics are generated:
arranged into bins listed in Table 18 based on Gr pixels. If

AE Stats AE Histogram

AE Histogram (for ROI)

10−bit image
Signal levels 0 to 2 10 mean mean
Gr pixels

ROI selection

Figure 24. AE Stats Calculation Block

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Table 18. AR0234 HISTOGRAM BINS

Pixel Value Bin Number Note Number of Bins

0−3 0 0 64
1 16

2 32

3 48

4−63 4 64 k = 0 to 59 120
5 66
4+k 64 + 2k
63 182

64−1023 64−79 184 k = 0 to 59 60

80−95 185

(64 + 16 x k) to (79 + 16 x k) 184 + k

1008−1023 243

Table 19. AR0234 HISTOGRAM BINS FOR TEST PATTERN

Pixel Value Bin Number Note Number of Bins

0−3 0 0 64

0−3 1 16

0−3 2 32

0−3 3 48

4−63 4 64 k = 0 to 59 120

4−63 5 66

4−63 4+k 64 + 2k

4−63 63 182

64−1023 64−79 184 k = 0 to 59 60

64−1023 80−95 185

64−1023 (64 + 16 x k) to (79 + 16 x k) 184 + k

64−1023 1008−1022 243

64−1023 1023 241

1. AE Histogram: Arranged into bins as specified in GRID FEATURE

Table 18 above. If a ROI is specified, the One new feature, a grid structure with 5x5 max size in
histogram is populated only with Gr pixels which region of interest (ROI) is added in AR0234. ROI region of
lie in the ROI. image is divided into 25 sub−regions which is basically 5x5
2. Mean: Mean code value of AE Histogram rectangle regions. AR0234 has the options to create the
The generation of statistics for use by off−chip AE parameters as well as histogram with only selected sub
algorithms must be enabled by setting register R0x3064[7] regions in the grid.
= 1. Embedded statistics will not be output if this register is
not set. Embedded data may also be enabled by setting IMPLEMENTATION
register R0x3064[8] = 1, but is not necessary for statistics The histogram is replaced with a new one. The current
generation. To enable on−chip auto exposure, however, both region of interest (ROI) is divided in a 5x5 grid. The division
embedded stats and data must be enabled. of the grid will be based on the different offset programmed

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by the below registers. Register selection is provided to x0_start_offset. Same way, any of the yy_start_offset
include each grid region in the histogram or not. can’t be less than y0_start_offset. Any unused
Following registers are added in for stats to define the new xx_start_offset and yy_start_offset should be set equal to
grid structure. Registers address and other details are given x_size and y_size respectively.
in below table. All the offset values are absolute from the
image location (0,0), top left corner. Any of the
xx_start_offset cannot be less than

Table 20. GRID STATS REGISTERS

SN Register Name Bit width Address Valid Values
ae_roi_x_start_off 11 0x3140
set

1 ae_x1_start_offset 11 0x3240 ae_roi_x_start_offset< ae_x1_start_offset <= min(ae_x2_start_offset,

x_size)

2 ae_x2_start_offset 11 0x3242 ae_x1_start_offset =< ae_x2_start_offset <= min(ae_x3_start_offset,

x_size)

3 ae_x3_start_offset 11 0x3244 ae_x2_start_offset =< ae_x3_start_offset <= min(ae_x4_start_offset,

x_size)

4 ae_x4_start_offset 11 0x3246 ae_x3_start_offset =< ae_x4_start_offset <= x_size

ae_roi_x_size 11 0x3144
ae_roi_y_size 11 0x3146
ae_roi_y_start_off 10 0x3142
set

5 ae_y1_start_offset 10 0x3248 ae_roi_y_start_offset < ae_y1_start_offset <= min(ae_y2_start_offset,

y_size)

6 ae_y2_start_offset 10 0x324A ae_y1_start_offset =< ae_y2_start_offset <= min(ae_y3_start_offset,

y_size)

7 ae_y3_start_offset 10 0x324C ae_y2_start_offset =< ae_y3_start_offset <= min(ae_y4_start_offset

y_size)

8 ae_y4_start_offset 10 0x324E ae_y3_start_offset =< ae_y4_start_offset <= y_size

9 Grid_sel_lo 25 0x3250 Bit[i] corresponds to grid numbered i. i is from 0 to 15.
Grid_sel_hi 0x3252 Bit[i] corresponds to grid numbered i + 16. i equals 0 to 8.

Grid numbers within the ROI are defined as row wise grid_sel[0] correspond to grid number 0 in the below
increment number as mentioned in below diagram. Bit diagram and so on.

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ae_roi_x_start_offset ae_x2_start_offset
ae_x4_start_offset

Image location ae_x1_start_offset

(0,0) ae_x3_start_offset

ae_roi_y_start_offset

0 1 2 3 4

ae_y1_start_offset

5 6 7 8 9
ae_roi_y_size

ae_y2_start_offset

10 11 12 13 14

ae_y3_start_offset

15 16 17 18 19

ae_y4_start_offset

20 21 22 23 24

ae_roi_x_size

Statistics Grid Structure bottom−right corner

image pixel
Figure 25. Stats Grid Structure

GRID NUMBER REDUCTION number are invalid and does not contain any pixel. Figure 26
If there is need for other grid dimension which is smaller shows the grid location after removing one grid in x
than 5x5 grid dimension, it can be achieved by setting direction and y direction each. Here x4_offset is set to x_size
unused offset register to same as end of ROI location. The and y4_offset is set as y_size. We can define more than one
end of ROI location is the point (x_size, y_size). Hence offset in x and y direction same as end of ROI to reduce the
unused xn_start offset will be set as x_size and unused grid size further.
yn_start_offset will be set to y_size. The unused grid

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ae_roi_x_start_offset ae_x2_start_offset ae_x4_start_offset

Image location ae_x1_start_offset ae_x3_start_offset

(0,0)

ae_roi_y_start_offset

0 1 2 3
ae_y1_start_offset
ae_roi_y_size

5 6 7 8
ae_y2_start_offset

10 11 12 13
ae_y3_start_offset

15 16 17 18
ae_y4_start_offset

ae_roi_x_size
Statistics Grid Structure

Figure 26. Grid Numbering with Reduced Size bottom-right corner

image pixel

AE Target Selection Exposure Control System

The Exposure Target Selection block determines a ratio The Exposure Control System outputs the new integration
based on the mean value of the generated histogram of the time along with a damping factor to prevent too rapid of a
current frame, and the target mean value as specified by the response. If enabled, analog and digital gains will be
user (R0x3102). This ratio allows the Control System to selected as well. The Control System will also monitor the
determine how much and in what direction to adjust the dark current. If the Exposure Target Selection block
exposure relative to the current exposure value. indicates that the exposure should be increased, but the dark
The mean target ratio (TargetRatio) is the exposure current exceeds a user specified threshold, the Control
change, expressed as a ratio, to move the current image mean System will maintain the current integration time. The
(CurrentMean) to a user−specified mean target automatic digital and analog gains and exposure limits
(TargetMean). See the “Exposure Control System” section enclosed by the dashed line in Figure 27 is illustrated in
and Figure 27 for more information. more detail in Figure 29 on page 32 and described in
“Controlling Auto Exposure” on page 43.

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ae_luma_target (0x3102) TargetRatio

ae_mean_l (0x3152) (TargetMean/CurrentMean) Current dark level Current exposure time

EVNewExp =log2(TargetRatio)

ae_damp_offset_reg
(0x310C) RecursiveDamp =
ae_damp_gain_reg dampOffset + abs(EVNewExp)×dampGain
(0x310E)

ae_damp_max_reg Limit to less than

(0x3110) RecursiveDamp_Max

EVNewExp_damped =
RecursiveDamp×EVNewExp

ae_min_ev_step_reg If abs(EV Exp damped) ≥ Max EV step, limit abs

(0x3108) (EV Exp damped) to Max EV step.
See Figure 29
ae_max_ev_step_reg If abs(EV Exp damped)
(0x310A) < Min EV step, set EV Exp damped to 0

NewExpRatio>1
and Dark Current > No
NewExpRatio = 2 EVNewExp_damped DarkCurrentThresh
ae_dark_cur_thresh_reg
(0x3124)

Yes

New integration time

= current integration
time
(no change in
exposure)
auto_ag_en (0x3100[1]) ae_ana_gain
(0x312A[10:0])
ae_ag_exposure_hi (0x3166) Digital Gain
Analog Gain
ae_ag_exposure_lo (0x3168) Exposure Time
Control ae_dig_gain
auto_dg_en (0x3100[4])
(0x312A[11:13])

ae_min_exposure_reg (0x311E)
Limit new integration time to between Max_int_time and Min_int_time
ae_max_exposure_reg (0x311C)

New integration time

ae_coarse_integration_time
(0x3164)

Figure 27. Exposure Control System

Values found here are described in Table 21 on page 30.

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Table 21. EXPOSURE CONTROL VARIABLES Table 22. AE ENABLE REGISTERS

Internal Value Description Register Name Function

EVNewExp Target ratio translated into EV units (stops). 0x3100[0] ae_enable 0: On−chip AE disabled
Can be positive or negative. In EV units, >0 1: On−chip AE enabled
means exposure is increasing, <0 means
exposure is decreasing. 0x3100[1] auto_ag_en 0: AE will not control analog
gain
RecursiveDamp Damping factor. Should be >0 and <1 for de- 1: AE will control analog gain
sirable AE operation. If less than
0, AE will step further from the target; if 0x3100[6:5] min_ana_gain Minimum analog gain to be
greater than 1, AE will overstep the target. used by AE
00: 1x (default)
EVNew- New exposure step in EV units. Can be posi- 01: 2x
Exp_damped tive or negative. 10: 4x
11: 8x
NewExpRatio New exposure step as ratio. Should be posi-
tive. As ratio, >1 means exposure is increas- Controlling Auto Exposure
ing, <1 means exposure is decreasing.
The histogram is generated and statistics calculated based
NewExp New exposure expressed as rows of integra- on the Gr pixels within a user specified region of interest.
tion or possibly msec (depends on rest of The ROI is specified by four programmable register values
system).
− ae_roi_x_start_offset, ae_roi_y_start_offset,
ae_roi_x_size and ae_roi_y_size. The ae_roi_x_start_offset
Auto Exposure Control
and ae_roi_y_start_offset values define the starting
Enabling Auto Exposure coordinate of the ROI with respect to the image window that
Several registers are used to enable various features of the is output and the ae_roi_x_size and ae_roi_y_size values
automatic exposure control. The auto exposure block is define the dimensions of the ROI. Each value must be an
enabled or disabled by register R0x3100[0]. By default, the even number. If the requested ROI extends ’beyond’ the
AEC will only modify the coarse integration time to reach image window then it will be restricted in size such that the
the target exposure. If enabled, analog and digital gains may final pixel of the ROI will be the final pixel of the image
be adjusted as well. Analog gain adjustment is enabled by window, as illustrated in Figure 28.
setting auto_ag_en (R0x3100[1] = 1) A minimum column
gain (1x, 2x, 4x, 8x), min_ana_gain, may be defined in
register R0x3100[6:5]. A summary of AEC enable registers
is listed in Table 22.

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Figure 28. Selecting the ROI

The target luma value may be set in the To extend the exposure range, the AE logic can also
ae_luma_target_reg register. The AE Target Selection block automatically adjust analog gain and digital gain. The
will use this value to determine the target ratio provided to controls for enabling automatic analog and digital gain
the Exposure Control System as illustrated in Figure 27 on selection may be found in Table 22 on page 30. The control
page 29. The exposure range can be limited by setting values flow chart is shown in Figure 29 and is an expanded view of
for ae_max_exposure_reg and ae_min_exposure_reg. The the portion of Figure 27 on page 29 that is enclosed by the
integration time fed back to the Sensor Digital Block (see dashed line.
Figure 23) will not fall outside of this specified range.

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New_Exposure_Time =
Current_Exposure_Time*
NewExpRatio

Yes
No
NewExpRatio>1

Yes Current_DG
=1

No

DG=
Current_DG x
NewExpRatio

No
DG<1

DG=1

No AG>
Min_AG

Yes AG_Hi_Thresh =ae_ag_exposuure_hi

(0x3166)
No New Exposure Time
≥AG_Hi_Thresh
AG_Lo_Thresh=ae_ag_exposure_lo New Exposure Time No
(0x3168) ≤AG_Lo_Thresh Yes

Yes
AG=3
Yes
or
New_Exposure_Time = Auto AG disabled
AG_gain_factor=2 New_Exposure_Time x
AG_gain_factor
No
AG=AG−1
New_Exposure_Time =
New_Exposure_Time / AG_gain_factor=0.5
AG_gain_factor
AG=AG+1

No Current_exposure_time
=Max_int_time

Yes

DG=
New_exposure_ratio x
Current_DG

Output New_Exposure_Time, AG, DG

END

Figure 29. Digital Gain, Analog Gain, and Exposure Time Control

If auto_ag_en is set, it is recommended to limit the analog analog gain is limited to 16x then AEC might try to increase
gain value not greater than 16x. Also, the read out value of the analog gain greater then 16x (ae_ana_gain can go to 32x,
the current analog gain, ae_ana_gain (R0x312A[13:11]), 64x and 128x) also in order to achieve the Target Mean but
value might still go as high as 128x but actually would be internally it would be 16x only even though ae_ana_gain
limited as per the settings internally. For example, if the reaches to 32x, 64x or 128x.

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colamp bypass ADC gain Colamp gain

Analog Gain Limit R0x3ED4[15:8] R0x3ED2[15:8] R0x3ED0[7:0] R0x3EEE[15:8] R0x3EEE[7:0]

1x 0xFF 0x00 0x00 DON’T CARE DON’T CARE
2x 0xFF 0x55 0x54 DON’T CARE DON’T CARE
4x 0x03 0x00 0x04 0xA4 0xAA
8x 0x03 0x55 0x44 0xA4 0xAA
16x 0x03 0x55 0x44 0xA4 0xFF
10. If auto_ag_en is set, coarse analog_gain (R0x3060[6:4]) will be ignored, the total analog gain is the multiplication of analog coarse gain in
AEC and the fine analog gain (R0x3060[3:0]).
11. If auto_ag_en is not set, the total analog is the same as the analog_gain (R0x3060[6:0]).
12. If auto_dg_en is set, the global gain (R0x305E[10:0]) will be ignored.
13. If auto_dg_en is not set, the digital gain is the same as the global gain (R0x305E[10:0]).

By setting a value for ae_ag_exposure_hi, the analog gain the incremental change from frame to frame. The selected
will not be increased until the integration time set by this new exposure value will be clipped to the minimum EV
register is reached. Similarly, the analog gain will not be step if it is less than the value specified in R0x3108.
decreased unless the integration time is reduced below the Because the minimum step size in EV units is typically a
value set in ae_ag_exposure_lo. To avoid oscillation, the small number less than one, it should be scaled by 256
ae_ag_exposure_lo setting should be lower than the before setting the register value.
ae_ag_exposure_hi setting. Refer to Table 23 on page 34 for Changes in exposure are smoothed based on damping
auto exposure control registers. parameters. A maximum damping value may be specified
The integration time and analog gain selected by the in R0x3110. Additional damping controls include
exposure control system may be found in the ae_damp_gain_reg and ae_damp_offset_reg. These can be
ae_coarse_integration_time (R0x3164) and thought of as a coarse and fine damping control,
ae_ana_gain(R0x312A[13:11]) registers, respectively. The respectively.
minimum analog gain to be selected may be set in the At high temperature, the sensor may have high dark
min_ana_gain (R0x3100[6:5]) register, and can be 1x, 2x, current which will increase with longer exposures. To
4x, or 8x or 16x. If auto_dg_en (R0x3100[4]) is set, the avoid increasing the exposure when there is excessive
digital gain selected by the exposure control system can dark current, AE has a dark current check. The sensor
be read from register ae_dig_gain (R0x312A[10:0]). The supplies the current dark current level to AE and if the
digital gain can vary from 1 to 15.9922. The minimum dark current is greater than the user−specified (R0x3124)
step is 1/128. darkCurrentThresh, AE does not increase exposure.
The step size of the AE control may be configured. If (NewExpRatio > 1) & (DarkCurrent >
Both a minimum and maximum step size may be set in DarkCurrentThresh) NewExpRatio = 1; //Do not increase
units of EV (exposure value) steps in registers 0x3108 and exposure
0x310A, respectively. The step size represents the
End
minimum or maximum value that the AE Target Selection
will use for the next exposure value. It does not represent

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Table 23. AUTO EXPOSURE CONTROL REGISTERS

Register Name Function

0x3140 ae_roi_x_start_offset Number of pixels into each row before the ROI starts

0x3142 ae_roi_y_start_offset Number of rows into each frame before the ROI starts

0x3144 ae_roi_x_size Number of columns in the ROI

0x3146 ae_roi_y_size Number of rows in the ROI

0x3102 ae_luma_target_reg Average Gr target value to be reached by the auto exposure multiplied by 16

0x3108 ae_min_ev_step_reg Minimum exposure value step size. Since min_ev_step sizes are small (typically
less than 1), they are multiplied by 256 and then the value is written to this regis-
ter.

0x310A ae_max_ev_step_reg Maximum exposure value step size. Since this value is always greater than 1
there is no need to multiply by 256 as in the case of min_EV_stepsize.

0x310C ae_damp_offset_reg Adjusts step size and settling speed.

0x310E ae_damp_gain_reg Adjusts step size and settling speed.

0x3110 ae_damp_max_reg Max value allowed for damping (multiplied by 256 since internal value is typically
<1). For most applications, the value of damping should be <1, otherwise AE will
overshoot the target. For applications with fast settling required, it may be desir-
able to allow damping >1. Default value: 0.875 * 256 = 0x00E0

0x311C ae_max_exposure_reg Maximum integration (exposure) time in rows to be used by AE.

0x311E ae_min_exposure_reg Minimum integration (exposure) time in rows to be used by AE.

0x3166 ae_ag_exposure_hi At this integration time, the analog gain is increased (when AE is enabled to
control analog gain).

0x3168 ae_ag_exposure_lo At this integration time, the analog gain is reduced (when AE is enabled to con-
trol analog gain).

0x3124 ae_dark_cur_thresh_reg The dark current level that stops AE from increasing integration time. Note that
increased integration time would increase dark current as well and signal level
(SNR) would drop because photo diode well capacity is limited.

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AE FRAME SYNCHRONIZATION module will perform its calculations during the vertical
A delay is incurred between the time when a frame with blanking time and the new exposure value will be seen by the
the newly updated AE value applied is seen by the AE sensor core logic after the next frame has started. Therefore
module and when it reaches the sensor core logic (which sets the result is that the third frame after the current frame will
the exposure times for the sensor). This delay is associated reflect the new exposure time. Figure 30 illustrates how the
with the Delay Buffers and Sensor Data Path delays. The AE exposure changes every two frames.

T0P T1 T2
Exposure changes every 2 frames

N−n
rows T0 T0 T1 T1 T2

n rows T0(Stats) T1(Stats) T2(Stats)

VBLANK Set T1 Set T2 Set T3

rows

N = total number of active pixel

rows

Output Output Output Output

n = number of rows required to
compute AE stats Frame Frame Frame Frame
Exp = T0 Exp= T1 Exp= T1 Exp= T2
VBLANK = vertical blank rows

Figure 30. AE Frame Synchronization

EMBEDDED DATA AND STATISTICS WITHIN output all zeros. The second line contains statistics based on
IMAGE the histogram for the current frame. The embedded data is
All the statistics data (including histogram data) is output as shown in Figure 32. The only relevant statistic for
embedded in the two rows immediately following the AR0234 auto exposure is the mean. If the on−chip auto
image. The embedded statistics are output as shown in expo− sure is not used, it is recommended that auto exposure
Figure 33. The first line contains histogram data. Only algorithms be developed based on the histogram data found
histogram data for bins 0 to 63 are relevant − higher bins will in line 1.

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RegisterData

Image HBlank

Status&StatisticsData

VBlank

Figure 31. Frame Format with Embedded Data Lines Enabled

Embedded Data • R0x3116

The embedded data contains the configuration of the • R0x3118
image being displayed. This includes all register settings
used to capture the current frame. The registers embedded
• R0x311A
in these rows are as follows: • R0x31F4
Line 1: Registers R0x3000 to R0x312F • R0x31F6
Line 2: Registers R0x3136 to R0x31BF, R0x31D0 to • R0x31F8
R0x31FF All non−defined registers listed below will have • R0x31F8
a value of 0. • R0x31FA
• R0x3020 In parallel mode, since the pixel word depth is
• R0x3032 10−bits/pixel, the sensor 16−bit register data will be
transferred over 2 pixels where the register data will be
• R0x306C broken up into 8 MSB and 8 LSB. The alignment of the 8−bit
• R0x307E data will be on the 8 MSB bits of the 10−bit pixel word. For
• R0x3080 example, of a register value of 0x1234 is to be transmitted,
• R0x309A it will be transmitted over 2, 10−bit pixels as follows: 0x120,
• R0x3164 0x340.
• R0x30D4 The first pixel of each line in the embedded data is a tag
value of 0x0A0. This signifies that all subsequent data is
• R0x30D6 10−bit data aligned to the MSB of the 10−bit pixel.
• R0x30D8 The figure below summarizes how the embedded data
• R0x3112 transmission looks like. It should be noted that data, as
• R0x3114 shown in Figure 32, is aligned to the MSB of each word:

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data_format_ {register_ {register_ {register_

8’hAA 8’hA5 8’h5A 8’h5A
code =8’h0A address_MSB} address_LSB} value_MSB}
Data line 1
{register_
8’h5A
value_LSB}

data_format_ {register_ {register_ {register_

8’hAA 8’hA5 8’h5A 8’h5A
code =8’h0A address_MSB} address_LSB} value_MSB}

Data line 2
{register_
8’h5A
value_LSB}

Figure 32. Format of Embedded Data Output within a Frame

The data embedded in these rows are as follows: Embedded Statistics

• 0x0A0 − identifier The embedded statistics contain frame identifiers and
• 0xAA0 histogram information of the image in the frame. This can be
used by downstream auto−exposure algorithm blocks to
• Register Address MSB of the first register make decisions about exposure adjustment. This histogram
• 0xA50 is divided into bins as specified in Table 18 on page 25. The
• Register Address LSB of the first register statistics only evaluates ROI region Gr pixels (not entire
• 0x5A0 frame). The first pixel of each line in the embedded statistics
• Register Value MSB of the first register addressed is a tag value of 0x0B0. This signifies that all subsequent
statistics data is 10−bit data aligned to the MSB of the 10−bit
• 0x5A0
pixel.
• Register Value LSB of the first register addressed The figure below summarizes how the embedded
• 0x5A0 statistics transmission looks like. It should be noted that
• Register Value MSB of the register at first address + 2 data, as shown in Figure 33, is aligned to the msb of each
• 0x5A0 word:
• Register Value LSB of the register at first address + 2
• 0x5A0
• etc.

data_format_ #words = {2’b00, frame {2’b00, frame {2’b00, frame {2’b00, frame histogram histogram
code =8’h2c 10’h1EC _count MSB} _count LSB} _ID MSB} _ID LSB} bin0 [19:10] bin0 [9:0]
stats line 1
histogram histogram histogram histogram
0x1C 0x1C
bin1 [19:10] bin1 [9:0] bin243 [19:10] bin243 [9:0]

data_format_ #words = hist_begin hist_begin hist_end hist_end

mean [ 19:10] mean [9:0]
code =8’h2c 10’hC [19:10] [9:10] [19:10] [9:10]

stats line 2
lowEndMean lowEndMean perc_lowEnd perc_lowEnd norm_abs_dev lnorm_abs_dev 0x1C
[19:10] [9:0] [19:10] [9:0] [19:10] [9:0]

Figure 33. Format of Embedded Statistics Output within a Frame

The statistics embedded in these rows are as follows: • Histogram Begin (ae_hist_begin)
Line 1: • Histogram End (ae_hist_end)
• 0x0B0 − identifier • Low End Histogram Mean
• Register 0x303A − frame_count • Percentage of Pixels Below Low End Mean
• Register 0x31D2 − frame ID (ae_perc_low_end) Normal Absolute Deviation
• Histogram data − histogram bins 0−243 Below are the definitions of the embedded statistics.
Line 2: • ae_mean
• 0x0B0 (identifier) The mean data value of the Gr pixels multiplied by 16 is
• Mean (ae_mean) given by:

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true mean + ǒ 16 S G (i)Ǔńn

n

i+1
r (eq. 37)
241 contains 7 pixels, bin 242 contains 9 pixels, and bin
243 contains 4 pixels. ae_hist_end_perc =
0.988(98.8%), then ae_hist_end will equal 3071 − the
where n is the number of Gr pixels in the ROI. Such a value last code value of the bin where pixel 988 falls (bin 242
is calculated by accumu− lating the actual pixel values over in this case).
the course of the frame/ROI. • ae_hist_end_mean
• ae_hist_begin A user programmable parameter, ae_hist_div, defines
ae_hist_begin is the code value corresponding to the the low end of the histogram for the purposes of the AE
histogram bin (starting at bin 0 and moving towards bin algorithm. ae_hist_div is a histogram bin identifier and
243) in, or below which ae_hist_begin_perc (where all bins from bin 0 to bin ae_hist_end are considered
ae_hist_begin_perc is a user programmable parameter) the ’low end’.
of pixels occur. So, as an example, consider a 1000 The ae_hist_end_mean is the equivalent of the mean
pixel sample whereif ae_hist_begin_perc = 0.01 (1%), value described earlier for the low end subset of the
then ae_hist_begin will equal 8 − the first code value of pixels.
the third bin where pixel 10 (1% of 1000) falls. • ae_perc_low_end
The user specifies ae_hist_begin_perc as a 16−bit value The ae_perc_low_end statistic indicates the proportion
of the form 0.xxxx...xxxx − so if ae_hist_begin_perc = of pixels that fall in the ’low end’ portion of the
16’b0010_0000_0000_0000, ae_hist_begin is histogram and is given by
considered to be the code value below or equal to ae_hist_div
which 12.5% of the pixels occur. h(i) S
• ae_hist_end i+1
ae_perc_low_end + (eq. 38)
Complementary to ae_hist_begin, ae_hist_end is the 243
code value corresponding to the histogram bin (starting
at bin 0 and moving towards bin 243) in, or below i+1
h(i) S
which ae_hist_end_perc (where ae_hist_end_perc is a
where h(i) represents the number of pixels in bin i.
user programmable parameter) of pix− els occur. So, as
an example, consider a 1000 pixel sample where bin
• ae_norm_abs_dev
The three−stage computation for norm_abs_dev is summarized below. First, pixel values below ae_hist_begin and
above ae_hist_end are clipped:

fclipped(i) + NJ 0
f(i)−ae_hist_begin
ae_hist_end−ae_hist_begin
if ǒf(i) t ae_hist_beginǓ
if ae_hist_begin v (f(i) v ae_hist_end)
if(f(i) u ae_hist_end)
(eq. 39)

where f(i) is the center code value for bin i.

Next, the absolute deviation can be calculated:
243
S ǒh(i)
i+1
|fclipped(i) * (1ń2)(ae_hist_end * ae_hist_begin)|Ǔ

abs_dev + (eq. 40)

243
S
i+1

Before finally being normalized:

norm_width + NJ ae_norm_width_min if ae_hist_end * ǒae_hist_begin t ae_hist_beginǓ

ae_hist_end * ǒae_hist_begin if ae_hist_end * ǒae_hist_begin w ae_norm_width_minǓǓ (eq. 41)

where ae_ norm_width_min is a user−specified minimum normalizing width, used when the histogram is very narrow.
abs_dev
ae_norm_abs_dev + (eq. 42)
norm_width
The result is the deviation from the center of the normalized histogram - a value < 1.

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GAIN (analog) gain can be set to 1x, 2x, 4x, 8x or 16x. This can be
The AR0234 has three gain options, digital, coarse and set in R0x3060[6:4](Context A) or R0x3060[14:12]
fine column (analog). (Context B). An additional 4−bit fine gain adjustment is
available. This can be set in R0x3060[3:0](Context A) or
Digital Gain
R0x3060[11:8] (Context B).
Digital gain can be controlled globally by R0x305E
(Context A) or R0x30C4 (Context B). There are also Let R0x3060[6:4] = s
registers that allow individual control over each Bayer color Let R0x3060[3:0] = t
channel: coarse gain = 2s
1. When s = 0 or 2
1
GreenR R0x3056 fine gain + (eq. 43)
t
1*
R0x305C 32
GreenB
2. When s = 1 or 3
Red R0x305A
1
R0x3058 fine gain +
Blue
INT ǒ2t Ǔ (eq. 44)
The format for digital gain setting is xxxx.yyyyyyy where 1* 16
0b00010000000 represents a 1x gain setting and 3. When s = 4
0b00011000000 represents a 1.5x gain setting. The step size 1
for yyyyyyy is 0.0078125 while the step size for xxxx is 1. fine gain +
INT ǒ4t Ǔ (eq. 45)
Therefore to set a gain of 2.09375 one would set digital gain 1* 8
to 0b00100001100. The maximum digital gain is 15.9922x.
Total analog gain + coarse_gain * fine_gain (eq. 46)
DigitalGain = Bit[10:7] + (Bit[6:0]/128)

Column Gain Recommended Gain Settings

The AR0234 has a column parallel architecture and Table 24 below show the recommended gain settings for the
therefore has an analog gain stage per column. The coarse AR0234.

Table 24. RECOMMENDED GAIN TABLE

R0x30BA[2:0]
Fine
Coarse R0x3060[6:4] R0x3060 Total Gain 90 MHz 45 MHz 22.5MHz
0 0x0000 1.00000 2 6 6
0x0001 1.03226 2 6 6
0x0002 1.06667 2 6 6
0x0003 1.10345 2 6 6
0x0004 1.14286 2 6 6
0x0005 1.18519 2 6 6
0x0006 1.23077 2 6 6
0x0007 1.28000 2 6 6
0x0008 1.33333 2 6 6
0x0009 1.39130 2 6 6
0x000A 1.45455 2 6 6
0x000B 1.52381 2 6 6
0x000C 1.60000 2 6 6
0x000D 1.68421 2 6 6
0x000E 1.77778 2 6 6
0x000F 1.88235 2 6 6

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Table 24. RECOMMENDED GAIN TABLE

R0x30BA[2:0]
Fine
Coarse R0x3060[6:4] R0x3060 Total Gain 90 MHz 45 MHz 22.5MHz
1 0x0010 2.00000 2 6 6
0x0012 2.13333 2 6 6
0x0014 2.28572 2 6 6
0x0016 2.46154 2 6 6
0x0018 2.66667 2 6 6
0x001A 2.90909 2 6 6
0x001C 3.20000 2 6 6
0x001E 3.55556 2 6 6
2 0x0020 4.00000 1 6 6
0x0021 4.12903 1 6 6
0x0022 4.26667 1 6 6
0x0023 4.41379 1 6 6
0x0024 4.57144 1 6 6
0x0025 4.74074 1 6 6
0x0026 4.92308 1 6 6
0x0027 5.12000 1 6 6
0x0028 5.33333 1 6 6
0x0029 5.56522 1 6 6
0x002A 5.81818 1 6 6
0x002B 6.09524 1 6 6
0x002C 6.40000 1 6 6
0x002D 6.73684 1 6 6
0x002E 7.11111 1 6 6
0x002F 7.52941 1 6 6
3 0x0030 8.00000 1 6 6
0x0032 8.53333 1 6 6
0x0034 9.14286 1 6 6
0x0036 9.84616 1 0 6
0x0038 10.66667 1 0 6
0x003A 11.63636 0 0 6
0x003C 12.90000 0 0 6
0x003E 14.22222 0 0 6
4 0x0040 16.00000 0 0 6

RECOMMENDED MINIMUM GAIN and used to compensate for its effect on black level in the
Due to different pixel full well saturation, the visible array.
recommended minimum overall gain is 1.684 for
eliminating artifacts. Enabling Black Level Correction
Black level correction is enabled by default, but may be
BLACK LEVEL CORRECTION manually enabled or disabled by writing to the
The AR0234 sensor has built in controls for black level delta_dk_sub_en (R0x3180[15]) register. Gradient removal
(delta dark) correction and calibration. By utilizing optically may be enabled by setting delta_dk_gradient_removal
dark rows, the magnitude of dark current can be measured (R0x3180[10]).

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Controlling Black Level Correction oscillations. Setting delta_dk_recalc (R0x3180[13]) = 0x1

The more rows, the more accurate the dark current allows manual retriggering of the dark current calculations.
compensation. The dark current is automatically This allows periodic recalculations from a watchdog timer
recalculated on changes in integration time. It may be forced on an ISP or FPGA. It also enables recalculation based on
to recalculate every frame or by asserting a control register. readings from the on−chip temperature sensor. The
To force dark current calculations every frame, set delta_dk_recalc register will reset to zero after one
delta_dk_every_frame (R0x3180[14]) = 0x1. Recalculating calculation is performed.
every frame is not recommended as it may result in

Table 25. BLACK LEVEL CONTROL REGISTERS

Register/Field Name Address Default Value Description
delta_dk_control 0x3180[15] 0x0001 delta_dk_sub_en
0: Disables delta dark correction.
1: Enables delta dark correction.
0x3180[14] 0x0000 delta_dk_every_frame
0: Dark current is not recalculated every frame.
1: Dark current is recalculated every frame.
0x3180[13] 0x0000 delta_dark_recalc
0: Manual delta dark recalculation is disabled.
1: Force recalculation of dark current.

AR0234 DEFECT CORRECTION surrounding nearest horizontal 4 pixels of the same color
plane to do correction. See the following figure. It is a mean
Tagged Defect Pixel Correction (static correction) weighting based defect correction. For the monochrome
This defect correction is only for correcting the tagged sensor will also be treated as a color sensor.
defect pixels detected during sensor production. It uses the

L4 L3 L2 L1 Pc R1 R2 R3 R4
Pc: current defect pixel
L4, L2, R2, R4: pixels of same color channel to be used for correction
L3, L1, R1, R3: pixels of different color channels won`t be used for correction
.
Defect pixels are stored in OTPM. The following table
illustrates how to enable static defect correction and option
of tagging defective pixels with a value of 0.

Tag
Correction Correction Mode Rx31E0[1] Rx31E0[0]
On Correct Tagged Pixels 1 1
On Replace Tagged Pixels with value of 0 0 1

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Dynamic 1−D Defect Pixel Correction determine if pixel correction is required. The final corrected
This algorithm will be applied to all the pixels in the pixel value will be based on the 4 nearest same color pixels.
image. The correction is based on the difference between the The mono sensor will be treated as the same as a color sensor.
current pixel and the surrounding horizontal 8 pixels to

L4 L3 L2 L1 Pc R1 R2 R3 R4
Pc : current defect pixel
L4, L2, R2, R4: pixels of same color channel to be used for correction
L3, L1, R1, R3: pixels of different color channels to be used for
how to do the correction .
The following table shows how to enable dynamic pixel
defect correction.

Dynamic Pixel Correction Rx31E0[3] Rx31E0[2] Rx31E0[1] Rx31E0[0]

On 1 1 1 1
Off 0 0 1 1

Set the following 1DDC parameters: enabled. Register R0x3044[5:4] should be changed back to
R0x3F4C=0x003F default value, 1, when disabled.
R0x3F4E=0x0018
R0x3F50=0x17DF Table 26. TEST PATTERN MODES
TEST PATTERNS Test_Pattern_Mode Test Pattern Output
The AR0234 has the capability of injecting a number of 0 No test pattern (normal operation)
test patterns into the top of the datapath to debug the digital
1 Solid color test pattern
logic. With one of the test patterns activated, any of the
datapath functions can be enabled to exercise it in a 2 100% color bar test pattern
deterministic fashion. Test patterns are selected by 3 Fade−to−grey color bar test pattern
test_pattern_mode register (R0x3070). Only one of the test 256 Walking 1s test pattern (10−bit)
patterns can be enabled at a given point in time by setting the
test_pattern_mode register according to Table 26. When test Color Field
patterns are enabled the active area will receive the value When the color field mode is selected, the value for each
specified by the selected test pattern and the dark pixels will pixel is determined by its color. Green pixels will receive the
receive the value in test_pattern_green (R0x3074 and value in test_pattern_green, red pixels will receive the value
R0x3078) for green pixels, test_pattern_blue (R0x3076) for in test_pattern_red, and blue pixels will receive the value in
blue pixels, and test_pattern_red (R0x3072) for red pixels. test_pattern_blue. See Figure 34 for a solid green pattern
Register R0x3044[5:4] should be set to 0 to avoid pixel with Gr = Gb = 3072.
value clipping below 992 decimal when test pattern is

Figure 34. Solid Color

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Vertical Color Bars

When the vertical color bars mode is selected, a typical
color bar pattern will be sent through the digital pipeline. See
Figure 35:

Figure 35. Vertical Color Bars

Walking 1s
When the walking 1s mode is selected, a walking 1s
pattern will be sent through the digital pipeline. The first
value in each row is 1. See Figure 36:

Figure 36. Walking 1s

TWO−WIRE SERIAL INTERFACE CRC • That checksum is stored in a two−wire serial interface
AR0234 includes a means of validating two−wire serial accessible register at address 0x31D6.
interface communications. The AR0234 confirms that all • The checksum can be read via two−wire serial interface
two−wire serial interface write requests to the device are and will also be output in the embedded registers (if
successful by means of a checksum, generated from all enabled).
address and data values associated with such transactions.
These requirements are interpreted as follows:
• A write via two−wire serial interface to the checksum
register will reset the checksum to the start value of
• For all two−wire serial interface writes to the camera 0xFFFF.
the 16−bit register address and 2 bytes of data are fed
into a 16−bit CRC to generate a checksum.

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Two−wire serial interface

required for this device?

Yes

Addressing
Write or Read? Read Yes Read back checksum.
checksum register?

Write

Addressing Reset checksum

Yes
checksum register? (to all 1s)

Input 16−bit
address to CRC

Input 16−bit data

value to CRC

Figure 37. Checksum Generation Flow Within the Sensor

The 16−bit value will be input to the CRC MSB first, i.e., polynomial x16 + x12 + x5 + 1, as illustrated in Figure 38 on
c15 through c0. The CRC used will implement the page 45.

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Figure 38. Definition of 16−bit CRC Shift Register

The recommended procedure to use CRC checksum as Step 2: Conduct two−wire serial interface write command to
follows: a desired register
Step 1: Reset CRC checksum register(R0x31D6) by writing Step3: Read CRC checksum register (R0x31D6) to verify
R0x31D6 with any value to reset CRC checksum register that two−wire serial interface write command was done
before write two−wire serial interface write command. successfully by comparing the read CRC checksum
register(R0x31D6) with a expected CRC checksum value.

Reset CRC checksum

R0x31D6 = 0x1234

Conduct
Try current Go to next
2−wire serial IF write
2−wire serial IF write 2−wire serial IF write
R0x301A = 0x0058
transaction again transaction

CRC checksum
matches
CRC checksum
does not match
Read R0x31D6
to verify 2−wire serial
IF transaction by
checking CRC
checksum

Figure 39.

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TWO−WIRE SERIAL INTERFACE SEQUENTIAL the pair of 8−bit addresses addressed by the 15 MSBs of the
WRITES 8−bit address, and the 8−bit write data value that is being
The input to the 16−bit CRC logic is either a 16−bit modified is combined with the 8−bit data address value NOT
address or a 16−bit write data value. If the 16−bit address being modified, and the resulting 16−bits is input into the
matches the CRC register, the CRC register is initialized to CRC for that 8−bit address.
all ones. Otherwise, the 16−bit write data value is input In summary, the CRC checksum(R0x31D6) continues to
(serially) into the CRC generator, and a 16− bit CRC value update, as all non−CRC registers are written. At any time, if
results unique to that 16−bit write data value. Sequentially, CRC register is read, the current CRC register value is read
either CRC address or other addressed data values are back. At any time, if CRC register is written (with any
presented to the CRC generator and resulting CRC register. value), the CRC register is initialized to all ones.
At the end of a sequential write of addresses with 16−bit
address data values, the CRC register contains the CRC READING THE SENSOR CRA AND CHROMATICITY
value of sequentially processed write data values that were Sensor CRA and CFA Chromaticity information is stored
sequentially addressed. in R0x31FE[9:4]. The value can be decoded according to
Note, if the two-wire serial interface write is only 8−bits Table 27.
to a single register address, that write is serviced by reading

Table 27. CRA AND CFA VALUE

Hex Value of R0x31FE[9:4] CRA Value Chromaticity
0x1 0 RGB
0x2 0 Mono
0x11 28 RGB
0x12 28 Mono

REVISION INFORMATION

Table 28.

Revision

Register Type 1 (AS) 2 (AS) 3 (AS) (ES) MP

0x300E[15:12] CREV 1 2 3 3 3
0x300E[2:0] Product Stage 1 1 1 2 4

READING THE SENSOR FUSE ID procedure to read OTPM. This information should always
The FuseID is stored in the OTPM; and OTPM must be be passed to ON Semiconductor whenever a technical
read in order to obtain the FuseID. The following is the inquiry is made to the Field Apps Engineers.

Figure 40.

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Below is the INI script that will read the Fuse ID from the Sensor: AR0234CS REV2
AR0234 OTPM Record Type 0x01 and output these values FuseID: 00000000058804C250606061BA532CA2
into the OTPM_DATA_* registers. The FID can only be
read when the parts is in standby state Revision Number: 0x2001
− CREV: 0x1
− CFA (None): 0x0
− CRA: 0x0
− MREV: 0x8

FID=R0x380E,R0x380C,...,R0x3800

= 0000 0000 0588 04C2 5060 6061 BA53 2CA2

Figure 41.

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USING DEVWARE TO READ THE FUSE ID 2. Click on the arrow next to the Diagnostics folder
The ”Get Fuse ID” button in DevWare is another way to 3. Select Fuse ID
read the fuse ID of the sensor. 4. Click on the Get Fuse ID button to read the fuse
1. Open DevWare and go the Image/ISP Control ID. See Figure Figure 42 after running preset
page [Read FID].

Figure 42. DevWare Get Fuse ID Button

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