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Design Techniques for Sub-micron RF Power Amplifiers

Fallesen, Carsten

Publication date:
2001

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Fallesen, C. (2001). Design Techniques for Sub-micron RF Power Amplifiers.

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 Carsten Fallesen

Design Techniques for Sub-micron

RF Power Amplifiers

PhD thesis

Nokia Mobile Phones

and
Department of Information Technology
Technical University of Denmark

May 2001
Design Techniques for Sub-micron
RF Power Amplifiers

Carsten Fallesen

Nokia Mobile Phones

Department of Information Technology

Technical University of Denmark
II DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS
 III

Abstract

In the last couple of years there has been an increased focus on integrated RF power am-
plifiers for wireless communications, especially mobile phones. The drivers of the de-
velopment high integration and low cost. The highest integration possible will most
probably be achieved with CMOS processes. At the same time CMOS is without doubt
the cheapest process available.
To be able to reach the goal some theory on RF power amplifiers is necessary. The
different classes of operation are explained, then the principles of impedance matching
is discussed. This includes the development of the simulated load-pull method and syn-
thesis of impedance matching networks. Then the biasing of the power amplifier is dis-
cussed along with the stability issues.
The choice of CMOS as a preferred technology for the power amplifier is justified.
The issues of modeling a complete power amplifier is treated. This includes modeling of
the transistors, the passive devices on-chip and off-chip as well as the package and PCB.
To ease the design of power amplifier a design method is developed based on the theory
and the experimental work.
At last the experimental work is described. The first part is a linearization system
based on digital predistortion. The digital predistortion can be used to increase the over-
all efficiency of varying envelope systems. Then three CMOS power amplifiers de-
signed during the project are introduced. The last of these power amplifiers shows
superior performance when compared to other CMOS power amplifiers. The output
power of this power amplifier is 30.4dBm with a power added efficiency of 55%. The
last power amplifier utilizes the design method develop as well as the models described.
The accurate modeling combined with superior performance proves the future of inte-
grated CMOS power amplifiers for wireless communication.
IV DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Resume (Danish)

I de seneste år har der været øget fokus på integrerede RF effektforstærkere til trådløs
kommunikation, især mobiltelefoner. Det der har drevet udviklingen er især ønsket om
høj integration og lav pris. Den højeste integration vil formentlig ske i en CMOS tekno-
logi. Samtidigt er CMOS uden tvivl den billigste teknologi der er til rådighed.
For at nå målet er det nødvendigt at gennemgå den basale teori om RF effektfor-
stærkere. De forskellige klasser af forstærkere bliver forklaret, efterfølgende bliver teo-
rien bag impedans tilpasning diskuteret. Dette inkluderer udviklingen af en metode til
simuleret load-pull og syntese af impedans tilpasnings netværk. Derefter bliver biasing
af effektforstærkere diskuteret sammen med stabilitet af effektforstærkere.
Valget af CMOS som den fortrukne teknologi til effektforstærkere bliver begrun-
det. Spørgsmålene omkring modellering af komplette effektforstærkere bliver behand-
let. Dette inkluderer modellering af transistorerne, de passive komponenter på og
udenfor den integrerede kreds såvel som pakken og printkortet. For at lette udviklingen
af effektforstærkere er en design metode blevet udviklet baseret på både teorien og det
eksperimentelle arbejde.
Til sidst bliver det eksperimentelle arbejde beskrevet. Den første del er et lineari-
serings system baseret på digital predistortion. Den digitale predistortion kan bruges til
at øge effektiviteten i systemer med varierende amplitude. Efter det bliver tre CMOS ef-
fektforstærkere der er blevet udviklet i løbet a projektet beskrevet. Den sidste af disse
effektforstærkere udviser bedre egenskaber end nogen anden CMOS effektforstærker.
Denne effektforstærker giver en udgangseffekt på 30.4dBm med en effektivitet på 55%.
Den sidste effektforstærker blev udviklet ved hjælp af den nye design metode sammen
med de modeller der bliver beskrevet. Den præcise simulering sammen med de uover-
trufne egenskaber demonstrerer fremtiden i integrerede CMOS effektforstærkere til
trådløse produkter.
Table of Contents
Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Basics of RF Power Amplifiers . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Definitions of Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.2 Definitions of Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Mobile Phone Standards . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 First Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2 Second Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.3 Third Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Classes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Class A through C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 Knee Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.2 Class A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.3 Class B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.4 Class AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.5 Class C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Class D and F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Class E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4 Class S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5 Differential Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . 21
2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 Load-Line Theory and Impedance Matching Networks . . . 23
3.1 Small-Signal Impedance Matching . . . . . . . . . . . . . . . . . 23

V
VI DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

3.1.1 S-Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.2 The Smith Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.3 Transducer Gain Method . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.4 Available Gain Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.5 Operating Gain Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2 Large-Signal Impedance Matching . . . . . . . . . . . . . . . . . 30
3.2.1 Load-Pull Contours . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.2 Load-Pull Measurement Systems . . . . . . . . . . . . . . . . . . . . . 31
3.2.3 Simulated Load-Pull . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3 Synthesizing Impedance Matching Networks . . . . . . . . . 35
3.3.1 Impedance Matching Basics . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3.2 Plotting Passive Components in the Smith Chart . . . . . . . . . 36
3.3.3 The L Matching Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3.4 The T Matching Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3.5 The Π Matching Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3.6 Cascaded Matching Networks . . . . . . . . . . . . . . . . . . . . . . . 40
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4 Stability and Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1 Bias Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1.1 DC Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1.2 RF Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.1.3 Generating the Bias Signals . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2 Stability of Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . 45
4.2.1 Stability Circles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2.2 Resistive Stabilisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2.3 Conductive Stabilisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2.4 Feedback Stabilisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3 Bias Circuit Instability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.4 Verifying Stability through Simulations . . . . . . . . . . . . . . 48
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5 CMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.1 Basic RF CMOS Behavior . . . . . . . . . . . . . . . . . . . . . . . . 51
5.1.1 I-V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.1.2 Breakdown Phenomena . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2 Comparison to Other Technologies . . . . . . . . . . . . . . . . . 53
5.2.1 SOI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2.2 LDMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2.3 GaAs MESFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
TABLE OF CONTENTS VII

5.2.4 Silicon BJT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.2.5 GaAs HBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2.6 SiGe HBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3 Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.1 BSIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.2 MOS9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.3 EKV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.4 BSIM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.5 Layout Related Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.4 Modeling of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.4.1 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.4.2 Spiral Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.4.3 Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.4.4 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.4.5 PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.4.6 Thermal Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6 Design Method for Integrated Power Amplifiers . . . . . . . . 63
6.1 Initial Design Decisions . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1.1 Differential or Single-ended Operation . . . . . . . . . . . . . . . . . 64
6.1.2 Number of Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1.3 Gain & Efficiency Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2 Design of Individual Stages . . . . . . . . . . . . . . . . . . . . . . . 64
6.2.1 Class of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.2.2 Transistor Sizing and Load Impedance Selection . . . . . . . . . 66
6.2.3 Source Impedance Selection . . . . . . . . . . . . . . . . . . . . . . . . 66
6.2.4 Design of Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3 Combination of Stages . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.1 Design of Interstage Matching Networks . . . . . . . . . . . . . . . 67
6.3.2 Check RF Performance of Power Amplifier . . . . . . . . . . . . . 68
6.3.3 Check Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7 Digital Predistortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.1 Theory of Digital Predistortion . . . . . . . . . . . . . . . . . . . . . 73
7.1.1 Digital Modulation of IS-95 Signal . . . . . . . . . . . . . . . . . . . . . 73
7.1.2 Modeling of Nonlinearities . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.1.3 Predistorting a Nonlinear Signal . . . . . . . . . . . . . . . . . . . . . . 75
7.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
VIII DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

7.2.1 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.2.2 Data Generation Software . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.3 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.4 Continued Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
8 Design of CMOS Power Amplifiers . . . . . . . . . . . . . . . . . . . 81
8.1 The First CMOS Power Amplifier . . . . . . . . . . . . . . . . . . . 82
8.1.1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.1.2 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.1.3 Design of the Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . 83
8.1.4 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
8.1.5 Summary of First CMOS Power Amplifier . . . . . . . . . . . . . . . 84
8.2 The Second CMOS Power Amplifier . . . . . . . . . . . . . . . . 86
8.2.1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.2.2 Design of the Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . 86
8.2.3 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.2.4 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.2.5 Revised PCB Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.2.6 Summary of Second CMOS Power Amplifier . . . . . . . . . . . . 91
8.3 Third Revision CMOS Power Amplifier . . . . . . . . . . . . . . 93
8.3.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.3.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.3.3 Summary of Third CMOS Power Amplifier . . . . . . . . . . . . . . 98
8.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Appendix A
Design Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
9.1 Initial Design Decisions . . . . . . . . . . . . . . . . . . . . . . . . . 105
9.2 Design Individual Stages . . . . . . . . . . . . . . . . . . . . . . . . 106
9.2.1 Transistor Sizing and Load Selection . . . . . . . . . . . . . . . . . 106
9.3 Combination of Stages . . . . . . . . . . . . . . . . . . . . . . . . . 107
Appendix B
Published Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
List of Figures
Figure 1.1 Simple power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 1.2 Principle of a two-stage power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 1.3 Output power as a function of input power [3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 1.4 Third-order intermodulation products [3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 1.5 Spectrum showing ACPR measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2.1 The generic setup for class A, AB, B and C amplifiers. . . . . . . . . . . . . . . . . . . . . 10
Figure 2.2 Simple RF small-signal model of MOS transistor. . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2.3 Relationship between biaspoint and conduction angle. . . . . . . . . . . . . . . . . . . . . 11
Figure 2.4 Harmonic components of current plotted as a function of conduction angle. . . . 12
Figure 2.5 The optimal load line as well as voltage and current clipping. . . . . . . . . . . . . . . . 13
Figure 2.6 Output power, DC power and efficiency as functions of conduction angle. . . . . 14
Figure 2.7 I-V characteristic of a typical submicron NMOS transistor. . . . . . . . . . . . . . . . . 14
Figure 2.8 Efficiency and output power vs. knee-voltage for a class B amplifier. . . . . . . . . 15
Figure 2.9 Class D amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 2.10 Class F power amplifier with third harmonic termination. . . . . . . . . . . . . . . . . . 18
Figure 2.11 Generic class E power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 2.12 Drain and capacitor current and drain voltage of a class E PA [1]. . . . . . . . . . . 19
Figure 2.13 Output power and peak voltage vs. conduction angle [1]. . . . . . . . . . . . . . . . . . 20
Figure 2.14 Class S power amplifier with Σ∆-modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 3.1 The Smith chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 3.2 Definition of impedances used for matching a two-port. . . . . . . . . . . . . . . . . . . . 25
Figure 3.3 Constant gain circles associated with the available gain method. . . . . . . . . . . . . 28
Figure 3.4 Constant gain circles associated with the operating gain method. . . . . . . . . . . . . 29
Figure 3.5 Operating gain circles of a conditionally unstable device. . . . . . . . . . . . . . . . . . . 30
Figure 3.6 1,2 and 3dB output power contours. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 3.7 Trade-off between output power (black) and power added efficiency (grey). . . . 32
Figure 3.8 Basic Load-Pull System [8]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 3.9 Impedance points chosen for load-pull measurements . . . . . . . . . . . . . . . . . . . . . 33
Figure 3.10 Load-pull impedance realized as a series combination. . . . . . . . . . . . . . . . . . . . 34
Figure 3.11 Load-pull impedance realized as a matching network. . . . . . . . . . . . . . . . . . . . . 34
Figure 3.12 Series and parallel representation of a complex impedance. . . . . . . . . . . . . . . . 35
Figure 3.13 The effects of passive components plotted in the Smith chart. . . . . . . . . . . . . . 36
Figure 3.14 The L section matching networks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 3.15 L matching network synthesized using CAD tool. . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 3.16 A Tee section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 3.17 T matching network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 3.18 A Π section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 3.19 Π matching network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

IX
X DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Figure 3.20 Two cascaded L sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 3.21 Insertion loss of one or two cascaded L section. . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 4.1 Bias circuit for MOSFET power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 4.2 Passive and active bias circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 4.3 Stability circles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 4.4 Resistive stabilisation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 4.5 Conductive Stabilisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 4.6 Feedback stabilisation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 4.7 Example of stable bias circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 5.1 I-V characteristic of a typical submicron NMOS transistor [1]. . . . . . . . . . . . . . . 52
Figure 5.2 Enhanced RF MOS transistor model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 5.3 On-chip capacitor model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 5.4 Simple Π network inductor model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 5.5 On-chip inductor model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 5.6 Simple RLC network metal wire model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 5.7 Leadframe model for two adjacent pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 5.8 Simplified thermal model of a power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 6.1 Overall design flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 6.2 Design flow for initial design decisions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 6.3 Design flow for individual stage design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 6.4 Design flow for transistor sizing and load impedance selection. . . . . . . . . . . . . . 66
Figure 6.5 Design flow for combination of individual stages. . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 7.1 Probability and class A efficiency vs. power levels. . . . . . . . . . . . . . . . . . . . . . . 72
Figure 7.2 Schematic of dynamic supply voltage power amplifier. . . . . . . . . . . . . . . . . . . . . 72
Figure 7.3 Total efficiency as a function of the output power. . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 7.4 Probability and efficiency combined. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 7.5 Constellation diagram showing phase transitions in QPSK and OQPSK. . . . . . . 74
Figure 7.6 Block diagram of digital OQPSK modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 7.7 Measurement setup for retrieving AM-AM and AM-PM data. . . . . . . . . . . . . . . 76
Figure 7.8 Measuring ACPR for digital predistortion system. . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 7.9 ACPR measurements with and without digital predistortion. . . . . . . . . . . . . . . . 77
Figure 7.10 The output spectrum of the DSV power amplifier
with and without digital predistortion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 7.11 Schematic of improved digital predistortion system. . . . . . . . . . . . . . . . . . . . . . 78
Figure 7.12 Effect of delay in DC-DC converter control loop. . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 7.13 Spectrum of improved digital predistortion system. . . . . . . . . . . . . . . . . . . . . . . 79
Figure 8.1 Schematic of the first CMOS power amplifier prototype. . . . . . . . . . . . . . . . . . . 83
Figure 8.2 Photograph of the first CMOS power amplifier PCB. . . . . . . . . . . . . . . . . . . . . . 85
Figure 8.3 Output power and power added efficiency of first CMOS PA. . . . . . . . . . . . . . . 85
Figure 8.4 Comparison of simulated and measured data. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 8.5 Schematic of the second CMOS power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 8.6 Measured output power and efficiency, biased for maximum power added efficiency.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 8.7 Measured output power and efficiency, biased for maximum output power. . . . 89
Figure 8.8 Measured output power and efficiency vs. supply voltage. . . . . . . . . . . . . . . . . . 90
Figure 8.9 Output power and efficiency vs. frequency, biased for maximum efficiency . . . 90
Figure 8.10 Output power and efficiency vs. frequency, biased for maximum output power 91
Figure 8.11 Measured output power and efficiency vs. supply voltage at 1730 MHz. . . . . . 91
Figure 8.12 Photograph of the IC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 8.13 Load-pull simulation of third CMOS power amplifier. . . . . . . . . . . . . . . . . . . . 94
LIST OF FIGURES XI

Figure 8.14 Schematic of third CMOS power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 8.15 Die photograph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 8.16 PCB photograph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 8.17 Output power and power added efficiency vs. frequency when biased for efficiency.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 8.18 Measured output power and power added efficiency vs. supply voltage at 1750
MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 8.19 Comparison of simulated and measured data. . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure A.1 I-V characteristics of 1mm wide transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure A.2 Voltage across and current through the output transistor channel. . . . . . . . . . . 108
XII DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS
List of Tables
Quick overview of the classes of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Specifications for the first CMOS PA prototype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Characteristics of the first CMOS power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Specifications for the second CMOS PA prototype.. . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Component values for the second CMOS power amplifier . . . . . . . . . . . . . . . . . . . . . . 92
Characteristics of the second CMOS power amplifier.. . . . . . . . . . . . . . . . . . . . . . . . . . 93
Component values for third CMOS power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Comparison of CMOS power amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Characteristics of the third CMOS power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Evolution of CMOS power amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Specifications for the third CMOS PA prototype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Gain and efficiency budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

XIII
XIV DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS
Glossary
ACP Adjacent channel power
ACPR Adjacent channel power ratio
AMPS Advanced mobile phones system
CAD Computer aided design
CDMA Code division multiple access
CMOS Complementary metal-oxide-semiconductor
COB Chip on board
DSP Digital signal processor
DSV Dynamic supply voltage
GaAs Gallium Arsenide
GMSK Gaussian minimum phase shift keying
GSM Global system for mobile communications
HBT Heterojunction bipolar transistor
IMD Intermodulation distortion
LDMOS Laterally diffused MOS
MOSFET Metal oxide semiconductor field effect transistor
MESFET Metal semiconductor field effect transistor
OQPSK Offset quadrature phase shift keying
PAE Power added efficiency
PCB Printed circuit board
QPSK Quadrature phase shift keying
RFC RF choke
SAR Specific absorption rate
SiGe Silicon Germanium
SMD Surface mount device
SOI Silicon on insulator
TDMA Time division multiple access
UMTS Universal mobile telephone system
W-CDMA Wideband code division multiple access

XV
Errata
p.4, eq. 1.4 Pch is the power in the channel, while Padj is the power in the
adjacent channel

p. 10, l. 9 output impedance should be load impedance

p. 17, l. 3 power added efficiency should be output power

2 2 2
1 – S 11 – S 22 + ∆
p. 28, eq. 3.19 K = --------------------------------------------------------
-
2 S 12 S 21
p. 37, l. 15 the impedance 10 - j10 should be 10 - j15

p. 41, fig 3.21 The gain in Fig 3.21 has not been normalized and the
maximum should be 0dB
CHAPTER 1
INTRODUCTION
Over the last couple of years there has been an increasing focus on highly integrated high
efficiency power amplifiers for wireless communication systems, especially mobile
phones. This is also the topic of this thesis.
In the first chapters of this thesis the basic theory is explained. Then the concept of
simulated load-pulling is introduced in conjunction with automated impedance matching
network synthesis. This is followed by a comparison of semiconductor technologies with
focus on CMOS. Then the modeling of active and passive components is described. A
number of experimental CMOS power amplifiers were constructed during the project
and the results of these are presented at last.
The design of power amplifiers in the past did not follow a stringent design method,
it rather seemed like black magic was performed. In this thesis a design method is
developed based on the basic theory of power amplifier design and this is used to
formalize the design process.
In the last part of this thesis experimental results on CMOS power amplifiers as
well as a digital linearizations system is presented. The CMOS power amplifiers show
results better than any other CMOS power amplifier presented so far, the results are even
comparable to commercial power amplifiers in more exotic technologies.
In the remainder of this chapter the basic definitions used in conjunction with
power amplifiers will be explained.

1.1 Basics of RF Power Amplifiers

A simple power amplifier is illustrated in Figure 1.1. The power amplifier consists
of an input impedance matching network, an amplifying stage and an output impedance
matching network. Furthermore DC bias is applied at the input and output ports of the
amplifying stage [1][2].

1
2 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Figure 1.1 Simple power amplifier.

The power amplifiers can be divided into narrowband and broadband power
amplifiers. In most communication systems narrowband power amplifiers are used,
since they are usually more efficient than the broadband amplifiers.
The power amplifier has a number of characteristic properties that will now be
explained. First of all the power gain of a power amplifier is defined as the output power
divided by the input power:
P out
G = --------- (1.1)
P in

In practice most power amplifiers will be multistage amplifiers to obtain sufficient power
gain. The combination of several stages often introduces problems with stability of the
power amplifier due to the increased gain from input to output. The principle of a two-
stage power amplifier is shown in Figure 1.2.

Figure 1.2 Principle of a two-stage power amplifier.

INTRODUCTION 3

1.1.1 Definitions of Efficiency

The efficiency is probably the most important property of the power amplifier,
since a very large part of the total power dissipated in a mobile phone is dissipated in the
power amplifier. The efficiency is limited by the selected class of operation and the
parasitic components, as described in chapter 2. The efficiency can be expressed as either
drain efficiency or power added efficiency. The drain efficiency is given by:
P out
η drain = ---------- (1.2)
P DC

On the system level the efficiency of the driver stages is also important, and then
the power gain of the power amplifier must be included. The power gain of a power
amplifier is also dependent upon the class of operation, as well as the chosen technology.
Different classes of operation have different relative power gains. The inclusion of the
power gain leads to the expression for power added efficiency:
P out – P in P out 
- ⋅  1 – ----
1
η add = -------------------- = --------- (1.3)
P DC P DC G

The power added efficiency is more relevant to the system designer than the drain
efficiency, but as mentioned above this depends highly of the technology. It is therefore
difficult to compare two classes of operation, without knowing the properties of the
power transistor.

1.1.2 Definitions of Linearity

One of the other important parameters in power amplifier design is the nonlinearity of
the power amplifier. The nonlinearity originates from the active components. If the
wireless communication system utilizes a varying envelope modulation the
nonlinearities will cause spectral regrowth which will pollute the neighboring channels.

Gain Compression
Gain compression describes the phenomenon, when the relationship between the input
and output power levels is no longer linear. When the output power is 1dB less than
expected by the linear relationship the so-called 1dB Gain Compression Point ( P 1dB ) is
reached. The gain compression is also known as AM-AM conversion.

AM-PM Conversion
The AM-PM conversion is caused by the phase shift of the power amplifier caused by
the amplitude of the signal. This can for instance be caused by the non-linear drain-
source capacitance of the MOSFET.

Intermodulation Distortion
The harmonic distortion is caused by the nonlinear active components of the amplifier.
The result is distortion components at integer multiples of the signal frequency.
4 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Figure 1.3 Output power as a function of input power [3].

Intermodulation distortion (IMD) is generated when more than one signal is
present on the input. The intermodulation distortion is also caused by the nonlinearities
of the amplifier. New third-order signals are generated at e.g. 2f 1 – f 2 and 2f 2 – f 1 . The
third-order products increase by 3 dB when the input signals increase by 1 dB. The point
at which the extrapolated power levels of the third-order products reach the wanted
power is called the Third-order Intercept Point ( P 3IP ). Although third-order distortions
will probably be the most important a number of other orders may also be significant.

Figure 1.4 Third-order intermodulation products [3].

Adjacent Channel Power Ratio

The adjacent channel power ratio (ACPR) is one of the most important ways of
characterizing the nonlinearity of a power amplifier in linear communication standards.
P adj
ACPR = --------- (1.4)
P ch

In Figure 1.5 a typical spectrum showing the ACPR is illustrated. The ACPR is an
easy way to measure the total distortion caused by the above mentioned nonlinearities.

1.2 Mobile Phone Standards

The mobile phone standards have evolved quickly over last decades. The first standards
used continuos time frequency modulation (FM), now wideband code division multiple
access (W-CDMA) or time division multiple access (TDMA) systems with quadrature
INTRODUCTION 5

Figure 1.5 Spectrum showing ACPR measurement.

modulation formats are being deployed. In the following sections the most important
features of the three generations introduced until now will be described.

1.2.1 First Generation

The first generation mobile phone standards employed analog modulation formats. The
first systems were used in USA in the 1950s. One of the most successful first generation
standards was the Nordic Mobile Telephone standard (NMT), developed in the nordic
countries in the early 1980s. This standard served as an example of the importance of
roaming across countries and different network operators.
A few of the first generation systems are still in use most notably the NMT and the
north-american Advanced Mobile Phone System (AMPS). Since these systems are all
FM systems, the nonlinearities of the power amplifiers are not a problem.

1.2.2 Second Generation

The second generation mobile phone standards all use digital modulation formats. The
the digital modulation allows for digital data services. The main advantage of the digital
modulation is however the possibility to share a single channel between several users.
The sharing is done either through time division multiple access (TDMA) or code
division multiple access (CDMA).

GSM-900/1800/1900
The Global System for Mobile Communications (GSM) standard is used all through
Europe, as well as most of North America and some parts of the Asia-Pacific area. The
GSM system employs GMSK modulation which is a constant envelope modulation. The
sharing of the channel is done through time division. A constant envelope modulation
uses a constant amplitude in the modulation, which means that the power amplifier can
be nonlinear. The GSM system features global roaming between different operators. The
6 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

bitrate of the GSM system is 9.6 kbits/s in a standard system, but changing the error
coding and using more than one timeslot up to 43.2 kbits/s has been achieved.

EDGE
The EDGE standard was originally developed as an extension for GSM only, but has now
been integrated in other standards as well. The EDGE standard uses a modified 8PSK
modulation, which is not constant envelope. The new modulation means that the
nonlinear power amplifiers can no longer be used. The EDGE standard allows for
bitrates up to 384 kbits/s.
The linearity requirements of the EDGE standard is expressed in terms of ACPR.
In the adjacent channel the ACPR must be better than -30dBc while in the alternating
channel the ACPR must be better than -54dBc. Since nonlinearities are also introduced
in the circuits prior to the power amplifier then specifications for the power amplifier will
typically be even harder. The ACPR is measured with a 30 kHz resolution bandwidth at
the center of the channels.

IS-95 CDMA
The IS-95 standard is used primarily in North America as well as some places in the
Asia-Pacific area. The IS-95 system uses QPSK modulation which utilizes varying
envelope, the sharing of the channel is achieved through code division [3].
While the number of simultaneous users on a channel in a TDMA systems is
determined by the number of timeslots, the number of simultaneous users in IS-95 is
determined by the noise level in the channel. The noise level is optimized through
aggressive power control to maximize the number of simultaneous users. Due to the
power control the power amplifier has to be able to control the output power in 1dB steps
over a range of 85dB.
The linearity requirements of the IS-95 standard is also expressed as ACPR. The
ACPR of the adjacent channel has to be better than -42dBc, but this is for the total output
power compared to a 30 kHz band, this relates to an ACPR of -26dBc.

1.2.3 Third Generation

The third generation of mobile phones is primarily focused on higher bitrates. The only
serious standard until now is the Universal Mobile Telephones System (UMTS) which
is a wideband CDMA system. The UMTS system will probably be the first standard with
true global coverage across countries and network operators.
The UMTS standard features bitrates up to 2 Mbits/s. This bitrate will be used for
multimedia applications on the mobile terminal e.g. audio and video clips. As was the
case for IS-95 the power control has 1dB steps and the dynamic range is 70dB posing a
real challenge for the power amplifier designer
INTRODUCTION 7

1.3 Summary
The power amplifier is the most power consuming component in a mobile phone, and it
is therefore interesting to reach higher efficiency levels for the power amplifier. There
are several ways to improve the efficiency, e.g. new circuit topologies, higher level of
integration and better technologies.
The linearity of a power amplifier will be an issue in future telecommunication
standards, such as EDGE and UMTS. There will therefore be a need for linear power
amplifiers, this can be achieved either by using linear topologies and/or linearization
techniques.
The future UMTS handsets will probably contain dual-mode functionality with
GSM, this means that the power amplifier must also be able to handle ordinary GSM
efficiently. The dual-mode solution will be very challenging, and might not even be the
optimal solution.
In this chapter the basic properties of an RF power amplifier has been defined. In
the following chapters the details of the power amplifiers will be discussed. In chapter 2
the classes of operation are discussed. The trade-offs between different class of operation
are discussed. The impedance matching of the power amplifier is described in chapter 3.
This includes methods to obtain optimal impedance matching as well as methods for
synthesizing the impedance matching networks. Chapter 4 deals with the biasing of the
power amplifier. In this chapter the issues of RF and bias stability is also discussed.
In chapter 5 the implementation technologies are discussed with focus on the deep
sub-micron CMOS technologies. The modeling of active and passive components on-
chip as well as on the PCB is also discussed. In chapter 6 the theory is collected in a
design method for integrated power amplifiers. The design method covers the complete
design of a power amplifier, from specification to verification.
In chapter 7 a digital predistortion is presented, which enables the use of nonlinear
power amplifiers in systems with varying envelope. The digital predistortion system was
built and experimental results obtained. Three CMOS power amplifiers have been
designed during the Ph.D. project. These power amplifiers are described in chapter 8. In
comparison with other published CMOS power amplifiers they shows superior
performance.

1.4 Acknowledgements
This Ph.D. project have been funded by Nokia Mobile Phones in Copenhagen. I have had
very fruitful discussions with a number of design engineers at Nokia. I would especially
like to thank Dan Rebild for an enormous support during the entire Ph.D. project.
8 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

References
[1] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Artech
House, 1999.
[2] H. L. Krauss, C. W. Bostian, and F. H. Raab, Solid State Radio Engineering.
John Wiley Sons, 1980.
[3] B. Razavi, RF Microelectronics. Prentice Hall, 1998.
CHAPTER 2
CLASSES OF OPERATION
The different topologies for power amplifiers can be divided into a number of classes of
operation. The classes have different properties with respect to e.g. linearity, efficiency
and power gain.
Usually the classes A, AB, B and C are treated as distinct modes of operation,
although in reality they are a continuum of biasing conditions for the same basic mode
of operation. It is therefore possible to describe class A through C as a single class with
different conduction angles. The analysis of class A through C is done in Section 2.1.
The classes D and F can also be analyzed as one class, this analysis will be carried out
in Section 2.2. The class E operation is quite different from the other classes and will be
treated separately in section Section 2.3. At last the class S operation will be described
in Section 2.4.
One of the important parameters of the amplifier classes is the load line, as the
name implies the load of the amplifier has an influence on the load line. The other
parameter that influences the load line is the quiescent bias point.

2.1 Class A through C

The class A, AB, B and C amplifiers are very similar, except for the biasing and
the output matching network. The basic class A through C power amplifier is illustrated
in Figure 2.1. The biasing of the output is obtained by the RF choke (RFC). To prevent
a DC current from flowing a DC block (CDC) is incorporated into the design. The
loadline of the power amplifier is controlled by the load resistance (RL), while the
resonator (LR, CR) filters out the harmonics at the output. The input matching, not
illustrated here, usually contains the biasing of the input, as will be described in Chapter
4.
Which of the classes the power amplifier actually operates in is defined by the
quiescent drain current, which again is defined by the input bias point. Apart from the
bias point of the amplifier the loadline is the most important feature. The transistor has
a large impact on the selection of the loadline of the power amplifier. To optimize the

9
10 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Figure 2.1 The generic setup for class A, AB, B and C amplifiers.
power amplifier, with respect to output power, efficiency or linearity, the load line
should be placed correctly. When the loadline is not selected properly the power
amplifier will be either current or voltage limited. The optimal load line of a power
amplifier is primarily controlled by the I-V characteristic of the transistor. To obtain
maximum output power the load line should be placed such that the amplifier is neither
current nor voltage limited.
In the analysis of the class A through C power amplifiers it is assumed that the
resonator has infinite impedance at the fundamental frequency while the impedance is
zero at all other frequencies. The output impedance is defined by the load resistor (RL).
The RF choke (RFC) is ideal and allows only DC currents to flow to the transistor. Under
these assumptions it is possible to derive the current and voltage waveforms at the output
of the power amplifier assuming a sinusoidal drive at the input.
The analysis starts by defining the conduction angle α, which is the amount of time
the transistor is conducting. Assuming a MOSFET, the conduction angle is determined
by the quiescent bias voltage (Vq) on the gate of the transistor, with a corresponding
quiescent current (Iq). The transistor is assumed to have a threshold voltage, below

Figure 2.2 Simple RF small-signal model of MOS transistor.

which the transistor will not draw any current. The maximum current that can be drawn
by the transistor is defined as Imax. The relation between conduction angle and bias point
is shown in Figure 2.3, where biasing for 360º, and 180º conduction angles are
illustrated. The selected bias points correspond to class A and B. In the same figure the
ideal currents drawn by the transistor is shown.
The currents drawn by the transistor can be formulated as:
CLASSES OF OPERATION 11

Figure 2.3 Relationship between biaspoint and conduction angle.

 I + ( I max – I q ) cos θ ,– α ⁄ 2 ≤ θ ≤ α ⁄ 2
id ( θ ) =  q (2.1)
 0 ,– π < θ < –α ⁄ 2 ;α ⁄ 2 < θ < π

where
Iq
cos ( α ⁄ 2 ) = – -------------------- (2.2)
I max – I q

isolating Iq in this equation gives:

I max cos ( α ⁄ 2 )
I q = ----------------------------------- (2.3)
cos ( α ⁄ 2 ) – 1

substituting (2.3) in (2.1) gives

 I max
 --------------------------------
i d ( θ ) =  1 – cos ( α ⁄ 2 -) [ cos θ – cos ( α ⁄ 2 ) ] ,– α ⁄ 2 ≤ θ ≤ α ⁄ 2 (2.4)

 0 ,– π < θ < – α ⁄ 2 ; α ⁄ 2 < θ < π

The DC current as well as the magnitude of harmonic frequency components can

be found using Fourier analysis. The DC current is then:
1- α ⁄ 2 --------------------------------
I max
I dc = ----- ∫
2π –α ⁄ 2 1 – cos ( α ⁄ 2 )
- [ cos θ – cos ( α ⁄ 2 ) ] dθ
(2.5)
I max 2 sin ( α ⁄ 2 ) – α cos ( α ⁄ 2 )
= ---------
- -------------------------------------------------------------
2π 1 – cos ( α ⁄ 2 )

The magnitude of the harmonic frequency components can be found by applying

Fourier analysis on the waveform described by (2.4). The magnitude of the nth is then:
12 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

α⁄2 I max
I n = --1- ∫ - [ cos θ – cos ( α ⁄ 2 ) ] cos nθ dθ
-------------------------------- (2.6)
π –α ⁄ 2 1 – cos ( α ⁄ 2 )

Solving (2.6) for the fundamental frequency gives:

I max α – sin ( α )
I 1 = ---------
- --------------------------------- (2.7)
2π 1 – cos ( α ⁄ 2 )

The DC and first five harmonic currents have been plotted against the conduction
angle in Figure 2.4.

Figure 2.4 Harmonic components of current plotted as a function of conduction angle.

The power consumption and output power can now be found with the help of the
the supply voltage VDD and the load impedance RL. Before the analysis the load
impedance has to be defined. Assuming an ideal transistor this corresponds to:
V DD
R L = ----------- (2.8)
I max

This gives maximum voltage and current swing as illustrated by line (a) in Figure
2.5. The case of voltage clipping where be current swing is reduced is illustrated by line
(b) while current clipping and the following reduced voltage swing is line (c).
When the load impedance is too high it corresponds to voltage clipping as
illustrated by line (b). In the case of voltage clipping it is easy to see that the value of
Imax is reduced to the effective value:
V DD
I max, eff = ----------- (2.9)
RL

When on the other hand the load impedance is too low the opposite case of current
clipping occurs. This can be accounted for by using the effective voltage VDD,eff in place
of VDD.
CLASSES OF OPERATION 13

Figure 2.5 The optimal load line as well as voltage and current clipping.
V DD, eff = I eff R L (2.10)

By substituting Imax with Ieff in (2.7) the effective RF current is found:

 V DD V DD
 -----------, ----------- < I max
 RL R L
I max, eff =  (2.11)
 V DD
 I max, ----------
R
- ≥ I max
 L

I max, eff α – sin ( α )

I 1 = -----------------
- --------------------------------- (2.12)
2π 1 – cos ( α ⁄ 2 )

Using the above equations it is now possible to obtain the DC and output power of
the power amplifier:

 I max R L, R L I max < V DD

V DD, eff =  (2.13)
 V DD, R L I max ≥ V DD

P DC = V DD I DC (2.14)

V DD, eff I 1 V DD, eff I 1

- ------- = -----------------------
P out = ------------------ (2.15)
2 2 2

it is now possible to define the drain efficiency of the power amplifier:

P out
η drain = ---------- (2.16)
P DC

it is now possible to plot the relationship between conduction angle, output power
and efficiency, see Figure 2.6.
14 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Figure 2.6 Output power, DC power and efficiency as functions of conduction angle.

2.1.1 Knee Effect

The knee effect is a property of the transistor used for the power amplifier. Due to the
behavior of the MOS transistor the drain current will not only depend on the gate voltage
but also on the drain voltage. This is especially noticeable at low drain voltages. The I-
V characteristic of a typical submicron NMOS transistor is shown in Figure 2.7, where
each of the curves represent a 0.25V increment in gate voltage.

Figure 2.7 I-V characteristic of a typical submicron NMOS transistor.

The knee voltage is defined as the drain voltage at which the transistor starts
operating in saturation for a given gate voltage. Due to the knee effect it is not possible
obtain maximum voltage and current swing using the same load-line, actually maximum
CLASSES OF OPERATION 15

voltage swing is only available at zero drain current. The impact of the knee effect can
be calculated by realizing that only the values of Veff and Ieff are affected. Since the
value of Ieff affects only the output power of the power amplifier and Veff affects output
power as well as efficiency it is possible to make trade-offs between output power and
efficiency for a given transistor.
To illustrate how seriously the knee-effect reduces the efficiency the output power
and efficiency is plotted vs. knee-voltage in Figure 2.8 for a class B amplifier.

Figure 2.8 Efficiency and output power vs. knee-voltage for a class B amplifier.

Now that the general coverage of the classes A through C is done, it is natural to
discuss the specific behavior of the original class definitions. This will be done in the
following sections.

2.1.2 Class A
The conduction angle of a class A amplifier is 360° . The maximal efficiency of a class
A amplifier is therefore 50%. The class A amplifier is the class with the best linearity,
but also the lowest efficiency. Ideally the load line of a class A amplifier is placed in such
a way that the quiescent current is half that of the maximal current needed. The drain
efficiency of a class A amplifier is given by [1][2]:
2 2
P out I q ⋅ RL
η = ---------- = ----------------
2
(2.17)
P DC 2 ⋅ V dd

The load which gives the maximum power at the output is V dd ⁄ I q , with this load
the maximum efficiency is 50%. When the saturation voltage of the device is taken into
account, the situation is even worse. The possible voltage swing is then only
V dd – V knee , this gives the load line ( V dd – V knee ) ⁄ I q . The maximum efficiency is then
given by:
16 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

V knee 2
 1 – ------------- 
 V dd 
η max = ------------------------------- (2.18)
2

For a 3.3 V process with a knee voltage of 0.5 V the maximum efficiency will be
42%. Although the efficiency is poor at maximum output power, it gets even worse when
less than maximum power is needed since the DC power PDC is unchanged, but the
output power Pout is lower.

2.1.3 Class B
The class B amplifier is biased in such a way that it amplifies only the positive part of
the signal. In the remaining part of the time, the output from the amplifier is zero. Since
the conduction angle of a class B amplifier is only 180° , a filter must be placed at the
output in order to filter the harmonics out of the signal. Another way to retrieve the
original signal is to couple two class B amplifiers in a push-pull configuration.
The class B amplifier is basically linear and has a maximum efficiency of 78.5%
with Vknee = 0, this can be shown for a single-ended amplifier as below.
V dd – V knee
I p = ----------------------------- (2.19)
RL
2 2
1
T
---
2 Ip ⋅ RL ( V dd – V knee )
P out = R L ⋅ --- ∫ 2 ( I p sin ωt ) dω = --------------- = ------------------------------------ (2.20)
T 0 4 4 ⋅ RL

I p V dd V dd ⋅ ( Vdd – V knee )
- = -----------------------------------------------
P DC = I D V dd = ------------- (2.21)
π π ⋅ RL

1 T
P diss = --- ∫ i DS ( t )v DS ( t ) dt (2.22)
T 0
2
P out ( V dd – V knee ) π ⋅ RL V dd – Vknee π
η max - = ------------------------------------ ⋅ -----------------------------------------------
= --------- - ⋅ ---
= ---------------------------- (2.23)
P DC 4 ⋅ RL V dd ⋅ ( V dd – V knee ) V dd 4

2.1.4 Class AB
Class AB amplifiers are biased in such a way that the conduction angle is between 180°
and 360° . The maximal efficiency is therefore between 50% and 78.5% depending on
the conduction angle. In practice most class B amplifiers will be designed slightly into
the class AB region, due to the nonlinearities of the turn-on region in the transistor. This
means that a vast majority of the power amplifiers for wireless communications operate
in class AB.
CLASSES OF OPERATION 17

2.1.5 Class C
In a class C amplifier the conduction angle, θ ,is less than 180° . The efficiency depends
upon the conduction angle and can ideally reach 100%. As the efficiency rises the power
gain decreases, and the power added efficiency, will eventually fall to 0. The Class C
amplifier operates highly non-linearly.
2 2
Ip ⋅ RL 2
P out = --------------- ⋅ ( 2θ – sin 2θ ) (2.24)
2
4π
V dd ⋅ I
P DC = -----------------p- ⋅ ( sin θ – θ cos θ ) (2.25)
π
P out 2θ – sin 2θ
η max = ---------- = ---------------------------------------- (2.26)
P DC 4 ( sin θ – θ cos θ )

2.2 Class D and F

Figure 2.9 Class D amplifier.

Much like the class A-C power amplifiers it is possible to treat class D and F as special
cases of the same general theory. The original definition of a class D power amplifier
uses two transistors operated as switches, see Figure 2.9. The on-resistance and therefore
the loss in the transistor should be zero. The efficiency is limited by the switching time
and the on-resistance of the transistor. Due to the switching behavior of the class D
amplifier it is very non-linear and in principle not even power control is possible. The
drain efficiency of a class D power amplifier is given by [2]:
R dc 8R L
-, R dc = ---------
V eff = V DD ----------------------- 2
- (2.27)
R dc + R on π
V eff sin θ s
η = ---------
- ------------- (2.28)
V dd θ s
18 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

where θs=2πts is the angle associated with the switching. The transient time ts is
the time required for one of the transistor to switch. This means that the switching of the
power amplifier is completed within 2ts.
The basic idea of class F amplifiers is to reduce the power dissipated in the transistor by
minimizing the voltage across the transistor at the time where the current through the
transistor is largest. This is accomplished by modifying a class B amplifier with a
quarter-wave stripline to short all even harmonics and appear as open at odd harmonics,
while the fundamental does not see the load as normal. The harmonic termination means
that the waveform of the output signal will be a square wave. This gives a maximum
achievable efficiency of 100% and is actually the same condition as class D although
single-ended [3].
Instead of a stripline a 3rd harmonic termination using a resonator consisting of an
inductor and a capacitor can be used. The maximum achievable efficiency for this type
of amplifier is then approximately 88%, which is about 10% better than the class B
amplifiers. The principle of the class F power amplifier with third harmonic termination
is shown in Figure 2.10.

Figure 2.10 Class F power amplifier with third harmonic termination.

It is also possible to use a 2nd harmonic termination. The maximum achievable

efficiency for this type of amplifier is then approximately 85%. A number different
configurations are possible, but in general the increased efficiency is followed by
increasing complexity. It is also important to bear in mind that the increased complexity
increases the total losses in the nonideal passive components.

2.3 Class E
The class E amplifier is a tuned amplifier, which ideally can reach an efficiency of 100%
[4]. The transistor works as a switch as is the case with class D amplifiers, but only one
transistor is used. The basic idea is to delay the voltage curve so that the drain voltage
does not rise till after the switching is done. This kind of operation causes the class E
amplifier to be very nonlinear. Even for a non-ideal transistor the efficiency of a class E
power amplifier can be quite high.
CLASSES OF OPERATION 19

Figure 2.11 Generic class E power amplifier.

The design of a class E power amplifier is characterized by the choice of
conduction angle, supply voltage and peak current. The output power and peak voltage
depends on the conduction angle. This means that they both rise with increasing
conduction angle. For a reasonable output power the peak voltage is at least three times
the supply voltage. This causes problems if the transistors used have relatively low
breakdown voltage.

Time (s)
Figure 2.12 Drain and capacitor current and drain voltage of a class E PA [1].

2.4 Class S
The class S amplifiers operate in the same way as class D, but the pulse width is
modulated. The class S amplifier demands even faster transistors than the class D
20 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Figure 2.13 Output power and peak voltage vs. conduction angle [1].
amplifier, since the pulsewidth modulation causes very short pulses to be generated.
Once again the efficiency can ideally reach 100%.
The pulsewidth modulations means that the power amplifier acts linearly assuming
the pulsewidth modulation is linear. In principle this configuration makes it possible to
build very high efficiency power amplifiers, but the generation of the pulsewidth
modulation is very troublesome.
One approach to the pulsewidth modulation is Σ∆-modulation [5], this is illustrated
in Figure 2.14. The RF signal is then oversampled, e.g. an oversampling rate of eight.
The drawback of this approach is that the digital logic will have to run at eight times the
frequency of the RF signal. At these frequencies the digital logic will have a large power
consumption which will degrade the total efficiency. Another drawback is the need for
a bandpass filter at the output of the power amplifier.

Figure 2.14 Class S power amplifier with Σ∆-modulation.

CLASSES OF OPERATION 21

2.5 Differential Power Amplifiers

The differential power amplifier differs from an ordinary power amplifier in a number
of ways. There are advantages as well as disadvantages of differential power amplifiers.
In principle a differential amplifier might just be two separate amplifiers coupled in
parallel, although a lot of the advantages will not be available then.
One of the big challenges of high efficiency power amplifiers is the inductance in
series with the ground. The effect of the ground inductance can be reduced by a
differential amplifier.
One of the main motivations to use differential power amplifiers is the tempting
idea that they can drive a differential antenna. The differential antennas have not yet
proven to be usable in mobile phones. One of the problems with differential antennas is
that the specific absorption rate (SAR) is higher than in single-ended antennas. Another
problem with the differential antennas is the fact that either the efficiency or the
bandwidth of the antennas drops when operated in differential mode. Since the
bandwidth of an antenna for mobile phones is already close to the specifications, a
differential antenna will have lower efficiency, thereby eliminating the best argument for
differential power amplifiers.
If a differential power amplifier will have to drive a single-ended antenna a
differential to single-ended conversion will have to take place somewhere after the
power amplifier. A differential to single-ended conversion is always associated with loss
and increased cost.

2.6 Summary
As described above there are numerous classes of operation, with different advantages
and disadvantages. In order get a quick overview of the different classes Table 2.1 can
be used.
Table 2.1 Quick overview of the classes of operation.

Maximum
Class efficiency Linearity Note
A 50% Good
AB 50-78.5% Fair
B 78.5% Fair
C 78.5-100% Poor
D 100% Poor
E 100% Poor
F 85% Fair 2nd harm.
F 88% Fair 3rd harm.
F 100% Fair Even harm.
S 100% Good
22 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

For a more detailed comparison, the properties of the transistor have to be included,
especially the maximum power gain, the supply voltage and the knee voltage.
In practice only a few of the classes of operation are useful for wireless
communication. The class A power amplifier is typically used for basestations as well
as mobile phone standards with high linearity requirements. The class AB power
amplifiers are used for a broad range of mobile phones. The class C power amplifiers are
also in use but typically introduce practical problems due to the relatively low output
power for a fixed transistor size.
The class B power amplifier does not exist in practical applications due to the
nonideal devices, which will cause the power amplifier to operate in either class AB or
C. The class D and E power amplifiers are difficult to use since they do not even
facilitate power control, class S on the other hand is almost impossible to use at RF
frequencies.
The only class of operation not in common use, which is suitable for wireless
communications is the class F power amplifier. The class F power amplifier is currently
the subject of a lot of research.
If one of the strongly nonlinear class of operation is to be used for wireless
communications one of the linearization systems will have to be introduced, but in
general they add complexity as well as lower the total efficiency.

References
[1] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Artech
House, 1999.
[2] H. L. Krauss, C. W. Bostian, and F. H. Raab, Solid State Radio Engineering.
John Wiley Sons, 1980.
[3] F. H. Raab, "Class-F power amplifiers with maximally flat waveforms," IEEE
Transactions on Microwave Theory and Techniques, vol. 45, pp. 2007--2012,
November 1997.
[4] N. O. Sokal and A. D. Sokal, "Class E - a new class of high efficiency tuned
single-ended power amplifiers," IEEE Journal of Solid State Circuits, pp. 168-
-176, June 1975.
[5] M. Iwamoto, J. Hinrichs, J. Arun, L. Larson, and P. M. Asbeck, "A push-pull
bandpass delta-sigma class-S amplifier," in 2000 IEEE Topical Workshop on
Power Amplifiers for Wireless Communications Technical Digest, September
2000.
CHAPTER 3
LOAD-LINE THEORY AND IMPEDANCE
MATCHING NETWORKS
As explained in Chapter 2 the load impedance along with the class of operation are
probably the most important aspects of power amplifier design. The source impedance
of the power amplifier stage will of course also have to be selected.
In the following sections a number of methods for selecting the source and load
impedances will be described. First the small-signal methods will be introduced, since
they are simple and can be based on S-parameter data which are usually available. After
the small-signal methods the large-signal methods will be described. The classical load-
pull measurement technique will be introduced. Then a similar simulation technique will
be developed for use in integrated circuit design.
After the proper source and load impedances has been selected, the impedance
matching networks must be synthesized. The different kinds of matching networks will
be described in this chapter. The steps involved in synthesis of the impedance matching
networks will also be explained. The synthesis methods will also be used as a part of the
load-pull simulation method.

3.1 Small-Signal Impedance Matching

The small-signal impedance matching approaches are primarily suited for small-signal
RF components such as LNAs. It is however useful to know the small-signal impedance
matching methods, since they can be used as a starting point for especially the matching
of the input of the power amplifier. The small-signal impedance matching methods are
all based on the properties of S-parameters which will be described shortly in the
following section.
To obtain maximum gain in a device the transducer gain method is used. It is
however not always desirable to achieve maximum gain match, since other parameters
such as noise and output power might be more important than the gain of the amplifier.
This means that the matching network is often a compromise between gain, output

23
24 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

power and noise. There are two methods to optimize the trade-offs of the matching
networks, namely the operating gain method and the available gain method. All of the
above mentioned matching methods will be described in the following sections.

3.1.1 S-Parameters
The scattering parameters, better known as S-parameters, is the most common set of
small-signal parameters used to characterize RF devices, active or passive. This is due
to the fact that Z and Y parameters can not be measured accurately at RF frequencies.
The difficulties of measuring Z and Y parameters at RF frequencies are caused by the
lack of good open and short terminations at RF frequencies. Furthermore the short-
circuits used in Z and Y parameter measurements, will often cause the device under test
(DUT) to become unstable.
The S-parameters are measured using normalized incident and reflected travelling
waves of transmission lines at the ports. The four parameters of a two-port S-parameter
measurement are:
S 11 = the input reflection coefficient

S 12 = the reverse transmission coefficient

S 21 = the forward transmission coefficient

S 22 = the output reflection coefficient

Once the S-parameters have been measured it is of course possible to convert them
to other small-signal representations, e.g. Z and Y parameters.

3.1.2 The Smith Chart

The Smith chart is used to represent the S-parameter data described above. The Smith
chart is a graphical representation of the reflection coefficient plane, the Γ plane, with
the relation
Z–Z
Γ = ---------------0-, Re [ Z ] ≥ 0 (3.1)
Z + Z0

where Z 0 is the reference impedance value. The basic Smith chart is shown in
Figure 3.1. The advantage of the Smith chart is that it is possible to depict all impedances
with a positive real part in a finite chart. The Smith chart is constructed of circles
representing constant resistance and constant reactance.
Another feature of the Smith chart is the possibility to plot a number of important
RF parameters as circles. Examples are stability circles, noise circles and constant Q
circles[1][2][3].
LOAD-LINE THEORY AND IMPEDANCE MATCHING NETWORKS 25

Figure 3.1 The Smith chart.

3.1.3 Transducer Gain Method

The maximum gain match condition is when no power is reflected at neither the input
port nor the output port, this will give the maximum small-signal gain of the device. This
maximum gain match is obtain by connecting a source with an impedance equal to the
complex conjugate to the impedance at the input port and a load equal to complex
conjugate to the impedance at the output port. This is called the transducer gain method
and can be used to obtain the maximum small-signal gain of a device. Depending on the
characteristics of the device, either the unilateral or bilateral method can be used.

Figure 3.2 Definition of impedances used for matching a two-port.

The matching networks can be constructed by inductors, capacitors and striplines.

The use of resistors is not optimal, since they will generate noise and dissipate power.
The actual implementation of the matching networks will be described in Section 3.3.
The impedances at the input and output ports of the device can be written as [3][4]:
S 12 S 21 Γ L
Γ IN = S 11 + ------------------------ (3.2)
1 – S 22 Γ L
26 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

S 12 S 21 Γ S
Γ OUT = S 22 + ----------------------- (3.3)
1 – S 11 Γ S

while the maximum gain achievable can be written as:

2 2 2
( 1 – Γ S ) S 21 ( 1 – Γ L )
G T = --------------------------------------------------------------------------------------------------2- (3.4)
( 1 – S 11 Γ S ) ( 1 – S 22 Γ L ) – S 12 S 21 Γ S Γ L

The maximum stable gain can be found from:

2
S 21
G MSG = ------------2- (3.5)
S 12

Unilateral Method
As mentioned above the unilateral transducer gain method can be used to optimize the
small-signal gain of a device. A two-port network is unilateral only if S 12 = 0 , that is
when there is no reverse gain. Even though a transistor is not unilateral the method can
still be used, but might not produce precise results. If it is assumed that S 12 = 0 , then
(3.4) can be rewritten as:
2 2
1 – ΓS 2 1 – ΓL
G TU = ----------------------------
-S
2 21
-----------------------------
2
(3.6)
1 – S 11 Γ S 1 – S 22 Γ L

It can be seen that the equation then consists of three terms. The first term depends
only on the source reflection Γ S and the input reflection of the device S 11 . The second
term depends only on the forward gain S 21 . The last term depends on Γ L and S 22 . It is
then obvious that the gain can be optimized by optimising the three terms separately. If
the device is left unchanged only Γ S and Γ L is left. The optimal solution is then the case
* *
where Γ S = S 11 and Γ L = S 22 . The maximum gain is then:
1 - S 2 ---------------------
1 - (3.7)
G TU, max = ---------------------
2 21 2
1 – S 11 1 – S 22

As mentioned above this expression is only accurate for a truly unilateral device,
and should be used with care on real devices.

Simultaneous Conjugate Match

The simultaneous conjugate match method can be used when the device is not unilateral.
The source and load terminations of the transistor can be derived from (3.4) [3]. The
matched source reflection is:
2 2
B 1 ± B1 – 4 C 1
Γ MS = -------------------------------------------- (3.8)
2C 1

where B1 and C1 are:

LOAD-LINE THEORY AND IMPEDANCE MATCHING NETWORKS 27

B 1 = 1 + S 11 2 – S 22 2 – ∆ 2 (3.9)
*
C 1 = S 11 – ∆S 22 (3.10)
∆ = S 11 S 22 – S 12 S 21 (3.11)

The matched load reflections is:

2 2
B 2 ± B2 – 4 C 2
Γ ML = -------------------------------------------- (3.12)
2C 2

and B2 and C2 are:

B 2 = 1 + S 22 2 – S 11 2 – ∆ 2 (3.13)
*
C 2 = S 22 – ∆S 11 (3.14)

3.1.4 Available Gain Method

The available gain method is used when the matching of the input port is the most
important as is the case for applications such as low noise amplifiers as well as the input
stage of a multistage power amplifier. The source impedance can be chosen arbitrarily
and the output of the device can then be conjugately matched [3][5].
2
1 – ΓS 2 1
GA = ----------------------------
- S 21 ---------------------------
- (3.15)
2 2
1 – S 11 Γ S 1 – Γ OUT

Equation (3.15) can be used to find the maximum gain for the given source
impedance, but to be able to make the trade-offs usually involved in RF design it can be
useful to have constant gain circles instead. The constant gain circles will indicate where
the gain has dropped by a certain amount, e.g. 1 dB. Combined with for instance the
noise circles often used in LNA design, it is possible to make a trade-off between gain
and noise. The output impedance associated with the center of the gain circle is:
2
1 – ΓS 2 1
GA = ----------------------------
- S 21 --------------------------------------
- (3.16)
1 – S 11 Γ S
2 S 22 – ∆Γ S 2
1 – ------------------------
1 – S 11 Γ S
GA
gA = ------------2- (3.17)
S 21
*
gA C 1
CA = ------------------------------------------------
2 2
- (3.18)
1 + g A ( S 11 – ∆ )

The radius of a gain circles is determined by:

28 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

2
1 – 2K S 12 S 21 g A + S 12 S 21 g A
rA = ---------------------------------------------------------------------------------
2 2
- (3.19)
1 + g A ( S 11 – ∆ )

In Figure 3.3 a typical set of constant gain circles are shown. The circles shown
represent the impedances where the gain has dropped 1, 2 and 3dB respectively.

S22

S11

Figure 3.3 Constant gain circles associated with the available gain method.

3.1.5 Operating Gain Method

When the selection of the load impedance is the most important parameter, as is the
case with power amplifiers, the operating gain method is used. Using the operating gain
method, the load impedance is arbitrarily defined, and the source is then matched. The
power gain can then be calculated as [3][6]:
2
1 2 1 – ΓL
G P = -------------------- S 21 ----------------------------
- (3.20)
2 2
1 – Γ IN 1 – S 22 Γ L

In (3.20) the input impedance is replaced by (3.2) giving

2
1 2 1 – ΓL
G P = ------------------------------------ S 21 ----------------------------
- (3.21)
S 11 – ∆Γ L 2
1 – S Γ
2
1 – ------------------------ 22 L
1 – S 22 Γ L

Since the operating gain method is good when the load impedance is already
chosen this will often be the small-signal matching method of choice when the source
impedance of a power amplifier is selected. As was the case with the available gain
LOAD-LINE THEORY AND IMPEDANCE MATCHING NETWORKS 29

method it is possible to draw gain circles based on the chosen load impedance. To
simplify the equations it is useful to define the variable gp:
GP
g P = ------------2- (3.22)
S 21

The center of a given gain circle is given by:

*
gP C2
C P = ------------------------------------------------
2 2
(3.23)
1 + g P ( S 22 – ∆ )

where C2 is defined as:

*
C 2 = S 22 – ∆S 11 (3.24)

As was the case for the available gain method it can be useful to plot gain circles.
The radius of the gain circle calculated by:
2 2
1 – 2K S 12 S 21 g P + S 12 S 21 g P
r P = --------------------------------------------------------------------------------
2 2
- (3.25)
1 + gP ( S 22 – ∆ )

In Figure 3.4 a typical set of constant gain circles are shown. If the device is
conditionally unstable part of the gain circles will be placed outside the Smith chart. The
GP,max can then be replaced by the maximum stable gain GMSG, an example of the gain
circles of a conditionally unstable device is shown in Figure 3.5. As can be seen in the
figure the gain circles intersect the Smith Chart in the same points as the stability circles.

S22

S11

Figure 3.4 Constant gain circles associated with the operating gain method.
30 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

S22
S11

Figure 3.5 Operating gain circles of a conditionally unstable device.

3.2 Large-Signal Impedance Matching

All of the methods described above are based on the small-signal behavior of the device,
but in a power amplifier the device is usually driven far into the nonlinear region of
operation. One way to take the large-signal model into account is the load-pull method.

3.2.1 Load-Pull Contours

Load-pull contours represents the behavior of a given parameter as a function of
the load impedance as was the case with e.g. the gain circles in the small-signal
approaches. Load-pull contours can be created using measurements, simulations or
analytical approaches. In the measured and simulated load-pull methods the load is
varied systematically while the source impedance is kept at a fixed impedance or
continuously kept conjugate matched according to the small-signal matching theory.
This can be performed with either measurements on a real device or within a large-signal
simulator.
The analytical approach to load-pull was introduced by S. Cripps in 1983 [7]. The
starting point in this approach is the ideal load-line theory, and the transistor is thought
of as an ideal current source with lumped parasitic elements. The basic idea is then to
identify which impedances will give e.g. the 1 dB contour. It is however cumbersome to
de-embed the intrinsic transistor and measured or simulated load-pulling will usually be
preferred. Furthermore it is virtually impossible to define a linear drain-source
capacitance in e.g. submicron CMOS, since this capacitance is very nonlinear.
LOAD-LINE THEORY AND IMPEDANCE MATCHING NETWORKS 31

One of the most common parameters plotted as a load-pull contour is the output
power at the 1dB compression point. When the simulations or measurements have been
performed the contours are found, e.g. the contour where the output power has dropped
1dB compared to the maximum achievable output power. An example of this plot is
shown in Figure 3.6, where the 1, 2 and 3dB output power contours are shown.
Unfortunately the large-signal contours are not circles as is the case for most small-
signal parameters. The large-signal contours can therefore not be manipulated as easily
as e.g. the small-signal gain circles.

Figure 3.6 1,2 and 3dB output power contours.

The output power at 1dB compression point is not the only interesting parameter
that can be found using load-pulling, other parameters that can be found are power added
efficiency and various distortion parameters. In practice all parameters of a power
amplifier that are measured or simulated to characterize a power amplifier can be used
in a load-pull analysis. Combining different types of contours gives the designer the
opportunity to make trade-offs based on the results. One of the most common trade-offs
is the one between output power and power added efficiency, the combination of output
power and power added efficiency contours is shown in Figure 3.7. The power added
efficiency contours are plotted in 5% steps relative to the maximum efficiency, while the
output power contours are in 1dB steps.

3.2.2 Load-Pull Measurement Systems

A basic load-pull measurement system is shown in Figure 3.8 [8]. Since a very large
number of measurements will have to be made, a computer is used to control the
measurement equipment. The heart of the system is a tuner placed at the output of the
power amplifier. The tuner transforms the load on its output from the standard 50Ω load
to any given impedance at the input of the tuner. Since there are parasitics between the
32 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Efficiency

Output power

Figure 3.7 Trade-off between output power (black) and power added efficiency (grey).

Figure 3.8 Basic Load-Pull System [8].

output of the power amplifier and the input of the tuner as well as some internal
parasitics the are some limitations to which impedances can be generated at the output
of the power amplifier.
The tuner can be implemented mechanically as for instance a sliding stub. The stub
can then be moved using a stepping motor. An important aspect when doing load-pull
measurements is the repeatability of the equipment, this means that the tuners should
reproduce exactly the same impedance every time they are used. If the repeatability is
not good the calibration performed before the actual measurements is without value.
To avoid the problems with repeatability in mechanical tuners it is possible to
implement electromechanical tuners using pin-diodes. This gives high repeatability and
switching speed, but the insertion loss is higher than in the purely mechanical tuner.
At last it is possible to use active tuners. The active tuners uses an auxiliary power
amplifier and a phase shifter to generate a virtual load impedance.
LOAD-LINE THEORY AND IMPEDANCE MATCHING NETWORKS 33

In the basic load-pull system only the fundamental frequency is tuned, but in more
complex systems it is possible to gain control of the impedances at a number of harmonic
frequencies. Since the measurements are done at discrete impedance points it is
important to choose these carefully. Often the impedance points are chosen such that
they give a uniform distribution in the Smith chart. It is seldom useful to get load-pull
data outside a specified impedance range, since only data a couple of dBs below
maximum gain are usable. In Figure 3.9 a typical set of load-pull impedance points are
shown.

Figure 3.9 Impedance points chosen for load-pull measurements

The input of the power amplifier is typically matched using one of the small-signal
methods or a fixed impedance point found experimentally. A signal generator is used to
generate the input signal. At the output a vector signal analyzer or power meter is
connected to the output of the tuner, to measure the desired parameters as a function of
the varying load impedance.
Once the tuner has been setup for the correct load impedance, the wanted
measurements can be performed. After the measurements have been performed the tuner
is moved to the next impedance point. Once all the impedance points have been visited
the computer will start postprocessing the data, this will then eventually result in the
load-pull contours mentioned in Section 3.2.1.

3.2.3 Simulated Load-Pull

The simulated load-pull method is related to the measured load-pull, but with the
important distinction that it is possible to use the simulated results during the design
phase. Instead of using the tuners and measurements the simulated load-pull will use
impedance matching networks and large-signal simulations. The large-signal simulation
34 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

can be either transient or steady-state, but the steady-state simulations will usually be
preferred for minimum simulation time. In place of the tuner an impedance transforming
network is used.
The wanted parameters, such as the output power and the efficiency, are then
extracted for each value of the load. When doing load-pull simulations it is important to
model the output device very carefully including the package.
The impedance used in the load-pull simulations can be realized in different ways.
The first and simplest way is to use a series or parallel combination of ideal resistive and
reactive components as shown in Figure 3.10.

Figure 3.10 Load-pull impedance realized as a series combination.

Another and perhaps more realistic way to implement the impedance is to select
the desired matching network topology and then calculate the necessary components
values for the desired impedance. The synthesis of the topology and values of the
components is the same as for the final networks and will be treated in the following
sections. This approach is shown in Figure 3.11.

Figure 3.11 Load-pull impedance realized as a matching network.

The advantage of the last approach is especially that the frequency dependence of
the matching network is built into the load-pull characteristics. This includes the
impedances at the harmonic frequencies, which will have an influence on the efficiency,
output power and distortion.
When the implementation of the load-pull impedance has been chosen, the
simulation is carried out. The wanted parameters will be simulated at each impedance
point selected. As was the case with measured load-pull the computer will postprocess
the data generated and derive the load-pull contours.
LOAD-LINE THEORY AND IMPEDANCE MATCHING NETWORKS 35

3.3 Synthesizing Impedance Matching Networks

When the source and load impedances have been chosen it is necessary to synthesize the
impedance matching network. This can be done using the Smith chart [3] or an analytical
method [9]. Both approaches have been integrated in CAD tools.
When designing impedance matching networks inductors, capacitances and
striplines are used almost exclusively, since resistive components are lossy. For size
critical applications such as mobile phones the striplines are not very well suited due to
their relatively large physical size.
The Smith chart is very useful, when designing impedance matching networks. The
effect of a component is drawn as described in Section 3.3.2. The synthesis of the
matching networks will be described for the graphical approach using the Smith chart as
well as the analytical approach suitable for CAD tools. The synthesis of the matching
networks are all based on alternating between series and parallel representation of the
impedances.
The synthesis will only be explained for ideal components without parasitic
effects. This is necessary to be able to keep the focus when designing the networks. Once
the topology has been selected and the values of the components chosen it is easy to use
a CAD tool to optimize the network to take the parasitic effects into account.
The bandwidth of a matching network is determined by the quality factor (Q) of
the network. It might therefore be important to choose a matching topology that allows
selection of the Q of the network. The Π and T matching sections allows increases in the
Q, while cascading matching section allows reduction of the Q. All of these methods are
described in the following sections.

3.3.1 Impedance Matching Basics

A complex impedance can be represented in either series or parallel form. This
duality is actually the basis of the impedance matching methods described in the
following. An impedance of R+jX can be represented in either parallel or series form as
illustrated in Figure 3.12.

Figure 3.12 Series and parallel representation of a complex impedance.

This relation is used when synthesizing the impedance matching network. The
network is synthesized by alternating between series and parallel impedance
representation. In practice this done by adding series and shunt components.
36 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

The complex impedances are handled by modifying the component closest to the
complex impedance. The basic principle in the handling of complex impedances is
absorption of the reactive part of the impedance.
If the component closest to the load or source is a series component the load or
source impedance will be represented by a resistor and a reactive part in series. If on the
other hand the component is a shunt component the parallel representation of the
impedance will be used.

3.3.2 Plotting Passive Components in the Smith Chart

As mentioned earlier the Smith chart is a very powerful graphically based tool, for RF
designs. Although the Smith chart is graphically based, it is possible to use it as a tool
for accurate impedance matching, especially when implemented in a CAD tool.
Usually only inductors or capacitors are used for impedance matching, and these
may be added as either series or shunt components. The series components follow the
constant resistance circles, while the shunt components follow the constant conductance
circles. The traces in the Smith chart caused by the components are shown in Figure
3.13.
It can also be useful to use striplines as part of the matching networks, but
depending on the use of the power amplifier it may be to area consuming on the PCB.
The striplines will follow circles with a center equal to the center of the Smith chart.

Figure 3.13 The effects of passive components plotted in the Smith chart.

3.3.3 The L Matching Section

Even though it is possible to design a large number of complex networks the simple L
sections turns out to be quite useful. The L sections, see Figure 3.14, are all the possible
combinations of a series and a shunt component. The frequency response of an L section
can be classified as either a low-pass or a high-pass filter. If the transformation and the
LOAD-LINE THEORY AND IMPEDANCE MATCHING NETWORKS 37

Figure 3.14 The L section matching networks.

frequency is determined for an L section, it is not possible to choose the transformation
Q of the section.
The L sections will either increase or decrease the resistive part of the impedance
depending on whether the first component is a series or shunt component. If the first
component is a shunt component the transformation will decrease the impedance. If
however the first component is a series component the impedance will be increased.
Since an L section with two capacitors or two inductors is not able to transform one
purely resistive impedance to another only a limited number of L sections are left for
general purpose transformations. For the general upward transformations two options
are therefore available, namely series C-shunt L and series L-shunt C. In the case of
downward transformation the options are shunt L-series C and shunt C-series L. These
cases are easily synthesized for arbitrary source and load impedances.
An example of an L matching network is illustrated in the Smith chart in Figure
3.15. The figure is generated by a CAD tool using the methods described here. The
impedance 10 - j10 should be matched to 50 + j20. In this example a low-pass network
has been selected and since the transformation is upward the network must be a Series
L-Shunt C network. The intermediate impedance in the matching network can be found
as:
Q = Re ( ZIN )Re ( YOUT ) – 1 (3.26)
1
Z B = Re ( Z IN )Q + j -------------------------
- (3.27)
Re ( Y IN )Q

X L = Im ( Z B ) + Im ( Z IN ) (3.28)
B C = Im ( Y OUT ) + Im ( Y B ) (3.29)
XL
L series = ------- (3.30)
ω
1
C shunt = ----------- (3.31)
BC ω
38 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Figure 3.15 L matching network synthesized using CAD tool.

3.3.4 The T Matching Section

Figure 3.16 A Tee section.

A T section consists of a series component, a shunt component and then another series
component. The T section actually contains two transformations. As was discussed in
the section about L sections the transformation is upwards when the first component is
a series component, then the shunt component transforms the impedance downwards
while the last series component compensates the reactive part of the impedance.
Compared to the L sections, this gives the additional freedom of specifying the
transformation Q of the matching network. When the T section is synthesized the Q of
an equivalent L section can be used as a starting point to set the lower bound on the
smallest transformation Q. If the transformation is upwards the first transformation Q is
the highest. If the transformation is downwards the second transformation Q is the
highest. It is not possible to reduce the highest transformation Q below the total
transformation Q with a T section.
An example of a T matching network is illustrated in the Smith chart in Figure
3.17. The highest transformation Q is set to 5. The network is synthesized by finding the
LOAD-LINE THEORY AND IMPEDANCE MATCHING NETWORKS 39

series component that will intersect the Q circle. The intersection impedance as the input
to an L section. The Q of an impedance point is given by the imaginary part of the
impedance divided by the real part.

Figure 3.17 T matching network.

3.3.5 The Π Matching Section

Figure 3.18 A Π section.

A Π section consists of a shunt component, a series component and then another shunt
component. As was the case for T sections, the Π sections allows for the specification of
the Q of the matching network.
As was the case with the T section the synthesis can be divided into two parts. The
first part is to find the component that will give the highest Q. When the transformation
is upwards the highest Q is in the second transformation. Again it is not possible for the
highest transformation Q to be lower than for the L section. An example of a Π matching
network is illustrated in the Smith chart in Figure 3.19.
40 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Figure 3.19 Π matching network.

3.3.6 Cascaded Matching Networks

If the transformation Q of a matching network is too high to sustain the bandwidth
needed it is possible to cascade two or more of the above mentioned basic matching
networks. For instance going from 1Ω to 50Ω would require a transformation Q of 7, if
however two sections were cascaded the required Q of each section would be reduced to
2.5. In Figure 3.20 two cascaded L sections are illustrated. The impact on the bandwidth
has been shown in Figure 3.21 where insertion loss of the two different circuits has been
simulated. The 3dB bandwidth is in this example increased from 560MHz to 1060MHz.
It is of course necessary to take the loss in the nonideal components into account
when deciding on the number of cascaded sections, since too many components may
increase the losses of the components above the loss due to the Q of the matching
network. The synthesis methods described here have all been implemented in the same
software program as the load-pull simulation framework. This enabled the use of load-
pull simulations using a more realistic impedance matching network.

3.4 Summary
The basics of impedance matching have been covered and small-signal as well as large-
signal impedance matching methods have been described.
Since no tools were readily available for simulated load-pulling a software
program was developed which will generate the input data to a large-signal simulator as
well as process the output from the simulator to give the load-pull contours. The program
LOAD-LINE THEORY AND IMPEDANCE MATCHING NETWORKS 41

Figure 3.20 Two cascaded L sections.

AC
Aplac 7.60 User: Nokia Corporation Mar 11 2001
11.00

6.15

1.30

-3.55

-8.40
1.000G 1.500G 2.000G 2.500G 3.000G
Freq
MagdB(Spectrum MagdB(Spectrum

Figure 3.21 Insertion loss of one or two cascaded L section.

generates all information needed by the simulator and postprocesses the output data from
the simulator thereby generating the output power and efficiency contours.
Furthermore the synthesis of the impedance matching networks has been
described. The synthesis is generic and handles purely resistive as well as complex
termination impedances. The synthesis of impedance matching networks with complex
terminations has been presented with a combination of graphical and analytical aids.
The synthesis of impedance matching networks was used in conjunction with the
load-pull simulations. The simulated load-pull method proves to a very powerful tool
during the design phase. This is due to the immediate retrieval of measures of the
42 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

optimized performance of the circuit. Using the simulated load-pull method it is possible
to use the obtain contours to make the necessary trade-offs between output power and
efficiency. When these results are available in the design phase it is possible to optimize
the circuit in an iterative process.

References
[1] P. H. Smith, Electronic Applications of the Smith Chart. In Waveguide, Circuits
and Components Analysis. McGraw-Hill, 1969.
[2] Hewlett-Packard, Application Note 95, S-Parameters, Circuit Analysis and
Design. Hewlett-Packard, September 1968.
[3] G. Gonzalez, Microwave Transistor Amplifiers, Analysis and Design. Prentice-
Hall, 2 ed., 1997.
[4] L. Besser, "RF/MW amplifier design," Applied Microwave Wireless, 1995.
[5] L. Besser and R. Frobenius, "Available gain amplifier design," Applied
Microwave Wireless, 1996.
[6] L. Besser and R. Frobenius, "RF/microwave amplifier design," Applied
Microwave Wireless, 1996.
[7] S. Cripps, "A method for the prediction of load-pull power contours in GaAs
MESFETs," in 1983 IEEE MTT-S International Microwave Symposium, 1983.
[8] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Artech
House, 1999.
[9] P. L. D. Abrie, Design of RF and Microwave Amplifiers and Oscillators. Artech
House, 1999.
CHAPTER 4
STABILITY AND BIASING
After choosing the class of operation and the impedance matching networks the basic
behavior of the power amplifier has been determined. Two important issues which will
also have to be taken into account when designing the matching networks are stability
and biasing. Although these two topics do not directly affect properties like the
efficiency of the power amplifier, they might cause the power amplifier to fail.
In the first part of this chapter the biasing of the power amplifier will be discussed.
The biasing networks are discussed first since they influence the matching networks as
well as the stability of the power amplifier.
In the remaining part of this chapter the stability of power amplifiers will be
discussed as well as some measures to improve the stability of the power amplifier. The
stability problems in a power amplifier can be divided into two types. The first problem
is in-band oscillation caused by an unstable transistor. The second problem is instability
caused by the biasing networks.

4.1 Bias Circuits

The biasing of the device is an important issue, since incorrect biasing may result in
unstable or dysfunctional circuits. In order to minimize the effect of the biasing network,
it has to be considered already when designing the matching networks. Some topologies
for the matching networks can be used for biasing without modifications.
The biasing of CMOS transistors is usually easier than of bipolar transistors, since
no DC power is consumed at the input.

4.1.1 DC Isolation
The input and output of a power amplifier is usually AC coupled, in order to get rid of
the DC components. The DC isolation makes the biasing of the transistor much easier,
since it is possible to set the input of the transistor to a specific DC value, without regard
to the DC level of the input signal.

43
44 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

For a class B amplifier the input of the transistor will be DC biased exactly at the
cut-off point. The DC isolation can be obtained with a series capacitor. The series
capacitor will prevent a DC current to flow through it, but depending on the size of the
capacitor an RF signal will flow unrestricted. It is then possible to apply a DC voltage
after the capacitor to control the operation of the transistor.

4.1.2 RF Isolation
When applying the DC voltage as described above it is important to have good RF
isolation, in order to keep the full input signal swing. This can be done with a series
inductor which will allow a DC current to flow, but will restrict the RF signal depending
on the size of the inductor. It is also possible to use a microstrip for the purpose of RF
isolation, especially the quarter wavelength microstrip is useful. An example of a bias
circuit for a MOSFET power amplifier using the DC and RF isolation techniques is
shown in Figure 4.1.

Figure 4.1 Bias circuit for MOSFET power amplifier.

4.1.3 Generating the Bias Signals

The DC signals can be applied directly from external signals or generated in the circuits
based on an external signal. The DC signals will often be used dynamically for e.g.
power control. When the bias signals are generated on-chip they can be purely passive
circuits or active circuits which for instance provide temperature compensation.
Examples of passive as well as active bias circuits are illustrated in Figure 4.2.

Figure 4.2 Passive and active bias circuit.

STABILITY AND BIASING 45

4.2 Stability of Power Amplifiers

A device can be characterized as either conditionally unstable or unconditionally stable.
An unconditionally stable device is stable no matter what passive source and load
impedances are connected to the ports of the device. A conditionally unstable device
does not fulfil this requirement, and might start oscillating under certain conditions
[1][2].
It is therefore important to analyze the stability of a device before using it in a
power amplifier. Although the device might be stable with the nominal source and load
impedances, these might change due to a shift in temperature, supply voltage or antenna
shielding. It is therefore necessary to characterize the device under all realistic operating
conditions.

4.2.1 Stability Circles

One way of visualizing the stability of the power amplifier is through stability circles.
The conditionally unstable regions of the source and load impedances can be represented
by stability circles in a Smith chart. The stability circle for the source impedance is given
by the center and a radius [2]:
( S 11 – ∆S 22∗ )∗
C S = ------------------------------------
2 2
- (4.1)
S 11 – ∆

S 12 S 21
r S = ---------------------------
- (4.2)
2 2
S 11 – ∆

∆ = S 11 S 22 – S 12 S 21 (4.3)

The center is a coordinate to be plotted in the Smith chart while the radius defines
the contour. Whether the inside or the outside area of the circle is the stable region, has
to be determined. This check can be performed by checking the stability of a single point.
The stability circle for the load can be found equivalently:
( S 22 – ∆S 11∗ )∗
C L = ------------------------------------
2 2
- (4.4)
S 22 – ∆

S 12 S 21
r L = ---------------------------
- (4.5)
2 2
S 22 – ∆

Since the stability circles are calculated using S-parameters it is obvious that they
depend upon the frequency. To assure that the device is stable over the entire frequency
range, it is therefore necessary to plot the stability circles at a number of frequency
points. Typical stability circles for a device is shown in Figure 4.3.
The device can be stabilized in a number of ways as described below, after the
stabilisation it is then useful to extract new S-parameters for the stabilized device.
46 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

a) Typical source stability circle. b) Typical load stability circle.

Figure 4.3 Stability circles.

4.2.2 Resistive Stabilisation

One of the ways to stabilize a device is resistive stabilisation, this is usually at the
input of the device, by connecting a resistor in series with the device. The input of the
resistor is then considered to be the input port of the device. In this way it will never be
possible to obtain an effective resistance lower than that of the resistor, and the
conditionally unstable region can therefore not be reached. The resistive stabilization is
shown in Figure 4.4, where the input impedance is then restricted to the grey area in the
Smith chart.

a) Resistive stabilisation principle. b) Resistive stabilisation circuit.

Figure 4.4 Resistive stabilisation.

If the stability is better at higher frequencies, which is usually the case, the effect
of the resistor can be reduced at high frequencies, with a parallel capacitor. The parallel
capacitor will then reduce the effective series resistance at higher frequencies.
STABILITY AND BIASING 47

4.2.3 Conductive Stabilisation

a) Conductive stabilisation principle b) Conductive stabilisation circuit.

Figure 4.5 Conductive Stabilisation
The conductive stabilisation is used at the output of the device to insure that the
load impedance will never exceed a certain value. This is done by putting a resistor is
parallel with the device. The shunt resistor restricts the achievable output impedance to
the grey area in the Smith chart in Figure 4.5.
If the stability is better at high frequencies, the effect can be reduced as with the
resistive stabilisation. For conductive stabilisation this is done by means of a series
inductor. The series inductor will then increase the effective shunt resistance at the
output node.

4.2.4 Feedback Stabilisation

The feedback stabilisation can be used as a supplementary to the other two methods. In

Figure 4.6 Feedback stabilisation.

addition to the stabilizing effect of feedback, the device will often be more linear than
prior to the feedback.
48 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

4.3 Bias Circuit Instability

As mentioned above one cause of instability in a power amplifier is the matching of the
device. Another cause is instability in the bias networks [3]. The instability in the bias
networks is probably the most common source of oscillation in practical power amplifier
designs.
To prevent instability caused by the bias circuit it is important to make sure the bias
signal is filtered properly. An example of a bias circuit with low-pass filtering is shown
in Figure 4.7.

Figure 4.7 Example of stable bias circuit.

4.4 Verifying Stability through Simulations

It is very difficult if not impossible to prove during the design phase that a power
amplifier is unconditionally stable in all operating conditions, but it is possible to give
strong indications. In principle all of the following simulations must be performed at all
operating conditions as well as all process corners. First of all the small-signal methods
based on S-parameters described above will have to be applied to the power amplifier,
but this will only reveal some of the potential problems and other methods will have to
be introduced.
One of the ways to find instability is through transient simulations. Typically a
node in the circuit is excited by a short pulse, this might start an oscillation in the circuit.
If an oscillation is started it is observed whether the amplitude of the oscillation is rising
or falling. If the amplitude rises a stability problems exists, if the amplitude is falling
further investigation is needed. The energy in the pulse might then be changed or some
of the operating conditions changed. If none of the modifications leads to an oscillation
with rising amplitude the circuit is most probably stable. This procedure will have to be
applied to all critical nodes in the circuits, especially the input port and the bias node.
Another method for revealing stability problems is focused on bias circuit stability.
The method is the small-signal analysis described above, where the RF ports are
analyzed based on the S-parameters. In addition to the RF ports the bias ports are
STABILITY AND BIASING 49

included in the S-parameter analysis. If not all ports are unconditionally stable over all
frequencies from DC to well above the operating frequency a stability problem might
exist.

4.5 Summary
Although it is possible to make a device unconditionally stable it is usually not desirable
in a power amplifier, since it will have a rather large impact on the performance of the
device. Instead the stability regions of the device is then compared with the expected
input and output impedances of the device.
Unlike the single active device it is often impossible to prove a complete power
amplifier to be unconditionally stable in the given operating conditions. It is however
possible to get a reasonable reassurance through the simulation methods described
above.

References
[1] L. Besser, "Avoiding RF oscillation," Applied Microwave Wireless, 1995.
[2] G. Gonzalez, Microwave Transistor Amplifiers, Analysis and Design. Prentice-
Hall, 2 ed., 1997.
[3] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Artech
House, 1999.
50 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS
CHAPTER 5
CMOS TECHNOLOGY
The choice of technology is affected by a large number of parameters, such as maximum
operating frequencies, substrate behavior, breakdown voltages, yield and cost. In the
following the choice of CMOS for this project will be motivated. The modeling of
CMOS transistors will be described along with some of the important features of the
CMOS process such as the breakdown effects.
In the last part of this chapter the modeling of complete power amplifiers is
discussed, this includes the passive components on-chip or off-chip as well as packages
and PCBs.

5.1 Basic RF CMOS Behavior

The CMOS technologies are very cheap and are already used almost exclusively in
the baseband part of a mobile phone. The most advanced CMOS technologies have gate
lengths well into the deep submicron range. The maximum operating frequencies of
these devices, are high enough for wireless RF applications. The main obstacles in
CMOS are the low breakdown voltages and the large parasitics associated with the
substrate. In the following section a simplified equation is given for the I-V
characteristics of a MOS transistor including the knee voltage. The RF properties of a
MOS transistor are rather complicated and will not be discussed here. The interested
reader can find further information in [1].

5.1.1 I-V Characteristics

The I-V characteristics of a CMOS transistor is quite simple for long channels, but
becomes complicated for short channels [1]. The strong inversion region is the most
important operating region for transistors used in power amplifiers. The simple models
divide the strong inversion into non-saturation and saturation. The boundary between
non-saturation and saturation is given by:
V GS – V T
V' DS = ----------------------- (5.1)
α

51
52 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Figure 5.1 I-V characteristic of a typical submicron NMOS transistor [1].

where α is a process dependent parameter. This drain voltage is the same as the
knee voltage discussed in Chapter 2. The drain current is given by:

W α 2
 -----µC' ox ( V GS – V T )V DS – ---V DS ,V DS ≤ V' DS
L 2
I DS =  (5.2)
2
 W ( V GS – V T )
 -----µC' ox ------------------------------- ,V DS > V' DS
 L 2α

These equations are of course very crude, but gives an impression about the I-V
characteristics of a MOS transistor used for power amplifiers. The I-V characteristics are
illustrated in Figure 5.1.

5.1.2 Breakdown Phenomena

A number of breakdown mechanisms can occur in semiconductor devices, common to
them all are that a large unwanted current starts flowing due to a high voltage applied to
one of the terminals. With exception of the oxide breakdown the breakdown
mechanisms are nondestructive, if the large currents are handled appropriately. The
breakdown phenomena in question for power amplifiers are described below.
The PN junction breakdown effects are all initiated in the border region of the
junction, when a sufficiently large reverse voltage is applied. If the circuit can handle the
increased current, the breakdown is not destructive.
CMOS TECHNOLOGY 53

Avalanche Multiplication
The avalanche breakdown occurs in reverse biased PN junctions [2][3]. The avalanche
breakdown causes the current to increase drastically. The voltage at which the avalanche
breakdown occurs depend upon the doping profile of the junction, the breakdown
voltage can be from a few volts to thousands of volts.
The avalanche breakdown is caused by some of the minority carriers gaining
enough energy to break a covalent bond. This process known as impact ionization causes
the creation of a new hole-electron pair. The creation of new hole-electron pairs
increases the probability of impact ionization. This multiplication effect is why the
phenomena is called avalanche breakdown.

Oxide Breakdown
The oxide breakdown is destructive in contradiction to the other forms of breakdown
mentioned above [1]. The oxide breakdown occurs when a large voltage is applied over
the gate oxide of a MOSFET. The effect on the transistor is a permanent short circuit
through the insulator. The oxide breakdown can be caused by static charge, this means
that ESD protective circuits must be used if an input is connected directly to the gate of
a MOSFET.

Hot Carrier Effects

The hot carrier effects are not exactly a breakdown phenomena but rather a stress
problem. The hot carriers are generated when carriers collide. The new carriers
generated by the collisions are called hot carriers. If these carriers acquire enough energy
they may cross the silicon-oxide barrier and cause damage in the gate-oxide. This causes
aging of the CMOS devices, due to charges trapped in the gate-oxide [1].

5.2 Comparison to Other Technologies

Although the focus has been on CMOS till now a number of other technologies are
available for the power amplifier designer. These technologies will be discussed briefly
in the following sections.

5.2.1 SOI
The Silicon On Insulator (SOI) technologies are now almost mature, the properties are
mostly the same as in CMOS, but the parasitics associated with the substrate are lower
due to the insulator. This means the operating frequency is higher and the passive
components will be better as well.
The breakdown voltage of an SOI transistor is dependent upon the type of the
transistor. There are generally two types of transistors: thin-film and thick-film. In a
thick-film transistor the region between the drain and the source is not fully depleted, and
there will be a region controlled by the gate, one controlled by the substrate and a neutral
54 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

region in the middle. The neutral region forms an open-base parasitic bipolar transistor
along with the drain and source.
In a thin-film transistor the region between the source and the drain are fully
depleted and no neutral region exists. An open-base bipolar transistor has a rather low
breakdown voltage, and this means that the breakdown voltage of a SOI transistor is
even lower than that of a CMOS transistor. Besides the low breakdown voltages poor
thermal conduction seems to be the largest problem.

5.2.2 LDMOS
The laterally diffused MOS (LDMOS) transistor is made of the same materials as the
standard CMOS transistor, but with some important changes in the structure to allow for
higher breakdown voltages. The main drawback of the LDMOS process is that the cost
is higher than CMOS without gaining anything but higher breakdown voltages. The
integration level is usually lower than in CMOS technologies.

5.2.3 GaAs MESFET

The GaAs MESFET transistors have previously been used extensively for power
amplifiers, but now GaAs HBTs seems to be preferred. One of the main drawbacks of
the GaAs MESFET processes is the relatively small wafers of typically four inches and
the low yield which leads to a high cost. Furthermore the transistors are depletion mode
devices, which implies the need of an additional negative supply voltages for biasing [4].
Due to the high resistivity substrate, the passive components are usually better than in
CMOS technologies.

5.2.4 Silicon BJT

The silicon bipolar junction transistors (BJT) have a slightly higher cut-off frequency
than an equivalent CMOS transistor. The cost of a pure bipolar process is a bit higher
than CMOS. As is the case for all other technologies it is difficult to achieve the same
level of integration as CMOS.

5.2.5 GaAs HBT

The Gallium Arsenide (GaAs) hetero-junction bipolar transistors (HBT) are widely used
for RF power amplifiers. Compared to a normal bipolar transistor the transconductance
and the cut-off frequency are higher. Typically no PNP devices are available in the
process. The considerations about wafer size and yield are the same as for GaAs
MESFET. As in GaAs MESFET technologies the passive components are decent [4].

5.2.6 SiGe HBT

The Silicon Germanium (SiGe) HBTs have been considered for power amplifiers, but
problems arise with the relatively low breakdown voltages compared to GaAs HBT.
CMOS TECHNOLOGY 55

Otherwise the SiGe HBTs are placed between ordinary bipolar processes and GaAs
HBTs with regard to performance as well as cost [5].

5.3 Simulation Models

There are a large number of simulation models available for MOS transistors, but only
three of them are suitable for RF circuits. The three models are BSIM3, MOS9 and EKV,
the foundations on which they are based are very different. Recently a fourth model has
been introduced namely the BSIM4 model. The difference in foundations of the models
gives rise to advantages and disadvantages when comparing the models. In the following
sections the models will be described briefly.

5.3.1 BSIM3
The BSIM3 model started out as a physically based model, but over time it progressed
into a more empirically based model with extra parameters for a lot of physical effects.
The BSIM3 model is the most widely used model for analog circuits.
The BSIM3 model is backed up by the Compact Modeling Council (CMC) which
is an industry association lead by the CAD vendors.

5.3.2 MOS9
MOS9 was from the beginning meant as an empirically based model, with the drawbacks
and benefits of empirical models. The drawback is mainly that the model does not scale
very well. The MOS9 model has earned a reputation as one of the best RF models,
furthermore it is supposed to model noise more accurately than the other simulation
models.
Although MOS9 is probably the best RF model now the future of the model seems
short. The analytical models such as BSIM3, BSIM4 and EKV are preferred due to better
ability to cover very different transistor geometries.

5.3.3 EKV
The EKV model was developed primarily by Enz, Krummebacher and Vittoz, hence the
name. The EKV model can be considered a back to the basics model, compared to
BSIM3 and MOS9.
The purpose of the EKV model is to provide a model which has a better transition
from weak inversion to strong inversion. Furthermore the EKV model facilitate hand
calculations on the same set of device parameters as for the precise CAD model.
Although very promising the EKV model has not yet reached a point at which the
model can be considered mature enough for commercial applications.
56 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

5.3.4 BSIM4
BSIM4 is the latest model from UC Berkeley and is based on BSIM3, this means that
the drawbacks and benefits of the BSIM3 is maintained. The most important
improvement of the model is the inclusion of layout related information. This means that
the BSIM4 model will be able to accurately predict the performance of e.g. a finger
transistor. The layout information is layout type, number of fingers and related
parameters.
As was the case for BSIM3 the BSIM4 model is supported by CMC, this means
that BSIM4 will probably dominate the modeling scene in the years to come.

5.3.5 Layout Related Issues

In order to simulate the behavior of a MOSFET precisely it is necessary to add
some information about the layout to the models. This is primarily done through the
specification of the areas and perimeters of the drain and source regions of the transistor.
In the simple case of a one finger transistor this is done easily, but the multifinger
transistors are used the calculation gets more involved. The only model which handles
these layout issues so far is the BSIM4 model.
Apart from the drain and source areas and perimeters the gate resistance is
probably the most important parameter for RF designers. The gate resistance is usually
not included in the transistor models from the vendor, it is therefore important to take
into account. The gate resistance can be calculated by assuming that the effective
resistance is equal to the resistance to the center of the gate [6].

Figure 5.2 Enhanced RF MOS transistor model.

5.4 Modeling of Modules

The modeling of the RF transistors is not the only problem when modeling a power
amplifier. A number of passive components will be placed on the chip as well as on the
PCB. Furthermore modeling of the package is of importance to achieve good results.

5.4.1 Capacitors
The modeling of on-chip plate capacitors is relatively simple compared to the
inductors, if care is taken during the layout phase. The capacitor can be modeled by the
CMOS TECHNOLOGY 57

intended capacitor, with an additional capacitor from the bottom plate to the substrate.
A parasitic series resistance is associated with each of the two plates. Usually a careful
design of the capacitor renders the used of a distributed model superfluous.

Figure 5.3 On-chip capacitor model.

Poly-poly capacitors are similar to metal-metal capacitors, but since the plates are
made of polysilicon instead of metal the series resistance associated with the capacitors
are typically 10-50 times larger than for metal-metal capacitors. This can to some extent
be reduced by designing the capacitor very carefully, but the performance will never be
as good as metal-metal capacitors.
Apart from the plate capacitors a number of other capacitors are available in a
CMOS process. Most commonly used is the MOS capacitor made up by the gate-oxide.
Due to the very thin gate-oxide the density of MOS capacitors is very high, but one of
the terminals have to be grounded. Since the density is high and one of the terminals is
grounded the MOS capacitors are used primarily for decoupling. The modeling of the
MOS capacitors is simply an ordinary MOS transistor with drain, source and bulk
connected as on of the terminals and the gate as the other terminal.

5.4.2 Spiral Inductor

Over the last couple of years a lot of research effort has been put into the
characterization and modeling of the on-chip inductors. Although no satisfactory
solution is yet available it is now possible get good models of the inductors during the
design phase.
Almost all of the models are based on a Π network as shown in Figure 5.4. One of
the more complete inductor models is shown in Figure 5.5 [7].
Some foundries have included scalable inductor generators and models in their
design kits. For instance STMicroelectronics has a scalable model based on Figure 5.5.
Using this approach the use of on-chip inductors is greatly simplified for the designer.

5.4.3 Interconnects
One of the important things when trying to simulate a complete chip is to maintain
the overview. If all interconnects were modeled regardless of their impact on the
performance, the simulation speed would increase drastically and hence prevent
58 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Figure 5.4 Simple Π network inductor model.

Figure 5.5 On-chip inductor model.

simulation of the complete chip. It is therefore important to carefully select which
interconnects should be modeled. In most cases it is sufficient to model the interconnects
with RLC networks. A simple model of a metal wire is shown in Figure 5.6.

Figure 5.6 Simple RLC network metal wire model.

5.4.4 Packaging
There are generally two different packaging topologies, the ordinary chip package
usually in plastic and the chip-on-board approach (COB). The package contains the
leadframe of the package as well as the bondwires, while the COB approach only
contains bondwires.
The bondwires are an important part of the entire RF design. The bondwires have
inductance, capacitance and resistance associated with them. The self-inductance of a
bondwire is [8]:
CMOS TECHNOLOGY 59

⋅ l ln  2l
----- – --- + - H
–6 3 r
L = 0.2 ⋅ 10 (5.3)
r 4 l

where l is the length of the wire and r is the radius of the wire. The mutual
inductance between the two parallel bondwires of equal length is:
2 2 d
M = --l- ln  --- + 1 +  --l-  –  1 +  d--- + --- H
l
(5.4)
5 d d l l

where d is the distance between the wires.

Using these two and related formulas it is possible to calculate the complete
inductance of the wires used for a single signal as well as the coupling to other signals.
More complicated equations exists for the mutual inductance of bondwires not parallel
and of different length [8]. Using these equations it is also possible to model the
bondwires in the package.
The leadframe is usually characterized using a electro-magnetic finite-element
simulator, a lumped model is then extracted from the simulator. In Figure 5.7 an example
of the package model is shown for a single pin. Between the different pins capacitive as
well as inductive couplings exist as sketched in the figure.

Figure 5.7 Leadframe model for two adjacent pins.

5.4.5 PCB
The PCB is modeled using microstrips. In some simulators e.g. APLAC, a number
of microstrip components are implemented. If the microstrips elements, e.g. Tees and
Stubs, are not implemented is possible to make macromodels for them, as long as the
basic microstrip is implemented in the simulator.
Another part of the PCB modeling is the passive components used in e.g. the output
matching network. Usually the vendors of the SMD components deliver frequency
dependent models of their components. These models are usually sufficient to get
accurate simulations.
60 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

5.4.6 Thermal Modeling

In power amplifier modeling it is important to include the thermal effects of the
power dissipation in the transistors. The thermal network is modeled with equivalent
current sources, capacitors and resistors modeling the heat generation, thermal capacity
and thermal resistance respectively [9][10][11]. A very simplified thermal model of the
power amplifier is shown in Figure 5.8.

Figure 5.8 Simplified thermal model of a power amplifier.

5.5 Summary
A number of technologies with very different properties are available for power
amplifier designers. The CMOS technology is very attractive in low-cost designs as well
as highly integrated transceivers.
The cost of a CMOS power amplifier is probably always going to be the lowest
possible, since the production cost and yield is better than any other technology,
furthermore the integration level is also very high.
The low breakdown voltages of CMOS is a problem compared to some of the other
technologies in question, but the low voltage performance of the transistor is better than
most other technologies. This means that a CMOS power amplifier can be operated on
the same supply voltages as the digital logic in the baseband part of the transceiver.
The modeling of RF power amplifiers is very troublesome, if accurate results are
expected. It is however possible to accurately model the power amplifiers by using the
models described in this chapter.

References
[1] Y. Tsividis, Operation and Modeling of the MOS Transistor. WCB/McGraw-
Hill, 2 ed., 1999.
[2] S. M. Sze, Semiconductor Devices, Physics and Technology. John Wiley Sons,
1985.
[3] R. M. Warner and B. L. Grung, Semiconductor-Device Electronics. Holt,
Rinehart and Winston, 1991.
CMOS TECHNOLOGY 61

[4] H.-O. Scheck, "Semiconductor technology handbook." Nokia Research Center,

1997.
[5] P. L. D. Abrie, Design of RF and Microwave Amplifiers and Oscillators. Artech
House, 1999.
[6] T. E. Kolding, "Calculation of MOSFET gate impedance," tech. rep., Institute
of Electronic Systems, Aalborg University, Aalborg, Denmark, August 1998.
[7] A. M. Niknejad and R. G. Meyer, "Analysis, design and optimization of spiral
inductors and transformers in Si RF ICs," IEEE Journal of Solid-State Circuits,
vol. 33, October 1998.
[8] F. W. Grover, Inductance Calculations, Working Formulas and Tables. D. van
Nostrand Company, Inc., 1946.
[9] C. Schaeffer, J.-P. Ferrieux, R. Perret, and B. Reymond, "Thermal simulation in
power electronics," IEEE, 1992.
[10] L. Hebrard, C. Klingelhofer, G. Jacquemod, B. Boutherin, and M. L. Helley,
"SETIPIC Electrothermal simulator for power integrated circuits in EDGE
environment," IEEE, 1992.
[11] K&K Associates, Thermal Network Modeling Handbook. K&K Associates,
2000.
62 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS
CHAPTER 6
DESIGN METHOD FOR INTEGRATED
POWER AMPLIFIERS
The design of power amplifiers has so far involved some amount of black magic
performed by experienced RF designers. A large part of this work has focused on
removing at least some of the black magic in power amplifier design. During the design
process a lot of choices will have to be made, if just one of the choices are wrong the
whole project is in jeopardy. The following design method will try to formalize the
decision process. A number of design methods have previously been published but have
all focused on single stage power amplifiers [1][2][3][4][5][6].
The design process starts at the output stage of the power amplifier, since this stage
will influence the rest of the power amplifier. The design will therefore start at the output
load and work backwards through the power amplifier.
The overall design flow is illustrated in Figure 6.1. As can be seen from the figure
the design flow is divided into three major parts. In Initial Design Decisions decisions
about differential or single-ended operation and the number of amplifying stages are
made. In Stage Design the individual stages of the power amplifier are designed. In
Combination of Stages the designed stages are combined. After the combination of the
individual stages the complete power amplifier is evaluated. If the result is not
satisfactory the individual stages are redesigned.

Figure 6.1 Overall design flow.

63
64 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

6.1 Initial Design Decisions

Before the actual design of the power amplifier starts a number of initial decisions will
have to be made. This includes the choice of the single-ended or differential operation,
the number of stages and a budget for gain and efficiency. The design flow for the initial
design decisions is shown in Figure 6.2.

Figure 6.2 Design flow for initial design decisions.

6.1.1 Differential or Single-ended Operation

As discussed in Chapter 2 there are a number of benefits and drawbacks of differential
operation of the power amplifier. The choice between single-ended and differential
operation will always be a trade-off between a number of different factors. It is also
possible to switch between differential and single-ended operation somewhere in the
power amplifier chain.

6.1.2 Number of Stages

The next decision to make is to decide on the number of stages in the power amplifier.
The number of stages is restricted by a number of requirements. The total gain necessary
along with the maximum gain of a single stage sets the absolute minimum number of
stages. The isolation obtainable in each stage and the total isolation needed also sets a
lower limit. Power control is another example that may increase the minimum number
of stages, but additional stages increase the cost and complexity of the power amplifier
and it is therefore desirable to keep the number of stages low. Another upper limit is set
by the total efficiency of the power amplifiers, since each extra stage will lower the total
efficiency of the power amplifier.

6.1.3 Gain & Efficiency Budget

To be able to design the individual stages in the following steps, it is necessary to have
information about the behavior of the individual stages. A budget is therefore made for
key parameters like gain and efficiency of the stages.

6.2 Design of Individual Stages

After the initial design decisions have been made, the actual design of each stages in the
power amplifier starts. The first stage to be designed is the output stage, since most of
the characteristics of the power amplifier will be derived from this stage. The necessary
output power from the preceding stage is also determined by the output stages. This
DESIGN METHOD FOR INTEGRATED POWER AMPLIFIERS 65

means that it is most rational to work backwards through the chain and start with the
output stage and stop with the input stage. In some applications however it will be more
convenient to start with the output stage then design the input stage and at last design the
remaining stages.
The design flow for the design of the individual power amplifier stages is shown
in Figure 6.3. First of all the class of operation is selected, then the transistor is designed
and at last the load and source impedance matching network are designed.

Figure 6.3 Design flow for individual stage design.

6.2.1 Class of operation

The choice of class of operation is the first decision to make in the design of the stage.
As described in Chapter 2 the mode of operation influences almost all parameters of the
power amplifier including linearity, gain and efficiency.
The class of operation of each stage is a trade-off between a number of factors. The
factors include linearity, power gain, efficiency, breakdown voltage and load
impedance. The individual stages of the power amplifier do not necessarily all operate
in the same class.
First of all the linearity requirements must be fulfilled for very high linearity
requirements such as that for base station power amplifiers class A will be a natural
choice. On the other hand constant envelope standards like GSM have very low linearity
requirements and most modes can be used. The newer standards such as EDGE and WB-
CDMA is placed somewhere in between and class AB could be a reasonable choice.
The efficiency and gain is the next thing to take into account. Although the drain
efficiency is in theory higher for reduced and switching mode amplifiers, the power
added efficiency may not differ that much due to the relatively low power gain of these
classes, this is especially true for low gain devices with 9-12 dB gain.
Another thing to take into account is the breakdown voltage of the output transistor,
this is especially true for CMOS, where the destructive breakdown of the gate-oxide
occurs at a relatively low voltage. Class C and E will results in voltage swings of 3-5
times the supply voltage. While class A, AB and B only have double voltage swing.
66 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

6.2.2 Transistor Sizing and Load Impedance Selection

An initial guess of the transistor size originates from the I-V characteristic of the
transistor. After an initial value is selected the more accurate RF behavior is found using
load-pull simulations. The design flow for transistor sizing and load impedance selection
is illustrated in Figure 6.4.

Figure 6.4 Design flow for transistor sizing and load impedance selection.

The load-pull simulations are the simulation equivalent of the load-pull

measurements [7]. The load-pull simulation determines not only the transistor size but
also the load impedance. In practice the load-pull simulation sweeps a range of
impedance points and draws e.g. power, efficiency and linearity contours. This is done
with either an ideal load impedance or a matching network with the desired topology. If
the matching network is chosen it will have to be synthesized at each impedance point,
but the results resembles the actual performance more closely. The load impedance is
then chosen as a trade-off between e.g. output power, efficiency and linearity. The load-
pull simulations are described in more detail in Chapter 3. The impedances at harmonic
frequencies are part of the definition of the mode of operation and is therefore defined
by the selection of the class of operation.

6.2.3 Source Impedance Selection

The source impedance can be found using the small-signal impedance matching
methods described in Chapter 3 [8]. Using one of the small-signal method with the load
impedance found in the previous step, a single source impedance will be given. It is also
possible to use a source-pull simulation in the same way as the load-pull simulation.

6.2.4 Design of Matching Networks

If the matching network topology was already chosen for the load-pull simulation it will
only have to be synthesized. In the synthesis it is necessary to take all the important
parasitics into account, this can be omitted in the initial load-pull simulations.
Based on the choice of impedance at fundamental and harmonic frequencies the
output matching network is designed. An important part of the output matching network
is the biasing, e.g. supply voltage. The topologies of the matching networks and the
synthesis of them have been described in Chapter 3.
DESIGN METHOD FOR INTEGRATED POWER AMPLIFIERS 67

When selecting the matching network topology the biasing of the stages is often an
important part. Selecting the right topology will give DC blocking and biasing at the
same time as the impedance matching.
Depending on the mode of operation the optimal drive conditions for the output
stage may differ. In the design of the input matching network biasing will also have to
be incorporated, either as an integrated part of the matching network or explicitly, the
latter will then have to be considered as a parasitic in the input matching network.

6.3 Combination of Stages

The final part of the power amplifier design is to combine the individual stages and the
input matching networks will have to be merged with the output matching networks of
the preceding stage. Then the stability of the complete power amplifier will have to be
examined. This is done using transient simulations and small-signal stability analysis.
The small-signal analysis uses all ports, DC or RF, as RF ports and the stability is then
analyzed [7].
The design flow for the combination of the individual power amplifier stages is
shown in Figure 6.5.

Figure 6.5 Design flow for combination of individual stages.

6.3.1 Design of Interstage Matching Networks

The design of the interstage matching networks will be based on the output matching
network of the preceding stage and the input matching network of the following stage.
It is often possible to reduce the number of passive components compared to the total
number of components used in the two initial networks. In integrated power amplifiers
the passive components often dominate the die size as well as the losses in the power
amplifier. It is therefore often desirable to minimize the number of passive components.
The design of the interstage matching networks is an iterative process where the
performance is verified continuously by a large-signal simulator. Based on the simulated
results the interstage matching network will be optimized.
68 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

6.3.2 Check RF Performance of Power Amplifier

After the interstage matching networks have been designed it is necessary to simulate
the complete power amplifier to verify the output power and efficiency. Usually it will
then be advantageous to fine tune the matching networks in an iterative process to
optimize the key parameters.
The RF performance is verified by steady-state and transient simulations. These
simulations will have to cover the different process corners, the discrete component
tolerances as well as the complete operating temperature.

6.3.3 Check Stability

When the RF performance is verified the stability of the complete power amplifier is
checked. The first check is the in-band stability, these checks have been described in
Section 4.2. Then the bias stability is verified as described in Section 4.3.
The stability is checked by small-signal and transient simulations. The input,
output and bias ports are all treated as RF ports in the small-signal simulations. The
transient simulations use pulses to excite the circuit to provoke oscillations. As was the
case for the RF performance verification all simulations will cover process corners,
component tolerances and the entire temperature range.

6.4 Summary
In this chapter a design method for integrated power amplifiers was presented. This
design method was developed and used through the design of the power amplifiers in
Chapter 8.
The design method describes the design of an RF power amplifier from
specification to the finalized design. Although the design has been formalized the
designer still has to make the decisions, but the formalized decision process ensures that
the choices are made in the right order.

References
[1] F. Giannini, G. Leuzzi, E. Limiti, and L. Scucchia, "Non-linear mixed analysis/
optimization algorithm for microwave power amplifier design," IEEE
Transaction on Microwave Theory and Techniques, vol. 43, pp. 552--558,
March 1995.
[2] F. Giannini, G. Leuzzi, and E. Limiti, "Class AB power amplifier advanced
design techniques," in IEEE MTT-S IMOC Proceedings, 1995.
[3] S.-J. Yi, B.-S. Kim, and S. Nam, "Design of high-efficiency power amplifier
using DC and small-signal S-parameter measurements," in Asia Pacific
Microwave Conference, pp. 513--516, 1997.
DESIGN METHOD FOR INTEGRATED POWER AMPLIFIERS 69

[4] P. A. Blakey and E. M. Johnson, "Generalized Kushner analysis of RF power

amplifiers," in IEEE MTT-S Digest, pp. 521--524, 1999.
[5] C. Duvanaud, P. Bouysse, S. Dietsche, J. M. Nebus, J. M. Paillot, and D.
Roques, "A design method for high efficient power amplifiers," in Third
International Workshop on Integrated Nonlinear Microwave and
Millimeterwave Circuits, pp. 205--210, 1994.
[6] G. A. Hoile and H. C. Reader, "Computer-aided design of an RF MOSFET
power amplifier," IEE Proc.-Circuits Devices Syst., vol. 141, pp. 433--438,
December 1994.
[7] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Artech
House, 1999.
[8] G. Gonzalez, Microwave Transistor Amplifiers, Analysis and Design. Prentice-
Hall, 2 ed., 1997.
70 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS
CHAPTER 7
DIGITAL PREDISTORTION
As mentioned in Chapter 1 some of wireless communication standards require linear
power amplifiers. The IS-95 standard which is used primarily in North America is one
of those standards and sets limitations on the ACPR allowed. These requirements can be
met by using either a linear power amplifier with relatively low efficiency or by
introducing linearization. One of the linearization methods is digital predistortion which
can be implemented without decreasing the efficiency of the usually effective nonlinear
power amplifiers.
To demonstrate the feasibility of digital predistortion a solution has been
implemented for an already existing power amplifier. The power amplifier used was
designed by Gary Hannington at University of California, San Diego for the IS-95
system.
In the IS-95 system the output power of the handset is usually substantially lower
than the maximum output power. The probability of each power level has been plotted
along with the efficiency of an ordinary class A power amplifier in Figure 7.1. As can
be seen from the figure the power amplifier hardly ever operates at maximum output
power and thereby maximum efficiency.
The power amplifier was implemented using GaAs MESFET transistors and
operates at a carrier frequency of 950MHz. The output power of the power amplifier is
controlled by supply voltage modulation. In the dynamic supply voltage (DSV) power
amplifier, a DC-DC converter is used to adjust the power supply voltage provided to the
output stage in accordance with the output signal level. This architecture can provide a
significant increase in overall efficiency, particularly if the amplifier is operated at
relatively low output power during a substantial fraction of the time [1]. The schematic
of the (DSV) power amplifier is shown in Figure 7.2.
The total efficiency of the power amplifier increases substantially at output powers
below the maximum output power compared to a conventional power amplifier. The total
efficiency including the DC-DC converter has been plotted as a function of output power
in Figure 7.3.

71
72 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Figure 7.1 Probability and class A efficiency vs. power levels.

Figure 7.2 Schematic of dynamic supply voltage power amplifier.

The probability from Figure 7.1 can be combined with the efficiencies from Figure
7.3 as illustrated in Figure 7.4. If the effective efficiency based on the probabilities is
calculated it can be seen that the same power amplifiers total efficiency increases by a
factor of 1.4 when the dynamic supply voltage is used.
It has been found, however, that the output linearity can be degraded in the DSV
system. The reduced linearity results from a variation in amplifier gain as the supply
voltage is varied. In previous work, it has been shown that by dynamically varying the
gate bias in a MESFET-based DSV amplifier along with the power supply voltage (drain
bias, VDD), the linearity of the amplifier can be restored [1]. In this work the
linearization of the DSV amplifier is done by predistorting the signal fed to the amplifier,
in a manner that can be accomplished with digital signal processing. Using a MESFET-
DIGITAL PREDISTORTION 73

Figure 7.3 Total efficiency as a function of the output power.

Figure 7.4 Probability and efficiency combined.

based DSV amplifier with DSP-based linearization the ACPR requirements of IS-95 is
met.

7.1 Theory of Digital Predistortion

The theory behind digital predistortion is based on memory-less bandpass nonlinearities.
To be able to implement the predistortion system it will also be necessary to have basic
information about the modulation format of the communication standard. In the
following section the modulation and the modeling and predistortion of the
nonlinearities will be described.

7.1.1 Digital Modulation of IS-95 Signal

The digital modulation used in IS-95 is based on offset quadrature phase shift keying
(OQPSK). OQPSK is one of the quadrature modulation formats, which are based on sin
74 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

ωct and cos ωct being orthogonal functions. Compared to conventional QPSK there are
no 180º phase transitions in OQPSK this means that there are no crossings through zero.
The zero crossings are usually difficult to handle in high efficiency power amplifiers due
to the amplitude going through zero. Since the requirements for the power amplifier are
lower than for QPSK, OQPSK are often favored in handsets. The phase transitions of
QPSK and OQPSK modulation formats can be represented in a constellation diagram as
shown in Figure 7.5 [2][3].

Figure 7.5 Constellation diagram showing phase transitions in QPSK and OQPSK.

A simple digital OQPSK modulator is shown in Figure 7.6. First the serial bit-
stream is parallelized. Then the two bits are passed through the two separate branches I
and Q. The Q signal will be delayed by half the symbol period. The two signals are low-
pass filtered to limit the output spectrum before they are upconverted with mixers to the
carrier frequency. The LO input of the I branch is a sine waveform while the Q branch
uses a cosine waveform. Finally the two separate branches are combined using an adder.

Figure 7.6 Block diagram of digital OQPSK modulation.

All of these blocks are easily implemented using a DSP. The low-pass filters are
usually constructed as FIR filters while the rest of the components are basic arithmetic
functions.

7.1.2 Modeling of Nonlinearities

The nonlinearity of a narrowband power amplifier can be modelled quite accurately
using memory-less bandpass nonlinearity theory [4]. This may seem like a limitation,
but in practice all wireless modulation standards, can be regarded as narrowband,
compared to the carrier frequency. To model the behavior of a power amplifier the CW
AM-AM and AM-PM characteristics are measured. These data can then be used in a
DIGITAL PREDISTORTION 75

baseband model of the power amplifier. A narrowband modulated signal can be

represented by:
j [ 2πf 0 t + φ ( t ) ]
x(t) = A( t) ⋅ e (7.1)

where A(t) is the amplitude of the signal as a function of time while φ(t) is the phase
of the signal.
j [ 2πf 0 t + φ ( t ) + φ dist [ A ( t ) ] ]
x dist ( t ) = A dist [ A ( t ) ] ⋅ A ( t ) ⋅ e (7.2)

where Adist(x) is the amplitude distortion, i.e. the difference between wanted and
actual amplitude, as a function of input power and φdist(x) is the phase distortion as a
function of amplitude. This can be rewritten as:
jφ dist [ A ( t ) ]
x dist ( t ) = A dist [ A ( t ) ] ⋅ e ⋅ x(t ) (7.3)

7.1.3 Predistorting a Nonlinear Signal

To predistort the signal is the distortion has to be inverted:
1 – jφ dist ( t )
x pre ( t ) = ------------------ ⋅e ⋅ x(t) (7.4)
A dist ( t )

For an efficient DSP implementation, it is necessary to do the predistortion at

baseband, and operate separately on the I and Q signals. The equations for the
predistorted I and Q signals are:
I ⋅ cos Φ dist + Q ⋅ sin Φ dist
I p = -------------------------------------------------------------- (7.5)
A dist ( A )

Q ⋅ cos Φ dist + I ⋅ sin Φ dist

Q p = -------------------------------------------------------------- (7.6)
A dist ( A )

7.2 Implementation
The implementation consists of a signal generator and a piece of software for data
generation. In this implementation, the I and Q channels outputs were precomputed in
software for a specific pseudorandom output data pattern, and fed to the system with a
signal generator which allows arbitrary I and Q waveforms to be specified.
The generation of the data is done using a C++ program. The digital predistortion
method presented here can be implemented effectively in a DSP.

7.2.1 Equipment
The equipment used for the project is a HP ESG-D signal generator. The signal generator
generates I and Q signals, which are then IQ upconverted to a RF frequency between 250
kHz and 4 GHz.
76 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

This signal generator is equipped with an option, which will allow an arbitrary I
and Q waveforms to be specified. The arbitrary waveforms can contain 1 Msample per
channel and the sampling frequency is between 1 sample/s and 40 Msamples/s. The
waveform data consists of 14 bits per sample per channel.
The arbitrary waveforms are generated on a computer and then transferred to the
signal generator through a GP-IB bus.

7.2.2 Data Generation Software

The generation of the data is done, using a C++ program. The C++ program will also
simulate the behavior of the amplifier with or without the predistortion. The simulation
is done with measured AM-AM and AM-PM distortion data. The predistorted I and Q
waveform are quantized to 14 bits as required by the signal generator.
The digital predistortion presented here can be implemented very effectively in an
already existing DSP. The overhead for implementing the predistortion is six
multiplications and two additions as well as 40-100 data entries in a table, all of the
above could be implemented as integer operations. In an IS-95 implementation with four
times oversampling this equals approximately 30 MIPS, compared to the several
hundred MIPS available in modern DSPs. The memory required would be 80-200 bytes.

7.3 Measurements
First of all the AM-AM and AM-PM characteristics have to be measured, this can be
done in several ways, but the easiest solution is to use a vector network analyzer. The
network analyzer is setup for a power sweep, and the gain and phase is retrieved from
the S 21 data. The measurement setup for getting the AM-AM and AM-PM data is shown
in Figure 7.7.

Figure 7.7 Measurement setup for retrieving AM-AM and AM-PM data.

These tables are put into the data generation program. An OQPSK signal is
generated and filtered according to the IS-95 standard. At this point the predistortion is
applied and the I and Q signals are then transferred to the signal generator. The signal
generated by the signal generator is passed through a pre-amplifier, to generate high
enough input power.
DIGITAL PREDISTORTION 77

The measurements of the ACPR is done using a spectrum analyzer, this can be done
using either a built-in function for the ACP calculation, or by transferring the spectrum
to a computer and do the calculations there. It is however necessary to do some averaging
of the results, regardless of how they are acquired. The setup for measuring the ACPR
of the digital predistortion system is shown in Figure 7.8.

Figure 7.8 Measuring ACPR for digital predistortion system.

Measurements of the ACPR were done using a spectrum analyzer. A built-in

function for the channel power calculation was used and the result was transferred to a
computer and used for ACPR calculations. Averaging of results over many runs was
done to obtain accurate values. Measurements have shown an improvement of the ACPR
of the power amplifier described above on the order of 4-6 dB, as shown in Figure 7.9.

Figure 7.9 ACPR measurements with and without digital predistortion.

The output spectrum with and without predistortion is shown in Figure 7.10. The
resulting output spectrum is capable of meeting IS-95 requirements. As a result of the
improved linearity of the power amplifier system, it was possible to increase the output
power by 4dB. The predistortion also means that the amplifier can be driven further into
compression, thereby achieving a higher efficiency.

7.4 Continued Work

After the initial digital predistortion system was completed the work continued in
directions suggested by the author. The author has been in continuos contact with UCSD
78 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Figure 7.10 The output spectrum of the DSV power amplifier

with and without digital predistortion.
and discussed implementation details. The improvements of the digital predistortion
system were mainly targeted at the dynamic supply voltage power amplifier used at
UCSD. Along with the digital predistortion described here the control of the DC-DC
converter was handed over to the DSP.

Figure 7.11 Schematic of improved digital predistortion system.

By removing the envelope detector and controlling the DC-DC converter directly
from the DSP it was possible to eliminate the delays in the control loop. The effect of
adding a delay in the DC-DC converter control loop has been simulated and the results
of different delays are shown in Figure 7.12. When controlling the DC-DC converter
directly no memory effects remain in the system.
The ACPR was improved by 8dB compared to a system without predistortion. The
results of this improved digital predistortion system are shown in Figure 7.13 [5].
DIGITAL PREDISTORTION 79

Figure 7.12 Effect of delay in DC-DC converter control loop.

Figure 7.13 Spectrum of improved digital predistortion system.

7.5 Summary
In simulations it is possible to obtain full linearization up to a certain output power level.
In practice this will not be the case. It has however been proven that the predistortion will
improve the linearity of the power amplifier.
Measurements have shown an improvement of the ACPR of the power amplifier
described above of 6-8dB depending on the implementation. These improvements may
be the difference between passing the ACPR tests or not. It also means that the amplifier
can be driven further into compression, thereby achieving a higher efficiency. The results
have been presented in [6][7] while the continued work has been presented in [5].
80 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

References
[1] G. Hanington, P. F. Chen, V. Radisic, T. Itoh, and P. M. Asbeck, "Microwave
power amplifier efficiency improvement with a 10 MHz HBT DC-DC
converter," in 1998 IEEE MTT-S Intl. Microwave Symposium Digest, vol. 2, pp.
589--592, 1998.
[2] B. Razavi, RF Microelectronics. Prentice Hall, 1998.
[3] L. E. Larson, ed., RF and Microwave Circuit Design for Wireless
Communications. Artech House, 1996.
[4] M. C. Jeruchim, P. Balaban, and K. S. Shanmugan, Simulation of
Communication Systems. Plenum, 1992.
[5] M. Ranjan, K. H. Koo, G. Hanington, C. Fallesen, and P. Asbeck, "Microwave
power amplifiers with digitally-controlled power supply voltage for high
efficiency and high linearity," in 2000 IEEE MTT-S International Microwave
Symposium, (Boston, USA), June 2000.
[6] C. Fallesen, G. Hanington, and P. M. Asbeck, "Improved linearity of a dynamic
supply voltage power amplifier using digital predistortion," in 1999 IEEE
Topical Workshop on Power Amplifiers for Wireless Communications, (San
Diego, USA), September 1999.
[7] P. M. Asbeck, G. Hanington, M. Ranjan, L. Larson, C. Fallesen, and H. Finlay,
"Envelope tracking or dynamic supply voltage power amplifiers for wireless
communications," in Efficiency and Linearity Enhancement Methods for
Portable RF/MW Power Amplifiers Workshop, (Boston, USA), June 2000.
CHAPTER 8
DESIGN OF CMOS POWER
AMPLIFIERS
Three CMOS power amplifiers have been designed to demonstrate the feasibility of
CMOS power amplifiers for wireless communication. To lower the risk of the designs a
gradual approach was chosen where the first power amplifier was a rather simple two
stage amplifier with external bias circuit. The third power amplifier was highly
integrated compared to other solutions published so far.
The power amplifiers were all designed for the STMicroelectronics BiCMOS6G
process which is a 0.35 µm bulk BiCMOS process with a substrate resistivity of 10-20
Ω-cm. Although most digital CMOS processes uses low resistivity epitaxial substrate to
prevent latch-up, it is possible to get medium resistivity bulk CMOS processes from a
number of foundries including STMicroelectronics, AMS, TSMC and UMC. The main
contribution of the bulk substrate is reduced losses in the on-chip inductors compared to
the standard epi-substrates.
The process has 5 metal layers although the first design was carried out in a version
with only four layers. The top metal layer is 2.5 µm thick, which is four times the
thickness of the remaining layers. This is consistent with the thick power supply rails in
modern digital CMOS processes.
The process has thin-oxide metal-metal capacitors involving one extra processing
step. The thin-oxide metal-metal capacitors have a high density and therefore the die size
(cost) of the complete power amplifier can be reduced. Apart from the thin-oxide metal-
metal capacitors a scalable inductor device generator and corresponding model is
available directly from the foundry.
The CMOS process used for the prototypes is actually a BiCMOS process. The
bipolar parts of the process is, however, not used. The reason for choosing the BiCMOS
process was mainly the availability of design-kit and transistor models which were
mature for RF design. A number of foundries now offers pure CMOS processes on bulk
substrate with metal-metal capacitors and a thick metal layer. ´

81
82 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

The two first prototypes were used to develop the design method described in
Chapter 6. While the third CMOS power amplifier was developed using this design
method.

8.1 The First CMOS Power Amplifier

The first CMOS power amplifier was a low-risk design primarily suited to obtain
valuable information about modeling and simulation of power amplifiers. Another goal
of the power amplifier was to investigate stability problems and output matching
topologies.
To limit the number of problems the operating frequency was 900 MHz,
corresponding to the GSM-900 standard. Besides the complete power amplifier the
individual amplifying stages were available for testing on the die. The on-chip biasing
network was limited to the RF parts with the DC part placed off-chip.

8.1.1 Specifications
As mentioned above the first CMOS prototype was targeted towards the GSM-900
standard. The most important specifications for the power amplifier are listed in Table
8.1.
Table 8.1 Specifications for the first CMOS PA prototype.

Parameter Min. Nom. Max. Unit

Input freq. 880 920 MHz
Input power level 5 10 dBm
Max. output power 34.5 dBm
Input impedance 50 Ohm
Output impedance 50 Ohm
Power added efficiency 40 %

8.1.2 Packaging
The packaging of the IC plays an important role in the design of a power amplifier. The
parasitics of the package, i.e. inductance and capacitance, has a big influence on the
matching networks of the power amplifier. Another issue with packaging for power
amplifiers is the thermal conduction, since the power amplifier produces a lot of excess
power.
A solution which is relatively easy to model and has good thermal conduction is
the chip-on-board approach. The principle in chip-on-board is simply to glue the die
directly onto the PCB. The pads of the IC are then wire-bonded directly onto the PCB
wires. In order to be able the bond reliably, the PCB must be plated with minimum 7 µm
gold. The properties of chip-on-board resembles the properties of the ceramic substrates
widely used for commercial power amplifiers without passive integration in the board,
DESIGN OF CMOS POWER AMPLIFIERS 83

but at a lower cost. The chip-on-board approach was therefore chosen for the CMOS
prototypes.

8.1.3 Design of the Power Amplifier

Figure 8.1 Schematic of the first CMOS power amplifier prototype.

The power amplifier consists of two stages with fully integrated input and
interstage impedance matching networks. The schematic of the power amplifier is
shown in Figure 8.1. The input matching network transforms the conjugate gate
impedance ΓIN to 50Ω as well as cancel the effect of the bondwires. It is made of a fully
integrated highpass LC matching section. This has been chosen because it incorporates
DC blocking and biasing at the same time as the impedance matching. The inductor is a
spiral inductor implemented in top metal layer, while the capacitor is a thin-oxide plate
capacitor between the two lowest metal layers.
The input stage operates in class AB, delivering up to 15 dB gain at maximum
output power. The transistor of the input stage is 1 mm wide and 0.35 µm long. The input
stage has an off-chip inductor acting as a RF choke (RFC).
The interstage matching network consists of a LC highpass section for the same
reasons as the input matching network. The implementation is made in the same way as
the input matching, but the interstage matching transforms the gate impedance to the
desired output load of the input stage.
The output stage operates in class AB close to B. There are a number of reasons to
choose this mode of operation:
1. Class AB close to B behaves relatively linearly. This is not the case for class C
and E amplifiers. The performance is, however, not as good as class A.
2. The efficiency is relatively good, the theoretical maximum is 78.5%, compared
with 50% for the class A amplifiers, class C and E have theoretical efficiencies
up to 100%.
3. The maximum drain voltage is twice the supply voltage, this is important due
to the possible breakdown of the gate-oxide. Class C and E amplifiers easily
exceed three times the supply voltage.
84 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

4. The power utilization factor (PUF), which is a measure of the gain compared to
the output power, is reasonable compared to class A, and better than class C
and E.
5. The required output load is not too low to implement efficiently, which is often
the case for class C.
The output transistor is 8 mm wide and has a length of 0.35 µm as the input stage.
The transistor is partitioned into 6 separate finger transistors, with 30 fingers each. The
gain of the output stage is approximately 12 dB.
The output matching network is placed off-chip due to efficiency considerations.
The RFC for the output stage is an SMD mounted inductor. The output matching
network consists of a bandpass T section, with a high transformation factor from
approximately 4 Ω to 50 Ω. In the design of the network, the parasitics of the RFC
microstrip were included.
In the design phase the two amplifier stages were initially treated separately and
optimized for 50 Ω input and output matching using load-pull simulations. After each
stage had been optimized an interstage matching network was designed using the
impedances found for each stage.

8.1.4 Measurements
As explained above, the CMOS power amplifier IC has been mounted on an
ordinary gold-plated PCB, and connected with wirebonding from the IC directly to the
PCB. This approach offers some advantages during the prototyping phase of the design.
The PCB can be produced with a PCB milling machine or at a normal PCB production
facility. A new test-board can be milled within hours, allowing for larger exploration of
the design space in the prototyping phase. There are however also some drawbacks when
milling the PCB, most importantly it is not possible to make filled via holes. The via
holes will then have to be filled with a wire and soldered on both sides of the PCB. The
dielectric material used for the PCB was standard FR4, with a relative dielectric constant
of approximately 4.3 at 1.75 GHz.
The output power and efficiency of the power amplifier over the desired frequency
range has been depicted in Figure 8.3. One of the most important aspects of the reliable
design of a power amplifier is accurate simulations. As mentioned above a lot of
emphasis was put on accurate simulations. The simulated and measured data was
compared, and minor modelling problems fixed, resulting in simulations with good
agreement between simulated and measured results.

8.1.5 Summary of First CMOS Power Amplifier

A CMOS power amplifier has been presented with an output power of 28.8 dBm.
The power added efficiency of the complete power amplifier is 35%. The operating
frequency of the amplifier is 860-900 MHz, which is 20 MHz lower than expected but
still reasonably close. Simulations show that a new PCB would improve both output
DESIGN OF CMOS POWER AMPLIFIERS 85

Figure 8.2 Photograph of the first CMOS power amplifier PCB.

40 Efficiency
Output Power (dBm) &

35
30
Effieciency (%)

25 Output power
20
15
10
5
0
860 870 880 890 900
Frequency (MHz)

Figure 8.3 Output power and power added efficiency of first CMOS PA.
power and efficiency of the power amplifier. The die area including pads is 2.5 sq. mm.
The tolerances in the bondwires were too big, therefore the next version contains on-chip
decoupling capacitors, to establish RF ground on-chip.
Based on the measurements, the modeling of the power amplifier was improved,
and used in the circuit simulator. Using the new model the simulation accuracy
improved. Simulations showed that moving part of the output matching network on-
chip, would greatly improve the output power and efficiency, since second harmonic
termination becomes more effective. The basic properties of the power amplifier have
been outlined in Table 8.2.
86 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Table 8.2 Characteristics of the first CMOS power amplifier.

Process 0.35 µm CMOS
Supply voltage 3.5 V
Input power 5 dBm
Output power 28.8 dBm
Frequency 860-900 MHz
Power added efficiency 35%
Die area 1.9 sq. mm.

8.2 The Second CMOS Power Amplifier

Based on the experiences from the first CMOS prototype a second version was designed.
The process and packaging are the same as for the first CMOS prototype. The second
version featured an improved pad and output transistor layout. The bias signals were
decoupled on-chip in order to control the center frequencies of the matching networks.

8.2.1 Specifications
The second CMOS power amplifier was targeted towards the GSM-1800 standard. The
specifications for the power amplifier are listed in Table 8.3.
Table 8.3 Specifications for the second CMOS PA prototype.

Parameter Min. Nom. Max. Unit

Input freq. 1710 1785 MHz
Input power level 5 10 dBm
Max. output power 31.5 dBm
Input impedance 50 Ohm
Output impedance 50 Ohm
Power added 40 %
efficiency

8.2.2 Design of the Power Amplifier

Compared to the first CMOS power amplifier a number of problems identified were
corrected in the second version. In the second version the pads were placed better with
regards to bonding. The layout of the output transistor was improved. The bias points
were decoupled on-chip to achieve lower sensitivity to the bondwires.
In order to have better harmonic termination, a capacitor is placed on-chip, directly
at the drain of the transistor, in parallel with the drain-source capacitor of the transistor.
This capacitor terminates the harmonics at the drain, but at the same time it transforms
the output impedance even lower, leaving a more difficult matching problem [1]. The
RFC for the output stage is a relatively short microstrip which can be implemented
without increasing the PCB size.
DESIGN OF CMOS POWER AMPLIFIERS 87

8.2.3 Simulations
In order to make precise simulations the PCB was characterized using simple short,
open and through structures. Using this approach, the transients in the SMA connector
to PCB interface could be modeled accurately. The simulations of these test structures
showed very good agreement with measured results up to 4 GHz. After the SMA
connectors and PCB were characterized, the output matching network was simulated and
measured.
The PCB has been modeled with microstrip lines and the SMD components have
been modeled according to vendor specifications. The bondwires have been modeled as
inductors and the mutual coupling between the bondwires were included as well.
The measurements of the output matching network were performed by mounting a
short piece of semi-rigid cable in place of the IC. The shield of the cable was soldered to
the ground plane, where the IC was supposed to be placed. The conductor of the cable
was attached at the microstrip on the PCB where the bondwires from the output of the
IC would go.
The IC simulations were based on parasitic extraction results from the transistor
and passive layout. The transistors were modeled by the MOS9 model. The spiral
inductors and the metal-metal capacitors were simulated using lumped models delivered
by the foundry.
Output power (dBm)

33
32 Simulated
31
30
29 Measured
28
27
1.65 1.75 1.85
Frequency (GHz)

Figure 8.4 Comparison of simulated and measured data.

The simulations were made in the APLAC simulator, primarily with small-signal
and harmonic balance simulations. For verification purposes transient simulations have
been performed in the Eldo simulator. The harmonic balance simulations proved to be
faster than the transient simulations, since only the steady-state solution is calculated, the
precision of the simulations proved to be the same.
The simulations of the complete power amplifier including the PCB showed very
good agreement between the simulated and measured results. The measured output
power was predicted within a few tenths of a dB. The comparison between simulated and
measured output power is shown in Figure 8.4.
88 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

8.2.4 Measurements
To get a realistic picture of the performance, the measurements were made in
pulsed mode according to the GSM1800 specifications, this means a duty cycle of
12.5%. The measurements showed that the input matching network was matched 70
MHz too high. The interstage matching network on the other hand was matched 80 MHz
too low. This means that the maximum output power was obtained at 1670 MHz instead
of the desired center frequency of 1750 MHz. Another effect of the mistuned matching
networks was that the input power had to be increased to get maximum output power and
efficiency. The highest power added efficiency was 40% at 1730 MHz, with an output
power of 30.3 dBm. The output power and efficiency biased for maximum power added
efficiency vs. frequency is shown in Figure 8.6.

Figure 8.5 Schematic of the second CMOS power amplifier.

The highest output power obtained was 31.5 dBm at 1670 MHz, with the input
power increased to 15 dBm. The output power and efficiency with biases set for
maximum output power vs. frequency is shown in Figure 8.7
In spite of the problems with the matching networks it was still possible to get 30.3
dBm output power with a power added efficiency of 40% at 1730 MHz. With minor
adjustments of the matching networks a new version of the IC can be designed to get the
highest output power and efficiency in the GSM-1800 band, while keeping the input at
the desired 5 dBm.
Since the power amplifier is operating in class AB close to B, it is inherently more
linear, than e.g. the class C, D and E amplifiers demonstrated in CMOS so far
[2][3][4][5]. This means that the power amplifier is suitable for digital predistortion as
described in [6] and [7]. In [6] it was shown, that an improvement of the adjacent channel
power ratio (ACPR) of 4-6 dB, is possible with simple low-power digital predistortion.
This again means that class AB power amplifiers can be used in most upcoming
amplitude modulated systems.
DESIGN OF CMOS POWER AMPLIFIERS 89

Output power (dBm) &

50 Efficiency
40

PAE (%)
30
Output Power
20
10
0
1.6 1.65 1.7 1.75
Frequency (GHz)

Figure 8.6 Measured output power and efficiency, biased for maximum power added
efficiency.
Output power (dBm) &

50
Efficiency
40
PAE (%)

30
Output Power
20

10

0
1.6 1.65 1.7 1.75
Frequency (GHz)

Figure 8.7 Measured output power and efficiency, biased for maximum output power.
The power amplifier operates on a supply voltage from 1 V to 3.6 V. The output
power and efficiency vs. supply voltage is shown in Figure 8.8. The maximum output
power was measured to be 32.2 dBm at 3.6 V.
One of the most important aspects of the reliable design of a power amplifier is
accurate simulations. As mentioned above a lot of emphasis was put on accurate
simulations. The simulated and measured data was compared, minor modeling problems
fixed, and good agreement between the simulated and measured results were obtained.

8.2.5 Revised PCB Version

Once the simulations were accurate it was possible to start optimizing the PCB
layout based on the simulations. After investigating a number of options it was clear that
the inductor used as the RF choke on the output stage contributed significantly to the
90 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Power added efficieci (%)

Output power (dBm) &
50
Efficiency
40
30
Output Power
20
10
0
1 2 3 4
Supply voltage (V)

Figure 8.8 Measured output power and efficiency vs. supply voltage.
losses. The simulations showed that replacing the inductor with a short microstripline
would increase the power added efficiency to 45%.
A new PCB was milled and a new set of measurements were performed. The
measurements performed showed very good agreement with the results predicted by the
simulations.
The highest power added efficiency was 45% at 1730 MHz, with an output power
of 30.4 dBm. The output power and efficiency measurements with the power amplifier
biased for maximum power added efficiency vs. frequency are shown in Figure 8.9.

50
Output power (dBm) &

Efficiency
45
PAE (%)

40

35
30
Output Power
25
1.65 1.75 1.85
Frequency (GHz)

Figure 8.9 Output power and efficiency vs. frequency, biased for maximum efficiency

The highest output power obtained was 31.3 dBm at 1720 MHz. The output power
and efficiency measurements with biases set for maximum output power vs. frequency
are shown in Figure 8.10.
DESIGN OF CMOS POWER AMPLIFIERS 91

50

Output power (dBm) &

45
Efficiency

PAE (%)
40

35

30
Output Power
25
1.65 1.75 1.85
Frequency (GHz)

Figure 8.10 Output power and efficiency vs. frequency, biased for maximum output
power
The power amplifier operates on a supply voltage from 1 V to 3.6 V. The output
power and efficiency vs. supply voltage is shown in Figure 8.11.
Output power (dBm) &

50
45 Efficiency
PAE (%)

40
35
30
25 Output Power
20
1 2 3
Supply voltage (V)

Figure 8.11 Measured output power and efficiency vs. supply voltage at 1730 MHz.

8.2.6 Summary of Second CMOS Power Amplifier

A CMOS power amplifier has been presented with an output power of 31.3 dBm
at 1720 MHz. The power added efficiency for the complete power amplifier is 45%
achieved at 1730 MHz. A redesign with minor adjustments of the input and interstage
matching networks will move maximum output power and efficiency to the GSM-1800
band.The die area including pads is 1.9 sq. mm. The values of the components are listed
in Table 8.4.
Based on the measurements, the modeling topology has been improved, and used
in the circuit simulator. Using the new topology the simulation accuracy was improved,
and is now within a few tenths of a dB, compared to measured results. The methods used
to achieve this accuracy have been described in Chapter 5. The transistor model was a
92 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Figure 8.12 Photograph of the IC.

Table 8.4 Component values for the second CMOS power amplifier

Component Value
Cin 0.8 pF
Lin 5.5 nH
Cis 50.0 pF
Lis 1.05 nH
C1 5.0 pF
L1 parasitic
C2 4.7 pF
C3 9.4 pF
RFC1 5.1 nH
RFC2 13.0/1.0 mm
M1 1000.0/0.35 µm
M2 6x1333.3/0.35 µm
MOS9 model with the enhancements described in Section 5.3.5. The passive
components, the package and the PCB were modeled as described in Section 5.4.
The power amplifier consists of one die, two RFCs and three matching component
plus decoupling capacitors, compared to 3 dies and 15-20 passives plus decoupling
capacitors for a typical commercial GaAs power amplifier were the integration level is
typically low.
The power amplifier operates in class AB, which gives good output power,
efficiency and linearity. Until now no 1 W CMOS power amplifiers, which do not
operate in a switched mode, have been published. The fact that this power amplifier
operates relatively linearly, means that it is easier to use in wireless applications,
especially in systems which utilizes amplitude modulation, such as IS-95, EDGE and
DESIGN OF CMOS POWER AMPLIFIERS 93

WB-CDMA. The basic properties of the power amplifier have been outlined in Table
8.5.
Table 8.5 Characteristics of the second CMOS power amplifier.
Process 0.35 µm CMOS
Supply voltage 3.5 V
Input power 5-15 dBm
Output power 31.5 dBm
Frequency 1710-1785 MHz
Power added 45%
efficiency
Die area 1.9 sq. mm.

8.3 Third Revision CMOS Power Amplifier

The third revision CMOS PA is an improvement of the second CMOS PA, which
contains integrated bias circuitry and improved performance of the on-chip matching
networks. The features that were considered for the third revision of the power amplifier
were on-chip RFC for first stage and on-chip output matching to approximately 10Ω.
These changes did not make onto the chip due to lack of time. These possible features
would only affect the integration level of the PA, reducing the external component count
to two plus decoupling.
Compared to the second CMOS power amplifier the on-chip input and interstage
matching networks were fine-tuned based on more precise active and passive models
from the foundry. A simple resistive bias network was implemented on-chip with all
necessary decoupling capacitors. This means that no external components were needed
off-chip for the biasing.
The layout of especially the output transistor was improved to reduce the ground
inductance. Even more ground bonds were added also to reduce the ground inductance.
Furthermore the groundplanes of the first and second stage of the power amplifier were
separated.
The PCB was produced at a commercial facility to get better vias. On the PCB two
short microstrips were used in place of the RFCs. In general the ground plane on the PCB
was vastly improved.
At last the use of the design method described in Chapter 6 also lead to some
improvements. Especially the use of the simulated load-pull was very useful.

8.3.1 Design
The design of this power amplifier followed the design and simulation
methodologies described in Chapter 6. The first choice to make was the number of stages
in the power amplifier. In this case a two-stage methodology was chosen.
94 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Then the class of operation was chosen for each of the stages. The input and output
stages operates in class AB close to class B. The reasons for choosing class AB operation
are the same as those outlined in Section 8.1.3.
Once the class of operation was chosen for the output stage it was possible to start
the dimensioning of the output transistor. This dimensioning was an iterative process
where the initial guess originated from the I-V characteristic of the output transistor.
From the I-V characteristic it was possible to find the voltage and current swings
possible for a given load-line. From the voltage and current swings the maximum output
power was then determined and a reasonable size of the transistor was found.
After an initial value is selected the more accurate RF behavior is found using load-
pull simulations. The load-pull simulations are the simulation equivalent of the load-pull
measurements as described in Section 3.2.3. The output from the load-pull simulations
are shown in Figure 8.13. Two sets of contours are presented in the figure namely output
power shown in black with the center and 1, 2 and 3dB contours. The power added
efficiency in grey shows center 5, 10 and 15% contours. The load-pull simulation was
used to make the trade-off between output power and power added efficiency. The
selected load impedance is approximately 4-j4Ω.

PAE

Output power

Figure 8.13 Load-pull simulation of third CMOS power amplifier.

The final schematic of the power amplifier is shown in Figure 8.14 where the
components mentioned below can be located. The output transistor (M2) was then
chosen to be 8 mm wide and with a length of 0.35 µm. The transistor is partitioned into
6 separate finger transistors, with 70 fingers each. The input stage also operates in class
AB. The transistor of the input stage (M1) is 1 mm wide and 0.35 µm long.
The output matching network is placed primarily off-chip due to efficiency
considerations. In order to have better harmonic termination, a capacitor (C1) is placed
on-chip, directly at the drain of the transistor, in parallel with the drain-source capacitor
DESIGN OF CMOS POWER AMPLIFIERS 95

of the transistor. This capacitor terminates the harmonics at the drain, but at the same
time it transforms the output impedance even lower, leaving a more difficult matching
problem. The RF chokes (RFC1, RFC2) for the output stage as well as the input stage are
relatively short microstrips, which can be implemented without increasing the overall
PCB size. The output matching network consists of a bandpass T section (L1, C2, C3),
due to the high transformation factor from 4 Ω to 50 Ω. The choice of the T section gives
a larger bandwidth than a single L section. The inductor in the T section consists of a
contribution from the bondwires as well as from the microstrip. In the design of the
network, the parasitics of the RFC microstrip were also included.
The input and interstage matching networks were both made with a fully integrated
highpass LC matching section. This was chosen because it incorporates DC blocking
and biasing at the same time as the impedance matching. The on-chip inductors are spiral
inductors implemented in the top metal layer, while the capacitors are made thin-oxide
metal-metal capacitors in the two lowest metal layers.
The schematic of the third CMOS power amplifiers is shown in Figure 8.14. The

Figure 8.14 Schematic of third CMOS power amplifier.

components and their values are listed in Table 8.6. Further details on the design of the
power amplifier can be found in Appendix A.

8.3.2 Measurements
The CMOS power amplifier IC was mounted directly on the PCB and wire bonded
directly onto the PCB microstrips as was the case with the other CMOS power
amplifiers. The PCB for this power amplifier was produced at a normal PCB production
facility and the PCB was the gold plated with 7µm gold. This meant that good filled via
holes were available hence improving the effectiveness of the groundplane on the PCB.
The passive components used on the PCB were 0402 SMD components. The SMA
connectors were mounted horizontally on the edge of the PCB, in order to reduce the
96 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

effects of the transition from SMA connector to PCB microstrip. The die photo is shown
in Figure 8.15 while the PCB is shown in Figure 8.16.
Table 8.6 Component values for third CMOS power amplifier

Component Value
Cin 1.0 pF
Lin 3.9 nH
Cis 20.0 pF
Lis 1.4 nH
C1 5.0 pF
L1 parasitic
C2 4.7 pF
C3 3.9 pF
RFC1 10.0/0.25 mm
RFC2 10.0/0.25 mm
M1 1000.0/0.35 µm
M2 6x1333.3/0.35 µm

Figure 8.15 Die photograph.

To get a realistic picture of the performance, the measurements were made in

pulsed mode according to the GSM1800 specifications, this means a duty cycle of
12.5%.
The highest power added efficiency was 55% at 1750 MHz, with an output power
of 30.4 dBm. The output power and efficiency measurements with the power amplifier
biased for maximum power added efficiency vs. frequency are shown in Figure 8.17.
The power added efficiency stays above 50% from the start of the measurements at
1.65GHz to 1.83GHz. While the output power starts at 30.8dBm at 1.65 GHz and stays
above 30dBm till 1780 MHz.
DESIGN OF CMOS POWER AMPLIFIERS 97

Figure 8.16 PCB photograph.

Output power (dBm) &

60 Efficiency
55
50
PAE (%)

45
40
35 Output Power
30
25
1.65 1.75 1.85
Frequency (GHz)

Figure 8.17 Output power and power added efficiency vs. frequency when biased for
efficiency.
The power amplifier operates on a supply voltage from 1 V to 3.4 V. The output
power and efficiency vs. supply voltage is shown in Figure 8.18. The output power is
20.8 dBm at 1V and 31.4 dBm at 3.4 V. The power added efficiency varies from 43% to
55% at 1V and 3.4V respectively. The power amplifier did not have sufficient
attenuation to be a plug-in for a standard mobile phone but this could easily be achieved
using a third stage between the first and second stages. Apart from the missing
attenuation the power amplifier was able to fulfill the requirements of the power-ramp
mask in GSM.
A comparison of all the published CMOS power amplifier results is shown in
Table 8.7. As can be seen from the table no other CMOS power amplifier has been
98 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

Output power (dBm)

60 Efficiency
55

& PAE (%)

50
45
40
35
30
25 Output Power
20
1 2 3
Supply voltage (V)

Figure 8.18 Measured output power and power added efficiency vs. supply voltage at
1750 MHz.
published with output power or power added efficiency as high as the work presented
here.
The simulations for the complete power amplifier including the PCB showed very
good agreement between the simulated and measured results. The measured output
power was predicted within a few tenths of a dB. The efficiency deviated less than 1%.
The comparison between simulated and measured output power is shown in Figure 8.19.
Output power (dBm) &

60 Efficiency
55
50
PAE (%)

45
40
35 Output Power
30
25
1.7 1.75 1.8
Frequency (GHz)

Figure 8.19 Comparison of simulated and measured data.

8.3.3 Summary of Third CMOS Power Amplifier

A CMOS power amplifier has been presented with a power added efficiency of
55% with an output power of 30.4 dBm at 1750 MHz. The power amplifier is designed
for GSM-1800 with a supply voltage of 3V, although it performs very well from 1V to
3.4V. The die area including pads is 1.1 sq. mm. By accurately modeling bondwires,
microstrips and SMD components the accuracy of the simulations was within a few
tenths of a dB, compared to measured results.
DESIGN OF CMOS POWER AMPLIFIERS 99

The power amplifier consists of one die, two short microstrips and two matching
components plus decoupling capacitors, compared to 3 dice and 15-20 passives plus
decoupling capacitors for a typical GaAs power amplifier. The power amplifier has
higher power added efficiency than any other CMOS power amplifier results published
so far, whether they operate linearly [8][9][10][11] or nonlinearly [12][2][13][5]. This
Table 8.7 Comparison of CMOS power amplifiers.

Frequency Pout PAE

(MHz) (dBm) (%) Class
T. Melly et. al. [12] 430 4.0 15 C
S.-J. Yoo et. al. [8] 433 13.0 30 AB
D. Su et. al. [2] 830 30.0 42 D
Fallesen (Section 8.1) 880 28.8 35 AB
B. Ballweber et. al. [9] 900 19.3 23 AB
C. Yoo et. al. [13] 900 29.5 41 E
K.-C. Tsai et. al. [5] 1980 30.0 41 E
Asbeck et. al. [10] 1950 29.2 27 B
Fallesen et. al. [11] 1730 30.4 45 AB
Fallesen et. al. [14] 1750 30.4 55 AB

work will be presented in [14].

The basic properties of the power amplifier have been outlined in Table 8.8.
Table 8.8 Characteristics of the third CMOS power amplifier.
Process 0.35 µm CMOS
Supply voltage 3.0 V
Input power 5 dBm
Output power 31.3 dBm
Frequency 1710-1785 MHz
Power added 55%
efficiency
Die area 1.9 sq. mm.

8.4 Summary
The first CMOS power amplifier prototype was representative for the CMOS power
amplifiers presented at the time of the measurements. The two last CMOS power
amplifiers were however better than all other work published at the time of publication.
The second power amplifier is on the same level as the other CMOS power amplifiers
presented so far, while the third power amplifier has significantly better power added
efficiency than any other CMOS power amplifier.
100 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

The good experimental results have been obtained by working structured through
the entire design process. The very first experiments were done using a discrete LDMOS
transistor in a discrete single stage power amplifier. This initial design revealed a
number of the potential problems especially stability problems. In the first CMOS power
amplifier design special focus was placed on stability and simplicity. This meant that the
bias networks were placed off-chip and the two stages were also available in single stage
versions.
The first CMOS power amplifier exposed a number of problems, especially in the
areas of bias stability and layout. In the second CMOS power amplifier these problems
were corrected and the operating frequency was changed from GSM-900 to GSM-1800.
The second power amplifier behaved close to the simulated performance, but some of
the parasitic components were not estimated accurately, resulting in a slightly lower
operating frequency than expected. The second CMOS power amplifier was used to
obtain detailed information of what parameters are important while designing and
simulating an integrated power amplifier.
Using the experiences from the first two CMOS power amplifiers a design method
was developed. This design method was used to design the third CMOS power amplifier.
The detailed insight in modeling and simulation of power amplifiers was then used to
optimize the third power amplifier to level at which no other CMOS power amplifiers
have achieved yet. The third power amplifier also achieved very good stability and good
thermal performance.
The good results were obtained by using the consistent design method described in
Chapter 6 combined with very accurate modeling of the power amplifiers described in
Chapter 5. Careful design of the different groundplanes and matching networks also
played an important role. The CMOS process was a bulk substrate with 10-20Ω-cm
resistivity which combined with thick top metal layer and metal-metal capacitors gave
good passive components.
During the design phase the simulated load-pull with the proper matching network
topology was used to achieve the high efficiency. If only ideal impedances were
presented to the power amplifier during the load-pull simulation the frequency
dependent behavior and the losses would not be modeled correctly. In conjunction with
the possibility to size the transistor this method proven very powerful.
The evolution of the CMOS power amplifiers have been tracked in Table 8.9.
Compared to other CMOS power the second CMOS power amplifier is comparable to
other CMOS power amplifiers published, while the third CMOS power amplifier is
better than any other CMOS power amplifier reported. The comparison of the CMOS
power amplifiers was shown in Table 8.7.
DESIGN OF CMOS POWER AMPLIFIERS 101

Table 8.9 Evolution of CMOS power amplifiers.

First PA Second PA Third PA

Center frequency 880 1730 1750 MHz
Output power 28.8 30.3 30.4 dBm
Power added efficiency 35 45 55 %
Die size 2.4 1.9 1.1 mm2
External components 11 10 4
Supply Voltage 3.3 3.5 3.0 V

References
[1] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Artech
House, 1999.
[2] D. Su and W. McFarland, "A 2.5-V, 1-W monolithic CMOS RF power
amplifier," in IEEE 1997 Custom Integrated Circuit Conference, 1997.
[3] R. Gupta and D. J. Allstot, "Parasitic-aware design and optimization of CMOS
RF integrated circuits," in 1998 IEEE Radio Frequency Integrated Circuits,
1998.
[4] A. Rofougaran, G. Chang, J. J. Rael, M. Rofougaran, S. Khorram, M.-K. Ku, E.
Roth, A. A. Abidi, and H. Samueli, "A 900 MHz CMOS frequency-hopped
spread-spectrum RF transmitter IC," in IEEE 1996 Custom Integrated Circuit
Conference, 1996.
[5] K.-C. Tsai and P. R. Gray, "A 1.9 GHz 1-W CMOS class-E power amplifier for
wireless communications," IEEE Journal of Solid-State Circuits, July 1999.
[6] C. Fallesen, G. Hanington, and P. M. Asbeck, "Improved linearity of a dynamic
supply voltage power amplifier using digital predistortion," in 1999 IEEE
Topical Workshop on Power Amplifiers for Wireless Communications, (San
Diego, USA), September 1999.
[7] M. Ranjan, K. H. Koo, G. Hanington, C. Fallesen, and P. Asbeck, "Microwave
power amplifiers with digitally-controlled power supply voltage for high
efficiency and high linearity," in 2000 IEEE MTT-S International Microwave
Symposium, (Boston, USA), June 2000.
[8] S.-J. Yoo, H. J. Ahn, M. M. Hella, and M. Ismail, "The design of 433 MHz class
AB CMOS power amplifier," in 2000 Soutwest Symposium on Mixed-Signal
Design, pp. 26--40, 2000.
[9] B. Ballweber, R. Gupta, and D. J. Allstot, "Fully-integrated CMOS RF
amplifiers," in International Solid-State Circuits Conference, pp. 154--155,
1999.
102 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

[10] P. Asbeck and C. Fallesen, "A RF power amplifier in a digital CMOS process,"
in 18th NorChip Conference, (Turku, Finland), November 2000.
[11] C. Fallesen and P. Asbeck, "A 1 W 0.35 um CMOS power amplifier for GSM-
1800 with 45% PAE," in 2001 IEEE International Solid-State Circuits
Conference, (San Francisco, USA), February 2001.
[12] T. Melly, A.-S. Porret, C. C. Enz, M. Kayal, and E. Vittoz, "A 1.2V, 430 MHz,
4 dBm power amplifier and a 250uW front-end, using a standard digital CMOS
process," in 1999 International Conference on Low Power Electronics and
Design, pp. 233--237, 1999.
[13] C. Yoo and Q. Huang, "A common-gate switched, 0.9W class-E power
amplifier with 41% PAE in 0.2 um CMOS," in 2000 Symposium on VLSI
Circuits, pp. 56--57, 2000.
[14] C. Fallesen and P. Asbeck, "A 1W CMOS power amplifier for GSM-1800 with
55% PAE," in 2001 IEEE International Microwave Symposium, May 2001.
CHAPTER 9
CONCLUSION
The primary goals of this thesis has been to develop a design method for highly
integrated power amplifiers as well as demonstrate the feasibility of submicron CMOS
power amplifiers for wireless communications. These goals were reached by explaining
the basic theory behind RF power amplifiers and through experimental results.
In the first part of the thesis the basic theory of power amplifiers was described. The
different classes of operation were discussed and advantages and disadvantages of the
classes were summarized. Then the selection of load and source impedances of a single-
stage power amplifier with either small-signal or large-signal methods was introduced.
The simulated load-pull technique was developed and used in conjunction with the
impedance matching network synthesis which was also described. In the experimental
part of the thesis the simulated load-pull technique proved to be very powerful. The
different network topologies were compared and the synthesis of these networks was
treated. After the initial design issues were covered the biasing of the power amplifier
was discussed, followed by techniques used to ensure stability of the designed power
amplifiers.
The fundamental characteristics of the CMOS technology was described with a
focus on the parameters important for power amplifier design. This included a coverage
of the breakdown mechanisms present in submicron CMOS processes. The other
technologies available for power amplifiers were briefly compared to CMOS and the
choice of CMOS for the experimental work was motivated.
Another important issue was the problems associated with modeling of power
amplifiers. The problems of modeling the CMOS transistors were explained and
different simulation models were compared. The modeling of the passive components of
a power amplifier on-chip as well as off-chip was discussed along with the package and
thermal models.
Based on the theory in the first part of the thesis along with the experiences from
the work with the CMOS power amplifiers a design method for integrated power
amplifiers was developed. The design method covers the design of an integrated power
amplifier from design specifications to complete power amplifier.

103
104 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

A digital predistortion system was introduced which enables the use of nonlinear
power amplifiers in linear modulation systems. As a starting point the power amplifier
has to be relatively linear. The improvement in ACPR was shown to be in the range 6-8
dB. The linearization technique was demonstrated on a dynamic supply voltage power
amplifier. In this configuration a standard power amplifier for IS-95 was modified with
dynamic supply voltage which deteriorated the ACPR. Applying the digital predistortion
meant that the total efficiency of the power amplifier was improved by 40%, while
restoring the original ACPR performance.
Based on the theory in the first part of the thesis three CMOS power amplifiers
were built. The first power amplifier was for the GSM-900 standard, and showed an
output power of 28.8 dBm with a power added efficiency of 35%. The remaining two
power amplifiers were designed for the GSM-1800 standard. The first of the GSM-1800
power amplifiers showed an output power of 30.3 dBm with a power added efficiency of
45%.
The last power amplifier had even higher integration than the first two power
amplifiers, with complete integration of input and interstage matching networks as well
as a fully integrated bias circuit. The power amplifier had an output power of 30.4 dBm
with a power added efficiency of 55%, which is better than any other results reported for
a CMOS power amplifier and comparable to the results of power amplifiers in better but
also more expensive technologies such as GaAs HBT. The power amplifier was designed
using the design method described in Chapter 6. Using the modeling techniques
described in Chapter 5 it was possible to achieve very good agreement between
simulated and measured results.
This work has demonstrated that it is possible to design power amplifiers in a
CMOS process with sufficient output power and power added efficiency. The CMOS
power amplifiers designed through the project shows that very high integration is
possible in CMOS, which leads to a very low component cost. Furthermore it was
demonstrated that design methods developed during the project can be used to design
integrated power amplifiers with very good performance.
In the future more effort will have to be placed in the development of CMOS
simulation models for RF usage. Also the modeling of some of the passive components
will have to be improved, especially the on-chip inductors.
There is no doubt about the fact that CMOS will be the cheapest process
technology available for a long time to come. It is therefore important that all
components for high volume, low cost products such as mobile phones can be produced
in CMOS. The power amplifier has been one of the few components which have not been
integrated in CMOS with sufficiently high performance, but this work has clearly
demonstrated the feasibility of CMOS power amplifiers for mobile phones.
Appendix A
Design Details
In this appendix the details of the design of the third CMOS power amplifier will be
described. This appendix is meant as a supplement to the design described in Section 8.3
rather than a complete description of the design. The design follows the design method
described in Chapter 6.
The main specifications for the power amplifier has been repeated in Table A.1.
The specification of the output power is slightly lower than necessary in a mobile phone,
but this was chosen to minimize the risk of the project. By choosing this slightly lower
output power it was possible to maintain the transistor sizing from the second power
amplifier.
Table A.1 Specifications for the third CMOS PA prototype.

Parameter Min. Nom. Max. Unit

Input freq. 1710 1785 MHz
Input power level 5 10 dBm
Max. output power 30 dBm
Input impedance 50 Ohm
Output impedance 50 Ohm
Power added 50 %
efficiency

A.1 Initial Design Decisions

The power amplifier is targeted towards GSM-1800 which is a constant envelope
standard. This means that the power amplifier will be operated in saturation to obtain
high efficiency.
The first choice is the between differential or single-ended operation. Based on the
problems with differential antennas described in Section 2.5 and differential to single-
ended conversion it was decided to design a single-ended power amplifier.

105
106 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

The next decision is the number of stages of the power amplifier. A two stage
design was selected, since it gives sufficient gain, demonstrates the important issues and
still has a reasonable complexity.
The gain and efficiency budget for the power amplifier is outlined in Table A.2.
Table A.2 Gain and efficiency budget

Stage Gain PAE

1. stage 12 55%
2. stage 12 55%
Total 24 50%

A.2 Design Individual Stages

The design of the individual stages starts by selecting the class of operation. Due to the
reasons outlined in Section 8.1.3 both of the stages are operating in class AB.

A.2.1 Transistor Sizing and Load Selection

The transistors initial size is based on the I-V characteristics of the transistor. To find the
initial size the I-V characteristics of a 1mm wide transistor was extracted. The I-V
characteristics are shown in Table A.1.
DC Analysis
Aplac 7.60 User: Nokia Corporation Jun 02 2001
0.70

0.52

0.35

0.17

0.00
0.000 1.750 3.500 5.250 7.000
Vdrain
-Idc(Vdrain_I)

Figure A.1 I-V characteristics of 1mm wide transistor.

From the load-line drawn in the I-V characteristics an output power of 0.25W could
be expected at low frequencies, since the operating frequency is 1.7GHz some headroom
should be included.
 107

The load-pull simulation results shown in Figure 8.13 was the result of an 8mm
wide transistor with minimum channel length of 0.35µm. The trade-off between output
power and efficiency was made by choosing the point on the 1dB power contour closest
to maximum efficiency, this was approximately at 4-j4Ω. The load-pull simulations
included all the parasitics associated with the package and interconnects. Then the
source impedance was found using the operating gain method described in Section 3.1.5.
While the transistor size determines the maximum output power it does not have any
direct influence on the efficiency of the power amplifier.
At last the output matching network was designed using the L matching section
described in Section 3.3.3. Once the initial values were found the complete matching
network including parasitics was simulated including RF choke and DC block. The
network was then optimized using the simulator. The reason for choosing the simple L
matching network is primarily to limit the losses in the matching network. Since the
bandwidth of the power amplifier was sufficient this could not warrant the use of
cascaded stages.
After the second stage had been designed the first stage was designed using the
same methods. This resulted in a transistor width of 1mm and a synthesized input
matching network. The input matching network was a simple L networks which allowed
biasing.
To be able to make all these simulations accurately it has been necessary to employ
the models described in Chapter 5. The transistor model used is MOS9 extracted by the
foundry explicitly for RF purposes furthermore the RF extensions described in Section
5.3.5. The modeling of the passive components and package were done according to the
models described in Section 5.4. Most interesting is probably the fact that a scalable
inductor model was available directly from the foundry. The scalable inductor model is
based on the model shown in Figure 5.5.

A.3 Combination of Stages

After the designing the two stages separately they had to be combined into a complete
power amplifier. First the interstage matching network was designed based on the load
impedance of the first stage and the source impedance of the second stage. The interstage
matching network was a simple L section as was the case for the input matching of the
first stage. Then the interstage matching network was optimized using simulations on the
complete power amplifier.
After the interstage matching network had been optimized the RF performance of
the complete power amplifier was verified. The output power and efficiency were
simulated over frequency. The bias circuit is a couple of resistive voltage divider with
ample decoupling capacitors. This circuit will not provide temperature compensation but
shows the feasibility of on-chip bias circuits.
108 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

After the RF performance was verified the stability of the power amplifier was
checked. The stability was checked as described in Chapter 4. All ports including bias
ports were treated as RF ports and conventional small-signal stability theory was
applied. Transient simulations were also used to verify the stability.
The voltage and current waveforms of the output transistor of the complete power
amplifier are shown in Figure A.2. The dip in the current waveform is caused by the
knee-effect and is one of the reasons for a reduced output power compared to the ideal
I-V characteristics.
Window 1
V Aplac 7.60 User: Nokia Corporation Jun 03 2001
8.00
V/V
5.95

3.90

1.85

-0.20
0.000 300.00p 600.00p 900.00p 1.200n
t/s
VWF(PA.Package
A Aplac 7.60 User: Nokia Corporation Jun 03 2001
1.20

0.89

0.59

0.28

-0.02
0.000 300.00p 600.00p 900.00p 1.200n
Figure A.2 Voltage across and current through the output transistor channel.
Appendix B
Published Papers
During the Ph.D. project a number of papers have been published. These papers are
attached in this appendix. The references of the papers are listed below:

References
[1] C. Fallesen, G. Hanington, and P. M. Asbeck, "Improved linearity of a dynamic
supply voltage power amplifier using digital predistortion," in 1999 IEEE
Topical Workshop on Power Amplifiers for Wireless Communications, (San
Diego, USA), September 1999.
[2] C. Fallesen and P. Asbeck, "A highly integrated 1 W CMOS power amplifier for
GSM-1800," in 2000 IEEE Topical Workshop on Power Amplifiers for Wireless
Communications, (San Diego, USA), September 2000.
[3] C. Fallesen and P. Asbeck, "A highly integrated 1 W CMOS power amplifier for
GSM-1800 with 45% PAE," in 18th NorChip Conference, (Turku, Finland),
November 2000.
[4] C. Fallesen and P. Asbeck, "A 1 W 0.35 um CMOS power amplifier for GSM-
1800 with 45% PAE," in 2001 IEEE International Solid-State Circuits
Conference, (San Francisco, USA), February 2001.
[5] C. Fallesen and P. Asbeck, "A 1W CMOS power amplifier for GSM-1800 with
55% PAE," in 2001 IEEE International Microwave Symposium, May 2001.
[6] M. Ranjan, K. H. Koo, G. Hanington, C. Fallesen, and P. Asbeck, "Microwave
power amplifiers with digitally-controlled power supply voltage for high
efficiency and high linearity," in 2000 IEEE MTT-S International Microwave
Symposium, (Boston, USA), June 2000.
[7] P. Asbeck and C. Fallesen, "A RF power amplifier in a digital CMOS process,"
in 18th NorChip Conference, (Turku, Finland), November 2000.

109
110 DESIGN TECHNIQUES FOR SUB-MICRON RF POWER AMPLIFIERS

[8] P. Asbeck and C. Fallesen, "A polar linearisation system for RF power
amplifiers," in 7th IEEE International Conference on Electronics, Circuits
Systems, (Kaslik, Lebanon), December 2000.
[9] P. Asbeck and C. Fallesen, "A 29dBm 1.9GHz class B power amplifier in a
digital CMOS process," in 7th IEEE International Conference on Electronics,
Circuits Systems, (Kaslik, Lebanon), December 2000.
 Improved Linearity of a Dynamic Supply Voltage Power Amplifier
Using Digital Predistortion
Carsten Fallesen1, 2, Gary Hannington1, Peter M. Asbeck1
1
Department of Electrical and Computer Engineering, UCSD, La Jolla, CA
2
Nokia Mobile Phones, Copenhagen, Denmark
In the dynamic supply voltage (DSV) power amplifier, a dc-dc converter is used to adjust the power supply
voltage provided to the output stage in accordance with the output signal level. This architecture can provide a
significant increase in overall efficiency, particularly if the amplifier is operated at relatively low output power
during a substantial fraction of the time [1,2]. It has been found, however, that the output linearity can be degraded
in the DSV system. The reduced linearity results from a variation in amplifier gain as the supply voltage is varied.
In previous work, it has been shown that by dynamically varying the gate bias in a MESFET-based DSV amplifier
along with the power supply voltage (drain bias, VDD), the linearity of the amplifier can be restored [2]. In this
work, we show that linearization of the DSV amplifier can also be easily performed by predistorting the signal fed
to the amplifier, in a manner that can be accomplished with digital signal processing. Using a MESFET-based
DSV amplifier, we show that DSP-based linearization allows the adjacent channel power ratio (ACPR)
requirements of representative CDMA systems to be met.
The structure of the DSV amplifier (without linearization) is shown in fig.1. A dc-dc converter capable of
rapid modulation (with a bandwidth comparable to that of the output signal bandwidth) is used to vary the supply
voltage VDD over the range 3.4V to 10V, in accordance with the required drain voltage swing of the MESFET.
Fig.2 illustrates the representative efficiency as a function of output power level obtained with a fixed VDD and a
dynamically adjusted VDD. An improvement in overall efficiency of the amplifier can be calculated using the
statistics of the output signal distribution. For representative cases, the improvement is near x1.4 [1]. Using the
DSV technique, however, the amplifier gain G varies with input power level Pin in a manner typically shown in
fig.3. In this work, we have introduced a digitally-computed fixed signal predistortion for an already existing DSP.
The distortion in the power amplifier can be modeled, to lowest order, using bandpass nonlinearity theory.
The AM-AM and AM-PM characteristics of the amplifier are measured using CW single-tone signals, and used to
model the amplifier output amplitude B(t) for modulated signals according to:
B(t) = G(A) ⋅ejΦ(A) ⋅A(t) (1)
where A(t) is the amplitude of the input signal, G(A) is the amplitude-dependent gain of the amplifier and Φ(A) is
the amplitude-dependent phase contribution of the amplifier. The required predistortion is then the inverse function:
Ap(t) = 1/Gdist(A)⋅e-jΦdist(A) ⋅A(t) (2)
where Gdist is the deviation from the linear gain of the amplifier, and Φdist is the deviation from the linear phase
contribution. For an efficient DSP implementation, it is necessary to do the predistortion at baseband, and operate
separately on the I and Q signals. The equations for the predistorted I and Q signals are:
Ip = (I⋅cos Φdist + Q⋅sin Φdist) /Gdist(A), Qp = (Q⋅cos Φdist - I⋅sin Φdist) /Gdist(A) (3)
In our implementation, the I and Q channels outputs were precomputed in software for a specific
pseudorandom output data pattern, and fed to the system with a signal generator which allows arbitrary I and Q
waveforms to be specified. The arbitrary waveforms can contain up to 1 Msample transferred to the signal
generator through a GP-IB bus. The generation of the data is done using a C++ program. The digital predistortion
presented here can be implemented very effectively in an already-existing DSP. The overhead for implementing the
predistortion is six multiplications, one addition, one subtraction and 40-100 data entries in a table.
Measurements of the ACPR were done using a spectrum analyzer. A built-in function for the channel
power calculation was used and the result was transferred to a computer and used for ACPR calculations.
Averaging of results over many runs was done to obtain accurate values. Measurements have shown an
improvement of the ACPR of the power amplifier described above on the order of 4-6 dB, as shown in fig.4. The
output spectrum with or without predistortion is shown in fig. 5 and fig. 6. The resulting output spectrum is capable
of meeting IS-95 requirements. The predistortion also means that the amplifier can be driven further into
compression, thereby achieving a higher efficiency.
[1] G. Hanington, P. F. Chen, V. Radisic, T. Itoh, and P. M. Asbeck, “Microwave Power Amplifier Efficiency Improvement
with a 10 Mhz HBT DC-DC Converter”, 1998 IEEE MTT-S Intl. Microwave Symposium Digest, Vol. 2, pp. 589-592 (1998).
[2] G. Hanington, P.F.Chen, L.Larson, K.Gard, and P. Asbeck (to be published)
 25

20

Efficiency
3.6V
DC-DC
Converter Dynamic VDD
15

VDD supply 10
RF Output

5
VDD = 10V
RF Input

Envelope detector 0
950 MHz PA
Vgg supply 0 5 10 15 20 25

Power out (dBm)

Figure 1: Dynamic supply voltage power amplifier Figure 2: Total efficiency of DSV amplifier

14 Gain 10
12 50
8
10 48
Phase (deg)

With predistortion
Gain (dB)

8 6 46
ACPR (dB)

6 Phase 44
4
42
4
2 40 Without predistortion
2
38
0 0 36
-10 -5 0 5 10 15 20
-6 -4 -2 0 2
Relative input power (dB) Relative Output Power (dB)

Figure 3: Relative gain and phase variation Figure 4: ACPR with or without predistortion vs.
vs. input power output power

0 0

-10 -10
Power(dBm)
Power(dBm)

-20 -20

-30 -30

-40 -40

-50 -50
948.5 949 949.5 950 950.5 951 951.5 948.5 949 949.5 950 950.5 951 951.5
Frequency (MHz) Frequency (MHz)

Figure 5: Spectrum without predistortion Figure 6: Spectrum with predistortion

 A Highly Integrated 1 W CMOS Power Amplifier for GSM-1800
Carsten Fallesen and Per Asbeck Nielsen
Nokia Mobile Phones and Technical University of Denmark
Until now power amplifiers for handheld wireless applications have been produced almost exclusively in GaAs
technologies, with a few exceptions in LDMOS, Si BJT and SiGe HBT. A CMOS power amplifier promises higher
integration as well as lower cost. A typical power amplifier for wireless communication consists of 3 dies and 15-20
passive components plus decoupling. The CMOS power amplifier component count can be reduced to one die and 3-
5 passives plus decoupling. This reduction in component count leads to a dramatic decrease of the cost.
The power amplifier presented in this work is targeted towards the GSM-1800 standard, which has a transmit fre-
quency range of 1710 to 1785 MHz. The power amplifier is designed for a 0.35 µm CMOS process with 5 metal lay-
ers and metal-metal capacitors The power amplifier consists of two stages with integrated input and interstage
impedance matching networks as well as the very first part of the output matching network. The two stages of the
power amplifier operates in class AB. The schematic of the power amplifier is shown in Figure 1 and Figure 2.
The input matching network is a fully integrated highpass LC matching section. This was been chosen since it
incorporates DC blocking and biasing at the same time. The inductor is a spiral inductor implemented in top metal
layer, while the capacitor is made with the two lowest metal layers. The transistor of the input stage is 1 mm wide
and 0.35 µm long. The input stage has an off-chip inductor acting as a RF choke (RFC). The interstage matching net-
work consists of a LC highpass section for the same reasons as the input matching network. The implementation is
made in the same way as the input matching. The output transistor is 8 mm wide and has a length of 0.35 µm , it is
partioned into 6 separate finger transistors, with 30 fingers each. The output matching network is placed primarily
off-chip due to efficiency considerations. In order to have better harmonic termination, a capacitor is placed on-chip,
directly at the drain of the transistor, in parallel with the drain-source capacitor of the transistor. This capacitor termi-
nates the harmonics at the drain, but at the same time it transforms the output impedance even lower. The RFC for the
output stage is incorporated in the output matching network. The output matching network consists of a bandpass T
section, due to the high transformation factor.
The CMOS power amplifier IC has been mounted directly on the PCB, and wire bonded directly on a goldplated
PCB microstrips. The passive components used on the PCB are 0402 and 0603 SMD components. The SMA connec-
tors have been mounted horizontally on the edge of the PCB, in order to reduce the effects of the transition from
SMA connector to PCB microstrip.
The measurements were made in pulsed mode according to the GSM1800 specifications. The highest power
added efficiency was 40% at 1730 MHz, with an output power of 30.3 dBm. The output power and efficiency biased
for maximum power added efficiency vs. frequency is shown in Figure 4. The highest output power obtained was
31.5 dBm at 1670 MHz, with the input power increased to 15 dBm. The output power and efficiency with biases set
for maximum output power vs. frequency is shown in Figure 3. The power amplifier operates on a supply voltage
from 1 V to 4 V. The output power and efficiency vs. supply voltage is shown in Figure 5 The maximum output
power is 32.2 dBm at 4 V.
One of the most important aspects of the reliable design of a power amplifier is accurate simulations, and a lot of
emphasis was put on accurate simulations. The simulations were made in the APLAC simulator, primarily with
small-signal and harmonic balance simulations, but transient simulations have also been used. The simulated and
measured data was compared, a few minor modeling problems were found and corrected. The simulations showed
very good agreement between the simulated and measured results, the output power were predicted within a few
tenths of a dB. The comparison between simulated and measured results are shown in Figure 6.
A redesign with minor adjustments of the input and interstage matching networks will move maximum output
power and efficiency to the GSM-1800 band.The die area including pads is 1.9 sq. mm. The power amplifier consists
of one die, two RFCs and three matching component plus decoupling capacitors, compared to 3 dies and 15-20 pas-
sives plus decoupling capacitors for a typical GaAs power amplifier. This power amplifier gives the highest output
power for a CMOS amplifier in the 1.8 GHz range. The efficiency is better than other CMOS amplifiers using linear
modes[1] and comparable to or better than the switched mode approaches typically used in CMOS [1][3].
[1] Brian Ballweber, Ravi Gupta and David J. Allstot, “Fully-Integrated CMOS RF Power Amplifiers”, 1999 IEEE International
Solid-State Circuits Conference
[2] David Su and William McFarland, “A 2.5-V, 1-V Monolithic CMOS RF Power Amplifier”, IEEE 1997 Custom Integrated Circuit
Conference, 1997.
[3] King-Chun Tsai and P. R. Gray, “A 1.9 GHz 1-W CMOS class-E power amplifier for wireless communications”, IEEE Journal of
Solid-State Circuits, July 1999, pp. 962-970.
 IC PCB
DC Bias DC Bias

Output
Matching

Figure 1 Schematic of the power amplifier. Figure 2 Schematic of the output matching network.

50 50

Output power (dBm) & Power

Output power (dBm) & Power
Added Efficiency (%)

added efficiency (%)

40 40

30 30

20 20

10 10

0 0
1.6 1.65 1.7 1.75 1.6 1.65 1.7 1.75
Frequency (GHz) Frequency (GHz)

Figure 3 Measured output power and efficiency, biased for Figure 4 Measured output power and efficiency, biased for
maximum output power. maximum power added efficiency.

50
Output power (dBm) & Power

35
40
added efficieci (%)

Output power (dBm)

34

30 33

20 32

10 31

0 30
1.6 1.65 1.7 1.75
1 1.5 2 2.5 3 3.5 4
Frequency (GHz)
Supply voltage (V)

Figure 5 Measured output power and efficiency vs. supply Figure 6 Comparison of simulated and measured data.
voltage.

Process 0.35 µm CMOS

Supply voltage 3.5 V
Input power 5 dBm
Output power 31.5 dBm
Frequency 1710-1785 MHz
Drain efficiency 45%
Total efficiency 40%
Die area 1.9 sq. mm

Figure 7 Photograph of the power amplifier IC Table 1. Characteristics of the power amplifier
 $+LJKO\,QWHJUDWHG:&0263RZHU$PSOLILHU
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Carsten Fallesen and Per Asbeck
Nokia Denmark A/S and Technical University of Denmark
Phone: +45 33292467 Fax: +45 33292001
[email protected]

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Until now power amplifiers for wireless applications have been produced almost exclu-
sively in GaAs technologies, with a few exceptions in LDMOS, Si BJT and SiGe HBT. The
submicron CMOS processes are now usable for power amplifier design, and are without doubt
the cheapest processes available. Due to the high yield in CMOS fabrication, higher integra-
tion is possible. A CMOS power amplifier therefore promises both higher integration and
lower cost. A typical power amplifier module for wireless communication consists of 3 dice
and 15-20 passive components plus decoupling. The CMOS power amplifier component
count can be reduced to one die and 3-5 passives plus decoupling. This reduction in compo-
nent count leads to a significant reduction in power amplifier cost.
Until recently, linearity of power amplifiers have not been a problem in most wireless stan-
dards. This was due to the fact that most systems, such as GSM, were constant envelope mod-
ulated, meaning that no information was stored in the amplitude. But non-constant envelope
systems, such as IS-95 and WCDMA, have introduced the need for linear power amplifiers.
The problem with nonlinear power amplifiers and amplitude modulated systems is caused
by spectral regrowth, due to the AM-PM conversion in the power amplifier. This means that
the modulated signal will leak into the neighboring channels. The leakage is characterized by
the adjacent channel power ratio (ACPR), relating the power in the channel to the power
leaked into the neighboring channel.
The requirement of IS-95 is an ACPR of 26 dB. This is, however, only the start, in the 3G
WCDMA wireless standards the requirement is 42 dB. Because of this, more effort will have
to be placed in the design of linear power amplifiers. The linearity can be achieved by design-
ing class A amplifiers with low efficiency or by applying linearization techniques to relatively
linear power amplifiers.
The power amplifier presented in this work is targeted towards the GSM-1800 standard,
which has a transmit frequency for the handset of 1710 to 1785 MHz. The goal has been to
design a power amplifier with a 1 W output power with a linearity sufficient to handle the
transition to 3G mobile standards, including the upcoming EDGE standard. The linearity will
be improved using linearization techniques in either software or hardware. However, it is
important that the starting point is reasonable, this is the case for the designed class AB power
amplifier.

 7+('(6,*1('&,5&8,7

DC Bias DC Bias

Figure 1 Schematic of the power amplifier.

The power amplifier is designed for a 0.35 µm bulk CMOS process with a substrate resis-
tivity of 10-20 Ω-cm. The process has 5 metal layers and thin-oxide metal-metal capacitors.
The special metal-metal capacitors has a high density and therefore the die size (cost) of the
complete power amplifier can be reduced.
The power amplifier consists of two stages with integrated input and interstage impedance
matching networks as well as the very first part of the output matching network. The sche-
matic of the power amplifier is shown in Figure 1.The input matching network transforms the
conjugate gate impedance to 50 Ω and cancels the effect of the bondwires. It is made with a
fully integrated highpass LC matching section. This has been chosen because it incorporates
DC blocking and biasing at the same time. The inductor is a spiral inductor implemented in
the top metal layer, while the capacitor is made with the two lowest metal layers.
The input stage operates in class AB, delivering up to 15 dB gain at maximum output
power. The transistor of the input stage is 1 mm wide and 0.35 µm long. The input stage has
an off-chip inductor acting as a RF choke (RFC).
The interstage matching network consists of a LC highpass section for the same reasons as
the input matching network. The implementation is made in the same way as the input match-
ing, but the interstage matching transforms the gate impedance of the output transistor to the
desired output load of the input stage.The output stage operates in class AB close to class B.
There are a number of reasons to choose this mode of operation:
1. Class AB close to class B is relatively linear. This is not the case for class C and E
amplifiers. The linearity is, however, not as good as class A.
2. The efficiency is relatively good, the theoretical maximum is 78.5%, compared with
50% for the class A amplifiers and Class C and E amplifiers have theoretical efficien-
cies of up to 100%.
3. The maximum drain voltage is twice the supply voltage, this is important due to the
possible breakdown of the gate-oxide. Class C and E amplifiers easily exceed three
times the supply voltage.
4. The power utilization factor (PUF), which is a measure of the gain compared to the
output power, is reasonable compared with class A, and better than class C and E.
 5. The required output load impedance is not too low to implement efficiently, which is
often the case for class C.
The output transistor is 8 mm wide and has a length of 0.35 µm as the input stage. The tran-
sistor is partitioned into 6 separate finger transistors, with 70 fingers each. The gain of the out-
put stage is approximately 12 dB.
The output matching network is placed primarily off-chip due to efficiency considerations.
In order to have better harmonic termination, a capacitor is placed on-chip, directly at the
drain of the transistor, in parallel with the drain-source capacitor of the transistor. This capaci-
tor terminates the harmonics at the drain, but at the same time it transforms the output imped-
ance even lower, leaving a more difficult matching problem. The RFC for the output stage is a
relatively short microstrip which can be implemented without increasing the PCB size. The
output matching network consists of a bandpass T section, due to the high transformation fac-
tor from 4 Ω to 50 Ω. The choice of the T section gives a larger bandwidth than a single L sec-
tion. In the design of the network, the parasitics of the RFC microstrip has to be included.
In the design phase the two amplifier stages were initially treated separately and optimized
for 50 Ω input and output matching using load-pull simulations. After each stage had been
optimized an interstage matching network was designed using the impedances found for each
stage.

 6,08/$7,216
In order to make precise simulations the PCB was characterized using simple short, open
and through structures. Using this approach, the transients in the SMA connector to PCB
interface could be modeled accurately. The simulations of these test structures were very pre-
cise up to 4 GHz. After the SMA connectors and PCB were characterized, the output matching
network was simulated and measured.
The PCB has been modeled with microstrip lines and the SMD components have been
modeled according to vendor specifications. The bondwires have been modeled as inductors
and the mutual coupling between the bondwires were included as well.
The measurements of the output matching network, were performed by mounting a short
piece of semi-rigid cable in place of the IC. The shield of the cable was soldered to the ground
plane, where the IC was supposed to be placed. The conductor of the cable was attached at the
microstrip on the PCB where the bondwires from the output of the IC would go.
The IC simulations were based on parasitic extraction from the transistor and passive lay-
out. The transistors were modeled by the MOS9 model. The spiral inductors and the metal-
metal capacitors were simulated using lumped models delivered by the foundry.

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 The simulations were made in the APLAC simulator, primarily with small-signal and har-
monic balance simulations. For verification purposes transient simulations have been per-
formed in the Eldo simulator. The harmonic balance simulations proved to be faster than the
transient simulations, since only the steady-state solution is calculated, the precision of the
simulations proved to be the same.
The simulations for the complete power amplifier including the PCB showed very good
agreement between the simulated and measured results. The measured output power was pre-
dicted within a few tenths of a dB. The comparison between simulated and measured output
power is shown in Figure 2.

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frequency, biased for maximum efficiency frequency, biased for maximum output power

The CMOS power amplifier IC was been mounted directly on the PCB, and wire bonded
directly onto the PCB microstrips. To enable the wire bonding, the PCB was gold plated, the
dielectric used in this work was standard FR4, with a relative dielectric constant of approxi-
mately 4.3 at 1.75 GHz.
The PCB can be produced either with a PCB milling machine or at a normal PCB produc-
tion facility. The first approach offers some advantages during the prototyping phase of the
design. A new PCB can be built within hours, allowing for larger exploration of the design
space, particularly the topology of the output matching network.
The passive components used on the PCB were 0402 and 0603 SMD components. The
SMA connectors were mounted horizontally on the edge of the PCB, in order to reduce the
effects of the transition from SMA connector to PCB microstrip.
To get a realistic picture of the performance, the measurements were made in pulsed mode
according to the GSM1800 specifications, this means a duty cycle of 12.5%.
The highest power added efficiency was 45% at 1730 MHz, with an output power of 30.4
dBm. The output power and efficiency measurements with the power amplifier biased for
maximum power added efficiency vs. frequency are shown in Figure 3
The highest output power obtained was 31.3 dBm at 1720 MHz. The output power and effi-
ciency measurements with biases set for maximum output power vs. frequency are shown in
Figure 4.
The power amplifier operates on a supply voltage from 1 V to 4 V. The output power and
efficiency vs. supply voltage is shown in Figure 5 The maximum output power is 32.2 dBm at
4 V.
  50



L
(IILFLHQF\
P F
45
H
% L
F
G L
I
40
 I
U
H H
 35
Z G
R H
S G
 G
30
W
D
X 
S U
W H
25 2XWSXW3RZHU
X Z
2 R 20
3
1 2 3
6XSSO\YROWDJH  9

Figure 5 Measured output power and efficiency vs. supply voltage at 1730 MHz.

Due to a mismatch in the input impedance matching network, the gain of the power ampli-
fier is lower than predicted at design time. The mismatch was caused by an error in the estima-
tion of the parasitics of input pins.
Since the power amplifier is operating in class AB, it is inherently more linear, than e.g. the
class C, D and E amplifiers demonstrated in CMOS so far [1][3][5][6]. This means that the
power amplifier is suitable for digital predistortion. The adjacent channel power of the power
amplifier was made without any optimizations towards lower ACPR. The measurements
showed that the ACPR requirements of EDGE was met up to 2 dB from maximum required
output power. At the maximum required output power the ACPR was -32 dBc, whereas the
requirement of EDGE is -40 dBc. It has been shown, that an improvement of the adjacent
channel power ratio (ACPR) of 8-10 dB, is possible with simple low-power digital predistor-
tion [7][8]. This means that the power amplifier can be used for EDGE if a simple digital pre-
distortion system is incorporated into the DSP.
A comparison of all the published CMOS power amplifier results is shown in Table 1. As
can be seen from the table no other CMOS power amplifier has been published with a output
power or efficiency as high as the work presented here.

)UHTXHQF\ 3RXW 3$(

0+] G%P  &ODVV
T. Melly et. al. [1] 430 4.0 15 C
S.-J. Yoo et. al. [2] 433 13.0 30 AB
D. Su et. al. [3] 830 30.0 42 D
B. Ballweber et. al. [4] 900 19.3 23 AB
C. Yoo et. al. [5] 900 29.5 41 E
K.-C. Tsai et. al. [6] 1980 30.0 41 E
Asbeck et. al. [9] 1950 29.2 27 B
7KLVZRUN    $%
Table 1. Comparison of CMOS Power Amplifiers
 Process 0.35 µm CMOS
Supply Voltage 3.5 V
Output Power 31.2 dBm
Frequency 1710-1785 MHz
Max. PAE 45%
Die area 1.9 sq. mm

Figure 6 Die photograph Table 2. PA summary

 &21&/86,21
A CMOS power amplifier has been presented with a power added efficiency of 45% with
an output power of 30.4 dBm at 1730 MHz. When biased for maximum output power 31.2
dBm is delivered while maintaining an efficiency of 42%. The die area including pads is 1.9
sq. mm. By accurately modeling bondwires, microstrips and SMD components the accuracy
of the simulations was improved, and is now within a few tenths of a dB, compared to mea-
sured results.
The power amplifier consists of one die, one RFC, one microstrip and two matching com-
ponents plus decoupling capacitors, compared to 3 dice and 15-20 passives plus decoupling
capacitors for a typical GaAs power amplifier.
The power amplifier operates in class AB, which gives good output power, efficiency and
linearity. Until now no CMOS power amplifiers with this output power or efficiency have
been published. The fact that this power amplifier is relatively linear, means that it is useful in
wireless applications, especially in systems which utilize amplitude modulation. With a digital
predistortion system the power amplifier can be used for EDGE.

 5()(5(1&(6
[1] T. Melly, A.-S. Porret, C. C. Enz, M. Kayal and E. Vittoz, “A 1.2V, 430 MHz, 4 dBm Power
Amplifier and a 250µW Front-End, using a Standard Digital CMOS Process”, 1999 International
Conference on Low Power Electronics and Design, pp. 233-237.
[2] Seoung-Jae Yoo, Hong Jo Ahn, M. M. Hella and M. Ismail, “The Design of 433 MHz Class AB
CMOS Power Amplifier”, 2000 Southwest Symposium on Mixed-Signal Design, pp. 26-40.
[3] David Su and William McFarland, “A 2.5-V, 1-V Monolithic CMOS RF Power Amplifier”, IEEE
1997 Custom Integrated Circuit Conference, 1997.
[4] Brian Ballweber, Ravi Gupta and David J. Allstot, “Fully-Integrated CMOS RF Amplifiers”, 1999
IEEE International Solid-State Circuits Conference, 1999, pp. 154-155.
[5] Changsik Yoo and Qiuting Huang, “A Common-Gate Switched, 0.9W Class-E Power Amplifier with
41% PAE in 0.2 µm CMOS”, 2000 Symposium on VLSI Circuits, pp. 56-57.
[6] King-Chun Tsai and P. R. Gray, “A 1.9 GHz 1-W CMOS class-E power amplifier for wireless
communications”, IEEE Journal of Solid-State Circuits, July 1999, pp. 962-970.
[7] Carsten Fallesen, Gary Hanington and Peter M. Asbeck, “Improved Linearity of a Dynamic Supply
Voltage Power Amplifier Using Digital Predistortion“, IEEE Topical Workshop on Power
Amplifiers, San Diego, Septembere,1999.
[8] M. Ranjan, K. H. Koo, G. Hanington, C. Fallesen and P. Asbeck, “Microwave Power Amplifiers with
Digitally-Controlled Power Supply Voltage for High Efficiency and High Linearity”, International
Microwave Symposium, Boston June, 2000.
[9] Per Asbeck and Carsten Fallesen, “A Power Amplifier for Wireless Applications in a Digital CMOS
Process”, Submitted to NorChip 2000.
 A 1W CMOS Power Amplifier for GSM-1800 with 55% PAE
Carsten Fallesen1,2 and Per Asbeck1,2
1Nokia Denmark, Copenhagen, DK-1790, Denmark
2Technical University of Denmark, Lyngby, DK-2800, Denmark

Abstract -- Until recently it was the common opinion that Then the class of operation was chosen for each of the
CMOS RF power amplifiers were not feasible for mobile stages. The input and output stages operates in class AB
handsets. This paper presents a CMOS power amplifier for
close to class B. There are a number of reasons to choose
the GSM-1800 standard, with only two external matching
components and a few decoupling capacitors. The perfor- this mode of operation:
mance of the power amplifier is better than any other CMOS 1. Class AB close to class B is relatively linear. This is not
power amplifier reported and comparable to commercially the case for class C and E amplifiers. The linearity is,
available power amplifier in other technologies.
however, not as good as class A.
2. The efficiency is relatively good, the theoretical maxi-
I. INTRODUCTION mum is 78.5%, compared with 50% for the class A
This paper presents the results achieved in the design of amplifiers and Class C and E amplifiers have theoreti-
a 1W CMOS power amplifier for GSM-1800. Due to the cal efficiencies of up to 100%.
high yield in CMOS fabrication, higher integration is pos- 3. The maximum drain voltage is twice the supply volt-
sible than e.g. in GaAs processes. A CMOS power ampli- age, this is important due to the possible breakdown of
fier therefore promises both higher integration and lower the gate-oxide. Class C and E amplifiers easily exceed
cost. A typical power amplifier module for wireless com- three times the supply voltage.
munication consists of 2-3 dice and 15-20 passive compo- 4. The power utilization factor (PUF), which is a measure
nents. The CMOS power amplifier component count can of the gain compared to the output power, is reasonable
be reduced to one die and 2-5 passives plus decoupling. compared with class A, and better than class C and E.
This reduction in component count leads to a significant
reduction in power amplifier cost. 5. The required output load impedance is not too low to
The power amplifier presented in this work is targeted implement efficiently, which is often the case for class
towards the GSM-1800 standard, which has a transmit fre- C.
quency for the handset of 1710 to 1785 MHz. The goal has Once the class of operation was chosen for the output
been to design a power amplifier with a 1 W output power stage it was possible to start the dimensioning of the output
transistor. This dimensioning was an iterative process
where the initial guess originated from the I-V characteris-
II. DESIGN tic of the power amplifier. From the I-V characteristic it
The design of this power amplifier followed the design was possible to find the voltage and current swings possi-
and simulation methodologies described in [1]. The design ble for a given load-line. From the voltage and current
is the second iteration of a 1W CMOS power amplifier for swings the maximum output power was then determined
GSM-1800, results of the first iteration have previously and a reasonable size of the transistor was found.
been presented [2]. This power amplifier shows higher After an initial value is selected the more accurate RF
integration and much better efficiency than previously pre- behavior is found using load-pull simulations. The load-
sented. pull simulations are the simulation equivalent of the load-
The power amplifier is designed for a 0.35 µm bulk pull measurements.
CMOS process with a substrate resistivity of 10-20 Ω-cm. The final schematic of the power amplifier is shown in
The process has 5 metal layers and thin-oxide metal-metal Fig 1 where the components mentioned below can be
capacitors. The thin-oxide metal-metal capacitors have a located. The output transistor (M2) was then chosen to be 8
high density and therefore the die size (cost) of the com- mm wide and with a length of 0.35 µm. The transistor is
plete power amplifier can be reduced. partitioned into 6 separate finger transistors, with 70 fin-
The first choice to make was the number of stages in the gers each. The input stage also operates in class AB. The
power amplifier. In this case a two-stage methodology was transistor of the input stage (M1) is 1 mm wide and 0.35
chosen. µm long.
 Vpc
RFC1

RFC2

C3
Bias
Lis
L1
Lin M2 C1 C2
In Cis
M1
Cin

Fig 1. Simplified schematic of the power amplifier.

The output matching network is placed primarily off- microstrip. The die photo is shown in Fig 5 while the PCB
chip due to efficiency considerations. In order to have bet- is shown in Fig 4.
ter harmonic termination, a capacitor (C1) is placed on- To get a realistic picture of the performance, the mea-
chip, directly at the drain of the transistor, in parallel with surements were made in pulsed mode according to the
the drain-source capacitor of the transistor. This capacitor GSM1800 specifications, this means a duty cycle of
terminates the harmonics at the drain, but at the same time 12.5%.
it transforms the output impedance even lower, leaving a The highest power added efficiency was 55% at 1750
more difficult matching problem. The RF chokes (RFC1, MHz, with an output power of 30.4 dBm. The output
RFC2) for the output stage as well as the input stage are power and efficiency measurements with the power ampli-
relatively short microstrips, which can be implemented fier biased for maximum power added efficiency vs. fre-
without increasing the overall PCB size. The output match- quency are shown in Fig 1.
ing network consists of a bandpass T section (L1, C2, C3),
due to the high transformation factor from 4 Ω to 50 Ω.
Power Added Efficiency (%)

The choice of the T section gives a larger bandwidth than a 60 Power Added Efficiency
Output power (dBm) &

single L section. The inductor in the T section consists of a 55

contribution from the bondwires as well as from the 50
microstrip. In the design of the network, the parasitics of 45
the RFC microstrip were also included. 40
The input and interstage matching networks were both 35 Output Power
made with a fully integrated highpass LC matching sec- 30
tion. This was chosen because it incorporates DC blocking 25
and biasing at the same time as the impedance matching. 1.65 1.7 1.75 1.8 1.85
The on-chip inductors are spiral inductors implemented in
Frequency (GHz)
the top metal layer, while the capacitors are made thin-
oxide metal-metal capacitors in the two lowest metal lay-
Fig 1. Output power and power added efficiency vs. frequency.
ers.
The power amplifier operates on a supply voltage from 1
V to 3.4 V. The output power and efficiency vs. supply
III. MEASUREMENTS
voltage is shown in Fig 2. The output power is 20.8 dBm at
The CMOS power amplifier IC was been mounted 1V and 31.4 dBm at 3.4 V. The power added efficiency
directly on the PCB and wire bonded directly onto the PCB varies from 43% to 55% at 1V and 3.4V respectively.
microstrips. To enable the wire bonding, the PCB was gold A comparison of all the published CMOS power ampli-
plated, the dielectric used in this work was standard FR4, fier results is shown in Table I. As can be seen from the
with a relative dielectric constant of approximately 4.3 at table no other CMOS power amplifier has been published
1.75 GHz. with output power or power added efficiency as high as the
The passive components used on the PCB were 0402 work presented here.
SMD components. The SMA connectors were mounted The simulations for the complete power amplifier
horizontally on the edge of the PCB, in order to reduce the including the PCB showed very good agreement between
effects of the transition from SMA connector to PCB the simulated and measured results. The measured output
 REFERENCES
[1] C. Fallesen and P. Asbeck, "Structured design and modeling
Power added efficiency (%)
60 Power Added Efficiency
of highly integrated RF power amplifiers." Submitted to
Output power (dBm) &

55
RFIC-2001.
50 [2] C. Fallesen and P. Asbeck, "A 1 W 0.35 um CMOS power
45 amplifier for GSM-1800 with 45% PAE," in 2001 IEEE
40 International Solid-State Circuits Conference, (San Fran-
35 cisco, USA), February 2001.
30 [3] S.-J. Yoo, H. J. Ahn, M. M. Hella, and M. Ismail, "The
25 Output Power design of 433 MHz class AB CMOS power amplifier," in
20 2000 Soutwest Symposium on Mixed-Signal Design, pp. 26--
1 1.5 2 2.5 3 3.5
40, 2000.
[4] B. Ballweber, R. Gupta, and D. J. Allstot, "Fully-integrated
Supply voltage (V) CMOS RF amplifiers," in International Solid-State Circuits
Conference, pp. 154--155, 1999.
Fig 2. Measured output power and power added efficiency vs. [5] P. Asbeck and C. Fallesen, "A RF power amplifier in a digi-
supply voltage at 1750 MHz. tal CMOS process," in 18th NorChip Conference, (Turku,
Finland), November 2000.
power was predicted within a few tenths of a dB. The effi- [6] T. Melly, A.-S. Porret, C. C. Enz, M. Kayal, and E. Vittoz,
ciency deviated less than 1%. The comparison between "A 1.2V, 430 MHz, 4 dBm power amplifier and a 250uW
simulated and measured output power is shown in Fig 3. front-end, using a standard digital CMOS process," in 1999
International Conference on Low Power Electronics and
Design, pp. 233--237, 1999.
[7] D. Su and W. McFarland, "A 2.5-V, 1-W monolithic CMOS
60 Power Added Efficiency
Output power (dBm) & Power

RF power amplifier," in IEEE 1997 Custom Integrated Cir-

55 cuit Conference, 1997.
Added Efficiency (%)

50 [8] C. Yoo and Q. Huang, "A common-gate switched, 0.9W

class-E power amplifier with 41% PAE in 0.2 um CMOS,"
45
in 2000 Symposium on VLSI Circuits, pp. 56--57, 2000.
40 [9] K.-C. Tsai and P. R. Gray, "A 1.9 GHz 1-W CMOS class-E
35 Output Power power amplifier for wireless communications," IEEE Jour-
30 nal of Solid-State Circuits, July 1999.
25
1.7 1.75 1.8
Frequency (GHz)

Fig 3. Comparison of simulated and measured data.

IV. CONCLUSION
A CMOS power amplifier has been presented with a
power added efficiency of 55% with an output power of
30.4 dBm at 1750 MHz. The power amplifier is designed
for GSM-1800 with a supply voltage of 3V, although it per-
forms very well from 1V to 3.4V. The die area including
pads is 1.1 sq. mm. By accurately modeling bondwires,
microstrips and SMD components the accuracy of the sim-
ulations was within a few tenths of a dB, compared to mea-
sured results.
The power amplifier consists of one die, two short
microstrips and two matching components plus decoupling
capacitors, compared to 3 dice and 15-20 passives plus
Fig 4. PCB photograph.
decoupling capacitors for a typical GaAs power amplifier.
The power amplifier has higher power added efficiency
than any other CMOS power amplifier results published so
far, whether they operate linearly [3][4][5][2] or nonlin-
early [6][7][8][9].
 TABLE I
COMPARISON OF CMOS POWER AMPLIFIERS.

Frequency Pout PAE

(MHz) (dBm) (%) Class
T. Melly et. al. [6] 430 4.0 15 C
S.-J. Yoo et. al. [3] 433 13.0 30 AB
D. Su et. al. [7] 830 30.0 42 D
B. Ballweber et. al. [4] 900 19.3 23 AB
C. Yoo et. al. [8] 900 29.5 41 E
K.-C. Tsai et. al. [9] 1980 30.0 41 E
Asbeck et. al. [5] 1950 29.2 27 B
Fallesen et. al. [2] 1730 30.4 45 AB
This work 1750 30.4 55 AB

Fig 5. Die photograph.

Ørsted•DTU
Technical University of Denmark
Ørsteds Plads
DTU-Building 348
DK-2800 Kgs. Lyngby
www.oersted.dtu.dk ISBN 87-91184-01-0