Silicon VLSI Technology Fundamentals, Practice and Modeling © 1999

by Plummer, Deal and Griffin

device parameters such as MOS threshold or turn-on voltage. In principle we could counter dope
the surface regions of the buried layers with opposite type dopants to produce these regions, but
this is not a manufacturable technique. This is easy to see if we imagine trying to counter dope a
1.0 x 1019 cm-3 N+ buried layer to form a 1.0 x 1016 cm-3 N layer. This would require 0.999 x 1019
cm-3 P type counter doping. No doping technique available today provides this degree of precision.

Boron

P+ Implant

N+ Buried Layer

P
P

Fig. 2.18: Process option incorporating buried and epitaxial layers. The P+ buried layer is implanted
using the thick SiO2 layer as a mask.

N + Buried Layer P+ Buried Layer

P
P

Fig. 2.19: Process option incorporating buried and epitaxial layers. The P+ and N+ buried layers
are driven-in together.

Fortunately there is an alternative, a process called epitaxy. The oxide layer on the surface
of the wafer in Fig. 2.19 is first stripped in an HF solution. This acid is highly selective to SiO2
over Si. After cleaning, the wafers are then placed into an epitaxial reactor which heats the wafers
to temperatures on the order of 800 - 1000˚C and exposes them to a gas ambient containing Si and
a small concentration of dopant. SiH4 or SiH2Cl2 might be used as the silicon source and B2H6 or
AsH3 for the P or N type doping, for example. The process of epitaxy is conceptually simple. Si
atoms fall on the wafer surface from the gas stream above it. At the high temperature in the reactor,

61
Silicon VLSI Technology Fundamentals, Practice and Modeling © 1999
by Plummer, Deal and Griffin

the Si atoms are somewhat mobile on the surface and can diffuse via surface diffusion to a lattice
site to which they can bond. Through this process, the crystal structure of the substrate is grown
upward, atom by atom, and layer by layer, producing a perfect crystalline or “epitaxial” layer. The
doping atoms in the gas stream are incorporated into the growing epitaxial layer in the same
manner. This process allows us to grow single crystal layers on single crystal substrates at a rate
of several tenths of a micron per minute and to dope those layers from 1014 cm-3 to 1020 cm-3 N or
P type. We will study this process in more detail in Chapter 9. In fact, epitaxy is really a special
case of CVD which we previously used to deposit Si3N4 and SiO2 layers. In epitaxy, the substrate
must be single crystal; in the more general CVD process, arbitrary substrates can be used because
the films that are deposited are amorphous or polycrystalline.
Fig. 2.20 illustrates our CMOS wafer after an epitaxial layer has been grown. The epilayer
for our devices is grown undoped (intrinsic) since we will be doping various parts of it later in the
process using ion implantation. The epilayer might typically be a few microns thick. Notice that
the step in the silicon surface which we created by oxidation of the N+ buried layers has propagated
upward during epi growth, so that it now appears on the new wafer surface. This step is visible
under an optical microscope and is necessary in order to align subsequent masks to the buried layer
patterns.

Epitaxial Layer

N + Buried Layer P+ Buried Layer

P
P

Fig. 2.20: Process option incorporating buried and epitaxial layers. The surface SiO2 layer is
stripped off the wafer and an epitaxial layer is then grown.

The remaining steps in this process option would follow the LOCOS steps (Figs. 2.3 - 2.5)
and the P and N well steps (Figs. 2.10 - 2.12). After the wells are driven-in, they link up with the
buried layers (which also diffuse upwards during all high temperature steps) as shown in Fig. 2.21.
Both downward and upward diffusion must be accounted for in order to determine the time and
temperature needed to accomplish this link-up. A typical set of conditions might be several hours
at 1000 - 1100˚C depending on the exact epitaxial layer thickness. This could be performed in a
largely inert ambient because no additional surface oxidation is needed at this point. Note that the
incorporation of the buried and epitaxial layers into the structure has only required one additional
mask (but many process steps!). As was the case in Fig. 2.12, the substrate as shown in Fig. 2.21

62
Silicon VLSI Technology Fundamentals, Practice and Modeling © 1999
by Plummer, Deal and Griffin

is now ready for active device fabrication. The step in the surface shown in Fig. 2.20 would still
be present in Fig. 2.21, but is not explicitly shown.

N Well P Well

N+ Buried Layer P+ Buried Layer

Fig. 2.21: Process option incorporating buried and epitaxial layers.

Finally, the structure shown in Fig. 1.34 is yet another variation on these process steps. This
structure incorporates a P- epitaxial layer and an N well using steps similar to those described
above. The process flow in this case is left as an exercise for the reader. (See Problem 2.1.)

2.2.6 Gate Formation

We now return to the main process flow and Fig. 2.12. If either of the process options
described above were to be used, the substrate would appear as shown in Fig. 2.15 or 2.21, but the
process flow from this point on would be substantially the same. So for simplicity, we will continue
the process description with Fig. 2.12.
The next several steps, shown in Figs. 2.22 - 2.26 are designed to form critical parts of the
MOS devices. Probably the single most important parameter in both the NMOS and PMOS
devices is the turn-on or threshold voltage, discussed in Chapter 1 and usually called VTH. VTH in
its simplest form is given by

2εS qNA (2φ f )

VTH = VFB + 2φf + (2.3)
Cox

where VFB is the gate voltage required to compensate for work function differences between the
gate and substrate, and for any electrical charges that may be present in the gate oxide. φ f is the
position of the Fermi level in the bulk with respect to the intrinsic level and ε S is the permittivity
of silicon. For our present purposes, the two terms that are important are the doping concentration
in the silicon NA and the oxide capacitance Cox. Since Cox is inversely proportional to the gate
oxide thickness, it is clear that we must control this thickness in order to control VTH.
In writing the above expression, we have assumed that the doping in the silicon under the
MOS gate is constant at NA. This is usually not the case in modern devices because ion
implantation is used to adjust the threshold voltage and this results in a non-uniform doping profile.
Again to first order, we can include the effect of the implant on VTH in the following way.

63