Sardar Patel Institute of Technology
Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058-India
(Empowered Autonomous Institute Affiliated to University of Mumbai)
Electronics and Telecommunication Engineering Department
Academic year 2024-2025
Experiment No. 6
AIM :To Design, implement and verify the functionality of the given Combinational/ Sequential logic
(anyone) using FPGA Development Board .
The given Combinational/ Sequential logic will be any of the following but not limited to Decoder, Encoder,
Multiplexer, Demultiplexer, Adder, Subtractor, Parity generator, Comparator, Synchronous Counter,
Asynchronous Counter, Ripple Counter, Shift Register etc. The students are expected to choose the appropriate
style of modeling in Verilog/VHDL.
PROBLEM STATEMENT:
1. Draw the schematic of the given Combinational/ Sequential circuits. Write a truth table in support of
the given combinational/ sequential circuits.
2. Develop the Verilog code of the given Combinational/Sequential circuits. Simulate in Vivado design
suite and verify the truth table by developing the test bench.
3. Program the FPGA Development Board by Synthesizing the code and check the functionality of the
design by appropriately selecting the input/output device on the board.
4. Take the screenshot of the simulation showing verification of the Truth table of the given
Combinational/Sequential circuit and the FPGA Development Board.
SCHEMATIC DIAGRAM:
Name: Dhruv Santosh Warik Batch:B4
UICD: 2023200130 Class:SE EXTC B
Sardar Patel Institute of Technology
Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058-India
(Empowered Autonomous Institute Affiliated to University of Mumbai)
Electronics and Telecommunication Engineering Department
Academic year 2024-2025
Name: Dhruv Santosh Warik Batch:B4
UICD: 2023200130 Class:SE EXTC B
Sardar Patel Institute of Technology
Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058-India
(Empowered Autonomous Institute Affiliated to University of Mumbai)
Electronics and Telecommunication Engineering Department
Academic year 2024-2025
Name: Dhruv Santosh Warik Batch:B4
UICD: 2023200130 Class:SE EXTC B
Sardar Patel Institute of Technology
Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058-India
(Empowered Autonomous Institute Affiliated to University of Mumbai)
Electronics and Telecommunication Engineering Department
Academic year 2024-2025
HDL PROGRAMMING:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
port(x : in std_logic;
clk : in std_logic;
reset : in std_logic;
z : out std_logic;
warning : out std_logic);
end counter;
architecture Behavioral of counter is
type states is (A,B,C,D,E);
signal current_state,next_state:states;
begin
Name: Dhruv Santosh Warik Batch:B4
UICD: 2023200130 Class:SE EXTC B
Sardar Patel Institute of Technology
Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058-India
(Empowered Autonomous Institute Affiliated to University of Mumbai)
Electronics and Telecommunication Engineering Department
Academic year 2024-2025
transition:process(clk)
begin
if rising_edge(clk) then
current_state <= next_state;
end if;
end process;
output: process(x,current_state)
begin
z<= '0';
if reset<='0' then
case current_state is
when A => if x = '0' then
z <= '0';
next_state <= A;
warning<='1';
else
z <= '0';
next_state <= B;
end if;
when B => if x = '0' then
z <= '0';
next_state <= A;
warning<='1';
Name: Dhruv Santosh Warik Batch:B4
UICD: 2023200130 Class:SE EXTC B
Sardar Patel Institute of Technology
Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058-India
(Empowered Autonomous Institute Affiliated to University of Mumbai)
Electronics and Telecommunication Engineering Department
Academic year 2024-2025
else
z <= '0';
next_state <= C;
end if;
when C => if (x = '0') then
z <= '0';
next_state <= D;
else
z <= '0';
next_state <= A;
warning<='1';
end if;
when D => if x = '0' then
z <= '0';
next_state <= A;
warning<='1';
else
z <= '0';
next_state <= E;
end if;
when E => if x = '0' then
z <= '1';
next_state <= A;
Name: Dhruv Santosh Warik Batch:B4
UICD: 2023200130 Class:SE EXTC B
Sardar Patel Institute of Technology
Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058-India
(Empowered Autonomous Institute Affiliated to University of Mumbai)
Electronics and Telecommunication Engineering Department
Academic year 2024-2025
else
z <= '0';
next_state <= A;
warning<='1';
end if;
end case;
else next_state<=A;
end if;
end process;
end Behavioral
#constraints file
set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS33 PULLDOWN true}
[get_ports {clk}];
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
#Button-left
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS33 PULLDOWN true}
[get_ports {reset}];
#Button-right
set_property -dict { PACKAGE_PIN L4 IOSTANDARD LVCMOS33 } [get_ports {x}];
set_property -dict { PACKAGE_PIN H3 IOSTANDARD LVCMOS33 } [get_ports {warning}];
set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {z}];
#set_property -dict { PACKAGE_PIN N11 IOSTANDARD LVCMOS33 } [get_ports { clk }];
Name: Dhruv Santosh Warik Batch:B4
UICD: 2023200130 Class:SE EXTC B
Sardar Patel Institute of Technology
Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058-India
(Empowered Autonomous Institute Affiliated to University of Mumbai)
Electronics and Telecommunication Engineering Department
Academic year 2024-2025
RESULTS AND ANALYSIS:
After the successful implementation and synthesis of the VHDL code for the BCD counter, we generated
a bitstream file. This file is essential for configuring the Atrix 7 FPGA board, allowing it to execute the
designed counter functionality. The bitstream contains all the necessary configuration data for the FPGA,
ensuring that the hardware operates according to the specified design.
CONCLUSION:
Through this experiment, I learned how to develop code for an FPGA board, gaining hands-on experience
with VHDL design. I also acquired the skills to generate a bitstream file, which is crucial for
programming the FPGA. Additionally, I learned how to write a constraints file (.xdc) to specify pin
assignments and timing requirements, ensuring that the hardware operates as intended. This
comprehensive understanding of the design flow and implementation processes significantly enhances my
capabilities in digital circuit design.
Name: Dhruv Santosh Warik Batch:B4
UICD: 2023200130 Class:SE EXTC B
