Candidate Name Kumudhwathi C
Total Experience 3.6 years
Relevant Experience 3.6 years
Current Location Bangalore
Preferred Location Bangalore
Bench Profile/ Market (If Market Notice Period) In notice period ( lwd: nov15th)
Current Company Capgemini
Current Client / Project Microchip
Primary Skill (Hands on Experience) DFT( ATPG, SIMULATION, SCAN INSERTION
BASICS , MBIST VALIDATION , POST SILICON
DEBUG)
Additional Skills SPYGLASS , ZOIX , CADENCE
Worked at QC before No
Education & Certification BE in EC , 2020 PASSOUT
Any additional Comments for candidate (Relevant TOTAL OF 3.6 YEARS IN DFT DOMAIN
exp within the industry)
Qualcomm Inputs Supplier Inputs
Name of
Projects in No: of
Skills possessed by the Mandato Description of work done
which the skills months
candidate to perform the role ry / using the skills & Rating
were used worked in
efficiently Optional (0-5) (5 - High,0- - Low)
(add rows if each Project
necessary)
Do Not fill
Unix Commands this
column
Synthesis
STA
Constraints / GCA
Full Chip / SOC STA
Sanity Check
CLP / VCLP
LEC/ Formality
PT-PX
PnR and Resolving Congestion
PV (DRC / LVS / ERC / Antenna
Fixes)
Full Chip PV
PDN (Grid Checks / Static-
Dynamic IR Analysis )
CAD - Shell Scripting
CAD - Perl
CAD – TcL
CAD - Python
Yorktown: 1
year
Yorktown- Titan: 1.8
DFT - ATPG RevB,C, Titan- years 5
RevA , Aria Aria:
8months(on-
going)
5months(on-
DFT - Scan Insertion Aria 3
going)
DFT - MBIST Titan 1 year 3
DFT - LBIST
Yorktown: 1
year
Yorktown- Titan: 1.8
DFT - Pattern Generation RevB,C, Titan- years 5
RevA , Aria Aria:
8months(on-
going)
Yorktown: 1
year
Yorktown- Titan: 1.8
DFT - EDT RevB,C, Titan- years 4
RevA , Aria Aria:
8months(on-
going)
DFT - GLS
Yorktown: 1
year
Yorktown- Titan: 1.8
DFT - LOC / LOS RevB,C, Titan- years 4
RevA , Aria Aria:
8months(on-
going)
DFT - JTAG
ICC -2
Fusion Compiler
Innovous
Genus
DC Compiler
Prime time
Tempus
Caliber
ICV
Tessant
RedHawk
RedHawk - SC
VCLP
Star RC
TestKompress
Tetramax
VCS
DFT Compiler
DFT MAX
Virtuso
Supplier Evaluation Comments
1. Each profile must be technically evaluated and must have the above sheet as a summary on top
of each and every resumes being submitted in Beeline
2. Profile without skills evaluation sheet will be rejected by the VMO
3.All the fields have to be filled completely by suppliers tech panel
4. Ratings have to be provided in the ratings box against each skills
Resume:
Kumudhwathi C
E-mail- [email protected] |
Contact- 6361718224 Experience- 3+
Years of experience in DFT .
To work for an organization which gives an opportunity to upgrade my skills and knowledge in the
field of DFT in VLSI and contribute my skills for the organization.
Academics
Program Institution Board/University CGPA/Percentage Comp
B.E Govt Engineering College Hassan VTU 7.5 CGPA 202
Department of Pre-
PUC Brilliant Pre University College University Education, 89.6% 201
Karnataka
10th Kendriya Vidyalaya, Hassan CBSE 8.4 CGPA 201
Professional Experience
Capgemini - April 2021 - Present
Profile Summary
Experience in DFT - ATPG, Simulation and Pattern Retargeting, PreSilicon on 6nm , Postsili-
con16nm Designs.
Experience in Stuck and Transition pattern generation at block level and retargeting at SoC level.
Experience in Test Coverage Analysis and Improvement for both AC and DC modes.
Experience in No timing Simulations and Timing SDF Simulations (Min & Max Corner).
Experience in ATPG DRC Analysis and Cleanup.
Experience in Reducing VGR (Vector to Gate Ratio)
Experience in Spyglass validation
Basic Knowledge in MBIST validation.
Experience in debugging and analytical skills.
Projects Undertaken
Project 1:
Aria- Block level pattern generation, Validation and Pattern Retargeting
Company: Capgemini
Client: Microchip Technology India Pvt Ltd Blocks: 2
Tools Used: Cadence- Modus, Xcelium, SimVision, Synopsys- VC-Z01X , Spyglass
Roles & Responsibilities
Top mapping validation for both PAD and DCSU-based timing sims with at-speed frequencies
validation.
Create a retarget environment for SoC level including Test Setup.
Collecting the core or Macro-level patterns and retargeting those patterns from the SoC level.
Worked on Coverage Analysis for stuck-at as well as at-speed faults.
Hands-on Synopsys VC-Z01X tool for improved ATPG test Coverage.
Doing some initial setup activities and spyglass for the blocks.
Did simulations to validate the patterns and troubleshoot for any mismatches without
SDF (no timing) and with SDF(Timing) on MIN & MAX corners as well.
Project 2:
Titan- SoC level and Block level pattern generation, Validation and Pattern Re-
targeting
Company: Capgemini
Client: Microchip Technology India Pvt Ltd Blocks: 4 (3 DFT+Layout, 1 Pure DFT region)
Tools Used: Cadence- Modus, Xcelium, SimVision, Synopsys- VC-Z01X
Roles & Responsibilities
Top mapping validation for both PAD and DCSU-based timing sims with at-speed frequencies
validation.
Create a retarget environment for SoC level including Test Setup.
Collecting the core or Macro-level patterns and retargeting those patterns from the SoC level.
Did simulations to validate the patterns and troubleshoot for any mismatches without
SDF (no timing) and with SDF(Timing) on MIN & MAX corners as well.
Worked on Coverage Analysis for stuck-at as well as at-speed faults.
Good Debug knowledge on scan chain broken issues.
Hands-on Synopsys VC-Z01X tool for improved ATPG test Coverage.
Reduced the VGR count as per the tester requirement.
Project 3:
DFT for SSD controllers
Company: Capgemini
Client: Microchip Technology India Pvt Ltd
Block: 2 (1Pure DFT region+1 DFT+LAYOUT)
Tools Used: Modus, Xcelium, Sim vision
Roles & Responsibilites:
Cleaning Scan Chain Blockage in ATPG
Analysis of Severe DRCs in ATPG
Pattern generation for both stuck at & TDF models
Test Coverage Analysis for Static and Dynamic
Test Coverage improvement for Static and Dynamic (AC & DC)
No timing Simulations for Static and Dynamic (AC & DC) and Debugging
Timing Simulations for Static and Dynamic (AC & DC)
Top Re-targetting Simulations for Static and Dynamic
Project 4:
DFT for SSD controllers
Company: Capgemini
Client: Microchip Technology India Pvt Ltd
Block: 1 (Pure DFT region)
Tools Used: Modus, Xcelium, Sim vision
Roles & Responsibilites:
Cleaning Scan Chain Blockage in ATPG
Analysis of Severe DRCs in ATPG
Pattern generation for both stuck at & TDF models
Test Coverage Analysis for Static and Dynamic
Test Coverage improvement for Static and Dynamic (AC & DC)
No timing Simulations for Static and Dynamic (AC & DC) and Debugging
Timing Simulations for Static and Dynamic (AC & DC)
Top Re-targetting Simulations for Static and Dynamic
Project 5:
Training Institute - VLSI GURU
● Multiple clock domains: 3 clocks
● No. of Scan Channels : 8
● Tools used: Tessent Scan, TestKompress, Tessent Fastscan, Questasim
Roles & Responsibilities
● Performed scan insertion with Tessent scan and analyzed scan violations.
● Performed EDT insertion with Testkompress where scan compression ratio is 23.
● Generated patterns for both stuck-at and At-speed using Tessent Fastscan.
● Validation of simulated patterns using Questasim.
● Test coverage analysis on both stuck-at and At-speed
