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Rockchip RV1103G_RV1106G
Hardware Design Guide
(Fuzhou Hardware Development Center)

Identifies：

Version： V1.1
Status:
[ ] draft Author： Linus.Lin
[ ] modifying Date： 2022-12-21
[ √ ] release
Approver：

Date：

瑞芯微电子股份有限公司
Rockchip Electronics Co.,Ltd.
 STATEMENT

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 Revision History

Preface
Overview
This document presents the key points of hardware design and notices for RV1103G/RV1106G
processors, aiming to help customers shorten developing period, improving product design stability and
reducing fault rate. Please refer to the requirements of this guide for hardware design, and use the relevant
core templates released by Rockchip. If you need to modify for special reasons, please strictly follow the
design rule of high-speed-digital-circuit and Rockchip Schematic&PCB checklist requirements.

Chipset model
This document is suitable for the following chipset model: RV1106G, RV1103G

Intended Audience
This this guide is mainly intended for:
 Hardware development engineers
 Layout engineers
 Technical support engineers
 Test engineers

Copyright © 2022 Rockchip Electronics Co., Ltd.

 Revision History

Revision History
This revision history recorded description of each version, and any updates of previous versions are
included in the latest one.

Version Revision
Author Revision Description Remark
No. Date

V1.0 Linus.Lin 2022.06.10 English version initial released (CN V1.1)

Correct the “release the button to make ADCIN1
V1.1 Linus.Lin 2022.12.21 return to high level (1.8V)” to “release the button to
make ADCIN0 return to high level (1.8V)” at 2.3.8

Copyright © 2022 Rockchip Electronics Co., Ltd.

 Contents

Contents
Preface ........................................................................................................................................................... II
Revision History ......................................................................................................................................... III
Contents .......................................................................................................................................................IV
Figures ..........................................................................................................................................................VI
Tables ....................................................................................................................................................... VIII
1 System Introduction .............................................................................................................................. 9
1.1 Overview ..................................................................................................................................... 9
1.2 Chip Differences ......................................................................................................................... 9
1.3 Block Diagram .......................................................................................................................... 10
1.4 Application Block Diagram....................................................................................................... 12
2 Schematic Design Recommendation .................................................................................................. 13
2.1 Minimum System Design .......................................................................................................... 13
2.1.1 Clock Circuit ................................................................................................................. 13
2.1.2 NPOR Circuit ................................................................................................................ 14
2.1.3 System Boot Sequence .................................................................................................. 15
2.1.4 System Initializes Configuration Signal ........................................................................ 15
2.1.5 JTAG Debug Circuit ..................................................................................................... 15
2.1.6 FSPI Circuit ................................................................................................................... 16
2.1.7 eMMC Circuit ............................................................................................................... 16
2.1.8 GPIO Circuit.................................................................................................................. 18
2.2 Power Supply Design ................................................................................................................ 19
2.2.1 Power Up Sequence....................................................................................................... 19
2.2.2 Power Off Sequence ...................................................................................................... 20
2.2.3 Power Supply Design Suggestion ................................................................................. 20
2.3 Functional Interface Circuit Design Guide................................................................................ 22
2.3.1 SDMMC Interface ......................................................................................................... 22
2.3.2 SDIO/UART Interface................................................................................................... 23
2.3.3 USB Interface ................................................................................................................ 24
2.3.4 FEPHY Interface ........................................................................................................... 27
2.3.5 Audio Interface .............................................................................................................. 29
2.3.6 VO Interface .................................................................................................................. 31
2.3.7 VI Interface.................................................................................................................... 33
2.3.8 SARADC ....................................................................................................................... 35
2.3.9 UART Debug Circuit .................................................................................................... 36
3 PCB Design Recommendations .......................................................................................................... 38
3.1 PCB Stackup Design ................................................................................................................. 38
3.2 General Design Recommendation ............................................................................................. 38

Copyright © 2022 Rockchip Electronics Co., Ltd.

 Contents

3.3 Interfaces Design Guide ............................................................................................................ 45

3.3.1 SDMMC/SDIO PCB Design ......................................................................................... 45
3.3.2 FEPHY PCB Design ..................................................................................................... 46
3.3.3 USB PCB Design .......................................................................................................... 47
3.3.4 Audio PCB Design ........................................................................................................ 47
3.3.5 FLASH PCB Design ..................................................................................................... 48
3.3.6 Video Input PCB Design ............................................................................................... 49
3.3.7 Video Output PCB design ............................................................................................. 51
4 Thermal Design Suggestion ................................................................................................................ 52
5 ESD/EMI Protection Design ............................................................................................................... 53
5.1 Overview ................................................................................................................................... 53
5.2 Terms Interpretation .................................................................................................................. 53
5.3 ESD Protection .......................................................................................................................... 53
5.4 EMI Protection .......................................................................................................................... 53
6 Soldering Process ................................................................................................................................. 55

Copyright © 2022 Rockchip Electronics Co., Ltd.

 Figures

Figures
Figure 1-1 RV1103G block diagram ............................................................................................................. 10
Figure 1-2 RV1106G block diagram ............................................................................................................. 11
Figure 1-3 RV1103G application block diagram .......................................................................................... 12
Figure 1-4 RV1106G application block diagram .......................................................................................... 12
Figure 2-1 RV1103G/RV1106G Crystal Circuit ........................................................................................... 13
Figure 2-2 RV1106G RTC crystal circuit ..................................................................................................... 14
Figure 2-3 RV1106G NPOR input ................................................................................................................ 14
Figure 2-4 eMMC Power Up and Power Down Sequence............................................................................ 17
Figure 2-5 RV1103G power up sequence ..................................................................................................... 19
Figure 2-6 RV1106G power up sequence ..................................................................................................... 20
Figure 2-7 RV1103G/RV1106G VDD_CPU power ..................................................................................... 20
Figure 2-8 The decouple of RV1103G/RV1106G VDD_CPU power .......................................................... 21
Figure 2-9 RV103G/RV1106G LOGIC&NPU Power .................................................................................. 21
Figure 2-10 The decouple of RV1103G/RV1106G LOGIC&NPU power ................................................... 21
Figure 2-11 RV1103G/RV1106G DDR controller power ............................................................................ 22
Figure 2-12 The decouple of RV1103G/RV1106G DDR power .................................................................. 22
Figure 2-13 RV1103G/RV1106G SDMMC module circuit ......................................................................... 23
Figure 2-14 RV1106G SDIO multiplexing interface 1 ................................................................................. 23
Figure 2-15 RV1103G/RV1106G SDIO multiplexing interface 2 ................................................................ 24
Figure 2-16 RV1103G/RV1106G USB 2.0 module...................................................................................... 25
Figure 2-17 RV1103G/RV1106G USB socket ............................................................................................. 25
Figure 2-18 RV1106G USB insert detection................................................................................................. 26
Figure 2-19 RV1103G/RV1106G USB Controller Power Surge Protection ................................................ 26
Figure 2-20 RV1103G/RV1106G USB Common mode choke .................................................................... 27
Figure 2-21 RV1103G/RV1106G FEPHY interface ..................................................................................... 27
Figure 2-22 RV1103G/RV1106G RJ45 interface ......................................................................................... 28
Figure 2-23 RV1103G/RV1106G FEPHY power series magnetic beads ..................................................... 29
Figure 2-24 RV1106G ACODEC Module .................................................................................................... 29
Figure 2-25 RV1103G ACODEC module .................................................................................................... 30
Figure 2-26 RV1106G I2S0 module ............................................................................................................. 31
Figure 2-27 RV1106G video output interface ............................................................................................... 32
Figure 2-28 RV1103G/RV1106G video output connect sequence ............................................................... 32
Figure 2-29 RV1103G/RV1106G MIPI-CSI module ................................................................................... 33
Figure 2-30 RV1103G/RV1106G MIPI/LVDS video input connect sequence ............................................ 33
Figure 2-31 RV1103G/RV1106G MIPI CSI power supply series magnetic beads ...................................... 34
Figure 2-32 RV1106G VI-CIF module ......................................................................................................... 34
Figure 2-33 RV1106G VI-CIF video input connect sequence ...................................................................... 35

Copyright © 2022 Rockchip Electronics Co., Ltd.

 Figures

Figure 2-34 RV1103G/RV1106G SAR-ADC module .................................................................................. 36

Figure 2-35 RV1103G/RV1106G SAR-ADC detection ............................................................................... 36
Figure 2-36 RV1103G/RV1106G UART2 multiplexing relationship M1 .................................................... 36
Figure 2-37 RV1103G/RV1106G UART2 multiplexing relationship M2 .................................................... 36
Figure 2-38 RV1103G/RV1106G TF to serial port conversion board .......................................................... 37
Figure 2-39 RV1103G/RV1106G serial port configuration .......................................................................... 37
Figure 3-1 Differential Pair Skew ................................................................................................................. 38
Figure 3-2 Discontinuous Reference Plane ................................................................................................... 39
Figure 3-3 Reference Plane Voiding ............................................................................................................. 39
Figure 3-4 Airgap Between Trace and Plane ................................................................................................ 39
Figure 3-5 Reference Plane Edge .................................................................................................................. 40
Figure 3-6 GND Via Placement .................................................................................................................... 40
Figure 3-7 GND Via Placement for ESD Component .................................................................................. 40
Figure 3-8 Winding Dimension..................................................................................................................... 41
Figure 3-9 Skew Compensation .................................................................................................................... 41
Figure 3-10 Gnd Via for Differential Via ..................................................................................................... 42
Figure 3-11 Gnd Via for Single-ended Via ................................................................................................... 42
Figure 3-12 symmetry layout ........................................................................................................................ 42
Figure 3-13 Gnd Via Placement .................................................................................................................... 42
Figure 3-14 Ground Shape Near Connector Pad ........................................................................................... 43
Figure 3-15 Airgap Between Pad to Plane .................................................................................................... 43
Figure 3-16 Ground Shielding....................................................................................................................... 44
Figure 3-17 Ground Shielding for Single-End Signals ................................................................................. 44
Figure 3-18 Serpentine Trace Recommendation ........................................................................................... 44
Figure 3-19 Trace Stub.................................................................................................................................. 45
Figure 3-20 RV1103G/RV1106G SDMMC layout recommendation ........................................................... 45
Figure 3-21 RV1103G/RV1106G FEPHY layout recommendations ........................................................... 46
Figure 3-22 RV1103G/RV1106G USB layout recommendations ................................................................ 47
Figure 3-23 RV1103G/RV1106G audio layout recommendations ............................................................... 48
Figure 3-24 RV1106G EMMC layout recommendations ............................................................................. 49
Figure 3-25 RV1103G/RV1106G MIPI CSI/LVDS RX layout recommendations ...................................... 50
Figure 3-26 RV1106G Parallel CIF layout recommendations ...................................................................... 51

Copyright © 2022 Rockchip Electronics Co., Ltd.

 Tables

Tables
Table 1-1 RV110x Chip Differences............................................................................................................... 9
Table 2-1 RV1103G/RV1106G 24MH clock requirements .......................................................................... 13
Table 2-2 RV1103G/RV1106G System Initialization Configuration Signal Description ............................ 15
Table 2-3 RV1103G/RV1106G JTAG Debug interface signal ..................................................................... 15
Table 2-4 RV1103G/RV1106G SPI interface desgin ................................................................................... 16
Table 2-5 RV1106G eMMC interface design ............................................................................................... 16
Table 2-6 RV1103G/RV1106G GPIO power pins description ..................................................................... 18
Table 2-7 RV1103G/RV1106G SDMMC Interface Design ......................................................................... 23
Table 2-8 RV1103G/RV1106G SDIO Interface Design ............................................................................... 24
Table 2-9 RV1103G/RV1106G UART Interface Design ............................................................................. 24
Table 2-10 RV1103G/RV1106G USB interface design ............................................................................... 27
Table 2-11 RV1103G/RV1106G FEPHY ..................................................................................................... 28
Table 2-12 RV1103G/RV1106G ACODEC interface design ....................................................................... 30
Table 2-13 RV1103G/RV1106G I2S0 interface design ................................................................................ 31
Table 3-1 SDMMC/SDIO Layout Requirements .......................................................................................... 46
Table 3-2 FEPHY Layout Requirements ...................................................................................................... 46
Table 3-3 USB Layout Requirements ........................................................................................................... 47
Table 3-4 FSPI Layout Requirements ........................................................................................................... 48
Table 3-5 EMMC Layout Requirements ....................................................................................................... 49
Table 3-6 MIPI CSI/LVDS RX Layout Requirements ................................................................................. 50
Table 3-7 Parallel CIF Layout Requirements................................................................................................ 51
Table 3-8 BT1120 Layout Requirements (≤74.25Mhz) ................................................................................ 51
Table 3-9 LCDC Layout Requirements (≤74.25Mhz) .................................................................................. 51

Copyright © 2022 Rockchip Electronics Co., Ltd.

 System Introduction

1 System Introduction

1.1 Overview

RV1106 is a highly integrated vision processor SoC, especially for AI related application.
It is based on single-core ARM Cortex-A7 32-bit core which integrates NEON and FPU. There is a
32KB I-cache and 32KB D-cache and 128KB unified L2 cache. The build-in NPU supports
INT4/INT8/INT16 hybrid operation and computing power is up to 0.5TOPs. In addition, with its strong
compatibility, network models based on a series of frameworks such as TensorFlow/MXNet/PyTorch/Caffe can be
easily converted. RV1106 introduces a new generation totally hardware-based maximum 5-Megapixel ISP (image
signal processor). It implements a lot of algorithm accelerators, such as HDR, 3A, LSC, 3DNR, 2DNR, sharpening,
dehaze, gamma correction and so on. Cooperating with two MIPI CSI (or LVDS) and one DVP
(BT.601/BT.656/BT.1120) interface, users can build a system that receives video data from multiple camera
sensors simultaneous.

1.2 Chip Differences

Table 1-1 RV110x Chip Differences

RV1103G1 RV1106G2
Sensor MAX 4M MAX 5M

DDR 64MB 128MB

Package QFN88 QFN128

MIPI: 1*4lane or 2*2lane

MIPI: 1*4lane (2*2lan)
VICAP: 16bit
Sensor In maximum 2-way,
maximum 3-way,
2lane*MIPI+2lane*MIPI
2lane*MIPI+2lane*MIPI+10bit DVP

FSPI
FSPI FSPI or 8bit eMMC
EMMC

SDMMC 1 1

SDIO 1 1

BT NA support

LCDC/BT1120 NA 18bit

RTC NA build-in

LPMCU NA build-in

Copyright © 2022 Rockchip Electronics Co., Ltd.

 System Introduction

1.3 Block Diagram

RV1103
System Peripheral Connectivity
Cortex-A7 Signle-Core
Clock & Reset MCU USB OTG 2.0
(32K/32K L1 I/D Cache)
PMU
I2S_TDM(8ch)
128KB L2 Cache 16KB Cache
PLL
UART x6
PVTPLL
Multi-Media Processor SPI x2
Timer(6ch)/Stimer(2ch)

PWM(12ch) ISP NPU I2C x5

Watchdog 100M Ethernet+PHY

JPEG Encoder VEPU(H.264/H.265)
Crypto
SDIO 3.0
SARADC(2ch)
RGA IVE GPIO
TSADC

DECOM ACODEC PHY

External Memory Interface
DMAC
SPI NOR SD3.0/MMC4.5 Embedded Memory
PVTM
System SRAM (256KB)
Mailbox 16-bit DDR2/3L
PMU SRAM (8KB)

Video Input Interface ROM (20KB)

POR
MIPI-CSI/LVDS
OTP (8Kbits )

Figure 1-1 RV1103G block diagram

Copyright © 2022 Rockchip Electronics Co., Ltd.

 System Introduction

System Peripheral
Clock & Reset
RV1106 Connectivity
USB OTG 2.0
PMU Cortex-A7 Signle-Core
(32K/32K L1 I/D Cache) I2S_TDM(8ch)
PLL MCU

128KB L2 Cache 16KB Cache UART x6

PVTPLL

Timer(6ch)/Stimer(2ch) SPI x2
Multi-Media Processor
PWM(12ch) I2C x5
Watchdog ISP NPU 100M Ethernet+PHY
Crypto
SDIO 3.0
SARADC(2ch) JPEG Encoder VEPU(H.264/H.265)

TSADC GPIO

DECOM RGA IVE ACODEC PHY

DMAC

PVTM External Memory Interface Embedded Memory

Mailbox
eMMC4.51 SD3.0/MMC4.5 System SRAM (256KB)

Video Output Interface

SPI NOR 16-bit DDR3L PMU SRAM (8KB)
BT.656/BT.1120
ROM (20KB)
RGB 18-bit LCD Controller
Video Input Interface
MIPI-CSI/LVDS OTP
(8Kbits )
RTC POR 16-bit DVP/BT.656/BT.1120

Figure 1-2 RV1106G block diagram

Copyright © 2022 Rockchip Electronics Co., Ltd.

 System Introduction

1.4 Application Block Diagram

Figure 1-3 RV1103G application block diagram

Figure 1-4 RV1106G application block diagram

Copyright © 2022 Rockchip Electronics Co., Ltd.

 Schematic Design Recommendation

2 Schematic Design Recommendation

2.1 Minimum System Design

2.1.1 Clock Circuit

The oscillator circuit inside RV1103G/RV1106G and the external 24MHz crystal form the system clock,
as shown in Figure 2-1.

Figure 2-1 RV1103G/RV1106G Crystal Circuit

NOTE
The selected capacitor needs to match the load capacitance of the crystal oscillator, which the material is
recommended to be NPO. It is recommended to use a 4Pin chip crystal oscillator, of which 2 GND pins are
fully connected to the ground to enhance the anti-ESD interference capability of the system clock. Use a crystal
with a frequency offset less than 20ppm.

The system clock can also be directly generated by an external active crystal circuit and input through
the OSC_XIN pin. The clock parameters are shown in Table 2-1 below:

Table 2-1 RV1103G/RV1106G 24MH clock requirements

Spec Description
Parameters
Min. Max. Unit
Frequency 24.000000 MHz
Frequency tolerance +/-20 ppm Frequency tolerance
Clock amplitude 1.8V±10% V

Compared with RV1103G, RV1106G has one more RTC. The circuit is shown in Figure 2-2 below. Pay
special attention to the RC parameters of the AVDD33_RTC power input, which must be 100ohm and 1uF.

Copyright © 2022 Rockchip Electronics Co., Ltd.

 Schematic Design Recommendation

Figure 2-2 RV1106G RTC crystal circuit

NOTE
RV1103G does not support RTC.
The selected capacitor need to match the load capacitance of the crystal oscillator, which the material is
recommended to be NPO.

2.1.2 NPOR Circuit

The RV1103G/RV1106G chip integrates a POR (Power on Reset) circuit. As shown in Figure 2-3, the
chip pin66 is pulled up to the PMU_VCC3V3 power supply through the resistor R1110, which is used as the
input reference of the voltage comparator of the internal NPOR. The capacitor C1114 is used to eliminate
jitter. Although the RV1103G has no NPOR pin, it is pulled up to the PMU_VCC3V3 power supply inside
the chip as the input reference of the voltage comparator. When laying out, place the resistor and capacitor
close to the RV1106G.

Figure 2-3 RV1106G NPOR input

Copyright © 2022 Rockchip Electronics Co., Ltd.

 Schematic Design Recommendation

2.1.3 System Boot Sequence

The system boot sequence of the RV1103G/RV1106G chip has the following priorities from high to low:
 SFC/SPI FLASH
 eMMC FLASH
 SDMMC CARD

2.1.4 System Initializes Configuration Signal

RV1103G/RV1106G multiplexes JTAG function with SDMMC function to reduce IO extraction and
switch output mode through pins. This function is mainly convenient for users to debug the system through
the SD card interface without disassembling the machine after the whole machine is installed. Pin
configuration as the follow table:

Table 2-2 RV1103G/RV1106G System Initialization Configuration Signal Description

Internal up and
Signal name Description
down
JATG pin multiplexing selection control signal:
0: Recognized as SD card insertion, SDMMC/JATG/UART pins are
SDMMC0_DET Pull up multiplexed as SDMMC output;
1: Recognized as SD card not inserted, SDMMC/JATG/UART pins are
multiplexed as JTAG/UART output (Default).

2.1.5 JTAG Debug Circuit

The RV1103G/RV1106G’s JTAG interface conforms to IEEE1149.1 standard. PC connect the

DSTREAM emulator through the SWD mode (tow-wire mode) to debug the ARM Core and MUC Core
inside the chip.
As mention above, it is necessary to ensure the SDMMCO_DET pin is high-level before connecting the
emulator, otherwise the JTAG debugging mode cannot be entered. Interface description as follow:

Table 2-3 RV1103G/RV1106G JTAG Debug interface signal

Signal name Description

JTAG_ARM_TCK ARM Cortex-A7 JTAG clock input

JTAG_ARM_TMS ARM Cortex-A7 JTAG mode select input

JTAG_LPMCU_TCK Low Power MCU JTAG clock input

JTAG_LPMCU_TMS Low Power MCU JTAG mode select input

JTAG_HPMCU_TCK High Performance MCU JTAG clock input

JTAG_HPMCU_TMS High Performance MCU JTAG mode select input

Copyright © 2022 Rockchip Electronics Co., Ltd.

 Schematic Design Recommendation

NOTE
RV1103G has no LPMUC.

2.1.6 FSPI Circuit

FSPI (Flexible-SPI) is a flexible serial peripheral interface host controller that interfaces with external
devices. It has the following characteristics:
 Support serial NOR and NAND FLASH
 Support SDR mode. Support single/dual/four-wire mode

The recommended design for pull-up and down and matching design of the SPI interface as show in the
Tab.2-4:

Table 2-4 RV1103G/RV1106G SPI interface desgin

Internal pull
Signal Connection mode Description(chipset)
up/down
FSPI_D[3:0] pull up direct connection FSPI data send/receive

FSPI_CS0 pull up direct connection SPI chip select signal

connect 22ohm
FSPI_CLK pull down SPI clock send
resistor in series

2.1.7 eMMC Circuit

2.1.7.1 eMMC Controller Introduction

The RV1106G eMMC interface supports eMMC 4.51 and is compatible with 4.41 and 5.0 protocol
devices. The controller has the following features:
 Support 1-bit, 4-bit and 8-bit data bus width;
 Up to HS200 mode is supported, but CMD Queue is not supported.

2.1.7.2 eMMC Topology and Connect Method

The recommended design for pull-up and down and matching design of the eMMC interface as show in
the Tab.2-5:

Table 2-5 RV1106G eMMC interface design

Internal pull
Signal Connection mode Description(chipset)
up/down
eMMC_DQ[7:0] pull up direct connection eMMC data send/receive
eMMC_CMD pull up direct connection eMMC command sent/receive
connect 22ohm
eMMC_CLK pull down eMMC clock sent
resistor in series

Copyright © 2022 Rockchip Electronics Co., Ltd.

 Schematic Design Recommendation

2.1.7.3 eMMC Power Up Sequence Requirment

The RV1106G chip eMMC controller belongs to the VCCIO3 power domain:
 GPIO3: I/O power supply of eMMC controller.

The eMMC have two sets of power supplies, refer to JEDEC standard for power-on sequence:
 There is no requirement for VCC and VCCQ in the power-on sequence;
 VCC and VCCQ must be powered on before the CMD command of RV1106G is issued, and
maintain a stable working voltage;
 After the chip enters sleep mode, RV1106G can turn off the VCC power supply to reduce power
consumption;
 Before the chip wakes up from sleep mode, the VCC power supply must be powered on and
maintain a stable working voltage.

Figure 2-4 eMMC Power Up and Power Down Sequence

2.1.7.4 eMMC Support List

ForRV11026G eMMC support list, please refer to the document "RKeMMCSupportList", which can be
downloaded from Rockchip redmine platform:
https://redmine.rockchip.com.cn/projects/fae/documents?tdsourcetag=s_pctim_aiomsg

NOTE
RV1103G does not support eMMC.

Copyright © 2022 Rockchip Electronics Co., Ltd.

 Schematic Design Recommendation

2.1.8 GPIO Circuit

In RV1103G/RV11026G, there are two types of GPIO: 1.8V and 3.3V, and supports self-adaption.

2.1.8.1 GPIO Drive Capability

In the RV1103G/RV1106G chip, GPIO provides 6 adjustable drive strengths, which are
2mA/4mA/6mA/8mA/10mA/12mA. The initial default drive strength is different according to the type of
GPIO. Please refer to the chip TRM for configuration modification.

2.1.8.2 GPIO Power

The power pins of GPIO power domain are described as follows:

 When the IO power pin name is PMU_VCC3V3, it means PMU power domain and only supports
3.3V. The GPIO1_VCC3V3 is similar.
 When the IO power name is VCCIO3_VCC, it means VCCIO3 power domain and supports 3.3V
or 1.8V. VCCIO5_VCC is similar.
 When the IO power pin name is MIPI_ VCCIO7_AVDD1V8, it means VCCIO7 power domain
and only supports 1.8V.
 It is recommended to place a 100nF decoupling capacitor on each power supply pin of the power
domain and place it close to the power supply pin. For detailed design, please refer to the
RV1103G/RV1106G chip reference schematic diagram.
 The power supply ripple is required to be ±5%.

Table 2-6 RV1103G/RV1106G GPIO power pins description

Power
GPIO Type Pin name Description
domain
PMU_DVDD0V9 0.9V logic power for this GPIO domain.
PMU 3.3V only
PMU_VCC3V3 3.3V IO supply for this GPIO domain.

VCCIO1 3.3V only VCCIO1_VCC3V3 3.3V IO supply for this GPIO domain.

VCCIO2 1.8V only SARADC_USB_AVDD1V8 1.8V IO supply for this GPIO domain.

VCCIO3 1.8V/3.3V VCCIO3_VCC 1.8V or 3.3V IO supply for this GPIO domain.

3.3V only
VCCIO4_VCC3V3 3.3V IO supply for this GPIO domain.
(RV1103G)
VCCIO4
1.8V/3.3V
VCCIO4_VCC 1.8V or 3.3V IO supply for this GPIO domain.
(RV1106G)

VCCIO5 1.8V/3.3V VCCIO5_VCC 1.8V or 3.3V IO supply for this GPIO domain.

VCCIO6 1.8V/3.3V VCCIO6_VCC 1.8V or 3.3V IO supply for this GPIO domain.

VCCIO7 1.8V only MIPI_VCCIO7_AVDD1V8 1.8V IO supply for this GPIO domain.

Copyright © 2022 Rockchip Electronics Co., Ltd.

 Schematic Design Recommendation

NOTE
RV1103G has no GPIO5 power domain.
RV1103G VCCIO4 only supports 3.3V mode.

2.2 Power Supply Design

2.2.1 Power Up Sequence

The power-on sequence of the RV1103G/RV1106G chip has the following requirements:
 It follows the principle that the same module is powered up first with low voltage and then powered
up with high voltage; the different module with the same voltage is powered up at the same time.
 Different timing intervals must be greater than 1ms.
 The soft-start time of the power device must be greater than 100us. Can’t use a device with a soft-
start time of less than 100us.
The recommended power-up sequence is as follows:
VDD_0V9&VDD_ARM-VCC_1V8&VCC_DDR-VCC_3V3

Figure 2-5 RV1103G power up sequence

Copyright © 2022 Rockchip Electronics Co., Ltd.

 Schematic Design Recommendation

Figure 2-6 RV1106G power up sequence

2.2.2 Power Off Sequence

There is no strict requirement for the power-off sequence of the RV1103G/RV1106G, and all power
sources can be powered off at the same time.

2.2.3 Power Supply Design Suggestion

2.2.3.1 CPU Power Supply

RV1103G/RV1106G uses CPU independent power domain for power supply. As shown in the Fig.2-8,
VDD_ARM supplies power for ARM Cortex-A7 core. It supports DVFS dynamic frequency modulation and
voltage regulation function, and uses DC-DC power supply for independent power supply with a peak current
of 400mA. The capacitors in the RV1103G/RV1106G chip reference design schematic cannot be omitted.
Place the capacitor close to the chip pins during layout, and the power supply ripple is required to be ±5%.
The capacitor is shown in Figure 2-8.

Figure 2-7 RV1103G/RV1106G VDD_CPU power

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 Schematic Design Recommendation

Figure 2-8 The decouple of RV1103G/RV1106G VDD_CPU power

2.2.3.2 LOGIC&NPU Power Supply

The RV1103G/RV1106G GPU & LOGIC power supply is powered by DC-DC separately, as shown in
the Fig.2-9 VDD_0V9, and the peak current can reach 1.6A, so please do not delete the capacitors in the
schematic diagram. When Layout, please place 2 10uF capacitors on the near power supply side and the far
power supply side of the RV1103G/RV1106G chip respectively. Each pin should have at least 1 100nF
decoupling capacitor placed close to the chip pins. The power supply ripple is required to be within ±5 %,
the capacitance is shown in Fig.2-10.

Figure 2-9 RV103G/RV1106G LOGIC&NPU Power

Figure 2-10 The decouple of RV1103G/RV1106G LOGIC&NPU power

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 Schematic Design Recommendation

2.2.3.3 DDR Power Supply

The RV1103G/RV1106G DDR power is powered by DC-DC separately, and the peak current is 400mA.
Do not omit the capacitors in the RV1103G/RV1106G chip reference design schematic. The power supply
ripple is required to be ±5%. Place capacitors close to the chip pins during layout.

Figure 2-11 RV1103G/RV1106G DDR controller power

Figure 2-12 The decouple of RV1103G/RV1106G DDR power

2.2.3.4 GPIO Power Supply

Please refer to Section 2.1.8 for GPIO power supply. It is recommended to place 1 100nF decoupling
capacitor per pin and place it close to the power supply pins. For detailed design, please refer to the
RV1103G/RV1106G reference design schematic.

2.3 Functional Interface Circuit Design Guide

2.3.1 SDMMC Interface

RV1103G/RV1106G provides an SDMMC interface controller that supports SD V3.0 (RV1103G only
supports SD V2.0) and MMC V4.51 protocol, as shown in Fig.2-13:
 The SDMMC controller is powered by a separate power domain;
 SDMMC and UART2, JTAG and other functions are multiplexed together, and function selection
is performed through SDMMC0_DET. For details, please refer to Section 2.1.4;
 VCCIO4_VCC is the IO power supply, which requires external 3.3V power supply (SD 2.0 mode)
or 3.3V/1.8V adjustable power supply (SD 3.0 mode);

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 Schematic Design Recommendation

Figure 2-13 RV1103G/RV1106G SDMMC module circuit

The design recommendations for the pull-up and down and matching design of the SDMMC interface
as show in Tab.2-7:

Table 2-7 RV1103G/RV1106G SDMMC Interface Design

Internal pull-
Connection mode
Signal up and pull- Description (chipset)
(SDR104 high speed mode)
down
SDMMC_DQ [3:0] Pull up Direct connect SD data sent/receive

SDMMC_CMD Pull up Direct connect SD command sent/receive

SDMMC_CLK Pull down Connect a 22ohm resistor in series SD clock sent

2.3.2 SDIO/UART Interface

RV1103G/RV1106G supports WIFI/BT modules with SDIO 3.0 interface, as shown in Fig.2-14. When
using WIFI/BT modules with SDIO and UART interfaces, it should be noted that the IO power supply
VCCIO5_VCC of the controller must be consistent with the IO level of the module.
Considering the flexibility of the application, SDIO has two multiplexing M0 and M1, which are located
in the VCCIO5 and VCCIO6 power domains respectively, and only one of them can be used at the same time.
As shown in Fig.2-14 and Fig.2-15.

Figure 2-14 RV1106G SDIO multiplexing interface 1

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 Schematic Design Recommendation

Figure 2-15 RV1103G/RV1106G SDIO multiplexing interface 2

2.3.2.1 SDIO

The design recommendations for the pull-up and down and matching design of the SDIO interface as
show in Tab.2-8:

Table 2-8 RV1103G/RV1106G SDIO Interface Design

Internal pull-
Signal up and pull- Connection mode Description (chipset)
down
SDIO_DQ [0:3] Pull down Direct connect SD data sent/receive

SDIO_CMD Pull down Direct connect SD command sent/receive

SDIO_CLK Pull down Connect a 22ohm resistor in series SD clock sent

2.3.2.2 UART

The design recommendations for the pull-up and down and matching design of the UART interface as
show in Tab.2-9:

Table 2-9 RV1103G/RV1106G UART Interface Design

Internal pull-
Signal up and pull- Connection mode Description (chipset)
down
UART0_RX Pull up Direct connect UART0 data input

UART0_TX Pull up Direct connect UART0 data output

UART0_CTSn Pull up Direct connect UART0 permit sent signal

UART0_RTSn Pull up Direct connect UART0 request sent signal

2.3.3 USB Interface

RV1103G/RV1106G has a group of USB 2.0 interface, which supports HOST and DEVICE mode.

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 Schematic Design Recommendation

Figure 2-16 RV1103G/RV1106G USB 2.0 module

Something be noted in design:

 If the UART/SD is not used for programming, there need to reserve interface since the USB is used
as firmware programming port.

Figure 2-17 RV1103G/RV1106G USB socket

 USB interface is Device mode by default.

 Since the USB_VBUS (USB_DET) is used as the USB device insertion detection, the input
detection voltage must be less than 3.3V, and the high level must be detected to be recognized by
the computer.

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 Schematic Design Recommendation

Figure 2-18 RV1106G USB insert detection

NOTE
RV1103G don’t has the USB insert detection.

 The 1.8V power supply of the controller needs to be connected with a 1ohm resistor in series to
avoid the damage caused by the surge.

Figure 2-19 RV1103G/RV1106G USB Controller Power Surge Protection

 The decoupling capacitor of controller power need to place close to the pin to enhance USB
performance.
 To suppress electromagnetic radiation, consider reserving a common mode choke on the signal line,
and choose the resistor or common mode choke according to the actual situation during the
debugging process.

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 Schematic Design Recommendation

Figure 2-20 RV1103G/RV1106G USB Common mode choke

The design recommendations for the pull-up and down and matching design of the USB 2.0 interface
as show in Tab.2-10:

Table 2-10 RV1103G/RV1106G USB interface design

Signal Connection method description

USB_DP/DM Connect a 2.2ohm resistor in series USB OTG input/output

USB_VBUSDET USB OTG insert detection

2.3.4 FEPHY Interface

RV1103G/RV1106G integrates a 100M PHY inside, and adds a network transformer and network port
connector externally to achieve 100M function.

Figure 2-21 RV1103G/RV1106G FEPHY interface

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 Schematic Design Recommendation

Figure 2-22 RV1103G/RV1106G RJ45 interface

Table 2-11 RV1103G/RV1106G FEPHY

Internal pull-
Signal up and pull- Connection mode Description (chipset)
down
connect a 0ohm resistor in
FEPHY_RXP/_RXN NA Data transmission differential pair signal
series
connect a 0ohm resistor in
FEPHY_TXP/TXN NA Data receive differential pair signal
series
Connect 6.04K precision
FEPHY_EXTR NA reference resistor
resistor in series to ground
Something be noted in design:
 The 0ohm resistor connected in series on the differential signal cannot be omitted and needs to be
reserved.
 The EXTR resistor is placed close to the chip.
 The AVDD18 power supply of FEPHY is susceptible to noise interference from digital signals, so
magnetic beads need to be placed nearby. Otherwise, packet loss may occur in poor cable quality
or in long cable mode (100m cable).

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 Schematic Design Recommendation

Figure 2-23 RV1103G/RV1106G FEPHY power series magnetic beads

2.3.5 Audio Interface

RV1103G/RV1106G has a built-in ACODEC, and provides a set of standard I2S interfaces for
expanding audio equipment, supports master mode, the highest sampling rate is up to 192kHz, and the bit
width supports 16bits to 24bits.

NOTE
The built-in ACODEC and the I2S for expansion are a common bus design, so only one of them can be used.

2.3.5.1 ACODEC

The build-in ACODEC of RV1106G supports 1-way lineout output, and 2-ways differential MIC input.

Figure 2-24 RV1106G ACODEC Module

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 Schematic Design Recommendation

The build-in ACODEC of RV1103G supports 1-way lineout output, and 1-way differential MIC input.
The differential MIC can be split into two single-ended input.

Figure 2-25 RV1103G ACODEC module

The design recommendations for the pull-down and matching design of the ACODEC interface as show
in the Tab.2-12.

Table 2-12 RV1103G/RV1106G ACODEC interface design

Internal
Signal pull-up and Connection mode Description (chipset)
pull-down
CODEC_MIC0P/MIC0N NA 1uF capacitor in series MIC0 differential input

CODEC_MIC1P/MIC1N NA 1uF capacitor in series MIC1 differential input

CODEC_LINEOUT NA LINEOUT output

Connect a 4.7uF capacitor

CODEC_VCM NA CODEC internal reference
to ground in series

CODEC_MICBIAS NA MIC Bias supply output

2.3.5.2 I2S0

As shown in the figure below, the I2S0 interface includes non-independent 8-channel output and 8-
channel input, and cannot realize all input and output at the same time. It should be noted that this group of
I2S interfaces belong to the GPIO5 power domain, please pay attention to the level matching of peripheral
IO.

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 Schematic Design Recommendation

Figure 2-26 RV1106G I2S0 module

The design recommendations for the pull-down and matching design of the I2S0 interface as show in
the Tab.2-13.

Table 2-13 RV1103G/RV1106G I2S0 interface design

Internal pull-
Signal up and pull- Connection mode Description (chipset)
down
I2S0_LRCK pull down Direct connect I2S0 frame clock, for soundtrack choose

I2S0_SCLK pull down 22ohm resistor in series I2S0 bit clock

I2S0_SDI0 pull down Direct connect I2S0 data input channel0

I2S0_SDO0 pull down Direct connect I2S0 data output channel0

I2S0_MCLK pull down 22ohm resistor in series I2S0 system clock output

I2S0 data output channel3

I2S0_SDO3_SDI1 pull down Direct connect
I2S0 data input channel1

I2S0 data output channel2

I2S0_SDO2_SDI2 pull down Direct connect
I2S0 data input channel2

I2S0 data output channel1

I2S0_SDO1_SDI3 pull down Direct connect
I2S0 data input channel3

2.3.6 VO Interface

The RV1106G chip has a built-in VOP, which supports RGB/MCU/BT1120/BT656 and other video
output modes. The software needs to configure the corresponding output mode, and the hardware should also
pay attention to the connection sequence of the signals.

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 Schematic Design Recommendation

Figure 2-27 RV1106G video output interface

NOTE
RV1103G doesn’t support display interface..

Figure 2-28 RV1103G/RV1106G video output connect sequence

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 Schematic Design Recommendation

2.3.7 VI Interface

2.3.7.1 MIPI CSI/LVDS RX Interface

The RV1103G/RV1106G has a set of MIPI CSI/LVDS RX inputs and built-in ISP processor.

Figure 2-29 RV1103G/RV1106G MIPI-CSI module

Figure 2-30 RV1103G/RV1106G MIPI/LVDS video input connect sequence

Something be noted in design:

 The decoupling capacitor of the controller power supply should be placed close to the pin to
improve MIPI-CSI performance;
 The power supply of the MIPI-CSI controller needs to be connected in series with a 1ohm resistor

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 Schematic Design Recommendation

to avoid the damage caused by the surge.

Figure 2-31 RV1103G/RV1106G MIPI CSI power supply series magnetic beads

2.3.7.2 VICAP Interface

RV1106G has 2 VI-CIF interfaces, VCCIO6 and VCCIO7. VI_CIF_M1 of VCCIO6 only supports
8/10bit parallel port and BT656 input, while VI_CIF_M0 of VCCIO7 supports 8/10/12 parallel port input,
BT656 and BT1120 input. In the product design, the interface only supports the 1.8V working level, so the
IO level/I2C pull-up level of the peripheral must be consistent with it, otherwise it will cause abnormal work
or fail to work.

Figure 2-32 RV1106G VI-CIF module

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 Schematic Design Recommendation

Figure 2-33 RV1106G VI-CIF video input connect sequence

NOTE
RV1103G doesn’t support VI CIF interface..

2.3.8 SARADC

The sampling range of SARADC is 0-1.8V with the accuracy is 10bits. The key array adopts a parallel
type. The input key value can be adjusted by adding or subtracting keys and adjusting the ratio of the voltage
divider resistance to realize multi-key input to meet customer product requirements. In the design, it is
suggested that the value of any two buttons must be greater than +/-35, that is, the center voltage difference
must be greater than 123mV.
The ADC_IN0 of the RV1103G/RV1106G chip is multiplexed as a RECOVER mode trigger (no need
to update the LOADER), as shown in the figure below. On the premise that the system has already
programmed the firmware, pull down ADCIN0 when the system starts, and keep SARADC_IN0 at 0V level,
then RV1103G/RV1106G enters the Rockusb programming mode. When the PC recognizes the USB device,
release the button to make ADCIN0 return to high level (1.8V), and then the firmware can be programmed.

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 Schematic Design Recommendation

Figure 2-34 RV1103G/RV1106G SAR-ADC module

Figure 2-35 RV1103G/RV1106G SAR-ADC detection

2.3.9 UART Debug Circuit

The UATT2_M1 interface of RV1103G/RV1106G can be used as a debugging serial port. The
UART2_M0 interface is multiplexed to the SDMMC interface, so if the product is debugged, the TF to USB
adapter board can be used for debugging to avoid the need to disassemble the machine during debugging.

Figure 2-36 RV1103G/RV1106G UART2 multiplexing relationship M1

Figure 2-37 RV1103G/RV1106G UART2 multiplexing relationship M2

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 Schematic Design Recommendation

Figure 2-38 RV1103G/RV1106G TF to serial port conversion board

For the UART port number, please select the port number of the PC connected to the development board,
the baud rate is 115200, and the flow control RTS/CTS does not need to be checked. If the built-in DB-9 port
on the PC does not support high-speed mode, please use the USB-to-serial method.

Figure 2-39 RV1103G/RV1106G serial port configuration

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 PCB Design Recommendations

3 PCB Design Recommendations

3.1 PCB Stackup Design

In order to reduce the reflection phenomenon in the process of high-speed signal transmission,
impedance matching must be maintained on the signal source, the receiving end and the transmission line.
The impedance of a single-ended signal line depends on its line width and its relative position to the reference
layer. The line width/line spacing between the differential pairs required for a specific impedance depends
on the selected PCB stackup. Since the minimum line width and minimum line distance depend on the PCB
type and cost requirements, due to this limitation, the selected PCB stackup must be able to achieve all
impedance requirements on the board, including inner and outer layers, single-ended and differential lines,
etc.
In RV1103G/RV1106G design, it’s recommended to use 4-layer PCB stackup. Please provide the
corresponding impedance requirements to the PCB manufacturer and design as required.

3.2 General Design Recommendation

(1) Trace length should include package and via.

(2) Intra-pair skew is the term used to define the difference length between + and - in a differential pair.
Inter-pair skew is used to define the difference length between a differential pair and another differential pair.
The space between signals is defined as air-gap distance.

Figure 3-1 Differential Pair Skew

(3) Route trace over continuous GND plane without interruption. Any discontinuity or split on the
reference plane will degrade signal integrity significantly.

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 PCB Design Recommendations

Figure 3-2 Discontinuous Reference Plane

(4) Voiding the ground plane underneath the SMT signal pad(as show in the follow figure red rectangle
area) is necessary to minimize the impedance mismatch. SMT component include AC capacitor, ESD,
CMC(common mode choke), connector, etc. If no specific requirement provided, keep the voiding size as
same as the pad or slightly bigger.

Figure 3-3 Reference Plane Voiding

(5) Recommend keeping traces ≥3 times the width of trace from GND plane on same layer.

Figure 3-4 Airgap Between Trace and Plane

(6) Avoid routing across different reference planes. Recommend that high-speed differential signals are
routed ≥ 40 mils from the edge on the reference plane.

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 PCB Design Recommendations

Figure 3-5 Reference Plane Edge

(7) It's not recommend to place test point on any high-speed signals.
(8) Bend should be minimized. If bends are needed, use 135° bends instead of 90°.
(9) Serial resistor recommend to be placed near transmitter.
(10) Each GND PAD at IC(such as emmc device、flash) recommend place a GND PTH Via.

Figure 3-6 GND Via Placement

(11) Avoid routing under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices or IC’s that used for duplicate clock signals.
(12) Remove all non-functional via pads.
(13) Recommend each ESD GND pad has a GND PTH via,and keep the length from pad to via as short
as possible.

Figure 3-7 GND Via Placement for ESD Component

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 PCB Design Recommendations

(14) Differential signals require equal lengths within pairs, that is, the time delay difference between P
and N should be as small as possible. Therefore, when the time delay difference occurs between the
differential lines P and N, the nearby winding is compensated. Special attention should be paid to the size of
the winding, which should meet the requirements shown in the figure below to reduce the impact of sudden
changes in impedance.

Figure 3-8 Winding Dimension

(15) If there is an unequal length (within 300mil) in the differential pair, make the compensation as soon
as possible.

Figure 3-9 Skew Compensation

(16) Place ground stitching vias near the signal transition vias. For differential signals, both signal vias
and stitching vias should be placed symmetrically.

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 PCB Design Recommendations

Figure 3-10 Gnd Via for Differential Via

Figure 3-11 Gnd Via for Single-ended Via

(17) Route differential pairs on symmetry.

Figure 3-12 symmetry layout

(18) It is recommended to place at least one ground through via in each ground pad of the high-speed
connector, and the through via should be as close as possible to the pad.

Figure 3-13 Gnd Via Placement

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 PCB Design Recommendations

(19) Ground shape at connector near GND PAD recommend ≤ PAD size.

Figure 3-14 Ground Shape Near Connector Pad

(20) Recommend distance between ground plane and pad ≥ 3 times the width of trace at connector.

Figure 3-15 Airgap Between Pad to Plane

(21) Proposed ground shielding.

L：GND via interval length.
D：Distance from shielding to trace ≥3*W.

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 PCB Design Recommendations

Figure 3-16 Ground Shielding

(22) Route important single-ended trace(such as emmc_clk、emmc_datastrobe、RGMII_CLK，etc)

with ground shielding. Add a GND via on shielding trace every 500mil.

Figure 3-17 Ground Shielding for Single-End Signals

(23) Serpentine traces (also called meander) are often needed when a certain trace length needs to be
achieved. Keep a minimum distance of four times the trace width between adjacent copper in a single trace.

Figure 3-18 Serpentine Trace Recommendation

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 PCB Design Recommendations

(24) Minimize the stub length as much as possible, it is recommended to keep the stub length as zero.

Figure 3-19 Trace Stub

(25) the signal can’t be routed over two different reference planes.

3.3 Interfaces Design Guide

3.3.1 SDMMC/SDIO PCB Design

SDMMC0/SDIO signal design requirements as follow:

 The length of SDMMC0_DATA/SDIO_DATA, SDMMC0_CMD/ SDIO_CMD is based on the
length of SDMMC0_CLK/SDIO_CLK, and the bias ≤120mil.
 The signal takes GND as the reference plane.
 SDMMC0 connect TF card. For ESD devices, select devices with a junction capacitance of less
than 1pF, and it is recommended to place them close to the connector.
 The length of package + PCB line should not exceed 4 inches.
 It is recommended that the SDMMC_DATA/CMD traces be grounded in the whole group, and the
SDMMC_CLK is recommended to be grounded separately. See (24) of section 3.2 “General
Design Recommendations” for details.

Figure 3-20 RV1103G/RV1106G SDMMC layout recommendation

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 PCB Design Recommendations

Table 3-1 SDMMC/SDIO Layout Requirements

Parameter Requirement
Trace Impedance 50Ω ±10% single ended

Data to clock matching <120mil

Max trace length <4 inches

The minimum spacing of SDMMC Signals At least 2 times the width of SDMMC trace.

3.3.2 FEPHY PCB Design

The FEPHY signal design requirements are as follows:

 The Intra-pair skew is controlled within ±30mil, and the differential impedance is controlled within
100ohm±10%.
 The differential signal must use GND as the reference plane. Maintain the integrity of the signal
reference plane.
 Avoid adjacent to other signals, and ensure that the distance from other signals is greater than 20mil.
 It is recommended to use TVS tube as the protection device, the breakdown voltage is 8kV, and
the response time is less than 1ns.

Figure 3-21 RV1103G/RV1106G FEPHY layout recommendations

Table 3-2 FEPHY Layout Requirements

Parameter Requirement
Trace Impedance 100Ω ±10% differential

Max intra-pair skew <30mil

Max trace length on carrier board <6 inches

Recommend less than 4 vias

Maximum allowed via
Cannot exceed 6 vias

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 PCB Design Recommendations

3.3.3 USB PCB Design

The USB signal design requirements are as follows:

 The Intra-pair skew is controlled within ±30mil, and the differential impedance is controlled within
90ohm±10%.
 The differential signal must use GND as the reference plane. Maintain the integrity of the signal
reference plane.
 The trace length of the USB2.0 differential signal line of the RV11XX should not exceed 6 inches,
and the number of vias should not exceed 6. A GND via needs to be placed near the USB signal
via for better signal quality.
 Avoid adjacent to other signals, and ensure that the distance from other signals is greater than 20mil.
 The parasitic capacitance of the ESD device is recommended to be less than 1pF.

Figure 3-22 RV1103G/RV1106G USB layout recommendations

Table 3-3 USB Layout Requirements

Parameter Requirement
Trace Impedance 90Ω ±10% differential

Max intra-pair skew <30mil

Max trace length on carrier board <6 inches

Recommend less than 4 vias

Maximum allowed via
Cannot exceed 6 vias

3.3.4 Audio PCB Design

The ACODEC signal design requirements are as follows:

 The MIC differential signal traces should be grounded and kept away from other high-speed signals.
 The LINEOUT signal needs to be grounded separately and away from other high-speed signals.
 The VCM capacitor is placed close to the chip.

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 PCB Design Recommendations

Figure 3-23 RV1103G/RV1106G audio layout recommendations

3.3.5 FLASH PCB Design

The FSPI FLASH signal design requirements are as follows:

 Avoid signal traces crossing the power split area, and keep the signal reference plane intact;
 The line length of FSPI CS and DATA is based on the line length of FSPI_CLK, and the bias is
controlled within 300mil.
 Package + PCB signal length does not exceed 4 inches.

Table 3-4 FSPI Layout Requirements

Parameter Requirement
Trace Impedance 50Ω ±10% single ended

Data to clock matching <300mil

Max trace length <4 inches

The minimum spacing of SFC Signals At least 2 times the width of SFC trace.

The eMMC signal design requirements are as follows:

 Avoid signal traces crossing the power split area, and keep the signal reference plane intact;
 The line length of EMMC_DATA and EMMC_CMD is based on the line length of EMMC_CLK,
and the bias is controlled within 120mil.
 Package + PCB signal length does not exceed 4 inches.

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 PCB Design Recommendations

Figure 3-24 RV1106G EMMC layout recommendations

Table 3-5 EMMC Layout Requirements

Parameter Requirement
Trace Impedance 50Ω ±10% single ended

Data to clock matching <120mil

Max trace length <4 inches

The minimum spacing of EMMC Signals At least 2 times the width of EMMC trace.

The minimum spacing between EMMC and other Signals Recommend 3 times the width of EMMC trace.
At least 2 times the width of EMMC trace.

3.3.6 Video Input PCB Design

MIPI CSI/LVDS RX signal design requirements:

 The differential signal takes GND as the reference plane and keeps the reference plane intact;
 The PCB trace length is recommended to be within 7.2 inches, the P/N equal length of the
differential pair is controlled within 24 mil, and the sampling differential clock is used as the
reference between the pairs, and the equal length is controlled within 42 mil (package + PCB joint
control equal length).
 The PCB traces of the MIPI RX differential pair control the differential impedance of
100ohm±10%.
 When differential signals pass through the connector, GND pins must be used for isolation between

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 PCB Design Recommendations

adjacent differential signal pairs.

 To improve MIPI-CSI performance, please place the decoupling capacitors of the controller power
supply close to the pins;
 The distance between the differential pair and other signals follows the 3W principle.

Figure 3-25 RV1103G/RV1106G MIPI CSI/LVDS RX layout recommendations

Table 3-6 MIPI CSI/LVDS RX Layout Requirements

Parameter Requirement
Trace Impedance 100Ω ±10% differential

Data to clock matching <120mil

Max trace length <7.2 inches

The minimum spacing of EMMC Signals At least 2 times the width of EMMC trace.

The minimum spacing between EMMC and other Signals Recommend 3 times the width of EMMC trace.
At least 2 times the width of EMMC trace.

Parallel CIF interface signal design requirements:

 Avoid signal traces crossing the power split area, and keep the signal reference plane intact;
 The spacing between adjacent signal traces should be kept to the principle of "3W";
 The line lengths of CIF_DATA, CIF_HSYNC, and CIF_VSYNC are based on the line lengths of
CIF_CLKOUT and CIF_CLKIN, and the deviation is controlled within ±50mil.

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 PCB Design Recommendations

Figure 3-26 RV1106G Parallel CIF layout recommendations

Table 3-7 Parallel CIF Layout Requirements

Parameter Requirement
Trace Impedance 100Ω ±10% differential
Data to clock matching <120mil
Max trace length <7.2 inches
The minimum spacing of EMMC Signals At least 2 times the width of EMMC trace.
The minimum spacing between EMMC and other Signals Recommend 3 times the width of EMMC trace.
At least 2 times the width of EMMC trace.

3.3.7 Video Output PCB design

Video output BT1120 and LCDC signal design requirements:

Table 3-8 BT1120 Layout Requirements (≤74.25Mhz)

Parameter Requirement
Trace Impedance 50Ω ±10% single ended

Data to clock matching <180mil

Max trace length <5 inches

The minimum spacing of LCDC Signals Recommend 2 times the width of LCDC trace.

Table 3-9 LCDC Layout Requirements (≤74.25Mhz)

Parameter Requirement
Trace Impedance 50Ω ±10% single ended

Data to clock matching <180mil

Max trace length <5 inches

The minimum spacing of LCDC Signals Recommend 2 times the width of LCDC trace.

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 Thermal Design Suggestion

4 Thermal Design Suggestion

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 ESD/EMI Protection Design

5 ESD/EMI Protection Design

5.1 Overview

This chapter provides ESD/EMI protection design suggestion for RV1103G/RV1106G product design
to help customers to improve anti-static and anti-electromagnetic interference ability of product.

5.2 Terms Interpretation

Terms of this chapter are explained as below：

 ESD: Electro-Static discharge
 EMI: Electromagnetic Interference, including conduction interference and radiation interference

5.3 ESD Protection

 Ensure reasonable mold design; anti-ESD devices should be reserved for ports and connectors.
 Protect and isolate sensitive components in PCB layout.
 Try best to put the RK3588 and core components in the center of PCB layout. If it may not be able
to put them in the center, ensure that the shielding cover has 2mm distance at least from the board
edge and is connected to GND safely
 PCB layout is based on function module and signal flow direction, sensitive components should be
mutually independent, and it is better to isolate the parts that are easy to produce interference;
 Place ESD components reasonably. Generally, place then near the source, that is, place ESD
components in the junction or where electrostatic discharge.
 The layout of the components should be far away from the edge of the board and a certain distance
from the connector.
 The PCB surface should have a good GND loop, and each connector should be with good GND
connection loop on the surface. If there is a shielding cover, it should be connected to the surface
ground as much as possible, and drill as much ground vias at the soldering place of the shielding
cover as possible. In order to do this, it is required that each connector should not be routed on the
surface, and there should not be traces with surface copper cut off in a large area;
 Do not go through the edge of surface layer and make as many ground vias as possible.
 Isolate signal from ground if necessary.
 Expose GND copper of PCB as much as possible, in order to strengthen the electrostatic discharge
effect, or to facilitate to add foam and other remedial measures

5.4 EMI Protection

 Electromagnetic interference has three factors: interference sources, coupling channels and
sensitive devices. We have no way to deal with sensitive devices, so EMI problem can only start
with interference sources and coupling channels. The best way to resolve EMI issues is to eliminate

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 ESD/EMI Protection Design

interference source. If it cannot eliminate, try to cut off coupling channels or avoid antenna effect;
 It is difficult to eliminate interference source on PCB. We can take actions such as filtering,
grounding, balancing, resistance controlling, improving signal quality (e.g. termination connection)
etc. Generally, several methods will be applied together, but the basic requirement is good
grounding;
 The commonly used EMI materials include shielding cover, special filter, resistor, capacitor,
inductor, magnetic bead, common mode choke/magnetic ring, wave-absorbing material, spread
frequency device, etc.;
 The rules to select filters: if the load (receiver) is high resistance (regular single ended signal
interface is high resistance, such as SDIO, RBG, CIF etc.), select capacitive filter components and
parallel connect to circuit; if the load (receiver) is low resistance (such as power output interface),
select inductive filter component and serial connect to circuit. After using the filter device, the
signal quality cannot exceed its SI permission. Differential interface usually uses common mode
choke to suppress EMI;
 The shielding measures on PCB should have good grounding, otherwise it will cause radiation
leakage or form antenna effect. The shielding of connectors should comply with relevant technical
standards;
 EMI has the same high requirement as ESD on layout. The ESD Layout requirements described
above are mostly suitable for EMI protection. Besides, add the following requirements:
 Try best to ensure the integrity of the signal;
 Differential line should in equal length and be tight coupling to ensure the symmetry of the
differential signal, minimize the misplacement of differential signals to avoid EMI problems
caused by phase mismatch;
 Components with metal shell such as plug-in electrolytic capacitors should avoid coupling
interference signals to radiate. Also need to avoid component interference signals coupling
from shell to other signal lines.

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 Soldering Process

6 Soldering Process

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