ISSN 2278-3091
Volume 9, No.5, September - October 2020
Ngangbam Phalguni Singh et al., International Journal of Advanced Trends in Computer Science and Engineering, 9(5), September - October 2020, 7461 – 7466
International Journal of Advanced Trends in Computer Science and Engineering
Available Online at http://www.warse.org/IJATCSE/static/pdf/file/ijatcse79952020.pdf
https://doi.org/10.30534/ijatcse/2020/79952020
Improved Scheduling Algorithm for the IIR Filter design for
Low power VLSI Applications
Ngangbam Phalguni Singh1, Shruti Suman2
1,2
Department of Electronics and Communication Engineering, KoneruLakshmaiah Education Foundation (KL
University), Vaddeswaram, Andhra Pradesh, India
[email protected],
[email protected] ABSTRACT
This flexible architecture can have 256 MAC operations per
The behavioural synthesis of infinite impulse response (IIR) sample. The distributed DSP resources are LUT, registers,
filter is a challenge when it comes to high speed VLSI multipliers and memory units [2] – [5]. The parallel
design applications. Implementation in FPGA is quite processing system maximizes the throughput and optimize
impossible due to huge hardware requirements and it is a the performance/cost tradeoff [6] – [8].
major obstacle to widespread acceptance. This paper
presents the algorithm that makes design decisions to reduce
power consumption. The operations are performed with
proper scheduling techniques like as soon as possible
(ASAP) and as late as possible (ALAP). The IIR filter is
considered for this implementation so that it makes easier to
identify the operations with successive clock cycles and
resource utilization. The power consumption has been
reduced by 15.27% with sampling rate from 10 MHz to 79
KHz.
Keywords: IIR Filter, FPGA, ASAP, ALAP
1. INTRODUCTION
Figure 1: FPGA implementation of IIR filter [1]
With increasing applications of VLSI design in digital signal
processing, the hardware implementation of filters has This paper contains the IIR filter design algorithms that are
become the essential demand. Behavioural synthesis is one modified for better VHDL descriptions in section 2. The
of the effective tools in designing the IIR filters in terms of scheduling of various resources is described in section 3
register operations and transform into gates and flip flops. with proper graphs. Section 4 shows the hardware
Previously, the conventional programming language C was implementation ofthe IIR filter. Section 5 represents the
used to design. However, high-level algorithmic description result analysis of the design. The conclusion is given in
can also be used for the same design. It can generate a section 6.
structural representation of the circuit for the filter.
Application Specific Integrated Circuits (ASICs) or Digital 2. IIR FILTER ALGORITHM
signal processors were used for hardware implementation of
IIR filters. The hardware implementation could have atleast There are two approaches of IIR filter implementation:
12 16-bit multipliers and 11 16-bit adders. This may use a) Direct Form I
almost 14 FPGAs with 442544 adders in total with same b) Direct Form II
number of clock cycles. This limitation does not allow to use Both consists of forward path and feedback path which
behavioural synthesis for higher order of IIR filter. This contribute to obtain the output. The filter is expressed with Z
paper proposes an algorithmic approach that minimizes the transfer functions and simulated in Matlab. The fixed point
number of resource utilization with proper scheduling implementation of IIR filter has certain limitations:
techniques. a) Co-efficient Quantization
b) Internal Quantization
The IIR filter implementation with 256 registers and 256 c) Overflow
multipliers is shown in figure 1 [1]. A conventional DSP d) Stability
processor takes 256 clock cycles whereas FPGA takes only a
single clock cycle for the same filter implementation.
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Ngangbam Phalguni Singh et al., International Journal of Advanced Trends in Computer Science and Engineering, 9(5), September - October 2020, 7461 – 7466
The proposed algorithm is used to demonstrate the multiplication and addition are performed at one clock cycle.
operations that can be executed concurrently with successive An as an as soon as possible (ASAP) schedule is introduced
clock cycles [9]. It will identify the dependency of data on to this graph showing five clock cycles; latency of five.
each other to expand the loops in behavioural description
using FPGA [10]. Algorithm 1 shows the behavioural This scheduling will perform the operations as early as
descriptions of the IIR filter. The generic ports are defined possible in a single clock cycle. It can be inserted using
as: algorithm 2 in the hardware descriptions of the IIR filter
generic (coeffa: integer_array (0 to order); design. But some of the operations are performed lately as
coeffb: integer_array (0 to order - 1)); required by the design structure. For that, as late as possible
port(input: in int; strobe: in BIT; output: out int); (ALAP) schedule technique is used.
Based on these generic ports, algorithm 1 is developed for
generating the structure of IIR filter. Delays are introduced
for clocking the modules, the filter behaviors are well
described by representing the algorithms in the graphical
formats.
Algorithm 1: Behavioural description
behavioural (descriptions_IIR)
{
begin
input_sum := input;
for j in 0 to order - 1 loop
input_sum := input_sum + (delay(j)*coeffb(j))/1024;
end loop; Figure 2: ASAP schedule in data dependency graph
output_sum := (input_sum*coeffa(order))/1024;
for k in 0 to order loop The sequence of operations may not be same as given by the
output_sum := output_sum + (delay(k)*coeffa(k))/1024; VHDL description. Equivalently, as late as possible (ALAP)
end loop; schedule can also be applied with five clock cycles as shown
for l in 0 to order - 1 loop in figure 3.
delay(l) := delay (l + 1);
end loop;
delay(order) := input_sum;
output<= output_sum;
wait on strobe;
end process;
Successive values can be differentiated by separating them
with single assignment form. In algorithm 2, output_sum
indicates the successive values.
Algorithm 2: Single assignment form
schedule (assignment form) Figure 3: ALAP schedule in data dependency graph
{
These scheduling techniques are employed using VHDL
input_sum := input + delay(0)*coeffb(0); descriptions so that the IIR filter can be implemented in
output_sum0 := input_sum*coeffa(1); hardware with less resource utilization [11] – [16]. The
output_sum1 := output_sum0 + delay(0)*coeffa(0); design is further divided into various resources with
output := output_sum1 + delay(1)*coeffa(1); different stages of clock cycles. For example, two
} multipliers and one adder are being considered just for
simplifying the design. Proper operations allocation or
The data dependency graph is constructed in figure 2 based mapping onto resources is required.
on algorithm 1. However, it is also assumed that each
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Ngangbam Phalguni Singh et al., International Journal of Advanced Trends in Computer Science and Engineering, 9(5), September - October 2020, 7461 – 7466
3. RESOURCE SCHEDULING [26]. Thus whenever a data arc crosses a clock boundary, a
register must be inserted, refer figure 6. The resources in
The number of cycles may increase if the resources can be register can be shared just like arithmetic resources. In this
constrained to a single arithmetic unit during scheduling. regards, multipliers can be employed for sharing the
Figure 5 shows the dependency graph with constrained resources. The possible hardware implementation is shown
resources. The number of possible scheduling increases with in figure 7.
relatively larger problems [17] – [20]. The total design area
increases while the speed and power consumption improve. The high pass 3rd order IIR filter is implemented with the
This approaches can trade speed and power consumption down samples of sampling rate from 10 MHz to 79 KHz.
against area by changing the schedule. The filter coefficients are A1 = -1, 93178; A2 = 0, 93403;
B0 = 0, 96645; B1 = -1, 93291; B2 = 0,96645. This is
implemented for four guard bits.
Figure 4: Resource constrained schedule.
Figure 6: Registers scheduling
Mapping of operations onto particular resources is done in
the figure 5. The shaded portions represent resources (two
multipliers and one adder) in respective clock cycles.
Figure 5: Mapping of operations onto resources
4. HARDWARE IMPLEMENTATION OF IIR FILTER
FPGA can be selected for the hardware implementation pf
the proposed algorithms [10], [21] – [22]. Two multipliers
and an adder are represented as resources by the three
shaded groups in different clock cycles. In the subsequent Figure 7: Hardware Implementation of 3rd order IIR filter
clock cycle, the result of each operation will be stored [23] –
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Ngangbam Phalguni Singh et al., International Journal of Advanced Trends in Computer Science and Engineering, 9(5), September - October 2020, 7461 – 7466
This FPGA implementation removes several level operations for the resource constraints @ voltage of 3.3 V, 2 multipliers
with proper resource mapping. This is one of the main and 1 adder. The proposed algorithm also reduces the
factors for reducing the power consumption. The mapping of number of levels for registers, thus minimizing the power
resources are converted to registers using multiplexers. The consumption. Figure 8 shows the simulation result of the
operations with high power consumptions are being replaced high pass 3rd order IIR filter. However, the frequencies
with the low power register mapping with every clock cycle. below 1 KHz still appear in the signal.
5. RESULT ANALYSIS Table 1 shows the comparative analysis of the power
consumption for 3rd order IIR filter. This result validates that
The proposed algorithms were implemented in VHDL the proposed algorithms are very effective in implementing
behavioural descriptions and run using Xilinx Vivado, the behavioural descriptions of IIR filter in FPGA.
FPGA technology Virtex 7. We run the scheduling algorithm is the power supply at 5V.
Figure 8: Simulation result of FPGA implementation of high pass IIR filter
Table 1: Power consumption analysis for 3rd order IIR filter
ACKNOWLEDGEMENT
Scheduling Power % Improvement
algorithm consumption (pJ) We thank the Department of Electronics and
[11] 10092 43.76 Communication Engineering – DST-FIST sponsored,
[12] 8092 15.27 KoneruLakshmaiah Education Foundation (KL University),
Proposed 7020 - Vaddeswaram, Indiafor allowing us to utilize the
laboratories and complete this research work in time.
6. CONCLUSION
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