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Experimental Verification and Evaluation of

Non-Stateful Logic Gates in Resistive RAM
Leon Brackmann , Tobias Ziegler, Dirk J. Wouters , Member, IEEE,
and Stephan Menzel , Senior Member, IEEE

Abstract— Resistively switching, non-volatile memory devices energy consumption and CMOS compatible integration. Due
facilitate new logic paradigms by combining storage and pro- to their different operation conditions compared to CMOS-
cessing elements. Several non-stateful concepts such as Scouting based SRAM, resistive memories enable new approaches for
or Majority have been proposed for the implementation of logic
Computing-in-Memory based on active 1T-1R crossbar arrays. implementing Computing-in-Memory (CIM) paradigms for
The operation reliability of these concepts critically depends logic evaluation or data processing [2]. A distinction is made
on the accurate readout current distinction. In this paper, between stateful CIM concepts which rely on a conditional
we perform experimental tests for several non-stateful logic gates RRAM switching, and non-stateful concepts in which the
based on transistor-coupled resistive devices (further denoted as resistive state is sensed. Both approaches exploit the switch-
1T-1R) using HfOx as the insulating material. The focus of our
investigation lies on the operation reliability and the influence able resistance difference in RRAM devices as data storage
of operation parameters. Based on our experimental findings, for binary or multi-level data. While stateful resistive CIM
we conduct a thorough statistical analysis, assessing the reliability concepts produce their operation result directly as non-volatile
and outline the limitations of non-stateful 1T-1R logic functions device state and therefore eliminate the need of additional
for Computing-in-Memory. data storage [3], the reliability of the conditional switching
Index Terms— ReRAM, 1T-1R logic, computing-in-memory, operation is limited [4], [5]. Furthermore, the initialization
majority, scouting. of the devices and the switching operation are both time-
and energy consuming [6]. In contrast to this, non-stateful
I. I NTRODUCTION concepts such as Scouting [7] or Majority [8] offer the benefit

T HE separation of memory and processing units in

Von-Neumann architectures gives rise to significant chal-
lenges as the frequent transfer of data between both units is
of a fast sensing operation compared to a prolonged RRAM
switching. Furthermore as the readout current shows less
variability, the readout operations demonstrate a lower error
both, energy and time consuming. The 3-dimensional DRAM rate [9], [10]. Based on the RRAM readout operation, several
technology tried to solve this issue by reducing the trans- logic gates have been proposed such as the Scouting AND,
fer distance between processor and memory unit. Another OR and XOR [7]. While the Scouting concept exploits only
promising approach are so-called Computing-in-Memory con- 2-Input logic functions, in theory also extended operations are
cepts [1], which aim to avoid the von-Neumann bottleneck possible, for instance the 3-Input Majority gate [11], [12].
by partially conducting data processing operations directly For an efficient usage, resistive memory arrays are imple-
in the memory or within the memory periphery. Resistive mented in a 1-Transistor 1-Resistor (1T-1R) configuration.
Memories (RRAM) are a class of emerging memory tech- This design uses a transistor, typically an n-type MOSFET,
nologies which consist of a metal-insulator-metal structure as access device for each RRAM device, which allows for
and are able to switch and maintain their electrical resis- a better selectivity and eliminates sneak path issues [13],
tance. RRAM offer a non-volatile data storage, low static [14]. A common fabrication technique for 1T-1R devices
Received 4 July 2024; revised 13 September 2024 and 22 October is to fabricate the CMOS components in the front-end and
2024; accepted 23 October 2024. This work was supported in part by afterwards integrate the RRAM devices in a back-end-of-line
the Priority Program “Memristive Devices Toward Smart Technical Sys- (BEOL) process. For these 1T-1R array structures, several
tems (Schwerpunktprogramm 2262),” which is funded by the Deutsche
Forschungsgemeinschaft (DFG, German Research Foundation); in part by the logic operations have been demonstrated such as the 2-Input
Federal Ministry of Education and Research (BMBF, Germany) within the OR, AND and XOR [15], [16], [17] or even a 16-Input
“NEUROTEC II” Project under Grant 16ME0398K and Grant 16ME0399; NAND/NOR [18]. Yet, a statistical investigation of their
and in part by the “NeuroSys A” Project under Grant 03ZU1106AA and
Grant 03ZU1106AB. This article was recommended by Associate Editor X. operation reliability is still missing. As the operation is based
Fong. (Corresponding author: Leon Brackmann.) on sensing a current, the current separability is a critical
Leon Brackmann, Tobias Ziegler, and Dirk J. Wouters are with the Insti- measure of success for non-stateful logic evaluations. This
tute for Electronic Materials II, RWTH Aachen University, 52074 Aachen,
Germany (e-mail: [email protected]). current is highly dependent on the operation conditions as well
Stephan Menzel is with the Peter-Grünberg-Institut 7-Electronic Materials, as the actual crossbar implementation. While the operations
Forschungszentrum Jülich GmbH, 52428 Jülich, Germany. AND, OR (respectively NAND and NOR) and XOR have been
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TCSI.2024.3486376. studied intensively [18], the concept of 3-Input Majority logic
Digital Object Identifier 10.1109/TCSI.2024.3486376 has only been theoretically proposed [8], but not yet been
© 2024 The Authors. This work is licensed under a Creative Commons Attribution 4.0 License.
For more information, see https://creativecommons.org/licenses/by/4.0/
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2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

realized. In this work, we investigate the operation conditions which negatively impacts the assignment of the resistance
of several non-stateful logic gates, including 3-Input Majority, ranges to the corresponding binary HRS/LRS values. The
based on resistive 1T-1R crossbars. In addition, we provide a broadening degrades the device performance as data storage
detailed statistical evaluation of their current separability. Our cell or in CIM computation [23]. Furthermore in co-integrated
main contributions here are: 1T-1R crossbars, the variability occurring from the CMOS
1) We statistically evaluate the readout currents for exper- transistor has to be taken into account.
imentally measured non-stateful 1T-1R logic gates with
1 and 2 logic inputs.
2) We investigate the influence of operation conditions, B. Logic Gates Based on Resistive Memories
namely operation voltages and positions, on the readout Resistive devices have recently been exploited for the imple-
current and its separability. mentation of functionally complete boolean logic or arithmetic
3) We demonstrate the evaluation of 3-Inputs and 5-Inputs functions within the memory crossbar [3], [24]. For this matter,
Majority-Gates based on 1T-1R resistive crossbars. the resistive devices are operated in a binary manner with
The rest of this article is structured as follows. In Section II, states LRS and HRS which are mapped to the boolean values
we briefly introduce the resistive device technology and its of ‘0’ and ‘1’. In the following, we will select the assignment
usage for implementing logic gates. The measurement setup (HRS = ‘0’/LRS = ‘1’), yet the inverted assignment is also
and methodology is explained in Section III while Section IV possible.
presents the experimental results for the resistive 1T-1R logic In stateful logic CIM paradigms, both inputs as well as
gates. Based on the measurement data in Section V we perform the operation outputs are represented by the resistance state
a statistical evaluation of the sensing capabilities and failure of a ReRAM device. The stateful operation is implemented
rates for the logic operations. Lastly, Section VI discusses the as a resistive voltage divider formed by one or several input
results and concludes this work. ReRAM devices which in turn determine the conditional state
switching of the output devices based on the given input states.
II. T HEORY AND BACKGROUND Prominent representatives of this class are the Memristor-
Aided-Logic (MAGIC) or Fast and Energy-Efficient Logic
A. Resistive Memories (FELIX) which can implement for example primitive NOR,
Resistive devices, also called Resistive RAM (RRAM), are NOT, NAND and OR gates [25], [26], [27]. However, these
a class of emerging, non-volatile storage memories based stateful concepts come in hand with several disadvantages such
on memristive devices. Memristive devices are two-terminal as a high energy consumption due to the cell initialization
electrical devices which are able to change and maintain and switching [6] and a limited reliability due to the inherent
their electrical resistance dependent on the applied elec- stochastic switching process [28], [29]. In order to avoid
tric field. Valence-change-mechanism (VCM) devices are a multiple switching processes, readout-based non-stateful logic
promising subclass of Redox-based resistive RAM (ReRAM) concepts have been proposed [7]. These concepts rely on a
[19]. A VCM device typically consists of a metal elec- non-destructive device readout and typically require only a
trode/insulating metal-oxide/metal electrode (MIM) structure. low number of programming step per device.
The switching mechanism of VCM devices is based on a local In non-stateful concepts, the logic operation is implemented
migration of ions, namely oxygen vacancies, within the metal- by sensing the state of one or several ReRAM devices in paral-
oxide. These oxygen vacancies can be seen as local n-type lel. While the logic inputs can again be represented by ReRAM
donors. Through an electroforming process redox-reactions resistance states, also a combination of non-volatile resis-
are triggered which results in the migration of ions inside tances states and volatile voltage inputs is possible [30]. The
the metal-oxide and the permanent formation of a highly operation output is computed as a volatile current. Under an
n-conductive filament. After this initial formation, the concen- applied readout voltage, the resulting current flowing through
tration of oxygen vacancies at the interface between filament the ReRAM device is directly proportional to its electrical
and metal electrode can be locally manipulated by the Joule conductance state. If several devices are readout in parallel,
heating assisted drift under sufficiently high electric fields. the total current Itotal is given as the sum of the individual
This leads to a change in the electrostatic barrier between currents, Itotal = I1 + I2 +· · ·+ In [7]. This can be exploited for
the filament surface and the metal electrode and a bipolar distinguishing the state combination of these devices [31]. The
analog switching of the electrical MIM resistance. As the local exemplary implementations of a 1-Input, 2-Input, and 3-Input
migration is a permanent effect, the VCM mechanism qualifies non-stateful operation are depicted in Figure 1. As the readout
as non-volatile switching. The resulting analog resistance current itself is an analog quantity, additional components
ranges can be mapped to digital values, for instance the binary are required to convert it to a digital voltage value. These
high-resistance state (HRS) and low-resistance state (LRS). parts, for example current-mode sense-amplifiers, are located
In the following, the switching process from the HRS to within the crossbar periphery. During the sensing, the sense
the LRS is referred to as “SET” and from LRS to HRS as amplifier compares the evaluated current, Isense to a reference
“RESET”. For VCM ReRAM the major variability sources current, Iref and outputs a digital voltage, typically GND
are cycle-to-cycle (C2C) variability, device-to-device (D2D) (‘0’) if Isense < Iref or otherwise VDD (‘1’) [8], [15].
variability and read instabilities [20], [21], [22]. This variabil- This design is comparable to standard 1T-1R crossbar arrays
ity leads to broader resistance distributions after SET/RESET for pure memory applications. Also in these structures, the
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BRACKMANN et al.: EXPERIMENTAL VERIFICATION AND EVALUATION OF NON-STATEFUL LOGIC GATES IN RESISTIVE RAM 3

Fig. 1. Schematic view of the primitive logic gate for a non-stateful 1T-1R operation with (a) 1 (b) 2 and (c) 3 resistive inputs. Denoted are also the possible
logic operations for each type.

crossbar periphery must enable at least an individual device

programming and a single device readout. A minor additional
peripheral circuit overhead arises from the implementation of
modified memory controllers which are necessary for applying
voltages to at least two crossbar lines for the two-device
parallel readout. If a multi-level readout such as XOR is
desired, the sense amplifier circuitry has to be replaced with
at least a 2-bit ADC which further increases the overhead.
Therefore, non-stateful concepts can enhance the execution
of basic computing operations directly inside the memory
while more complex task are still performed in dedicated
processing units [16]. This combination of computing and
storage functionality with an afforable circuit overhead and
a high degree of flexibility is the main advantage of readout-
based Computing-in-Memory concepts. However, in the case
of unlike state representations, such as volatile voltages and
non-volatile resistances as in the demonstrated non-stateful
operations, some kind of conversion logic or write-back loops
becomes necessary if cascading operations are intended. These
cascading operations are used if complex arithmetic such as
full adders or arithmetic-logic-units are implemented fully Fig. 2. Idealized readout current distributions for a non-stateful readout
within the memory crossbar and its periphery. This intro- with 1, 2 and 3 logic inputs. The green distributions are intentionally displayed
duces a challenging trade-off between the complexity of the with a horizontal separation for better visualization. In general, all distributions
for a unique set of ‘0’s and ‘1’s (HRS and LRS) will result in similar currents.
performed operation and the dedicated peripheral circuitry
required for the chosen logic implementation, whether stateful
or non-stateful [32]. margin, e.g., the distance between the current distributions,
The non-stateful logic functions are related to the ana- exists, a correct state determination is possible. As soon
log vector-matrix-multiplication based on Kirchhoff’s current as the distributions overlap, the concepts breaks done. For
law [33]. Yet here, multiple current levels have to be distin- example, a device in the high-resistive state will be wrongly
guished which requires complex peripheral structures such as classified as logic ‘1’ if the sensed current lies above the
n-bit Analog-to-Digital converters [34], [35]. An advantage separating reference current. Vice versa, if a device in the
of the evaluation outside of the crossbar is that different low-resistive state returns a current lower than the reference,
logic functions can be implemented in one crossbar design it will return a false logic ‘0’. This event refers to a logic
by solemnly adjusting the reference current [7], [18] within error. Due to the stochastic nature of these variability effects,
the periphery. the occurrence of errors is represented by an error probability.
In general, for a number of n ReRAM devices with binary For broader current distributions and a narrow sensing margin,
states ‘0’ and ‘1’, 2n input combinations are possible. Yet the probability of logic errors increases which reduces the
only n + 1 distinguishable current levels are expected as reliability of the concepts.
several input combinations are permutations. Due to variability
effects in the programmed ReRAM states (D2D, C2C), the
readout (read instability) or in the access transistors, the C. Related Work and State-of-the-Art
output currents Isense are part of a distribution rather than a Non-stateful Computing-in-Memory concepts for logic eval-
fixed value. Figure 2 visualizes this phenomena of arbitrary uation have been a topic of research for several years [36].
output current distributions for 1-, 2- and 3-Input non-stateful As example, the Scouting concept was proposed in 2017 for
readout evaluations. As long as a sufficient large sensing the evaluation of 2-Input logic AND/OR/XOR by sensing
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4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

the state-dependent current of resistive devices [7]. In the

same year, a similar approach was successfully demonstrated
in fully integrated HfOx 1T-1R structures [15]. Later on,
measurements of readout current distributions [17], [34], high-
level modeling approaches [37] and the usage of bit-wise
logic operations for database operations were published [16].
Recently based on HfOx 1T-1R crossbars, it was possible to
extend the distinction of readout currents towards 16-Input
NAND/NOR/XOR logics [18]. However as these approaches
focus on the implementation of AND/OR or NAND/NOR Fig. 3. (a) Schematic layout of the 1T-1R crossbar memory array used for
respectively, other promising logic families such as the Major- the non-stateful logic evaluation (b) Custom design measurement circuitry.
ity logic are rarely investigated [8], [11].
Typically, non-stateful logic operations are validated by
performing a high number of readouts and evaluate if the
output distributions overlap [18]. This approach requires a
high number of measurements for providing a significant
result, thereby increasing the effort required for data collection.
To avoid this we exploit a different statistical failure evaluation
framework [38]. Similar to other evaluations, it is based on
measuring current distributions and fit normal or log-normal
probability functions to the data [17]. Yet, instead of simply
checking for any overlap in the measured data, as consecutive
step we calculate the probability for an occurring overlap. This
method can estimate the logic error probability even for a
mediocre number of performed measurements. In addition, the
current evaluation is highly dependent on the operation volt-
ages and the crossbar parasitic, e.g. line resistances. However, Fig. 4. Current traces of a single 1T-1R device readout operation after
these influences are missing in most discussions so far. SET (Blue) and RESET (Red). Displayed are 10 cycles of SET-Readout-RE-
SET-Readout for 256 devices each.

III. M EASUREMENT S ETUP AND M ETHODOLOGY

The non-stateful 1T-1R measurements were performed on
a Memory Advanced Demonstrator 200 mm (MAD200) inte- Depending on the device state, a low (HRS) or high (LRS)
grated ReRAM computing chip. The MAD-200 process was current is observed. This standard readout is also part of any
offered by the Circuits Multi-Projects (CMP) manufacturer array for storage applications in order to access the stored
with BEOL TiN/HfO2 /Ti-based ReRAM device from CEA- data. Therefore, no matter if the information is solemnly read
LETI [39] and a CMOS design in the HCMOS9A 130 nm out and transported to a dedicated processing unit or if it is
process from STMicroelectronics. For connecting the com- processed within the memory, any error at this stage will have
puting chip, we designed a custom layout printed circuit a crucial impact on the memory quality.
board (PCB) which connects to a Labjack T7 data acquisition The assignment of HRS/LRS to the binary values ‘0’/’1’ can
board (digital circuitry), a standard DC lab power supply be seen as logic NOT. In order to investigate the influence of
for V DD and a µ C module from aixACCT Systems for switching variabilities on the current distributions, we measure
providing analog voltage inputs. The circuit layout did not 10 cycles of SET-Readout-RESET-Readout for 256 1T-1R
contain any CMOS sense amplifiers and therefore the readout devices each. The resulting time-current signals are displayed
currents are also measured by the µ C module. We performed in Figure 4. In the measured current traces no overlap of the
all measurements within a 512 × 32 crossbar array in the observed states is present. A detailed statistical investigation
“pseudo-crossbar” layout. In this layout, the transistor gates of the overlap is given in Section V.
are connected by the word lines (WL) 1-512 which are aligned In the 1T-1R arrangement, the total resistance path consists
in parallel with the source lines (SL) 1-512 connecting the of both, one transistor and one ReRAM device. Therefore, the
transistor sources. Orthogonal to these lines, the common total current Isense is inseparably influenced by the interplay
ReRAM electrodes are connected by the bit lines (BL) 1-32. between ReRAM state and the transistor behavior. While the
The schematic array layout as well as the measurement inte- ReRAM state is mostly controlled by its resistive switching
gration are depicted in Figure 3. mechanism, the transistor behavior significantly depends on
the applied operation voltages, Vread and VGate . These voltage
will determine the drain-source current of the transistor, ID,S ∝
IV. L OGIC G ATE E VALUATION
VG,S = VGate − Vread , which effectively correlates to the
A. Single Device channel resistance. In order to sense the ReRAM state as
The most straight-forward sensing operation is a single precisely as possible, the transistor should be operated with
device readout. Here, only one 1T-1R device gets activated. a low series resistance.
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BRACKMANN et al.: EXPERIMENTAL VERIFICATION AND EVALUATION OF NON-STATEFUL LOGIC GATES IN RESISTIVE RAM 5

Fig. 5. Dependency of the readout currents for (a) HRS and (b) LRS on the applied read voltage and transistor gate voltage, Vread and VGate . Each boxplot
contains the data of 1024 resistance states, evaluated from 32 switching cycles for 32 devices.

In Figure 5a and Figure 5b, we investigated the dependency

of the output current for the HRS and LRS state on Vread
and VGate . The data set contains 32 switching cycles for each
32 devices, in total 1024 resistances states. For each state,
the current is readout 25 times in a matrix-measurement for
5 values of Vread and 5 values of VGate . During the readout, the
voltages are stepped through progressively in order to reduce
any read disturb.
The data emphasizes the critical influence of the transis-
tor operation mode on the accuracy of the 1T-1R readout.
Especially when measuring an LRS current, a reduced gate
voltage VGate ≤ 3 V will lead to a higher transistor channel
resistance and therefore a limited 1T-1R readout current.
Furthermore for both HRS and LRS, the readout current
increases proportionally with the applied sensing voltage. This
implies that a higher Vread is beneficial for increasing the
absolute current sensing margin. However, the read voltage
Vread must be adjusted sufficiently low to ensure that the stored
resistance state is preserved. In the used setup, a permanent
state change was observed for Vread ≥ 0.5 V. It has to be taken Fig. 6. Readout HRS/LRS current distributions for increasing Vread values
into account that frequent reading might induce a state change at constant Vgate = 5 V. Note that the x-axis containing the currents is scaled
due to thermal crosstalk [40], [41] or read disturb [34], [42]. in a logarithmic fashion. Each histogram contains 1024 data points evaluated
from 32 switching cycles for 32 devices.
To quantify the influence of Vread on the readout current
margin, we analyse the current distributions for 3 different
Vread at a constant Vgate = 5 V in Figure 6. It is observable that TABLE I
both current distributions, HRS and LRS, shift towards higher C ALCULATED D ISSIPATED P OWER IN D EPENDENCE OF THE A PPLIED
absolute current values with increasing voltages. At the same R EAD VOLTAGE Vread FOR A S INGLE D EVICE R EADOUT /1-I NPUT NOT
G ATE . T HE C ALCULATION I S P ERFORMED BASED ON THE
time, the absolute difference of the distribution means, 1Mean , C URRENT /VOLTAGE DATA D ISPLAYED IN F IGURE 6
increases too. This can be explained by the nearly linear
dependency of the readout current on Vread . If Vread is scaled
by a factor k, the absolute current differences approximately
scale by the same factor, k × 1Mean . For the combination
Vread = 0.3 V, Vgate = 5 V the distribution means show an
absolute distance of nearly 70 µA without any observed state
overlap. While this demonstrates the sufficient separability of
a non-stateful 1-Input logic NOT, the critical influence of the Based on the mean currents for the measured data in Figure 6,
ReRAM variability as well as the operation conditions has to we calculate the power dissipation for a single device readout
be taken into account, too. in Table I.
While an increased Vread improves current window, it comes Due to the higher readout current, the low-resistive
in hand with an enhanced power dissipation, P = V (t) × I (t). state shows a higher power dissipation compared to the
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6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 8. Boxplot representation of a 2 1T-1R device Parallel readout performed

in different crossbar positions along one bitline containing 512 devices. Each
combination is programmed 16 times across each device pairs. Following each
programming, the readout is performed 100 times to include any potential read
instability.
Fig. 7. Current traces and according histogram distributions of a 2 1T-1R
device Parallel readout for the input combinations ‘00’ (Red), ‘10’/’01’
(Green) and ‘11’ (Blue). Each combination is programmed 16 times across
16 device pairs, resulting in a total 256 programmed combinations. Following As previously mentioned, the physical arrangement of the
each programming, the readout is performed 100 times to include any potential operations inputs was neglected. However due to parasitic
read instability. effects, i.e. IR-drops along the interconnecting lines, the volt-
age applied at each device will depend on its specific position
high-resistive state [23]. As the available resistance ratio in a within the crossbar [44], [45]. As already seen, the sensed
RRAM device is mainly determined by the selected material output current is highly voltage-dependent. Therefore if Vread
stack [43], it can only be marginally influence during the decreases due to the line resistances, it might impact the
actual memory operation. Therefore, the readout voltage Vread operation reliability.
is the most important operation parameter regarding the power The measured crossbar contains 512 WLs/SLs and 32 BLs.
dissipation. While the BL is kept constant, the two-device readout is
performed for 5 different pairs of WLs/SLs along the total
line. Each pair and input combination is programmed 16 times
B. Two-Input AND/OR/XOR Gate
and readout 100 times afterwards to include C2C variability
When a second 1T-1R device is activated in parallel, 4 dif- and read instability.
ferent input state combinations are possible: ‘00’, ‘01’, ‘10’ Figure 8 depicts the measurement data as boxplots. The
and ‘11’. The sum of both individual 1T-1R currents then results indicate no correlation between the measured output
yields the total sensed current. Under the assumption that the current and the relative distance of the operations, e.g., 1 to
physical device arrangement, i.e. IR-effects, can be neglected, 512 or their absolute distance from the line select, e.g., 511 to
the combinations ‘01’ and ‘10’ can be treated as equivalent 512. This observation implies a low parasitic line resistance
distributions. With a single sense amplifier 2 primitive logic within the exploited crossbar. Based on the CMOS design
gates are possible: OR, by setting the reference current above parameters such as sheet resistance and line width, a para-
‘00’ and AND, by setting it above the ‘01’/’10’ values. If the sitic line resistance of ≈ 0.1  per unitcell was estimated.
sense-amplifier is inverted as before for the NOT gate, also Therefore, the above mentioned assumption of neglecting
NAND or NOR operations can be implemented. If two sense- the crossbar position is valid for crossbar dimensions up to
amplifiers are exploited, the results of AND and OR can 512. However, the line resistance scales with the underlying
be combined which yields to an XOR. This logic evaluation CMOS process [46] and this verification has to be repeated for
concept is known in the literature as Scouting logic based on each memristive crossbar implementation individually. In case
the publication of Xie et al. [7]. of an observed parasitic voltage drop the inherent ReRAM
Figure 7 presents the time-current traces and distribution non-linearity has to be considered too.
histograms for 2-Input Parallel Readout operations. Each of the
4 state combinations was programmed 16 times into 16 dif-
ferent device pairs, which yields to 256 total programming C. Multi-Input Majority Gate
combinations. To account for any read instability between In contrast to the standard 2-Input boolean logic, a Majority
the measurements, each programmed combination is measured (MAJ) logic gate specifically requires an uneven number of
100 times. This is of particular importance as non-stateful operation inputs. The Majority gate evaluates to 1 if and
concepts typically program the devices once and only perform only if more than half of all inputs are 1, otherwise it will
readouts afterwards. The measurement data confirms the previ- return 0. If this operation is inverted, it represents a Minority
ously mentioned assumptions, that the current distributions for (MIN) function. The 8 possible combinations for a 3-Input
combinations ‘10’ and ‘01’ are inseparable. Yet, the 3 different MAJ gate are ‘000’, ‘001’ (plus 2 permutations), ‘011’ (plus
logic output states show an distinct level spacing without any 2 permutations) and ‘111’. As before, the output current distri-
observable overlap. Therefore, similar to the 1-Input NOT also butions for the 3 ‘001’, respectively for the ‘011’ permutations,
the 2-Input AND/OR/XOR gates have proven to be feasible. should be equivalent. The measurement results are depicted in
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BRACKMANN et al.: EXPERIMENTAL VERIFICATION AND EVALUATION OF NON-STATEFUL LOGIC GATES IN RESISTIVE RAM 7

Fig. 9. Current traces and according histogram distributions of a 3 1T-1R Fig. 10. Current Traces and according histogram distributions of a 5 1T-1R
device Parallel Readout. Displayed are the input combinations ‘000’ (Red), device Parallel Readout. Displayed are only the input combinations ‘00000’,
‘001’/’010’/’100’ (Green), ‘011’/’101’/’110’ (Grey) and ‘111’ (Blue). Each ‘00001’, ‘00011’, ‘00111’, ‘01111’ and ‘11111’ without their respective
combination is programmed 10 times into one device triple. Following each permutations. Each combination is programmed 16 times into a device
programming, the readout is performed 100 times to include any potential quintuple. Following each programming, the readout is performed 20 times
read instability. to account the read instability.

Figure 9. As indicated, an inseparability of the readout cur- the binary output values ‘0’ and ‘1’. As previously explained,
rents is observable for the permutated combinations of ‘001’ this assignment is based on a current comparison with a
and ‘011’. Therefore the readout currents are separated into reference current. Yet, independent of the exploited sensing
4 distinct levels which indicates the feasibility of the Majority circuitry, the separability collapses in any case if the readout
logic. Especially between the two intermediate combinations, current distributions for different logic outputs start to overlap.
‘001’ and ‘011’, no current overlap was observed in our Therefore, we exploit the distribution overlap [47] as esti-
data. This matches to the results in [8] where the Majority mation for the failure probability of each non-stateful logic
output currents were simulated and calculated based on a gate. Our error calculation framework based on [38] consists
co-integrated 0.18 µm CMOS/ReRAM process. of 3 steps:
As a first proof-of-concept, we extended the number of MAJ 1) Fitting either normal or log-normal probability density
gate inputs to 5. In this 5-Input MAJ operations, 32 total functions (PDF) to the output current distributions.
resistance state combinations are possible. As previously men- 2) Calculating the intersection points xi of all pairs of
tioned, the output currents for combinations with the same ‘0’ and ‘1’ output distributions for each desired logic
number of HRS and LRS state are inseparable. Therefore to function,
reduce the number of costly measurements, we only evaluated 3) Calculate the overlap probability as the cumulative
the combinations ‘00000’, ‘00001’, ‘00011’, ‘00111’, ‘01111’ probability function (CDF) of the intersection point,
and ‘11111’. Figure 10 depicts the resulting time-current C D F(xi ).
traces. Each combinations was programmed 16 times into a For an expected logic output of ‘0’, the expression
set of 5 devices and then readout 20 times to include the read 1 − C D F(xi ) resembles the logic error probability as
instability as before. The readout current levels split according the probability for observed current values larger than xi
to the unique state combinations in 6 different current levels, (‘False 1’). Respectively, C D F(xi ) states the error probability
each with an approximate distance of 60 µA between each for expected ‘1’ outputs which relates to observed current
level. For none of the combinations a state overlap was values lower than xi (‘False 0’).
observed. This results acts as a first proof-of-concept for the At first, we investigate the error probability for a
feasibility of the 5-Input Majority gate. However due to the voltage-dependent single device readout which relates to a
small number of samples the significance of this separability 1-Input NOT gate as previously depicted in Figure 6.
is limited. Yet, our observations match the results from Bengel For the logic functions with multiple inputs, we calcu-
et al. [34], who investigated the multi-level readout for binary late all possible error probabilities and select the maximum
vector-matrix multiplications. among them as this value will determine the operation’s
worst-case performance. The distributions are taken from
V. S ENSING C APABILITY the measurements in Figure 7 (2-Input AND/OR/XOR) and
Figure 9 (3-Input MAJ) with a constant Vread = 0.3 V. For
A. Logic Error Evaluation the 2-Input XOR operation, we calculate the probability of
In order to quantify the reliability of the demonstrated the intermediate combinations ‘01’ and ‘10 to be higher than
non-stateful logic gates, we perform a statistical evaluation ‘00’ while being lower than ‘11’ at the same time. Table III
of their current sensing capabilities. The non-stateful logic lists the corresponding results. It can be seen that increasing
evaluation requires the assignment of analog current ranges to the number of operation inputs from 2 to 3 has a negative
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8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

TABLE II
C ALCULATED VOLTAGE -D EPENDENT E RROR P ROBABILITIES FOR A
S INGLE D EVICE R EADOUT /1-I NPUT NOT G ATE . T HE
C ALCULATION I S P ERFORMED BASED ON THE
DATA D ISPLAYED IN F IGURE 6

TABLE III
C ALCULATED M AXIMUM E RROR P ROBABILITIES FOR THE M EASURED
N ON -S TATEFUL O PERATIONS W ITH 2 AND 3
L OGIC I NPUTS AT Vread = 0.3 V

Fig. 11. Calculated error probabilities of a 1-Input NOT, 2-Input AND/OR

and 3-Input MAJ for an increasing current margin [x − a, x + a] between the
logic output states.

The resulting error probabilities for the single device

readout/1-Input NOT at 0.3 V, the 2-Input AND/OR and
3-Input MAJ are depicted in Figure 11. As the readout
effect on the operation reliability. This agrees with the pre- margin increases, the likelyhood of errors increases due to the
dictions in [17] as each device will add additional variability, effective shrinking of the analog current ranges. The authors
both C2C/D2D and read instabilities, to the readout current. in [8] proposed a current-mode sense amplifier design with a
The sample size of the 5-Input Majority was too small in minimum sensing margin of 4.5 µA. At this value, the 2-Input
order to resolve the distribution width appropriately. Therefore OR has an accuracy of 1.09 × 10−13 while the accuracy of the
the error probability calculation is not significant. The data 2-Input AND and Three-Input MAJ are both around 1 × 10−5 .
set particularly lacks measurements of D2D variability and
the different permutations. It is expected that the operation VI. D ISCUSSION AND L IMITATIONS
accuracy worsens in comparison to the 3-Input Majority gate
In this paper, we experimentally demonstrated several non-
if these features are resolved appropriately as each input
stateful 1T-1R logic operations. In addition we performed a
causes additional variability. However, the measured data
quantitative analysis of the logic error probabilities.
in Figure 10 indicates at least the general feasibility of a
Due to the voltage-dependency of the readout current, the
5-device parallel readout as the distribution means demonstrate
correctness of all sensing-based logic operation can vary by
a constant spread with a sufficiently large separating margin
several orders of magnitude. Therefore it is crucial to adjust the
in between.
operation voltages properly. This includes a high VGate in order
An interesting observation is the major error probability
to reduce influence of the transistor channel resistance and a
difference between the 2-Input AND and OR. For a logic OR,
high Vread to maximize the absolute current margins. However,
the distribution of ‘00’ has to be distinguished from the three
when adjusting Vread it must be ensured that the ReRAM state
cases of ‘01’, ‘10’ and ‘11’. Respectively, for a logic AND,
is not disturbed. A further drawback of an increased read
the separation is made between ‘11’ and the others. As seen in
voltage is the increased dissipated power. Therefore during
Figure 7, the intermediate distributions ‘01’/’10’ are located
the operation design there is a trade-off to be made between
closer to ‘11’ than to ‘00’. This absolute readout current
energy-efficiency and operation accuracy.
distance results in the unbalanced error rates. The 2-Input
The 1-Input NOT and 2-Input AND/OR/XOR readout oper-
XOR is the combination of a 2-Input AND and OR. Therefore
ations were successfully demonstrated without any observed
its error probability is dominated by the most unreliable of
output current overlap. This emphasizes the feasibility of the
both, in this case the 2-Input AND.
Scouting logic family as previously reported by [17]. Although
an overlap was not experimentally observed, the calculated
error probabilities indicate that the logic AND is more vulner-
B. Circuit Sensitivity
able than the logic OR due to the asymmetric current scaling.
In real-life implementations, the sensing capability is deter- This asymmetric proneness to errors significantly influences
mined by the sense amplifier accuracy and its current sensing also the 2-Input XOR operation at it depends both on a
margin [48], [49]. Therefore, instead of using an idealized reliable AND and OR implementation. Yet, the experimental
intersection point x, we now calculate the error probability separability of the 2-Input readout currents strengthen the role
for an sensing margin [x − a, x + a]. In this case, an error of the Scouting operation scheme as promising candidate for
for an expected logic ‘0’ output occurs for readout current reliable resistive Computing-in-Memory.
values Isense > x − a, for an expected ‘1’ output at values Furthermore, the 3-Input Majority logic gate, which was
Isense < x + a respectively. proposed theoretically in [8], was successfully demonstrated
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

BRACKMANN et al.: EXPERIMENTAL VERIFICATION AND EVALUATION OF NON-STATEFUL LOGIC GATES IN RESISTIVE RAM 9

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Peter-Grünberg-Insitut 7, Forschungszentrum Jülich
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