Howard M.

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 Howard M. Berlin

EXPERIMENTS IN
ELECTRONIC DEVICES
Fourth Edition

To dently

ELECTRONIC DEVICES
an d
ELECTRONIC DEVICES:
ELECTRON-FLOW VERSION

Prentice Hall
See Cliffs, New Jersey Columbus, Ohio
Cover photo: Copyright © Superstock
Editors: Dave Garza and Judith Casillo
Developmental Editor: Carol Hinklin Robison
Production Editor: Rex Davidson
Cover Designer: Brian Deep
Production Manager: Patricia A. Tonneman
Marketing Manager: Debbie Yarnell

This book was printed and bound by Quebecor Printing/Book Press. The
cover was printed by Phoenix Color Corp.

== © 1996 by Prentice-Hall, Inc.

Kt
MUN A Simon & Schuster Company
Englewood Cliffs, New Jersey 07632

All rights reserved. No part of this book may be reproduced, in any form
or by any means, without permission in writing from the publisher.

Printed in the United States of America

PORORS sO 5e4 3 2 al

ISBN: 0-13-399544-5

Prentice-Hall International (UK) Limited, London

Prentice-Hall of Australia Pty. Limited, Sydney
Prentice-Hall Canada Inc., Toronto
Prentice-Hall Hispanoamericana, S. A., Mexico
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Editora Prentice-Hall do Brasil, Ltda., Rio de Janeiro
 PREFACE

This laboratory workbook is designed for use with the texts Elec-
tronic Devices, Fourth Edition, and Electronic Devices: Electron-
Flow Version Second Edition by Thomas L. Floyd. The 43 experi-
ments cover virtually every basic aspect of circuits containing
rectifier and zener diodes; bipolar, field effect (JFET, MOSFET),
and unijunction transistors; silicon-controlled rectifiers; opera-
tional amplifiers; and integrated-circuit voltage regulators, timers,
and phase-locked loops.
Although the experiments are specifically referenced to the
companion text, they are nevertheless general enough to be easily
integrated with any other textbook on semiconductor devices at the
electrical/electronics technology level. The experiments in this book
reinforce and expand upon the concepts presented in the class-
room. The student is able to verify these concepts by performing
detailed step-by-step experiments that are easily accomplished in
a typical two- to three-hour lab session. In all cases, experimen-
tal measurements can be reasonably compared to theory. Although
there are 43 experiments, the student will be expected to perform
only a select number of them. It is not necessary to treat all the
experiments separately; some may be conveniently combined as a
single major experiment. Experiments 9 through 12, for example,
concentrate on the biasing of bipolar transistors and can easily be
consolidated.
 PREFAC m™m

Several features enhance the utility of this workbook:

1. The purpose of each experiment is clearly defined. In addition,

a short background summary on the operation of the circuit to
be investigated is included.
2. At selected portions in a number of experiments, photographs
of the oscilloscope’s display give students a picture of what they
should observe on the screen.
3. For each experiment, a list of required parts and test equipment
is included. All parts are low in cost and are readily obtainable
from a number of sources, including Radio Shack. For conve-
nience, a summary list of these required parts appears in the
Appendix.
4. When appropriate, a summary of useful formulas is included to
enable the student to compare measured results to theory.
5. A summary of “What You Have Done,” presented at the end of
each experiment, restates and re-emphasizes the main points
of the experiment as stated in the “Purpose and Background”
section of the experiment.
6. There are “student response” pages at the end of each experi-
ment. These pages are for the student to enter the objectives/
purpose, the schematic diagram(s), all measured data (on a
blank graph page when required), and the results and con-
clusions of the experiment. These pages are perforated so that
they, along with the optional review questions, can be easily re-
moved to be submitted to the instructor as a complete laboratory
report.
7. Multiple-choice review questions are included.

I would like to thank the many users of the previous editions

who have offered their helpful suggestions for improvement. I also
wish to express my gratitude to the reviewers, who offered both
praise and constructive suggestions: Richard Burchell, Riverside
City College; Ronald Emery, Indiana University—Purdue Univer-
sity; Gary House, DeVry Institute of Technology—Atlanta; Maurice
Nadeau, Central Minnesota Vocation-Technical Institute: Tim Sta-
ley, DeVry Institute of Technology—Dallas; Guy Tolbert, Surry
Community College; Ulrich Zeisler, Utah Technical College at Salt
Lake City; Steve Harsanny, Mount San Antonio College, who
checked this manual for accuracy; and especially Thomas L. Floyd,
the author of the text to which this book is a companion.

Howard M. Berlin
 CONTENTS

PERFORMING THE EXPERIMENTS

Introduction 1
Breadboarding it
Rules for Setting Up the Experiments 2
Format for the Experiments 3
Helpful Hints and Suggestions 5
The Laboratory Report 6

EXPERIMENTS

The Diode Ly
Diode Rectifier Circuits 23
The Capacitor Input Rectifier Filter 33
The Diode Limiter 41
The Diode Clamper 51
The Diode Voltage Doubler 59
FE
WH
DO
fF
oO
HNOThe Zener Diode and Voltage Regulation 67
vi CONTENTS

Using an Ohmmeter to Test Transistor Diode

Junctions ao
Transistor Base Biasing 89
Transistor Emitter Biasing 97
Transistor Voltage-Divider Biasing 105
Transistor Collector-Feedback Biasing 113
The Common-Emitter Amplifier 121
The Common-Collector Amplifier (Emitter-Follower) 129
The Combination Common-Emitter Amplifier and
Emitter-Follower 137
The Common-Base Amplifier 145
The Class A Common-Emitter Power Amplifier 153
The Class B Push-Pull Emitter-Follower Power
Amplifier 163
The JFET Drain Curve 173
The JFET Transfer Characteristic Curve 181
JFET Self-Bias 189
The Depletion-Mode MOSFET 199
The Enhancement-Mode MOSFET 207
VMOSFET Relay Driver 25
The Common-Source Amplifier 223
The Common-Drain Amplifier (Source-Follower) 251
Amplifier Low-Frequency Response 239
The Silicon-Controlled Rectifier 249
The Unijunction Transistor 261
Op-Amp Slew Rate 271
Op-Amp Common-Mode Rejection 279
Op-Amp Inverting and Noninverting Amplifiers 287
Op-Amp Comparators 297
Op-Amp Differentiator and Integrator 307
The Butterworth 2nd-Order Low-Pass Active Filter 317
The Butterworth 2nd-Order High-Pass Active Filter o2e
The Active Band-Pass Filter 333
The Active Band-Stop Filter 345
The Phase-Shift Oscillator 357
CONTENTS vii

40 The 555 Timer Astable Multivibrator 365

41 The Phase Detector 373
42 The 567 Phase-Locked Loop Tone Decoder 383
43 The Integrated-Circuit Voltage Regulator a9

APPENDIX

Required Parts and Equipment for the Experiments 401

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 PERFORMING THE
EXPERIMENTS

INTRODUCTION

A laboratory experiment, although a powerful learning tool in the

educational process, is a double-edged sword. In order to receive the
benefits it can provide, you must follow several rules so that your
experiment will be successful. This section illustrates these rules
and describes how each of the 43 experiments is presented.

BREADBOARDING

The breadboard is designed to accommodate the experiments that

you will perform. The various transistors, diodes, integrated cir-
cuit devices, resistors, capacitors, and other components, as well as
power and signal connections, all tie directly to the breadboard. Fig-
ure 1 shows the top view of the “solderless” breadboarding socket,
which is manufactured or sold by several companies, including AP
Products, Continental Specialties, and Radio Shack.
Breadboarding is an art that cannot be learned in a few min-
utes. Rather, it takes practice and experience to develop an efficient
technique. An artist plans his creation, making sure that the picture
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will fit on the canvas in the proper proportions without crowding,

and the same is true for breadboarding electronic circuits.
When breadboarding, keep the following rules in mind:

1. Only no. 22, 24, or 26 insulated wire should be used, and it

must be solid, not stranded!
2. Never insert too large a wire or component lead into a bread-
boarding terminal.
3. Never insert a bent wire. Straighten out the bent end with a
pair of pliers before insertion.
4. Try to maintain an orderly arrangement of components and
wires, keeping all connections as short as possible. Generally,
the circuit is arranged on the breadboard in the same way that
it appears on a schematic diagram. This rule is useful when you
are trying to locate possible wiring errors.

RULES FOR SETTING UP THE EXPERIMENTS

Throughout this laboratory workbook, you will have the opportunity

to breadboard a variety of circuits. Before setting up any experi-
ment, you should do the following:

1. Plan your experiment. Know what types of results you are ex-
pected to observe.
2. Disconnect, or turn off, all power and external signal sources
from the breadboard.
3. Clear the breadboard of all wires and components from previous
experiments, unless instructed otherwise.
4. Check the wired-up circuit against the schematic diagram to
make sure that it is correct.
 Unless otherwise instructed, never make component or wiring
changes on or to the breadboard with the power or external
signal connections to the breadboard. This rule reduces the
possibility of accidentally destroying electronic components and
equipment.
When you have finished, make sure that you disconnect every-
thing before you clear the breadboard of wires and components.

FORMAT FOR THE EXPERIMENTS

The instructions for each experiment are presented in the following

format:

1. Purpose and Background. The material under this heading

states the purpose of the experiment. You should have this pur-
pose in mind as you conduct the experiment. In addition, there
is a short summary about the operation and characteristics of
the circuit that you will be building.
Text Reference. The corresponding section number and title
in Electronic Devices are given here. These sections discuss the
background for the experiment.
Required Parts and Equipment. A listing of the required
circuit components and test equipment necessary for the exper-
iment is given under this heading. Virtually all parts are low-
cost and readily available from a variety of commercial sources,
including local Radio Shack stores. (A list of the necessary com-
ponents needed for all the experiments is given in the Appendix;
in most cases, each component also includes Radio Shack’s cat-
alog number.)
Several pieces of equipment will be required for the exper-
iments:
Oscilloscope. Just about any general-purpose type will do,
and it should be a dual trace type. Input sensitivity generally
ranges from 5 mV/division to 10 V/division and has a bandwidth
from 5 MHz to 20 MHz. When needed, the schematic symbol of
Figure 2 will be used.

FIGURE 2
 VOM, VTVM, or DMM. A general-purpose type capable of
measuring dc and ac voltages and current, as well as resistance,
is necessary. If you can obtain one, use a digital type; otherwise,
any VOM used should have at least a 50 kQ)/V rating so as not
to introduce serious loading errors.
Adjustable de power supply. The de power supply should
have an adjustable output voltage range from 0 V to at least
15 V, with the capability of delivering 500 mA. Some experi-
ments will require two power supplies.
Frequency counter. It need not be an expensive one, but it
should have a resolution of 1 Hz for precise measurements.
There are several units available in kit form for less than $80.
Function generator. A function generator is a signal source
capable of producing selectable sine, triangle, and square wave-
forms of variable frequency and amplitude. Generally, they will
have voltage levels from several millivolts to approximately
20 V peak-to-peak with an output impedance to 50 2 over a
frequency range from 1 Hz to 100 kHz. Also, there is usu-
ally a TTL level pulse output. When needed, the schematic sym-
bol of Figure 3 will be used.

Sine wave Square wave

FIGURE 3

4. Useful Formulas. Under this heading is a summary of the

equations, when applicable, that apply to the design and oper-
ation of the circuit. These formulas are presented so that you
can compare measured results with theory.
5. Procedure. First the following diagrams are presented:
Schematic diagram of circuit. This figure shows the com-
pleted circuit that you will wire up for the experiment. You
should analyze this diagram in an effort to obtain an under-
standing of the circuit before you proceed. When used, the os-
cilloscope connections to the circuit are shown with bolder lines
so that they will not be confused with the normal circuit.
Pin configuration. These configurations are given for all
transistors and integrated circuit devices used in the experi-
ment.
Next, a series of numbered, sequential steps gives detailed
instructions for performing portions of the experiment. When
 appropriate, photographs of the oscilloscope’s display are in-
cluded so that you will be able to compare your results. In addi-
tion, questions are included at appropriate points. Any numeri-
cal calculations are performed easily on many of the pocket-type
calculators.
6. What You Have Done. Under this heading is an explanation
of the main points gained in performing the experiment.

HELPFUL HINTS AND SUGGESTIONS

Besides the necessary parts and equipment, only three small hand
tools are necessary for all of the experiments given in this book:

1. A pair of long-nosed pliers

2. A wire stripper/cutter
3. A small screwdriver

The pliers are used to straighten out the bent ends of hookup
wires that are used to wire the circuits on the breadboard. They
are also used to straighten out or bend the resistor, capacitor, and
other component leads to the proper position so that they can be
conveniently inserted into the breadboard.
The wire stripper/cutter is used to cut the hookup wire to size
and strip about °/s inch of insulation from each end.
The screwdriver can be used to remove the integrated-circuit
devices from the solderless breadboarding socket by gently prying
them loose.
In general, each experiment will ask you to compare a measured
value with an expected value, that is, a value you would expect to
obtain if you had not done the experiment. Generally, this value
will be determined from theory. To compare your experimental re-
sult with the predicted value, calculate the percent error, or percent
difference. The formula for determining the percent error is
measured value — true value
% error = x 100%
true value
For example, if you measure a voltage of 5.36 V and you expect
the value (from theory) to be 4.97 V, the percent error is

Gp error tes 2 Some Ley Ghar Bo,

4.97
The most common sources of error are the tolerance of component
values and the loading effects of meters. The measured result is
generally acceptable if the percent error is within 10%.
THE LABORATORY REPORT

As with any laboratory-oriented course, there is usually more to the

laboratory exercise than merely performing the experiment. Per-
forming the laboratory experiment should be followed by writing
what was done in a technical report. As an educational exercise,
writing the report serves two major purposes. First, a written re-
port documents what took place in the laboratory and gives the
instructor an indication of how well the student has understood the
principles and concepts that were supposed to be demonstrated by a
particular experiment. Second, writing a technically oriented report
provides the student with the practice of developing the communi-
cations skills that will be useful in his or her professional career.
It is my experience that many students, even in standard courses
in English composition, receive little or no instruction in writing
technical material about their particular area of study.
Many instructors or departments may have their own guide-
lines and rules concerning the format of the laboratory report. Fol-
lowing is a brief discussion of the guidelines used in the Electrical
and Electronics Technology program here at Delaware Technical and
Community College, Stanton Campus.
The completed laboratory report may be either neatly hand-
written in ink (black or blue) or typewritten. The point here is that
neatness and legibility are important. If the instructor cannot read
a sloppily written or typed report, then the effort and time taken in
its preparation has been wasted. In our courses, ample time (usu-
ally one week) is given from the date the experiment was performed
until the report is due. A report should contain the following ele-
ments:

1. Title. The title of the experiment at the beginning of the

report should be a descriptive phrase that identifies the ex-
periment. As an example, “The Common-Emitter Amplifier” is
more descriptive than “Experiment 4” because it may not be
apparent what the substance of Experiment 4 actually is. In
addition, the name of the person submitting the report should
be included, along with the names of other laboratory part-
ners. Finally, the date the experiment was performed must be
included.
2. Purpose or Objective. The particular experiment is to be
performed for some definite reason. A brief statement (one to
three sentences) that explains why the experiment is being
performed is included.
3. Wiring (Schematic) Diagram. A schematic diagram of the
circuit(s) used in the experiment must be included. The di-
agram must be neatly drawn and properly labeled with all
component values used. The use of templates to draw elec-
tronic symbols is not mandatory, and the symbols can be drawn
freehand. However, all connecting lines must be drawn with a
straightedge.
Equipment and Special Supplies. The serial number and
model number of the equipment used in the experiment should
be recorded. In some cases, the student may be asked to re-
peat the experiment to show why unusual results have been
obtained. In practice, faulty results may be obtained because
of a faulty meter or other equipment, a fact the student can
prove only if the exact instrument is used in the repeated ex-
periment.
Procedure. This contains short comments in chronological
order about the measurements, instruments used, and any spe-
cial techniques used. Such comments are usually sufficient to
explain what was done during the experiment. Long explana-
tions are generally not necessary and usually not desirable.
The comments nevertheless should be complete enough to al-
low another person to perform the experiment for verification.
Data Tables. In almost all experiments, a number of mea-
sured values should be recorded in ink. Charts are the most
convenient method of recording these data, since all values are
readily available for analysis. The data sheet on the perforated
page at the end of each experiment in this laboratory workbook
serves as the format for the data table.
The student should also understand that all erasures and
changes in data are observed by others with great suspicion.
Recording errors should not be erased. They should be indi-
cated as errors by drawing a single line through the incorrect
data and writing the correct value beside it. Many industrial
firms also require that the employee initial the change along
with the date. Indicating the error by the single-line method re-
tains the original measurement for future analysis if it should
be found to be important. In some experiments, the possible er-
ror is the only interesting part of the experiment, and the mea-
surement would be completely lost if it were erased, scratched
out, or otherwise defaced.
Calculations. All experiments require a certain number of
calculations before final results are obtained. Sample calcula-
tions that are completely identified should be included. It is
not necessary to show repeated calculations.
Graphs. Data that have been recorded in long columns on
charts cannot be analyzed quickly, but the graph provides a
visual, or pictorial, presentation of the data. The graph can be
used to determine trends and unusual results, such as a data
point that is probably in error.
 Input Voltage
FIGURE 4 Sample hand drawn graph.
 The guidelines in constructing a graph are very simple:
e Always label the axes. Generally, one parameter is plotted
as another parameter is varied. The dependent variable is
represented on the vertical axis, and the independent vari-
able on the horizontal axis. If, for example, the gain of the
amplifier is measured as the input frequency is changed,
the amplifier gain is the dependent variable because its
value depends on the value of the input frequency.
e All graphs should include a title, name of the preparer,
and the date the graph was made. At some later time, this
basic information pins down what the graph depicts, who
did it, and when it was done.
e If various conditions plotted on the same graph result in
more than one curve or line, the data points from one set
of data should be easily distinguishable from data points
belonging to a different set. Data points are frequently
marked using a dot surrounded by a small circle, or A, +,
x, ~ symbols.
e The data points should be connected smoothly with the
best-fit straight line between all points, or with a “French
curve” to construct a smooth curve between points. Fig-
ure 4 shows an example of a completed hand-drawn graph
of the measured output frequency of an oscillator as the
input voltage is varied.
Results and Conclusions. The results and conclusions are
probably the most important part of the experiment. The en-
tire experiment is considered a failure if the student does not
understand the results and cannot decide how to express the
conclusion. Many instructors read this part of the report first
and then refer to the first eight items for supporting informa-
tion. The conclusion should be as brief as possible (less than
one written page). Long conclusions often tend to bury the ac-
tual results of the experiment and instead become a procedure
sheet. One statement that should be avoided is “Everything
went well, as expected.”
10. Answers to Review Questions (optional). At the end of
each experiment in the workbook are several multiple-choice
questions. Some instructors may want to have the student in-
clude the answers to these questions as part of the laboratory
report.
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 THE DIODE

PURPOSE AND BACKGROUND

The purpose of this experiment is to examine characteristics of a

silicon diode. When the diode’s anode is at a higher potential than is
the cathode, the diode is forward biased. For conventional current
flow, current will flow through the diode from anode to cathode. For
electron flow, current will flow from cathode to anode. Unlike a re-
sistor, in which the current is directly (that is, hnearly) proportional
to the voltage across it, the diode is a nonlinear device. When the di-
ode is forward biased, a small but measurable voltage drop, called the
barrier potential, occurs across the diode. For germanium diodes, this
value is typically 0.3 V; for silicon diodes, it is approximately 0.7 V.
Text Reference: 1—9, The Diode

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 0-15 V de power supply

100 |] Signal generator
100 0 Dual trace oscilloscope
1k, VOM
1N914 (1N4148 or equivalent) Breadboarding socket
silicon, small-signal diode 11
USEFUL FORMULA

Ia

FIGURE 1-1 Graphic determination of diode forward resistance.

The determination of Ry, the diode forward resistance, is shown

graphically in Figure 1-1.

— AVa
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PROCEDURE

1. Very often one can use a VOM to check quickly whether a diode
is good or bad. Unless they have a specific function for this pur-
pose, most DMMs are not able to perform this test properly.
Using your VOM as an ohmmeter, first select a low-resistance
meter range, such as the “R x 100” range. Then connect the
positive lead of the VOM to the diode’s anode terminal while
the negative lead is connected to the diode’s cathode termi-
nal, as shown in Figure 1—2A. (Most diodes have a single col-
ored band, several bands, the diode symbol, or the letter “K”
at one end to indicate the cathode terminal.) The VOM’s inter-
nal battery then forward biases the diode. Note the resistance
reading.
If a DMM with a “ diode check” feature is used, the dis-
play usually indicates the voltage drop across a good diode from
anode to cathode when it is forward biased. When reverse bi-
ased, the DMM generally indicates some form of out-of-range
condition, such as a blinking display or the letters “OL.”
 1N914

Oscilloscope
Vertical
input (J,)

100

* Conventional current flow.

Direction is reversed for
= Cc = electron flow.

FIGURE 1-2 Schematic diagram of circuits.

2. Now reverse the VOM’s leads so that the meter’s positive termi-
nal is connected to the cathode terminal of the diode, which is
now reverse biased. Note the resistance reading.
The reading you have just obtained should be much higher
(typically several hundred thousand ohms) compared to the re-
sistance reading of Step 1, which is typically a few hundred
ohms or less. Consequently, the diode exhibits a low forward
resistance while having a high, or nearly infinite, reverse re-
sistance. The actual resistance readings obtained are not as
important as their relationship to each other. If both readings
indicate virtually the same low resistance, then the diode is
shorted; if a very high resistance is obtained in both directions,
the diode is open.
When measuring resistances, some VOMs have the polar-
ity of their leads reversed from the normal sense. That is, the
positive lead is actually wired to the internal battery’s nega-
tive terminal. In this case, the forward and reverse resistance
readings will be the opposite of those indicated in these two
steps. When it functions as a voltmeter or an ammeter, this
type of VOM has its leads internally connected in the normal
sense.
3. Wire the circuit shown in Figure 1—2B. Adjust the dc power
supply to give the voltages across the 1-kQ resistor shown in
 Table 1-1. For each voltage, measure and record the de voltage
drop (V,) across the diode. The diode current is also the current
flowing through the 1-kO resistor. Determine the diode current
by using Ohm’s law in each case.
Plot the resulting diode curve (diode current versus voltage)
on the graph page in this experiment. Graphically determine
the diode’s barrier potential (Vg) and forward resistance (Rf),
recording your results in Table 1-2.
Disconnect the power from the breadboard and wire the circuit
shown in Figure 1—2C. In this part, the oscilloscope is set up to
function as an X-Y plotter. Set the oscilloscope controls to the
following approximate settings:
Vertical (or Y) input sensitivity: 10 mV/division,
de coupling
Horizontal (or X) input sensitivity: 1 V/division,
de coupling

After the oscilloscope has warmed up, center the trace dot at
the center of the scope’s screen. Adjust the sine wave frequency
of the signal generator to approximately 100 Hz, and vary the
generator’s output level so that you observe the characteristic
diode curve similar to the one plotted in Step 4. The oscilloscope
display should be similar to that shown in Figure 1-3. If it is
not, the leads of the oscilloscope may be interchanged or there
may be wiring error.
The horizontal input measures the voltage across the diode
(Vi), neglecting the small voltage drop across the 10- resistor.
The vertical input measures the voltage drop across the 10-0

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FIGURE 1-3
14
 resistor. By Ohm’s law, the vertical input can be made to show
the diode current (J, ). If the vertical sensitivity is 10 mV/division,
then in terms of the current through the 10-Q resistor, which
is the same as the diode current,
10 mV/ division
Vertical sensitivity =
100
= 1 mA/division
As in Step 4, from the oscilloscope’s display graphically de-
termine the diode’s barrier potential and forward resistance,
recording your results in Table 1-2. How does this compare with
Step 4 for the same diode?

WHAT YOU HAVE DONE

This experiment examined the characteristics of a silicon diode. You

learned how to properly test a diode using a VOM or DMM, and how
to determine the diode’s barrier potential and forward resistance.
By graphing the diode’s forward characteristic, you observed that
the diode is a nonlinear device.

15
 NOTES

16
Name Date

THE DIODE

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 17

ING tiie ne See Date

DATA FOR EXPERIMENT 1

TABLE 1-1

Voltage across Diode Diode Forward

1-kQ Resistor Voltage Current

On

10V

© 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

TABLE 1-2

Parameter Step 4

Diode barrier potential, Vz

Diode forward resistance, Rr

© 1996 Prentice-Hall, Inc. All rights reserved. 19

 NOTES

20
Namen eat
= Date

DATA FOR EXPERIMENT 1

© 1996 Prentice-Hall, Inc. All rights reserved. 21

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 1

1. When an ohmmeter is used to test a diode, as in Figure 1—2A,

a very low resistance (but not zero) in one direction means that
the diode is
(a) open (b) shorted
(c) forward biased (d) reverse biased
In this experiment, the measured diode barrier potential is ap-
proximately
(a) 0.3 V (b) 0.6 V (c) 0.9 V (d) 1.2V
If the 10-Q resistor in Figure 1—2C is changed to 100 © and
the oscilloscope’s vertical sensitivity is 0.5 V/division, then the
vertical axis, in terms of current, is
(a) 0.5 mA/division (b) 5 mA/division
(c) 50 mA/division (d) 0.5 A/division
For which region of your experimental diode curve does the diode
look like an open circuit?
(a) Diode voltages less than the barrier potential
(b) Diode voltages greater than the barrier potential
For the region of the diode curve greater than the diode’s barrier
potential,
(a) the curve is essentially horizontal
(b) the diode forward resistance approaches an open circuit
(c) the diode voltage increases rapidly
(d) the diode current increases rapidly ( )

22 © 1996 Prentice-Hall, Inc. All rights reserved.

 DIODE RECTIFIER CIRCUITS

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the characteristics

of three different diode rectifier circuits! half-wave rectifier, center-
tapped full-wave rectifier, and full-wave bridge rectifier. Each type
causes an ac input voltage to be converted into a pulsed waveform
having an average, or dc, voltage output.
Text References: 2-1, Half-Wave Rectifiers; 2—2, Full-Wave Rec-
tifiers.

REQUIRED PARTS AND EQUIPMENT

1-kQ resistor, 1/2 W Dual trace oscilloscope

|] Four 1N4001 silicon VOM or DMM
rectifier diodes Breadboarding socket
12.6-V rms secondary
center-tapped transformer

23
 USEFUL FORMULAS

Half-wave rectifier

(1) de voltage output =

Vs — Vp (sine wave input)

(2) Diode PIV = V,

(3) Output frequency = input frequency
Center-tapped full-wave rectifier

(4) de voltage output = 2Vs

— Vp (sine wave input)
TT

(5) Diode PIV —2V,

(6) Output frequency = 2 x input frequency
Full-wave bridge rectifier
2(Vs — Vp
(7) de voltage output = ! (sine wave input)
TT

(8) Diode PIV = V,

(9) Output frequency = 2 X input frequency

PROCEDURE

Le Wire the half-wave rectifier circuit shown in Figure 2—1A, paying

careful attention to the polarity of the 1N4001 diode. You should
be very careful to be sure that your connections to the 117-V pri-
mary of the transformer are properly protected so that you will
not get a shock by accidentally touching them. Furthermore,
you should have a 1/2-A fuse on the primary side of the trans-
former. Note that neither of the transformer’s primary leads is
grounded, while the center-tapped secondary lead is not used
in this section!
Set your oscilloscope to the following approximate settings:
Channels 1 and 2: 10 V/division, de coupling
Time base: 5 ms/division
Apply 117 VAC (rms) to the transformer’s primary leads. Con-
nect one scope probe to the anode terminal of the 1N4001 diode
(point A), and the other probe to the diode’s cathode terminal
(point B). If everything is working properly, you should obtain
the waveforms shown in Figure 2-2.
Measure the transformer’s peak secondary voltage (Vs), as well
as the peak voltage (V,,) across the 1-kQ resistor, recording your
results in Table 2-1. Are the two readings the same?
24
 117 VAC

117 VAC

<—

117 VAC

Cc. =

FIGURE 2-1 Schematic diagram of circuits.

You should find that these two readings differ slightly. The
voltage difference is the barrier potential of the diode (Vg), which
is approximately 0.7 V for silicon diodes. When the peak voltage
is at least ten times larger than this diode voltage drop, the
barrier potential usually can be safely neglected, so that these
two readings can be considered essentially the same.
4, With your VOM or DMM, measure the dc voltage (Vpc) across
the 1-kQ resistor, and record your result in Table 2-1. Compare
this result with that obtained from the equation for the average
or de voltage of a half-wave rectifier (Equation 1).
Observe both waveforms. Notice that the frequency of the
rectified output sine wave is the same as that of the input
sine wave, even though half of each cycle of the output is zero.
Why?
5. Turn off the power to the transformer, and wire the center-
tapped full-wave rectifier circuit shown in Figure 2—1B. Again,
pay careful attention to the polarity of both diodes and the
 Point A
10 V/division

Point B
10 V/division

FIGURE 2-2 Time base: 5 ms/division.

connections to the 117-V primary of the transformer. The

center-tapped lead is grounded for this section.
Now set your oscilloscope to the following approximate settings:
Channels 1 and 2: 5 V/division, de coupling
Time base: 5 ms/division
Apply 117 VAC (rms) to the transformer’s primary leads. Con-
nect one probe to the anode terminal of the 1N4001 diode (point
A), and the other probe to one of the diode’s cathode terminals
(point B). If everything is working properly, you should obtain
the waveforms as shown in Figure 2-3.
Measure the transformer’s peak secondary voltage (Vs) with re-
spect to the grounded center tap, as well as the peak voltage
(V,) across the 1-kQ resistor, recording your results in Table
2-1. How do these readings compare with those of Step 3?
The peak secondary voltage should be half that of Step 3.
With your VOM or DMM, measure the de voltage (Vpc) across
the 1-kQ resistor, and record your result in Table 2-1. Compare
this result with that obtained from the equation for the average
or de voltage of a center-tapped full-wave rectifier (Equation 4).
Observe both waveforms. Notice that the frequency of the
rectified output sine wave is now twice that of the input sine
wave. Why?
Turn off the power to the transformer, and wire the full-wave
bridge rectifier circuit shown in Figure 2-1C. Pay careful at-
tention to the polarity of all four diodes and the connections to
the 117-V primary of the transformer. The center-tapped lead
is not used for this section. Remove the oscilloscope probe from
the anode of the diode.
26
 Point A
5 V/division

Point B
5 V/division

FIGURE 2-3 Time base: 5 ms/division.

10. Apply 117 VAC (rms) to the transformer’s primary leads. With
the channel set to de coupling, connect only the probe to the
ungrounded lead of the 1-k) resistor (point A). If everything
is working properly, you should obtain the same full-wave rec-
tified waveform obtained in Step 6.
11. Measure the peak voltage (V,,) across the 1-k( resistor, record-
ing your result in Table 2-1. How does this reading for V,
compare with those of Steps 3 and 7?
The peak secondary voltage should be the same as that of
Step 3 and twice that of Step 7. In addition, you should find
that the peak voltage across the 1-k) resistor is smaller than
the secondary voltage by twice the barrier potential. Why?
12. With your VOM or DMM, measure the dc voltage (Vpc) across
the 1-kO resistor, and record your result in Table 2-1. Compare
this result with that obtained from the equation for the average
or de voltage ofa full-wave bridge rectifier (Equation 7).
Observe both waveforms. Notice that the frequency of the
rectified output sine wave is twice that of the input sine wave.
Why?

WHAT YOU HAVE DONE

This experiment compared the output characteristics of three types

of rectifier circuits: half-wave rectifier, full-wave rectifier using a
center-tapped transformer secondary, and a full-wave bridge recti-
fier. Each converts an ac voltage into a pulsed waveform having an
average or dc voltage output. 27
 NOTES

28
IN21 C= ee ee Date

DIODE RECTIFIER CIRCUITS

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 29

 Name Date

DATA FOR EXPERIMENT 2

TABLE 2-1
=a
Center-Tapped Bridge
Measured Half-Wave Full-Wave Full-Wave
Parameter Rectifier Rectifier Rectifier

Same as
Vs center-tapped
full-wave rectifier

Vp
Voc

30 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 2

ilk For the half-wave rectifier circuit of Figure 2—1A, the peak load
voltage is approximately
(a) 6 V (b) 12 V (CymI ony (d) 24 V
For an input frequency of 60 Hz, the period of the half-wave
signal is approximately
(a) 4ms (b) 8 ms (c) 16 ms (d) 32 ms
Compared to the de output voltage of the half-wave rectifier
of Figure 2-1A, the de output voltage of the full-wave bridge
rectifier of Figure 2-1C is approximately
(a) one-half as large (b) the same (c) twice as large
In this experiment, the rectifier circuit that has the lowest diode
peak inverse voltage is the
(a) half-wave rectifier (b) full-wave center-tapped rectifier
(c) full-wave bridge rectifier (d) both a and c
In this experiment, the rectifier circuit that has the greatest dc
output voltage is the
(a) half-wave rectifier (b) full-wave center-tapped rectifier
(c) full-wave bridge rectifier

© 1996 Prentice-Hall, Inc. All rights reserved. 31

 NOTES

32
 THE CAPACITOR INPUT
RECTIFIER FILTER

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation of

a capacitor input filter when connected to the output of a full-wave
bridge rectifier. The filter, which consists of a single resistor and
capacitor in parallel, smooths out the pulsating output voltage of
the rectifier.
Text References: 2—3, Power Supply Filters; Appendix B, Deriva-
tions.

REQUIRED PARTS AND EQUIPMENT

1-kO resistor, 1/2 W [] 12.6-V rms secondary

Capacitors (25 V): center-tapped transformer
100 uF [} Dual trace oscilloscope
470 pF VOM or DMM
CL] Four 1N4001 silicon Breadboarding socket
rectifier diodes

33
 USEFUL FORMULAS

de output voltage

(1) Vac = [ a | (when R,C Ze Tinput)

R iC
rms ripple voltage

Cees ae eae Ue
RzC
Percent ripple factor

(3) Yr = Ve x 100%
de

PROCEDURE

Oscilloscope
CH 1

1N4001
(4)

FIGURE 3-1 Schematic diagram of circuit.

1. Wire the full-wave bridge rectifier circuit shown in Figure 3-1,

paying careful attention to the polarity of the 1N4001 diodes.
You should be very careful to be sure that your connections to
the 117-V primary of the transformer are properly protected
so that you will not get a shock by accidentally touching them.
Furthermore, you should have a 1/2-A fuse on the primary
side of the transformer. Note that neither of the transformer’s
primary leads is grounded, while the center-tapped secondary
lead is not used. Also observe the polarity of the 100-uF filter
capacitor.
2. Apply 117 VAC (rms) to the transformer’s primary leads. With
one oscilloscope channel set to de coupling, connect the probe to
the ungrounded junction of the 1-kQ resistor and the 100-uF
capacitor. If everything is working properly, you should obtain
the waveform shown in Figure 3-2.
34
 »
x
*
s

5 V/division

Ground reference

FIGURE 3-2 Time base: 2 ms/division.

3. With the oscilloscope, measure the peak output voltage (V,)

across the 1-kQ resistor and the 100-uF capacitor. With your
VOM or DMM, measure the de voltage (Va-) and compute the
expected dc voltage, rms ripple, and percentage ripple factor
using Equations 1, 2, and 3. Record all results in Table 3-1.
4, Turn off the 177-VAC primary voltage, and then place a piece of
wire or a screwdriver across both capacitor leads, which, in ef-
fect, discharges the capacitor. With the relatively low secondary
voltages used in this experiment, the risk of getting a severe
shock is small. However, this practice is a good habit to acquire
when working with power supplies and filters. By discharging
(that is, shorting) the filter capacitor after the supply voltage
has been turned off or removed, you then eliminate the possi-
bility of coming in contact with a fully charged capacitor, which,
depending on its capacitance and voltage, can deliver quite an
unexpected Jolt.
Remove the 100-uF capacitor from the circuit and replace
it with a 470-uF capacitor. Then apply 117 VAC to the trans-
former’s primary.
5. With your oscilloscope, measure the peak output voltage across
the 1-kQ resistor and the 470-uF capacitor. As in Step 3, mea-
sure the de output voltage and, using Equations 1, 2, and 3,
calculate the expected values for the dc voltage, rms ripple
voltage, and percent ripple factor. Record all results in Table
3-1.
6. If you have wired the circuit correctly, you should now observe
very little ripple voltage on the oscilloscope’s display. Now
change the input to ac coupling, and increase the sensitivity of
 the oscilloscope channel to about 10 mV/division so that you can
clearly see the output ripple.
7. For each capacitor value, compare your values for de output
voltage, rms ripple voltage, and percent ripple factor. When you
increase the value of the filter capacitor, what happens to the
dc output voltage, rms ripple voltage, and percent ripple factor?
For a fixed load resistance of 1 k{), increasing the capaci-
tance of the input filter capacitor should increase the dc output
voltage toward the peak output voltage while decreasing both
the rms ripple voltage and the percent ripple factor.

WHAT YOU HAVE DONE

This experiment demonstrated the operation of a capacitor input

filter when connected to the output of a full-wave bridge rectifier.
The filter, using a parallel resistor-capacitor circuit, smooths out the
pulsating output voltage of the rectifier. As the RC time constant
of the filter was made larger, the ripple voltage of the filter was
reduced further.

36
INI Coe eee ee ee ee ee eee Date

THE CAPACITOR INPUT RECTIFIER FILTER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 37

Name Date

DATA FOR EXPERIMENT 3

TABLE 3-1

Parameter Step 3 Step 5

Secondary peak voltage, V,,:

Measured

de output voltage, Vic:

Calculated

Measured

rms ripple voltage, V,:

Calculated

Measured (peak-to-peak)

% ripple factor, % r:
Calculated

© 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 3

ie For the circuit of Figure 3—1, the time constant of the capacitor
input filter is
(a) 1 ms (b) 10 ms (c) 100 ms (d) 1s
In Step 5, the de output voltage is approximately
(a) 6V (b) 12 V (c) 18 V (d) 24 V
As the time constant of the input filter is decreased, the dc
output voltage
(a) decreases (b) increases (c) remains the same
As the time constant of the input filter is decreased, the output
ripple voltage
(a) decreases (b) increases (c) remains the same
In a well-designed power supply, the percent ripple factor should
be
(a) close to 0% (b) approximately 50%
(c) close to 100%

© 1996 Prentice-Hall, Inc. All rights reserved. 39

 NOTES

40
 THE DIODE LIMITER

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation of a

diode limiter. Diode limiters are wave-shaping circuits in that they
are used to prevent signal voltages from going above or below certain
levels. The limiting level may be either equal to the diode’s barrier
potential or made variable with a de source voltage. Because of this
clipping capability, the limiter is also called a clipper.
Text Reference: 2—4, Diode Limiting and Clamping Circuits.

REQUIRED PARTS AND EQUIPMENT

15-k© resistor, 1/4 W |] 0-15 V de power supply
L) 5-kO potentiometer, or Signal generator
10-turn “trimpot” [|] Dual trace oscilloscope
[] 1N4001 silicon rectifier Breadboarding socket
diode

41
 PROCEDURE
15 kQ V

CH 2 CH 2
Oscilloscope Oscilloscope
CH 1 CH 1

15 kQ V.

CH 2 CH 2
= Oscilloscope Oscilloscope
CH 1 CH 1
B. = D. —

FIGURE 4-1 Schematic diagram of circuits.

1. Wire the limiter circuit shown in the schematic diagram of Fig-

ure 4-1A. Set your oscilloscope to the following approximate
setting:
Channels 1 and 2: 1 V/division, de coupling
Time base: 1 ms/division
Without any input signal connected to the breadboard, position
the two lines on the oscilloscope’s display so that they are at the
same level (that is, zero volts).
2. Now connect the signal generator to the breadboard. Adjust the
signal generator’s output level at 6 V peak-to-peak at a fre-
quency of 200 Hz. You should see two waveforms similar to
those shown in Figure 4—2. Notice that the positive peaks of
the limiter’s output waveform are removed, or clipped off. No-
tice also that the clipping level is not perfect; the positive peaks
are clipped not at zero volts, but at a small positive voltage.
When the input waveform goes positive at a level greater than
the barrier potential of the diode, the diode is forward biased,
the equivalent ofa short circuit in series with a small de voltage
source. Thus, approximately 0.5 to 0.7 volt (the barrier potential

42
 for a silicon diode) is dropped across the diode. When the input
waveform goes negative, the diode looks like an open circuit,
and essentially all of the input appears at the output. Such an
arrangement is called a positive limiter because the circuit lim-
its the positive peaks of the input waveform. On the data page
at the end of this experiment, sketch your clipped waveform,
showing the positive and negative peak values.

4
¢
=

FIGURE 4-2

3. Now reverse the polarity of the diode in the circuit, as shown

in Figure 4—1B. How does this waveform compare with that of
Step 2?
The behavior is opposite that of the positive limiter. The
waveform has all negative peaks of the input signal removed,
as shown in Figure 4—3. Again, notice that the clipping level is
not perfect; the negative peaks are clipped not at zero volts, but
at a small negative voltage. Such an arrangement is called a
negative limiter because the circuit clips off the negative peaks
of the input waveform. On the data page at the end of this
experiment, sketch your clipped waveform, showing the positive
and negative peak values.
Now connect the circuit of Figure 4-1C. Apply power to the
breadboard and adjust the potentiometer so that the de volt-
age (Vpc) is +1.5 V. Connect the signal generator, set at 6 V
peak-to-peak, to the breadboard. What do you notice about the
output of the limiter?
The clipping level is higher than that measured in Step 2.
The circuit uses a de source voltage to bias, or set, the clipping

43
 %
y
6

a
e

— 0 volts

FIGURE 4-3

level. Consequently this arrangement is called a positive-biased

limiter. On the data page at the end of this experiment, sketch
the clipped waveform, showing the de positive and negative peak
values.
Note that the positive clipping level is the de source volt-
age plus the diode’s barrier potential. For the diode to become
forward biased, the positive peaks of the input signal must be
greater than the de source voltage and the diode’s barrier po-
tential.
Vary the resistance of the potentiometer from one extreme to
the other. What happens to the clipping level?
The clipping level changes with the setting of the poten-
tiometer. At one extreme, when the de bias voltage (Vpc) is zero,
the positive clipping level should be the same as was measured
in Step 2. At the other extreme, there should be no clipping, as
the dc bias voltage is about +5 V. Since the input positive peaks
are at +3.0 V, the diode is effectively reverse biased and looks
like an open circuit, and thus the input appears unchanged at
the output.
Now reverse the polarities of both the diode and the de power
supply in the circuit, as shown in Figure 4—1D. Adjust the po-
tentiometer so that the de voltage (Dpc) is —1.5 V. Connect the
signal generator, set at 6 V peak-to-peak, to the breadboard.
What do you notice about the output of the limiter?
Note that the clipping level is lower than that measured
in Step 3. The circuit uses a de source voltage to bias, or set,
the clipping level. Consequently, this arrangement is called a

44
 negative-biased limiter. On the data page at the end of this ex-
periment, sketch the clipped waveform, showing the dc positive
and negative peak values.
Notice also that the negative clipping level is the dc source
voltage plus the diode’s barrier potential. For the diode to be-
come forward biased, the negative peaks of the input signal
must be greater than the de source voltage and the diode’s bar-
rier potential.
7. Vary the resistance of the potentiometer from one extreme to
the other. What happens to the clipping level?
The clipping level changes with the setting of the poten-
tiometer. At one extreme, when the dc bias voltage (Vpc) is zero,
the positive clipping level should be the same as was measured
in Step 3. At the other extreme, there should be no clipping, as
the dc bias voltage is about —5 V. Since the input negative peaks
are at —3.0 V, the diode is effectively reverse biased and looks
like an open circuit, and thus the input appears unchanged at
the output.

WHAT YOU HAVE DONE

This experiment demonstrated the operation of a diode limiter, or

clipper, which limits signal voltages from going above or below preset
levels. You worked with both positive and negative limiters whose
clipping level was equal to the diode’s barrier potential. In addition,
it was shown how to make the clipping level variable by using an
external de voltage source.

45
 NOTES

46
Name Date

THE DIODE LIMITER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 47

 NOTES

48
Name __ = : te Oe Date

DATA FOR EXPERIMENT 4

Volts cy seen 111) CLV — Volts/div=__._.. Time/div=

Positive clipper (Step 2) Negative clipper (Step 3)

Volts) Ci y= enneeenne DTTC) 11), ee Volts/div=_____________ Time/div=

Positive-biased clipper (Step 4) Negative-biased clipper (Step 6)

© 1996 Prentice-Hall, Inc. All rights reserved. 49

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 4

1. For the positive limiter circuit of Figure 4—1A, the positive peak
voltage is approximately
(a) OV (Db) 0:6) (c) +3 V (d) +6V
For the negative limiter circuit of Figure 4—1B, the positive
peaks are not clipped because the diode is
(a) reverse biased (b) forward biased
In all the limiting circuits in this experiment, the 15-k resistor
is used to
(a) set the clipping level
(b) set the peak output voltage
(c) limit the voltage across the diode
(d) limit the peak forward diode current
For the circuit of Figure 4—1C, the potentiometer is used to set
the clipping level of the output’s
(a) positive peaks (b) negative peaks
(c) positive and negative peaks
For the circuit of Figure 4—1D, the potentiometer is used to set
the clipping level of the output’s
(a) positive peaks (b) negative peaks
(c) positive and negative peaks ( )

50 © 1996 Prentice-Hall, Inc. All rights reserved.

 THE DIODE CLAMPER

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation

of a diode clamper. Like the diode clipper, the clamper is a wave-
shaping circuit, but it adds a dc level to the input waveform. Thus,
the clamper is often referred to as a dc restorer. However, unlike
that of the clipper, the shape of the input signal of a clamper is not
changed.
Text Reference: 2—4, Diode Limiting and Clamping Circuits.

REQUIRED PARTS AND EQUIPMENT

10-kO resistor, 1/4 W Signal generator

10-uF electrolytic capacitor, Dual trace oscilloscope
25 V Breadboarding socket
1N4001 silicon rectifier
diode

51
 USEFUL FORMULAS

Clamper time constant

(1) 10R,C
> Tinput
Peak output voltage
(2) Vout(peak) = Vin (peak-to-peak) — Vz

PROCEDURE

CH 2
Oscilloscope
CHa

FIGURE 5-1 Schematic diagram of circuit.

1. Wire the clamper circuit shown in the schematic diagram of

Figure 5-1. Set your oscilloscope to the following approximate
settings:
Channels 1 and 2: 2.0 V/division, de coupling
Time base: 0.2 ms/division
Without any input signal connected to the breadboard, position
the two lines on the oscilloscope’s display so that they are at the
same level (that is, zero volts).
2. Now connect the signal generator to the breadboard. Adjust the
signal generator’s output level at 5 V peak-to-peak at a frequency
of 1 kHz. You should see two sine waves. Notice that the clamper’s
output signal level is above the input’s. This action is that of a pos-
itive clamper, so the input waveform is shifted upward. This effect
is the same as that obtained by adding a de voltage onto the input
waveform. On the data page at the end of this experiment, sketch
both the input and the output waveforms, showing the positive
and negative peak values for both.
3. Note that the clamping action is not perfect. The negative peaks
of the output waveform are clamped not at zero volts, but at a
small negative voltage. When the input waveform goes nega-
tive at a level greater than the barrier potential of the diode,
the diode is forward biased, the equivalent of a short circuit

52
 in series with a small de voltage source. Thus, approximately
0.5 to 0.7 volt (the barrier potential for a silicon diode, V,) is
dropped across the diode, while the remainder of the peak neg-
ative voltage (V, — Vi) charges the 10-uF capacitor. On the next
positive-going half-cycle, the diode is reverse biased, looking like
an open circuit, and the voltage stored on the capacitor is then
added to the time-varying input voltage. The result is that the
peak output voltage is now approximately equal to the peak-to-
peak input voltage, less the voltage drop of the diode.
4. Increase the peak-to-peak input voltage. What happens?
Although the peak-to-peak output voltage increases, its neg-
ative peak remains clamped at the same negative voltage level
measured in Step 3. You should find that the positive peak out-
put voltage is again approximately equal to the peak-to-peak
input voltage.
5. Now reverse the polarity of the diode in the circuit, and repeat
Steps 2, 3, and 4. Now what happens?
The behavior is opposite that of the positive clamper. Notice
that the clamper’s output signal level is below the input’s. This
action is that of a negative clamper, so the input waveform is
shifted downward. This effect is the same as that obtained by
adding a negative dc voltage onto the input waveform. On the
data page at the end of this experiment, sketch both the input
and the output waveforms, showing the positive and negative
peak values for both.
6. Again you should notice that the clamper action is not perfect.
The positive peaks of the output waveform are clamped not at
zero volts, but at a small positive voltage.
7. Increase the peak-to-peak input voltage. What happens?
You should see that although the peak-to-peak output volt-
age increases, its positive peak remains clamped at the same
positive voltage level measured in Step 6. You should find that
the negative peak output voltage is again approximately equal
to the peak-to-peak input voltage.

WHAT YOU HAVE DONE

This experiment demonstrated the operation of a diode clamper.

This circuit does not change the waveshape of the input signal, but
merely adds a dc level to the input waveform.

53
 NOTES

54
Name Date

THE DIODE CLAMPER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 55

 NOTES

56
Name

DATA FOR EXPERIMENT 5

(a

100
90

Wollasyeiny=_ Wl
Positive clamper (step 2)

or

be )
Volts/div=______
sd Time/div=
Negative clamper (step 5)

© 1996 Prentice-Hall, Inc. All rights reserved. SN

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 5

Lt For the circuit of Figure 5—1 to function properly, the input fre-
quency should be at least
(a) 1 Hz (b) 10 Hz (c) 100 Hz (d) 1 kHz
For the circuit of Figure 5-1, if the input signal has a peak
voltage of V,, then the output signal is
(a) shifted upward by approximately V,,
(b) shifted upward by approximately 2V,,
(c) shifted downward by approximately V,,
(d) shifted downward by approximately 2V,
For the circuit of Figure 5-1, the negative peak voltage of the
output signal is approximately
(a) =n

(b)e—0-7 V
(c) OV
(d) +0.7 V
If the peak-to-peak input voltage is increased,
(a) the peak-to-peak output voltage remains approximately
equal to the peak-to-peak input voltage
(b) the negative peak output voltage remains clamped at ap-
proximately —0.7 V
(c) the output peak voltage approximately equals the peak-to-
peak input voltage
(d) all of the above
In order to change the circuit of Figure 5-1 to a negative clam-
per, you must
(a) reverse the polarity of the signal source
(b) reverse the polarity of the diode
(c) reverse the polarity of the capacitor
(d) all of the above ( )

58 © 1996 Prentice-Hall, Inc. All rights reserved.

 THE DIODE
VOLTAGE DOUBLER

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation of

both the half-wave and the full-wave diode voltage doublers. Diode
voltage doublers are used to double the peak rectified voltage with-
out the necessity of increasing the input transformer’s voltage rat-
ing. The half-wave voltage doubler is actually a positive clamper
followed by a half-wave rectifier with a capacitor input filter (peak
detector). It charges a series capacitor on each positive half-cycle.
Consequently, the ripple frequency is the same as the input fre-
quency.
The full-wave voltage doubler, on the other hand, has the
same rectified peak output voltage as the half-wave doubler. It
charges one of two series capacitors on the first half-cycle, while
the other capacitor is charged on the remaining half-cycle. There-
fore, it has a ripple frequency that is twice the input frequency.
Consequently, for the same filter time constant, the peak-to-peak
ripple voltage is smaller when a full-wave voltage doubler is
used.
Text Reference: 2-5, Voltage Multipliers.

59
 REQUIRED PARTS AND EQUIPMENT
10-kQ resistor, 1/4 W [] 12.6-V rms secondary
Two 100-uF capacitors, center-tapped transformer
2D Vi C) Dual trace oscilloscope
[| Two 1N4001 silicon [|] VOM or DMM
rectifier diodes (] Breadboarding socket

USEFUL FORMULAS

Output voltage
(Von
2Vina 2Va
Ripple frequency
(QQ faeple = "fin (half-wave doubler)
(3) fripple = 2fin (full-wave doubler)
Diode peak inverse voltage
(4) PIV = 2V,

PROCEDURE

1. Wire the half-wave diode voltage doubler shown in the schematic

diagram of Figure 6—-1A.
2. Set your oscilloscope to the following approximate settings:
Channels 1 and 2: 5 V/division, de coupling
Time base: 2 ms/division
Apply the 117-V rms ac, 60-Hz power line voltage to the trans-
former’s primary.
3. You should see two sine waves on the oscilloscope’s display. On
Channel 1 at point A, it should show the secondary voltage of
the transformer. Measure the positive peak voltage V, and the
frequency fin, recording these values in Table 6-1.
On Channel 2, you should see the same waveform at point
B, but it should be positively clamped near zero volts and the
positive peak voltage should be nearly twice that of the trans-
former’s secondary voltage. Measure this peak voltage, V,, and
record this value in Table 6-1.
4. Now take the Channel 1 probe and connect it to the 10-kO load
resistor (point C). You should see two signals similar to those
shown in Figure 6-2. Measure the de voltage Vpc across the
10-kQ resistor with a VOM or DMM, and record this value in

60
 117 VAC

CH
Oscilloscope
CH |

1N4001

aA

117 VAC 7

CHEZ
Oscilloscope
CH I

B.

FIGURE 6-1 Schematic diagram of circuits.

Point C

Point B

FIGURE 6-2

61
 Table 6-1. You should have measured a dc voltage that is nearly
twice that of the transformer’s peak secondary voltage, less two
diode voltage drops.
5. Now switch Channel 1 to ac coupling, and increase the sensi-
tivity to 0.05 V/division to display adequately the output ripple
voltage. Measure both the peak-to-peak ripple voltage and the
ripple frequency. Record both values in Table 6-1. You should
find that both the ripple frequency and the input power line
frequency are the same.
6. Disconnect the power line voltage from the transformer, and
wire the full-wave diode voltage doubler shown in the schematic
diagram of Figure 6—-1B.
7. Set your oscilloscope to the following approximate settings:
Channels 1 and 2: 5 V/division, de coupling
Time base: 2 ms/division
Apply the 117-V rms ac, 60-Hz power line voltage to the trans-
former’s primary.
8. You should see two sine waves on the oscilloscope’s display. On
Channel 1 at point A, you should see the transformer’s sec-
ondary voltage positively clamped near zero volts. Measure its
positive peak voltage V, and its frequency fin, recording these
values in Table 6-2. Measure the de voltage Va. across the 10-
k© resistor with a VOM or DMM, and record this value in Table
6—2. You should have measured a de voltage that is nearly twice
that of the transformer’s peak secondary voltage, less two diode
voltage drops.
9. Now switch Channel 2 to ac coupling and increase the sensi-
tivity to 0.05 V/division to display adequately the output ripple
voltage. Measure both the peak-to-peak ripple voltage and the
ripple frequency. Record both values in Table 6—2. You should
find that the ripple frequency is twice that of the power line
input and that the peak-to-peak ripple voltage is smaller than
that of the half-wave doubler circuit using the same capacitor
and resistor values. These differences occur because the capac-
itors are charged and partially discharged twice as fast as they
are in a half-wave doubler.

WHAT YOU HAVE DONE

This experiment demonstrated the operation of half-wave and full-

wave diode voltage doublers. The half-wave doubler was actually
a positive clamper circuit followed by a half-wave rectifier with a
capacitor input filter acting as peak detector. For the same filter
RC time constant, the peak-to-peak ripple voltage of the full-wave
62 doubler is smaller than the half-wave circuit.
INA Ce
ee ee Date

THE DIODE VOLTAGE DOUBLER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

63
© 1996 Prentice-Hall, Inc. All rights reserved.
 Name Date

DATA FOR EXPERIMENT 6

TABLE 6-1 Half-wave diode voltage doubler.

Parameter Measured Value

Vv, Vv

fics Hz

V, V

Vie V

feels lala

Vero V

TABLE 6—2 Full-wave diode voltage doubler.

Parameter Measured Value

Ve V
|
fin lil

Vie V

nae Hz

Vises Vv

64 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 6

il, For the half-wave voltage doubler of Figure 6-1A, the output
ripple frequency is
(a) one-half the input frequency
(b) the same as the input frequency
(c) twice the input frequency
For the full-wave voltage doubler of Figure 6—-1B, the output
ripple frequency is
(a) one-half the input frequency
(b) the same as the input frequency
(c) twice the input frequency
If the peak input voltage is 10 V, then the peak inverse voltage
of both diodes of a half-wave voltage doubler is
(a) 5V (b) 10 V (c) 20.V (d) 40 V
If the peak input voltage is 10 V, then the peak inverse voltage
of both diodes of a full-wave voltage doubler is
(a) 5V (b) 10 V (c) 20 V (d) 40 V
For the half-wave voltage doubler of Figure 6—1A, the capacitor
and diode arrangement between points A and Bisa
(a) peak detector (b) negative limiter
(c) positive clamper (d) negative clamper

© 1996 Prentice-Hall, Inc. All rights reserved. 65

 NOTES

66
 THE ZENER DIODE AND
VOLTAGE REGULATION

PURPOSE AND BACKGROUND

The purposes of this experiment are to demonstrate (1) the charac-

teristics of azener diode and (2) its use as a simple voltage regulator.
Unlike rectifier diodes, zener diodes are normally reverse biased, so
they maintain a constant voltage across their terminals over a spec-
ified range of current. Like a rectifier diode, a zener diode can be
approximated by a constant de voltage source in series with a re-
sistor. When used as a regulator, the zener diode maintains a dc
output voltage that is essentially constant even though the load
current may vary.
Text References: 3-1, Zener Diodes; 3—2, Zener Diode Appli-
cations.

REQUIRED PARTS AND EQUIPMENT

Resistors: _] Signal generator

100 0, 1/4 W _] Two DMMs (preferred) or
eet wo 220) (e727 W VOMs
[] 1N753,.6.2-V, 400-mW ] Dual trace oscilloscope
zener diode Breadboarding socket
LJ 0-15 de power supply 67
 USEFUL FORMULAS

Maximum limiting series resistance

(1) R,(max) = Vintmin) ~ Vout

T,,(max)
Output voltage
(2A Vee (ideal)
(3) Vou = Vz + IzRz (actual)
where Iz = zener diode current
Rz = zener diode internal resistance = AVz/AlIz
Zener diode current
(A lz = io ly
Source current
Vin — Vout
Gy ) iis = ee Rs

Zener diode power dissipation

(6) Pz = IzVz
Percent load regulation

(7) GVR = WET VEL x 100%

FL
where Vy; = no-load (open circuit) output voltage
Ve, = full-load output voltage
Output ripple voltage

(8) V,(ripple) = Ri ||\Rz |

Vin(ripple)
Rs + (R7\|Rz)

PROCEDURE

1. Wire the circuit shown in the schematic diagram of Figure

7-1A (p. 60).
2. Increase the de supply voltage in small steps while simulta-
neously measuring the voltage across (Vz) and the current
through ([z ) the zener diode. In the vicinity of the zener’s knee
voltage (approximately 6 V), make these steps approximately
0.05 V. Do not exceed a zener current of 40 mA. Record your
data in Table 7—1A, and plot your results for the correspond-
ing zener current and voltage values on the graph provided

68
 100

FIGURE 7-1 Schematic diagram of circuits.

for this purpose. What do you notice about the current-voltage

curve for the zener diode?
Note that initially, the zener diode current is essentially
zero for diode voltages less than the knee voltage. You should
find that as the voltage drop approaches the diode’s knee volt-
age, the diode’s current increases rapidly, while, at the same
time, the voltage stays essentially constant. Consequently, the
zener diode maintains an essentially constant voltage drop
when it is sufficiently reverse biased.
The 1N753 diode is rated at 6.2 V with a tolerance of 10%.
From your graph, determine the voltage across the zener diode
at a current of approximately 20 mA. Within 10%, your value
 should be 6.2 V. Record the measured zener voltage in Table
7-1B.
Determine the internal resistance Rz of your 1N753 zener
diode from your data by taking the change in zener voltage,
AVz, divided by the corresponding change in current, Alz. Do
this calculation only on the straight-line breakdown region of
your diode curve that you plotted in Step 2. Record your result
for the internal zener resistance in Table 7—1B.
Now wire the circuit shown in the schematic diagram of Figure
7-1B.
Apply dc voltage (Vi,) to the breadboard. Measure the source
current (Is), zener current (Iz), load current (I, ), and full-load
output voltage Vp_, recording your values in Table 7—2A. Using
the zener voltage and the internal zener resistance calculated
in Steps 2 and 3, compare the measured output voltage with
the expected value (Equation 3).
Now disconnect the 220-Q load resistor. Measure the source
current (Js), zener current (Iz), and output voltage with no
load Vyz, recording your values in Table 7—2B. Using the zener
voltage and the internal zener resistance determined in Steps
2 and 3, compare the measured no-load output voltage with
the expected value.
For this circuit, determine the percent load regulation, and
record your result in Table 7—2B.
Now add a signal generator in series with the de voltage source
as shown in Figure 7—1C. Adjust the output of the signal gen-
erator at 0.5 V peak-to-peak with a frequency of 1 kHz.
With your oscilloscope at point A, observe both the de and the
ac voltage levels, using your oscilloscope set on dc coupling.
You should see a 0.5 V peak-to-peak sine wave superimposed
on a 15-V dc level above ground.
10. With your oscilloscope at point B, measure the dc output volt-
age of the zener diode regulator, recording your value in Table
7—2B. At this point you should see virtually no ripple voltage
on the regulator’s output signal. How does this voltage com-
pare with that measured in Step 5?
11. Now set your oscilloscope to ac coupling and increase its sen-
sitivity to 5 mV/division. You should now observe a sine wave
ripple signal, but now much smaller than the 500-mV input
ripple voltage. Measure the output peak-to-peak ripple voltage
and compare it with the expected value (Equation 8), recording
your results in Table 7—2B.
Notice that the zener diode regulator provides a relatively
constant output voltage as long as the input voltage is greater
than the zener’s knee voltage. If there is any voltage varia-
tion or ripple on the input voltage signal, the output remains
essentially constant.
70
WHAT YOU HAVE DONE

This experiment demonstrated the characteristics of a 6.2-V zener

diode. The zener diode is normally reverse biased so that it main-
tains a constant voltage between its anode and cathode terminals
over a specified range of current. This experiment demonstrated the
concept of voltage regulation where the output voltage remained es-
sentially constant with changes in load current.

71
 NOTES

72
Name Date

THE ZENER DIODE AND VOLTAGE REGULATION

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 73

 Name Date

DATA FOR EXPERIMENT 7

TABLE 7-1 Zener diode characteristic curve.

A.

Zener Voltage, Zener Current,

Vz (V) Tz (mA)
|

=
|

Ie

lk

B.

Zener knee voltage Vv

(@ Iz = 20 mA

Internal zener resistance Q)

4

74 © 1996 Prentice-Hall, Inc. Alll rights reserved.

Name __ wee ; es Date

TABLE 7-2 Zener diode voltage regulator.

A. Full-load data

Measured Value | Expected Value | % Error

Eira
B. No-load data

Measured Value | Expected Value

% load regulation,
IVR

de input voltage,
Vin (dc)
-_
ac input ripple
voltage, V,, (ripple),
peak-to-peak

de output voltage,
V, (de)

ac output ripple we
voltage, V, (ripple),
peak-to-peak

© 1996 Prentice-Hall, Inc. All rights reserved. 75

 NOTES

76
INSMe eee ee SE ne Date

DATA FOR EXPERIMENT 7

© 1996 Prentice-Hall, Inc. All rights reserved. 77

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 7

Ly From your data, the zener voltage for the zener diode used in
this experiment is approximately
(a) 0.3 V (b) 0.7 V (ce Gay. (d) 10 V
For which portion of the diode curve does the zener diode look
like an open circuit?
(a) Diode voltages less than the zener voltage.
(b) Diode voltages greater than the zener voltage.
For the circuit of Figure 7—1B, if the input voltage is less than
6 V, the output voltage is
(a) OV (b) 6 V (c) the same as the input
If the load resistor of Figure 7—1B is disconnected, the current
through the zener diode is approximately
(a) OmA (b) 10 mA (c) 20 mA (d) 40 mA
The power dissipated by the zener diode for the circuit of Figure
7—1B is greatest when
(a) the zener diode is shorted
(b) the load resistor is removed
(c) the load resistor is shorted
(d) the input voltage is increased ( )

78 © 1996 Prentice-Hall, Inc. All rights reserved.

 USING AN OHMMETER TO
TEST TRANSISTOR DIODE
JUNCTIONS

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate how to test npn

and pnp transistors using an ohmmeter. Since a transistor can be
represented internally by two diode junctions, an ohmmeter can be
used to check each diode junction, as was done in Experiment 1.
Thus, there is a simple test for open or shorted diode junctions. If
the three terminals are known, then it is possible to determine if a
giveng transistor is npn or pnp.
Text Reference: 4—7, Troubleshooting.

REQUIRED PARTS AND EQUIPMENT

1N914 (or 1N4148) diode VOM

2N3904 npn transistor Breadboarding socket
2N3906 pnp transistor (optional)

79
PROCEDURE

1. Often one can use a VOM to check quickly whether a diode

is good or bad. Unless they have a specific function for this
purpose, most DMMs are usually not able to perform this test
properly. When VOMs are used to measure resistances, the po-
larities of their leads are sometimes reversed from the normal
sense. That is, the positive lead is actually wired to the nega-
tive terminal of the internal battery. In this case, the forward
and reverse resistance readings will be the opposite of those in-
dicated in these two steps. When this type of VOM functions as
a voltmeter or an ammeter, its leads are internally connected
in the normal sense.
In order to determine the polarity of your ohmmeter’s
leads, perform a simple test first on a 1N914 diode. Set the
ohmmeter’s resistance range switch to a low range, such as the
“R x 100” range, and then place one meter lead on the diode’s
anode lead and the other meter lead on the diode’s cathode
lead. Note whether the resistance reading is high or low. Then
reverse the leads and note if the resistance reading is higher
or lower than the first reading.
The placement of the ohmmeter’s leads that results in the
lower resistance reading is the arrangement that forward bi-
ases the diode. The lead that was connected to the diode’s anode
lead is the ohmmeter’s positive (+) lead. Conversely, the lead
that was connected to the diode’s cathode is the negative (—)
lead. In the following steps, we will refer to the ohmmeter’s
positive and negative leads as determined by this method, re-
gardless of how the leads are actually labeled on the ohmmeter.
It is very important to have this new convention in mind so
that you will be able to test a transistor properly in the follow-
ing steps. Thus, the internal circuit of the ohmmeter can be
represented by the circuit of Figure 8-1.

+ Lead (c

Ohmmeter B

— Lead es)

A. 2N3904/2N3906
(bottom view)

FIGURE 8-1 Schematic diagram ofcircuit.

 B

——
C.
B

FIGURE 8-2
4 Je

Pin configuration of 2N3904 and 2N3906 transistors.

If a DMM having a “diode check” feature is used, the dis-

play usually indicates the voltage drop across a good diode from
anode to cathode when it is forward biased. When reverse bi-
ased, the DMM generally indicates some form of out-of-range
condition, such as a blinking display or the letters “OL.”
Using a 2N3904 npn transistor, whose schematic diagram and
diode junction representation are shown in Figure 8—2B, con-
nect the ohmmeter’s positive lead to the transistor’s base lead,
with the ohmmeter’s negative lead connected to the transis-
tor’s emitter lead. In this manner, you have forward biased the
transistor’s base-emitter diode junction.
Note whether the reading is at the high end or the low end
of the meter’s scale. Record your result in Table 8-1 as either
“high” or “low.”
Reverse the meter’s leads so that the positive lead is connected
to the emitter and the negative lead is connected to the base.
Note the meter reading, and record either a “high” or a “low”
result in Table 8-1.
Now connect the meter’s positive lead to the base and the neg-
ative lead to the transistor’s collector lead. Note whether the
reading is at the high end or the low end of the meter’s scale.
Record your result in Table 8-1 as either “high” or “low.”
Reverse the meter’s leads so that the positive lead is connected
to the collector and the negative lead is connected to the base.
Note the meter reading, and record either a “high” or a “low”
result in Table 8-1.
The base-emitter diode junction was forward biased in Step
2 and reverse biased in Step 3. If this junction is good, then
you should have obtained a low reading in Step 2 and a high
reading in Step 3.
81
 The base-collector diode junction was forward biased in Step
4 and reverse biased in Step 5. If this junction is good, then you
should have obtained a low reading in Step 4 and a high reading
in Step 5. By examining the diode junction representation for
an npn transistor shown in Figure 8—2B, you should be able to
understand the operation of Steps 2 through 5.
Now connect the meter’s positive lead to the collector and the
negative lead to the transistor’s emitter lead. Note the ohmme-
ter reading, and record this value in Table 8—1. Now reverse
the meter’s leads so that the positive lead is connected to the
emitter and the negative lead is connected to the collector. Note
the meter reading, and record this value in Table 8-1.
If the transistor is good, both readings should be virtually
the same, namely, an infinite resistance. As neither of the two
diodes between the collector and emitter leads is forward or
reverse biased simultaneously, the result is basically an open
circuit. Such a test of the collector-emitter junction is used to
detect what is sometimes referred to as a “puncture short,”
which would result in a low-resistance path between the col-
lector and emitter leads.
Using a 2N3906 pnp transistor, whose schematic diagram and
diode junction representation are shown in Figure 8—2C, con-
nect the ohmmeter’s positive lead to the transistor’s base lead,
with the ohmmeter’s negative lead connected to the transis-
tor’s emitter lead. Note whether the reading is at the high end
or the low end of the meter’s scale. Record your result in Table
8-2 as either “high” or “low.”
Reverse the meter’s leads so that the positive lead is connected
to the emitter and the negative lead is connected to the base.
Note the meter reading, and record either a “high” or a “low”
result in Table 8-2.
10. Now connect the meter’s positive lead to the base and the neg-
ative lead to the transistor’s collector lead. Note whether the
reading is at the high end or the low end of the meter’s scale.
Record your result in Table 8—2 as either “high” or “low.”
11. Reverse the meter’s leads so that the positive lead is connected
to the collector and the negative lead is connected to the base.
Note the meter reading, and record either a “high” or a “low”
result in Table 8-2.
12. As in Step 7, connect the meter’s positive lead to the collector
and the negative lead to the transistor’s emitter lead. Note the
ohmmeter reading, and record this value in Table 8—2. Now re-
verse the meter’s leads so that the positive lead is connected to
the emitter and the negative lead is connected to the collector.
Note the meter reading, and record this value in Table 8-2.

82
 If the transistor is good, both readings should be virtually
the same, namely, an infinite resistance. As neither of the two
diodes between the collector and emitter leads is forward or
reverse biased simultaneously, the result is basically an open
circuit.
13. Compare the results of Tables 8-1 and 8-2. Note that if both
transistors are good, npn and pnp transistors have opposite
results. The base-emitter diode junction was forward biased in
Step 9 and reverse biased in Step 8. If this junction is good,
then you should have obtained a low reading in Step 9 and a
high reading in Step 8.
The base-collector diode junction was forward biased in Step
11 and reverse biased in Step 10. If this junction is good, then you
should have obtained a low reading in Step 11 anda high reading
in Step 10. By examining the diode junction representation for
a pnp transistor shown in Figure 8—2C, you should be able to
understand the operation of Steps 8 through 12.

WHAT YOU HAVE DONE

This experiment demonstrated how to properly test npn and pnp

transistors using either a VOM or DMM. This is because a transistor
can be represented internally by two diode junctions.

83
 NOTES

84
Name Date

USING AN OHMMETER TO TEST TRANSISTOR

DIODE JUNCTIONS

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 85

INET Cee Date

DATA FOR EXPERIMENT 8

TABLE 8-1 2N3904 NPN transistor.

——-T

Ohmmeter Leads |
Step
Number Result

Emitter

Emitter

4 Base Collector

5 Collector Base

a Collector Emitter

g | Emitter Collector

TABLE 8—2 2N3906 PNP transistor.

Ohmmeter Leads
Step
Number + Result
ee las

9 Emitter Base
p=
10 Base Collector

11 Collector Base

12 Collector Emitter

IZ Emitter Collector

86 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 8

UU An ohmmeter reads a low resistance when its negative lead

is connected to a pnp transistor’s base lead, with the meter’s
positive lead connected to the collector. The transistor junction
is then
(a) forward biased (b) reverse biased
(c) open (d) shorted
An ohmmeter reads an infinite resistance when its positive lead
is connected to an npn transistor’s base lead, with the meter’s
negative lead connected to the emitter. The transistor junction
is then
(a) forward biased (b) reverse biased
(c) open (d) shorted
An ohmmeter reads zero resistance when its negative lead is
connected to an npn transistor’s base lead, with the meter’s
positive lead connected to the collector. The transistor junction
is then
(a) forward biased (b) reverse biased
(c) open (d) shorted
An ohmmeter reads a high resistance when its positive lead is
connected to a transistor’s base lead, with the meter’s negative
lead connected to the emitter or the collector leads. The tran-
sistor is then
(a) forward biased (b) reverse biased
(c) an npn type (d) a pnp type

© 1996 Prentice-Hall, Inc. All rights reserved. 87

 NOTES

88
 TRANSISTOR BASE BIASING

PURPOSE AND BACKGROUND

The purpose of this experiment is to verify the voltages and cur-

rents in a base-biased circuit as well as to construct its de load line.
In spite of its simplicity, a base-biased circuit does not effectively
stabilize a transistor’s quiescent point. Consequently, the Q point is
affected by the transistor’s current gain (f).
Text References: 5-1, The DC Operating Point; 5—2, Base Bias.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 0-15 V de power supply

1kD [|] VOM or DMM (preferred)
560 kQ Breadboarding socket
1 MQ) potentiometer
Two 2N3904 npn silicon
transistors

89
 USEFUL FORMULAS

Quiescent dc base voltage

(1) Vp = Voc —IpRhp = VBE

Quiescent dc collector (emitter) current

(2) Ic= VocRa/B

— Ver
B

Quiescent dc base current

Oi ee VBE
B
Quiescent dc collector-to-emitter voltage
(4) Ver = Voc —IcRc
dc load line

(5) Lets = Veo (saturation)

Rc
(6) Verwm = Vec (cutoff)
In general, make
(7) Voc > Ver

PROCEDURE

Wire the circuit shown in the schematic diagram of Figure 9-1,

and apply power to the breadboard.
With your VOM or DMM, measure the voltage across the base
and collector resistors, and, using Ohm’s law, determine the
corresponding currents, recording your values in Table 9-1.
From these two sets of values, determine the de current gain
or beta (Ba-) for this transistor so that

Bae >
Ie
Tp
Record this value of beta in Table 9-1.
Use your VOM or DMM to measure individually Vg and Vor.
Record your results in Table 9-1.
Compare the values of Step 3 with the expected values, using
the value of Ba. determined in Step 2 and a typical base-emitter
voltage of 0.7 V. Record these values in Table 9-1.
Now use a hand-held hair dryer to blow hot air against the
transistor’s case for a few seconds while measuring the
90
 == 1S)W

Rp 1kQ
560 kO

Vp 2N3904

FIGURE 9-1 Schematic diagram of circuit.

collector current using your VOM or DMM. Does the collector

current increase or decrease?
You should find that the collector current increases, which
in turn causes the circuit’s Q point to change.
Using Equations 5 and 6 in the “Useful Formulas” section of
this experiment, determine the saturation and cutoff points on
the dc load line for this circuit, and record these values in Table
9-2. On the blank graph provided, plot the dc load line, using
the calculated values of Iisa) and Vegiorp) as the endpoints of
the load line. Now plot the Q point based on the measured
values of Ic and Vog on the same graph. What do you notice
about the Q point?
You should find that the measured Q point lies essentially
on the dc load line.
Using a different 2N3904 transistor, repeat Steps 2 through 5,
and record your results in Table 9-1. Do you find any differ-
ences between the two transistors?
You will usually find that the two transistors give different
values for the quiescent voltages and currents. In addition, you
will usually find differences in the de current gains.
Disconnect the power from the breadboard and replace the
560-k0 resistor (Rg) with a 1-MQ potentiometer. Again apply
power to the breadboard and connect a voltmeter between the
transistor’s collector terminal and ground.
Now vary the resistance of the potentiometer until Vog as read
by the voltmeter reaches a minimum value, Vogisat). Then mea-
sure the corresponding collector current, Ic(sat). Record both
values in Table 9-2.
10. Continue to vary the resistance of the 1-MQ potentiometer un-
til Vor reaches a maximum value, Vogiom). Then measure the
91
 corresponding collector current I¢(off). If the collector current
is not essentially zero, then temporarily disconnect one lead of
the potentiometer from the circuit so that the base current is
zero. The collector current should also be zero. Measure the
corresponding collector-emitter voltage, Voegjor. Record both
I cvoft) and VoE (off) in Table 9-2.
At saturation, Vogisat) is ideally zero, while at cutoff, Icyo¢p)
is zero. Plot the values for Jc and Vor at cutoff and saturation
on the graph constructed in Step 6. You should find that both
points lie essentially on the dc load line very close to the ideal
endpoints of cutoff and saturation.
11. If you disconnected the potentiometer in Step 10, reconnect
the potentiometer as in Step 8. Vary the potentiometer so that
you are able to measure about five combinations of Ic and Veg
over the active region of the dc loan line, recording all values
in Table 9-2. Then plot these values on the graph. As in Step
10, each point should lie essentially on the dc load line, as the
load line is a plot of all possible combinations of Jc and Vor.

WHAT YOU HAVE DONE

This experiment verified the voltages and currents in a base-biased

circuit as well as constructing the de load line for the circuit. In
addition, the effect of temperature on the stability of the bias circuit
was also demonstrated.

92
Name Date

TRANSISTOR BASE BIASING

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved.

93
Name Date
DATA FOR EXPERIMENT 9

TABLE 9-1

Transistor 1 Transistor 2

Measured Expected Measured Expected

Parameter Value Value Value Value

ifaw

Ic

Bac

V, Mg AE OL WY
a (typical) (typical)

Vor

TABLE 9-2

Calculated Values Measured Values

Condition Ic Vor Ic Vor

I Saturation
(Step 9)

Cutoff
(Step 10)

Active |
Region
(Step 11)

© 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

DATA FOR EXPERIMENT 9

© 1996 Prentice-Hall, Inc. All rights reserved. 95

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 9

1. For the circuit of Figure 9-1, if 8B= 150, then Jz is

(a) 10 pA (b) 15 pA
(c) 20 pA (d) 25 wA
If 6 of the transistor in the circuit of Figure 9-1 increases, then
(a) Jp decreases (b) Ic increases
(c) Vor decreases (d) all of the above
If Rg is made smaller in the circuit of Figure 9-1, then
(a) Ip decreases (b) Ic increases
(c) Vor decreases (d) all of the above
The collector saturation current for the circuit of Figure 9-1 is
approximately
(a) 4mA (b) 6 mA (c) 10 mA (d) 15 mA
At cutoff, the collector-to-emitter voltage for the circuit of Figure
9-1 is
(a) 5 V (b) 7.5 V (c) 10 V (d) 15 V ( )

96 © 1996 Prentice-Hall, Inc. All rights reserved.

TRANSISTOR EMITTER BIASING
10

PURPOSE AND BACKGROUND

The purpose of this experiment is to verify the voltages and currents

in an emitter-biased circuit as well as to construct its de load line.
Unlike other biasing schemes, emitter bias uses both a positive and
a negative supply voltage. In this manner, the base is approximately
at ground while the negative emitter supply voltage forward biases
the base-emitter junction.
Text References: 5-1, The DC Operating Point; 5-3, Emitter
Bias.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): Two 0-15 V de power

Two 1 kD supplies
Bese VOM or DMM (preferred)
Two 2N3904 npn silicon Breadboarding socket
transistors

97
 USEFUL FORMULAS

Quiescent dc emitter voltage

(1) Ve = Ver — Ver
Quiescent dc base voltage
(2).V5 = Vane = lpltpe— Ven
Quiescent dc collector (emitter) current

(3) Ic =
Veg — Vee (Ic =Ig for large B)
Re + (Rp/B)
Quiescent dc base current

(4) Ip = i EN
Rp BRe + Rp

Quiescent dc collector-to-emitter voltage

(5) Ver = Vec —Ichc + Vez
dc load line

(6) Leésat) = Voc

+ Ver (saturation)
Rco+Re
(7) Verwr = Veco + Veg (cutoff)
In general, make

(8) Re > Rp
B
(9) Ver > VBE

PROCEDURE

1. Wire the circuit shown in the schematic diagram of Figure 10-1,

and apply power to the breadboard.
2. With your VOM or DMM, measure the base, emitter and collec-
tor voltages, with respect to ground, and measure the base and
collector currents, recording your values in Table 10—1. From
these two sets of values, determine the de current gain, or beta
(B), for this transistor so that

Bac =
Ne
Ip
Record this value of de beta in Table 10-1.

98
 ar ISSWY

2N3904

FIGURE 10-1 Schematic diagram of circuit.

Then measure Vog, and record your results in Table 10-1.

Compare these values and those of Steps 2 and 3 with the ex-
pected values, using the value of beta determined in Step 2 and
a typical base-emitter voltage of 0.7 V. Record these values in
Table 10-1.
Now use a hand-held hair dryer to blow hot air against the
transistor’s case for a few seconds while measuring the emitter
current using your VOM or DMM. Does the emitter current
increase or decrease?
You should find that the emitter current increases, which
in turn causes the circuit’s Q point to change.
Using Equations 6 and 7 in the “Useful Formulas” section of
this experiment, determine the saturation and cutoff points on
the dc load line for this circuit, and record these values in Table
10—2. On the blank graph provided, plot the dc load line, using
the calculated values of J¢jsat) and Vogiofp) as the endpoints of the
load line. Now plot the Q point based on the measured values
of Ic and Veg on the same graph. What do you notice about the
Q point?
You should find that the measured Q point les essentially
on the dc load line.
Using a different 2N3904 transistor, repeat Steps 2 through 5,
and record your results in Table 10-1. Do you find any differ-
ences between the two transistors?
You will usually find that the two transistors give different
values for the quiescent voltages and currents. In addition, you
will usually find differences in the current gains.

99
 WHAT YOU HAVE DONE

This experiment verified the voltages and currents in an emitter-

biased circuit using two power supplies as well as constructing the
dc load line for the circuit. In addition, the effect of temperature on
the stability of the bias circuit was also demonstrated.

100
ANT ea Nd i Date

TRANSISTOR EMITTER BIASING

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 101

 Name Date

DATA FOR EXPERIMENT 10

TABLE 10-1

Transistor 1 Transistor 2

Measured Expected Measured Expected

Parameter Value Value Value Value

Ic

Tp
L
Bac

Vp

Ve

Ve

Vcr

TABLE 10-2

Parameter Calculated Value

VoR (off) V

I Cisat) mA

1 02 ۩) 1996 Prentice-Hall, Inc. All rights reserved.

INS
IN 6 ee ee ee ee ee Cee ee ee Date

DATA FOR EXPERIMENT 10

© 1996 Prentice-Hall, Inc. All rights reserved. 103

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 10

1. For the circuit of Figure 10-1, if B = 100, then Vc is

(a) 6 V (b) 8V (c) 10 V (d) 15 V ( )
2. If B increases for the transistor of Figure 10-1, then
(a) Ic decreases (b) Vz decreases
(c) Voge decreases (d) all of the above ( )
3. If Rg is made smaller in the circuit of Figure 10-1, then
(a) Ip decreases (b) Ze increases
(c) Vor increases (d) all of the above ( )
4. The collector saturation current for the circuit of Figure 10-1 is
approximately
(a) 4mA (b) 7.5 mA (c) 11.5 mA (d) 23 mA ( )
5. At cutoff, the collector-to-emitter voltage for the circuit of Figure
10-1 is
(a) tow) (b) 8 V (Gc) el 54) (d) 23 V ( )

104 © 1996 Prentice-Hall, Inc. All rights reserved.

 TRANSISTOR VOLTAGE-
11
DIVIDER BIASING

PURPOSE AND BACKGROUND

The purpose of this experiment is to verify the voltages and cur-

rents in a transistor voltage-divider bias circuit as well as to con-
struct the de load line. Voltage-divider bias is often used because
the base current is made small compared to the currents through
the two base (“voltage-divider”) resistors. Consequently, the base
voltage and therefore the collector current are stabilized against
changes in the transistor beta.
Text References: 5-1, The DC Operating Point; 5—4, Voltage-
Divider Bias.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): Two 2N3904 npn silicon

Two 1 kO transistors
Ant kO _] 0-15 V de power supply
10 kO [] VOM or DMM (preferred)
LJ] 10-kQ potentiometer [] Breadboarding socket

105
 USEFUL FORMULAS

Quiescent dc base voltage

(1) Vg = Rg
|——"— Ve
~ a = = of

Quiescent dc emitter voltage

(2) Ve = Vp = VaR

Quiescent dc collector (emitter) current

(3)Ic=—V; (Uc = Iz for large B)

Re
Quiescent collector voltage
(4) Ve = Voce — Ichc¢
Quiescent dc collector-to-emitter voltage
(5) Ver = Vec —Ic(Re + Re) = Vo — Ve
dc load line

(©) teas) = Voc (saturation)

Rc t+Re

(7) Vororry = Vec (cutoff)

In general, make
(8) Ry ||Ro < BRe

PROCEDURE

1. Using a typical value for the base-emitter voltage of a silicon

transistor (0.7 V), calculate the expected values of the quies-
cent dc base voltage (Vg), emitter voltage (Vz), collector voltage
(Vc), and collector-emitter voltage (Vcr) for the voltage-divider
bias circuit shown in the schematic diagram of Figure 11-1.
Record these values in Table 11-1.
2. Now wire the circuit shown in the schematic diagram of Figure
11-1, and apply power to the breadboard.
3. Use your VOM or DMM to measure in turn Vz, Vo, Ve, and Vor.
Record your results in Table 11-1, comparing these measured
values with the expected voltages determined in Step 1. Your
results should agree within 10 percent.
4. Now measure the quiescent collector current and compare this
value with the expected value (Equation 3). Record this value
in Table 11-1.

106
 +15 V

R, Re
10k 1kO

Ve

Va 2N3904

Ve
R, Re
4.7kQ 1k

FIGURE 11-1 Schematic diagram of circuit.

5. Now use a hand-held hair dryer to blow hot air against the
transistor’s case for a few seconds while measuring the col-
lector current using your VOM or DMM. Does the collector
current increase or decrease?
You should find that there is very little change in the col-
lector current, or that the change is not as fast or as great as is
obtained with a circuit using base biasing. The well-designed
voltage-divider bias circuit makes the Q point essentially in-
dependent of transistor beta.
Using Equations 6 and 7 in the “Useful Formulas” section of
this experiment, determine the saturation and cutoff points
on the dc load line for this circuit, and record these values in
Table 11-2. On the graph provided, plot the dc load line, us-
ing the calculated values of I¢isat) and Vogiop) as the endpoints
of the load line. On the same graph, plot the Q point based on
the measured values of Jc and Vog. What do you notice about
the Q point?
You should find that the measured Q point lies essentially
on the dc load line.
Using a different 2N3904 transistor, repeat Steps 3 through 6,
recording your results in Table 11-1. Do you find any differ-
ences between the two transistors?
You should find that there are essentially no differences in
the measured values, as the voltage-divider bias circuit basi-
cally makes the circuit’s quiescent voltages and current inde-
pendent of beta.
Using transistor #2, disconnect power from the breadboard
and replace resistors R; and R2 with a 10-k) potentiometer,
as shown in Figure 11-2.

107
 sil)NY

10 kQ 2N3904

Ry
il 1kQ

FIGURE 11-2 Schematic diagram from Step 8.

Connect the power to the breadboard and connect a voltmeter

between the transistor’s collector and emitter terminals. Slowly
vary the 10-kQ potentiometer until Vog as read by the volt-
meter reaches a minimum value, Vog;sat). Then measure the
corresponding collector current, I¢(sat). Record both values in
Table 11-2.
10. Continue to vary the resistance of the 10-kQ potentiometer
until Vog reaches a maximum value, Vogiom). Then measure
the corresponding collector current, Icio¢). Record both Icom)
and Vogior) in Table 11-2.
At saturation, Vogisat) 18 ideally zero, while at cutoff, Icio
is zero. Plot the values for Jc and Vor at cutoff and saturation
on the graph constructed in Step 6. You should find that both
points le essentially on the dc load line very close to the ideal
endpoints of cutoff and saturation.
11. Vary the potentiometer so that you are able to measure about
five combinations of Jc and Vog over the active region of the de
load line, recording all values in Table 11-2. Then plot these
values on the graph. As in Step 10, each point should lie es-
sentially on the dc load line, as the load line is a plot of all
possible combinations of Jc and Vor.

WHAT YOU HAVE DONE

This experiment verified the voltages and currents in a voltage

divider-biased circuit as well as constructing the dc load line for
the circuit. In addition, the effect of temperature on the stability of
the bias circuit was also demonstrated.
108
Name Date

TRANSISTOR VOLTAGE DIVIDER BIASING

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 109

Name Date

DATA FOR EXPERIMENT 11

TABLE 11-1

Measured Values

Parameter Transistor 1 Transistor 2 Expected Value

Vp

Ic

TABLE 11-2

Calculated Values Measured Values

Condition Ic Vcr Ic Vor

Saturation |
(Step 9)

Cutoff
(Step 10) [

Active
Region
(Step 11)

110 © 1996 Prentice-Hall, Inc. All rights reserved.

Name __ ee. eee
ee Date

DATA FOR EXPERIMENT 11

© 1996 Prentice-Hall, Inc. All rights reserved. 111

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 11

1. For the circuit of Figure 11—1, /¢ is approximately

(a) 2mA (b) 4mA (c) 6mA (d) 7.5 mA ( )
2. For the transistor in the circuit of Figure 11-1, if B increases,
Vp will
(a) decrease (b) increase
(c) remain essentially the same ( )
3. If Re is increased, then
(a) Vp decreases (b) Ic decreases
(c) Vor increases (d) Vo decreases ( )
4. The collector saturation current for the circuit of Figure 11—1 is
approximately
(a) 4mA (b) 7.5 mA (c) 10 mA (d) 15 mA ( )
5. At cutoff, the collector-to-emitter voltage for the circuit of Figure
11-1 is
(a) 4V (b) 8V (c) 10 V (dG) $5. Yi ( )

112 © 1996 Prentice-Hall, Inc. Alll rights reserved.

 TRANSISTOR COLLECTOR-
12
FEEDBACK BIASING

PURPOSE AND BACKGROUND

The purpose of this experiment is to verify the voltages and currents

in a collector-feedback bias circuit as well as to construct its dc
load line. This arrangement is different from other biasing schemes
in that the collector voltage provides the bias for the base-emitter
junction. The result is a very stable Q point, which reduces the
effects of transistor beta.
Text References: 5-1, The DC Operating Point; 5—5 Collector-
Feedback Bias.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 0-15 V de power supply

ie 27k) VOM or DMM (preferred)
[] 560 kQO |] Breadboarding socket
Two 2N3904 npn silicon
transistors

113
 USEFUL FORMULAS

Quiescent dc base voltage

(Cl Ve —" Ver

Quiescent de collector (emitter) current

2) 1e= Voo — Vaz

Re x (Rp/B)

Quiescent dc base current

fy) Lee ee
BRc
+ Rp
Quiescent dc collector-to-emitter voltage
(4) Voz = Vec —IcRc
de load line

CS ies) = Vee (saturation)

Rc
(6) VoR (off) = Vec (cutoff)

In general, make

GyRae
B
(8) Veo > Vor

PROCEDURE

1. Wire the circuit shown in the schematic diagram of Figure 12-1,

and apply power to the breadboard.
2. With your VOM or DMM and Ohm’s law, measure the quiescent
base and collector currents, recording your values in Table 12-1.
From these two values, determine the de current gain or de beta
(Ba) for this transistor so that
Ic
Bac ip

Record this value of beta in Table 12-1.

3. Use your VOM or DMM to measure individually Vg and Vor.
Record your results in Table 12-1.
4. Using the value for de beta determined in Step 2 for both tran-
sistors, and using a typical base-emitter voltage of 0.7 V, cal-
culate the expected values for Jc, Ig, and Vog (Equations 2,
3, and 4). Record your results in Table 12-1. The measured re-
sults should be within approximately 10 percent of the expected
results.
114
 is
2.7kQ

Rp
560 kD
AM Vo

Vp 2N3904

FIGURE 12-1 Schematic diagram of circuit.

5. Now use a hand-held hair dryer to blow hot air against the
transistor’s case for a few seconds while measuring the collector
current using your VOM or DMM. Does the collector current
increase or decrease?
You should find that there is very little change in the col-
lector current, or that the change is not as fast or as great as
is obtained with a circuit using base biasing. A well-designed
collector-feedback bias circuit makes the Q point essentially in-
dependent of transistor beta.
6. Using Equations 5 and 6 in the “Useful Formulas” section of
this experiment, determine the saturation and cutoff points on
the dc load line for this circuit, and record these values in Table
12-2. On the blank graph provided, plot the dc load line, using
the calculated values of I¢sat) and Voxiof) as the endpoints of
the load line. On the same graph, plot the Q point based on the
measured values of Jc and Vcg. What do you notice about the
Q point?
You should find that the measured Q point lies essentially
on the dc load line.
7. Using a different 2N3904 transistor, repeat Steps 2 through 5,
and record your results in Tables 12-1 and 12-2. Do you find
any differences between the two transistors?

WHAT YOU HAVE DONE

This experiment verified the voltages and currents in a collector-

feedback biased circuit as well as constructing the dc load line for
the circuit. In addition, the effect of temperature on the stability of
the bias circuit was also demonstrated.
115
 NOTES

116
Name

TRANSISTOR COLLECTOR-FEEDBACK BIASING

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 117

 Name Date

DATA FOR EXPERIMENT 12

TABLE 12-1

| Transistor 1 Transistor 2

Parameter Measured Expected Measured Expected

—" I¢

Bac

Va 0.7 Vv 0.7 Vv
(typical) (typical)

Vcr |

TABLE 12-2

Parameter |Expected Value

Lc(sat) mA

Vervoft) Vv

118 © 1996 Prentice-Hall, Inc. All rights reserved.

NAM 6 eee
NR eS Date

DATA FOR EXPERIMENT 12

© 1996 Prentice-Hall, Inc. All rights reserved. 119

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 12

1. For the circuit of Figure 12-1, if 8B= 200, then J¢ is approxi-

mately
(a) 2.2 mA (b) 3.9 mA
(c) 4.8 mA (d) 14.3 mA
In the circuit of Figure 12-1, if 8 of the transistor increases,
then
(a) Ip decreases (b) IJc@ increases (c) Vor increases
(d) all of the above
The collector saturation current for the circuit of Figure 12-1 is
approximately
(a) 4mA (b) 6mA (c) 10 mA (d) 15 mA
4. At cutoff, the collector-to-emitter voltage for the circuit of Figure
12-1 is
(a) 5V (b) 7.5 V (c) 10 V (d) 15 V ( )

120 © 1996 Prentice-Hall, Inc. All rights reserved.

 THE COMMON-EMITTER
13
AMPLIFIER

PURPOSE AND BACKGROUND

The purposes of this experiment are to (1) demonstrate the oper-

ation and characteristics of the small-signal common-emitter am-
plifier and (2) investigate what influences its voltage gain. The
common-emitter amplifier is characterized by application of the am-
plifier input signal to the base lead while its output is taken from
the collector, which always gives a 180° phase shift.
Text Reference: 6-3, Common-Emitter Amplifiers.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 (W): 2N3904 npn silicon

aletS0:.0 transistor
(ail 2g) 0-15 V de power supply
Two 3.9 kQ Signal generator
).4.7, kO VOM or DMM (preferred)
10 kO [J Dual trace oscilloscope
Capacitors (25 V): Breadboarding socket
LI Two 2.2 uF
PlLOUE i
121
 USEFUL FORMULAS

Voltage gain from base to collector

Gihyk = eee
Vin

OC) Re | Ra (normal circuit)

Rr cielo

(Ae = Epics? (no load)

Rr Staal

(4) A, = __ Rel Rr __ (no bypass capacitor)

Rr + Reg+ Te

Transistor ac emitter resistance (at normal room temperature)

=, Ae amy
r i

Quiescent dc base voltage

(6) Vp = i =(pee
|——— |]JWec
Ro

Quiescent dc emitter voltage

(1) Ve = Va — Ver
Quiescent dc emitter current

(8) ly = ———
Ve (Ic = Ig for large B)
Rr + Rr
Quiescent dc collector voltage
(9) Ve = Vec —IcRc
Quiescent dc collector-emitter voltage
(10) Voz = Veo —Ic(Rc + Rei + Reo)

PROCEDURE

1. Wire the circuit shown in Figure 13-1, omitting the signal gen-
erator and the power supply.
After you have checked all connections, apply the 15-V supply
voltage the breadboard. With a VOM or DMM, individually mea-
sure the transistor de base, emitter, and collector voltages with
respect to ground, recording your results in Table 13-1. Based
on the resistor values of Figure 13-1, determine the expected
values of these three voltages (Equations 6, 7, and 9), assuming
a base-emitter voltage drop of 0.7 V, and compare them with
122 the measured values in Table 13-1.
 +15V

CH 1
Oscilloscope
CHZ

FIGURE 13-1 Schematic diagram of circuit.

3. Connect Channel 1 of your oscilloscope to point J (vi,) and Chan-

nel 2 to point O (Vout). Then connect the signal generator to the
circuit as shown in Figure 13-1, and adjust the sine wave out-
put level of the generator at 0.2 V peak-to-peak at a frequency
of 5 kHz.
You should observe that the output signal level (Vout) is
greater than the input level (vi,). In addition, voyt is inverted,
or 180° out-of-phase, with respect to the input. These points
are two major characteristics of a common-emitter amplifier. In
order to observe the phase shift, you must display both signals
simultaneously on the oscilloscope; otherwise you will not see
any phase shift.
4. Using the measured value for the de emitter voltage obtained
in Step 2, calculate the de emitter current (Equation 8) and
the resultant transistor ac emitter resistance, r, (Equation 5).
Record these values in Table 13-2.
5. With an oscilloscope, measure the ac peak-to-peak voltage at
the junction of Rg; (150 1) and Reg (2.7 kQ). Even at the os-
cilloscope’s highest input sensitivity, you should measure vir-
tually no ac voltage at this point. The 10-uF bypass capacitor,
in parallel with Rg2, serves essentially as a short-circuit path
to ground since its reactance at 5 kHz is very small compared
with the 2.7-kQ resistance. Consequently, the junction of Rr;
and Rpg is effectively at ac ground.
Measure the ac peak-to-peak voltage at the transistor’s emit-
ter lead. Note that the ac voltage is slightly less than the input 123
 voltage, Vin. In addition, both signals are in-phase. Since Rp; is
used to minimize the temperature effects of r,, an ac voltage
will be present at the emitter terminal, which is approximately
equal to, and in-phase with, the input signal.
6. Calculate the expected voltage gain from base to collector using
Equation 2 given in the “Useful Formulas” section of this ex-
periment and record the value in Table 13-3. Now measure the
actual voltage gain by dividing the peak-to-peak output voltage
Vout by the peak-to-peak input voltage vin, recording your result
in Table 13-3.
7. Now remove R,. You should observe that the output voltage level
increases. It does so because the load resistance affects the volt-
age gain of the amplifier stage. As in Step 6, experimentally
determine the voltage gain by measuring Upyt and vin, compar-
ing your measured result with the expected value (Equation 3).
Record your results in Table 13-3.
8. Reconnect the 3.9-kQ load resistor as in the original circuit of
Figure 13-1. Remove the 10-4F emitter bypass capacitor from
the circuit. You should observe that the output voltage decreases
tremendously. It does so because the total ac emitter resistance
is now Re; +Ree, in addition to the transistor’s internal ac emit-
ter resistance, r,. As in the previous two steps, experimentally
determine the voltage gain by measuring v,,; and vin, compar-
ing your results with the expected value (Equation 4). Record
your results in Table 13-3.
From the results in Table 13-3, you should now understand
how both the emitter bypass capacitor and the load resistance
affect the base-to-collector voltage gain of a common-emitter
amplifier.

WHAT YOU HAVE DONE

This experiment demonstrated the operation and characteristics of

a small-signal common-emitter amplifier, which has a 180° phase
shift. Here, the input signal is applied to the transistor’s base lead,
while the output signal is taken from the collector lead. The ex-
periment also showed how the load resistance and emitter bypass
capacitor each influence the circuit’s voltage gain.

124
IEE aoe ae
<Se DR ee Date

THE COMMON-EMITTER AMPLIFIER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 125

 Name Date

DATA FOR EXPERIMENT 13

TABLE 13-1

Parameter | Measured Value | Expected Value

Vp

TABLE 13-2

TzE (calculated)

r. (calculated)

TABLE 13-3

Measured Expected
Condition é Gain Gain % Error

Normal circuit
(Step 6)

No load (Step 7)

No bypass capacitor
(Step 8)

126 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 13

13 For the circuit of Figure 13-1, the voltage gain from base to
collector is approximately
(a) 1 (b) 12 (ej 12 (d) 224
The output signal of a common-emitter amplifier is out-of-phase
with the input by
(a) 0° (b) 45° (ec) 90° (d) 180°
If the emitter bypass capacitor in Figure 13-1 is removed, the
amplifier voltage gain will
(a) increase (b) decrease
(c) remain essentially the same
If the emitter bypass capacitor in Figure 13-1 is shorted,
(a) the voltage gain will increase
(b) the voltage gain will remain the same
(c) the transistor will saturate
(d) none of the above
If the load resistor Ry, in the circuit of Figure 13-1 is made
larger, the amplifier voltage gain will
(a) increase (b) decrease
(c) remain essentially the same

© 1996 Prentice-Hall, Inc. All rights reserved. 127

 NOTES

128
 THE COMMON-COLLECTOR
14
AMPLIFIER
(EMITTER-FOLLOWER)

PURPOSE AND BACKGROUND

The purposes of this experiment are (1) to demonstrate the oper-

ation and characteristics of the small-signal common-collector am-
plifier and (2) to investigate what influences its voltage gain. The
common-collector amplifier, often referred to as an emitter-follower,
is characterized by application of the amplifier input signal to the
base lead while its output is taken from the emitter. The output sig-
nal is never larger than the input but is always in-phase with the
input. Consequently, the output follows the input. The main advan-
tage is that the input impedance of a common-collector amplifier is
generally much higher than for other bipolar transistor circuits.
Text Reference: 6—4, Common-Collector Amplifiers.

129
 REQUIRED PARTS AND EQUIPMENT
Resistors (1/4 W): 2N3904 npn silicon
68 D transistor
100 0-15 V de power supply
Two 1 kQ signal generator
22 kO VOM or DMM (preferred)
ZINK) Dual trace oscilloscope
Capacitors (25 V): |] Breadboarding socket
roe (te
100 uF

USEFUL FORMULAS

Voltage gain from base to emitter

Gy Age ae
Vin

y= ee ies
(Re IVago) or i

Transistor ac emitter resistance (at normal room temperature)

(are 25 mV
Ir
Quiescent dc base voltage

Quiescent dc emitter voltage

(5) Ve = Vp — Ver
Quiescent dc emitter current

Amplifier input impedance

(7) Mie = Ry | Rg | bl Re | R,) als rel

130
PROCEDURE

+15V

CH 2
| Oscilloscope
CH I

FIGURE 14-1 Schematic diagram of circuit.

1. Wire the circuit shown in Figure 14-1, omitting the signal gen-
erator and the power supply.
2. After you have checked all connections, apply the 15-V supply
voltage to the breadboard. With a VOM or DMM, individually
measure the transistor dc base and emitter voltages with re-
spect to ground, recording your results in Table 14-1. Based
on the resistor values of Figure 14—1, determine the expected
values of these two voltages (Equations 4 and 5), assuming a
base-emitter voltage drop of 0.7 V, and compare them with the
measured values in Table 14-1.
3. Connect Channel 1 of your oscilloscope at point J (vin) and Chan-
nel 2 to point O (Vout). Then connect the signal generator to the
circuit as shown in Figure 14—1, and adjust the sine wave out-
put level of the generator at 0.2 V peak-to-peak at a frequency
of 5 kHz.
You should observe that the output signal level (Vout) is very
nearly the same as the input level (v;,). In addition, there is
no phase shift. These points are two major characteristics of a
common-collector amplifier.
4. Using the measured value for the dc emitter voltage obtained
in Step 2, calculate the dc emitter current Jz and the resultant
transistor ac emitter resistance r, (Equation 3). Record these
values in Table 14—2.
131
 5. Using the oscilloscope, measure the ac peak-to-peak voltage
across the 1-kQ load resistor. Calculate the voltage gain from
base to emitter using Equation 2 given in the “Useful Formu-
las” section of this experiment. Record this result in Table 14—3.
Now measure the actual voltage gain by dividing the peak-to-
peak output voltage Vout by the peak-to-peak input voltage vin,
recording your result in Table 14—3.
6. Repeat Step 5 using the remaining load resistance values spec-
ified in Table 14-3. You should observe that the output voltage
level decreases slightly. It does so because the load resistance
affects the voltage gain of the amplifier stage. As in Step 5, ex-
perimentally determine the voltage gain by measuring Upyt and
Vin, Comparing your measured result with the expected value
(Equation 3). Record your results in Table 14-3.

WHAT YOU HAVE DONE

This experiment demonstrated the operation and characteristics of

a small-signal common-collector amplifier, or emitter—follower, which
has no phase shift. Here, the input signal is applied to the transis-
tor’s base lead, while the output signal is taken from the emitter
lead. The experiment also showed how the load resistance influenced
the circuit’s voltage gain.

132
INE rr
ee = as Date

THE COMMON-COLLECTOR AMPLIFIER

(EMITTER-FOLLOWER)

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 133

 Name Date

DATA FOR EXPERIMENT 14

TABLE 14-1

Parameter | Measured Value Expected Value % Error

Vp

ge J

TABLE 14-2

Parameter Value

Tz (calculated)

r, (calculated)

TABLE 14-3

Load | Measured Expected |

Resistance Divs Vout Gain Gain
+— % Error

aS
|

134 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 14

1. The voltage gain of a common-emitter amplifier, or an emitter-

follower, is always
(a) greater than 1 (b) equal to 1 (c) less than 1
The output signal of a common-collector amplifier is out-of-
phase with the input by
(a) 0° (b)s45° (ec) 90° (d) 180°
If the load resistor Ry, in the circuit of Figure 14—1 is increased,
the voltage gain will
(a) increase significantly (b) decrease significantly
(c) remain essentially the same
For the voltage gain to approach 1,
(a) R; must be omitted (b) R; must be shorted
(c) 6B must be as large as possible
(d) r. must be as small as possible
Which of the following is not characteristic of acommon-collector
amplifier?
(a) 0° phase shift (b) Voltage gain less than 1
(c) Output taken from emitter (d) Low input impedance

© 1996 Prentice-Hall, Inc. All rights reserved. 135

 NOTES

136
 THE COMBINATION
19
COMMON-EMITTER AMPLIFIER
AND EMITTER-FOLLOWER

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation of

a combination common-emitter amplifier and emitter-follower cir-
cuit. This type of circuit, sometimes referred to as a phase-splitter
or a paraphase amplifier, produces two identical output signals to
identical loads, except that they are 180° out-of-phase with each
other. The output signal from the collector is simply a common-
emitter amplifier whose voltage gain is 1 in addition to being 180°
out-of-phase with the input signal. The output signal is from the
emitter-follower and is in-phase with the input signal.
Text References: 6—2, Transistor AC Equivalent Circuits; 6—3,
Common-Emitter Amplifiers.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 2N3904 npn silicon transistor

Four 1 kQ 0-15 V de power supply
[] Two 10 kO Signal generator
Capacitors (25 V): VOM or DMM (preferred)
[] Two 2.2 pak Dual trace oscilloscope
LJ] 100 uF | Breadboarding socket
137
 USEFUL FORMULAS
Voltage gain from base to collector
(1) Ag = Voutl

Vin

(2) A, = Rc ||Roi
(Re |Ris) Te
Voltage gain from base to emitter

Gi Ape
Vin

(4) Ae = Re || Ri2

(Rg ||rg) +Tre

Transistor ac emitter resistance (at normal room temperature)
me 20 nn,
(5) Te
ls
Quiescent dc base voltage
Ro
6) Vee = eV,
iO) 408 ee ve
Quiescent dc emitter voltage
(7) Ve = Vp — Ver
Quiescent dc emitter current

(8) Iz = Uist Uo =I for large GB)

Re
Quiescent dc collector voltage
(9) Ve = Vec —IcRc

PROCEDURE

1. Wire the circuit shown in Figure 15-1, omitting the signal gen-
erator and the power supply.
2. After you have checked all connections, apply the 15-V supply
voltage to the breadboard. With a VOM or DMM, individually
measure the transistor de base, collector, and emitter voltages
with respect to ground, recording your results in Table 15-1.
Based on the resistor values of Figure 15—1, determine the ex-
pected values of these three voltages (Equations 6, 7, and 9),
assuming a base-emitter voltage drop of 0.7 V, and compare
them with the measured values in Table 15-1.
3. Connect Channel 1 of your oscilloscope to point J (vin) and Chan-
138 nel 2 to point OA (Vout). Then connect the signal generator to
 the circuit as shown in Figure 15-1, and adjust the sine wave
output level of the generator at 0.5 V peak-to-peak at a frequency
of 5 kHz.

ap issWY

Oscilloscope
CH |

FIGURE 15-1 Schematic diagram of circuit.

You should observe that the output signal level (vout1) is the
same as the input level (v;,). In addition, there is a 180° phase
shift between the output and input signals.
Using the measured value for the dc emitter voltage obtained
in Step 2, calculate the dc emitter current (Equation 8) and the
resultant ac emitter resistance, r, (Equation 5). Record these
values in Table 15-2.
Measure the ac peak-to-peak voltage across the 1-kQ load re-
sistor (R;1) with the oscilloscope. Calculate the expected volt-
age gain from base to collector using Equation 2 in the “Useful
Formulas” section of this experiment, and record this value in
Table 15-3. Now measure the actual voltage gain by dividing
the peak-to-peak output voltage Vout1 by the peak-to-peak input
voltage vj, (Equation 1), recording your result in Table 15-3.
Measure the ac peak-to-peak voltage across the 1-k load re-
sistor (Rz2) with the oscilloscope. Calculate the expected volt-
age gain from base to emitter using Equation 4 in the “Useful
Formulas” section of this experiment, and record this value in
Table 15-3. Now measure the actual voltage gain by dividing
the peak-to-peak output voltage Voutg by the peak-to-peak input
voltage vin (Equation 3), recording your result in Table 15-3. 139
 7. Connect Channel 1 of your oscilloscope to point OA (Vout1) and
Channel 2 to point OB (voutz). You should observe that both
output signal levels are the same as the input level, except for
a 180° phase shift between them.

WHAT YOU HAVE DONE

This experiment demonstrated the operation and characteristics of

a combination common-emitter amplifier and emitter-follower cir-
cuit, which is sometimes referred to either as a phase splitter or a
paraphase amplifier. This type of circuit produces two identical out-
put signals to identical loads, except that they are 180° out-of-phase
with each other.

140
Name ____ ee ee Date

THE COMBINATION COMMON-EMITTER AMPLIFIER

AND EMITTER-FOLLOWER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 141

 Name Date

DATA FOR EXPERIMENT 15

TABLE 15-1

Parameter [bese Value Expected Value % Error

Vp

Ve

nai lain
TABLE 15-2

Parameter i Value

Ir (calculated) |

r. (calculated) lL |

TABLE 15-3

Phase Measured Expected

hee Vin Usur Shift Gain Gain % Error

OA

OB

142 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 15

INF The voltage gain at either output for the phase-splitter circuit
of Figure 15-1 is
(a) significantly less than 1 (b) essentially equal to 1
(c) significantly greater than 1
The two output signals are out-of-phase with each other by
(a) 0° (b) 45° (ce) 90° (d) 180°
If Rr2 in the circuit of Figure 15-1 is omitted, vout1
(a) increases significantly (b) decreases significantly
(c) remains essentially the same
If Ry; in the circuit of Figure 15-1 is omitted, voute
(a) increases significantly (b) decreases significantly
(c) remains essentially the same
If Rr; in the circuit of Figure 15-1 is omitted, vout1
(a) increases significantly (b) decreases significantly
(c) remains essentially the same

© 1996 Prentice-Hall, Inc. All rights reserved. 143

 NOTES

144
 THE COMMON-BASE
16
AMPLIFIER

PURPOSE AND BACKGROUND

The purposes of this experiment are (1) to demonstrate the oper-

ation and characteristics of the common-base amplifier and (2) to
investigate what influences its voltage gain. The common-base am-
plifier is characterized by application of the amplifier input signal to
the emitter lead while its output is taken from the collector. Thus,
as in the emitter-follower, both signals are in-phase. However, the
voltage gain of a common-base amplifier is like that of a common-
emitter amplifier.
Text Reference: 6-5, Common-Base Amplifiers.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 2N3904 npn silicon transistor

470 Q Two 0-15 V de power supplies
myiwor.k) L] Signal generator
10 kD VOM or DMM (preferred)
Capacitors (25 V): Dual trace oscilloscope
Daa |] Breadboarding socket
[] 100 pF
145
 USEFUL FORMULAS

Voltage gain from emitter to collector

(1) A, = Cot
Vin

(NT Ay Re ||Ri (normal circuit)

Te
Ro ;
(3) A, = —= (without load)
re

Transistor ac emitter resistance (at normal room temperature)

Gyr 25 mV
Iz
Quiescent dc emitter voltage
(5) Ve = —Veg
Quiescent de emitter current

(6) Ip = ae (Iz ~ Ic for large B)

Quiescent dc collector voltage

(7) Ve = Vec — IcRe

PROCEDURE

1. Wire the circuit shown in Figure 16—1, omitting the signal gen-
erator and the power supply.
2. After you have checked all connections, apply the +9-V and
—9-V supply voltages to the breadboard. With either a VOM
or DMM, individually measure the transistor dc emitter and
collector voltages with respect to ground, recording your re-
sults in Table 16—1. Based on the resistor values of Figure 16-1,
determine the expected values of these two voltages (Equations
5 and 7), assuming a base-emitter voltage drop of 0.7 V, and
compare them with the measured values in Table 16-1.
3. Connect Channel 1 of your oscilloscope to point J (vin) and Chan-
nel 2 to point O (Vout). Then connect the signal generator to the
circuit as shown in Figure 16—1, and adjust the sine wave output
level of the generator at 25 mV peak-to-peak at a frequency of
5 kHz. If you cannot reach 25 mV, then adjust vj, so that there
is no clipping on the output signal.
You should observe that the output signal level (vou) is
greater than the input level (vj,). In addition, vout is in-phase
with respect to the input. These points are two major charac-
146 teristics of a common-base amplifier.
4. Using the measured value for the de emitter voltage obtained
in Step 2, calculate the de quiescent emitter current (Equation
6) and the resultant transistor ac emitter resistance, r, (Equa-
tion 4). Record these values in Table 16-2.

-9V +9V

2N3904

CH
Oscilloscope
CH

FIGURE 16-1 Schematic diagram ofcircuit.

5. Calculate the voltage gain from emitter to collector using Equa-

tion 2 given in the “Useful Formulas” section of this experiment,
and record the value in Table 16-3. Now measure the actual
voltage gain by dividing the peak-to-peak output voltage Vout by
the peak-to-peak input voltage v;, (Equation 1), recording your
result in Table 16—3.
6. Remove R;,. You should observe that the output voltage level in-
creases. It does so because the load resistance affects the voltage
gain of the amplifier stage. As in Step 5, experimentally deter-
mine the voltage gain by measuring Vout and vin, comparing your
measured result with the expected value (Equation 3). Record
your results in Table 16—3.
7. Finally, connect a 470- resistor for R,. Calculate the voltage
gain from emitter to collector using Equation 2 given in the
“Useful Formulas” section of this experiment, and record the
value in Table 16-3. Now measure the actual voltage gain by
dividing the peak-to-peak output voltage Vou by the peak-to-
peak input voltage vin, recording your result in Table 16—3.
From the results in Table 16—3, you should now understand
how the load resistance affects the emitter-to-collector voltage
gain of a common-base amplifier. 147
 WHAT YOU HAVE DONE

This experiment demonstrated the operation and characteristics of

a small-signal common-base amplifier, which has no phase shift.
Here, the input signal is applied to the transistor’s emitter lead,
while the output signal is taken from the collector lead. The exper-
iment also showed how the load resistance influenced the circuit’s
voltage gain.

148
NAIC eee ee eS eee SS et Date

THE COMMON-BASE AMPLIFIER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 149

 Name Date

DATA FOR EXPERIMENT 16

TABLE 16-1

Parameter | Measured Value | Expected Value % Error

Vie

Vo

Ty

|
TABLE 16-2

Parameter Value

Tp (calculated) [

r. (calculated)

TABLE 16-3

Load Measured Expected

Resistance Uin Vout Gain Gain % Error
ae
1kQ

None

470 Q

150 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 16

if For the circuit of Figure 16-1, the voltage gain from base to
collector is approximately
(a) 1 (b) 17 (c) 34 (d) 50
The output signal is out-of-phase with the input by
(a) 0° (b) 45° (c) 90° (d) 180°
If the emitter supply voltage is made more negative, the voltage
gain will
(a) increase
(b) decrease
(c) remain essentially the same
For the circuit of Figure 16-1, Vg is approximately
(a) —9V (b) OV (GC) ie Urey, (d) +0.7 V
Which of the following is not a normal characteristic of acommon-
base amplifier:
(a) 180° phase shift
(b) low input impedance
(c) output taken from collector
(d) voltage gain greater than 1

© 1996 Prentice-Hall, Inc. All rights reserved. 151

 NOTES

152
 THE CLASS A
1/
COMMON-EMITTER
POWER AMPLIFIER

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation of a

Class A common-emitter power amplifier. The Class A amplifier is
biased such that collector current always flows during the entire cy-
cle of the input waveform. Ideally, the amplifier’s Q point should be
biased at the center of the ac load line so that the output signal can
have the maximum possible swing in both directions. Consequently,
clipping will occur simultaneously on both peaks of the output sig-
nal if the amplifier is overdriven. If the Q point is not centered on
the ac load line, output waveform clipping will occur first, either at
saturation or at cutoff. Despite the simplicity of the Class A am-
plifier, the maximum efficiency that can be expected for it with a
capacitively coupled load is only 25 percent.
Text Reference: 7—1, Class A amplifiers.

153
 REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): Capacitors (25 V):

L] 220 0 El Two 2-262
[] 560 0 L} 100 pF
1 kQ (| 2N3904 npn silicon transistor
4.7 kQ (] 0-15 V de power supply
me LOAKG [} VOM or DMM (preferred)
CJ 100 kQ L) Signal generator
L] 5-kO potentiometer, or |] Dual trace oscilloscope
10-turn “trimpot” |] Breadboarding socket

USEFUL FORMULAS

Quiescent dc base voltage

b= lista)
(1) Vg = Ro Ye

Quiescent dc emitter voltage

(2) Ve = Vp — Vee
Quiescent collector current

(3) Ice = ae Ir = Ice for large B)

E

Quiescent dc collector-emitter voltage

(A Vero — Veo =lcohcw he)
ac load line
Collector saturation current:

(5) Leisaty) = Ice + “ose

Collector-emitter cutoff voltage:

(6) Voeccuto) = Vere + IcaRe
For centered Q point
(7) Ietsat) = 21cq
(8) Vorcutom = 2VerQ
Pie Yong
Ice
where R. = R,||Rz
rms output (load) power

(10) -P(@ms) =
[V.(rms)|?
154 Ry
dc power supplied to amplifier
(11) Pace = VecIce
Amplifier percent efficiency
P,(rms)
(12) %n = x 100%
dc

PROCEDURE
ap leyWY

CH?
Oscilloscope
CH 1

FIGURE 17-1 Schematic diagram of circuit.

1. Wire the circuit shown in Figure 17-1, omitting the signal gen-
erator and the power supply.
2. After you have checked all connections, apply only the 15-V
supply voltage to the breadboard. With the VOM or DMM, in-
dividually measure the transistor dc base and emitter voltages
with respect to ground, as well as Vege, recording your results
in Table 17-1. Based on the resistor values of Figure 17-1, de-
termine the expected values of these three voltages, assuming
a base-emitter voltage drop of 0.7 V, and compare them with
the measured values in Table 17-1.
3. Measure the quiescent de collector current /¢g, comparing it
with the expected value (Equation 3). Record your values in
Table 17-1. 155
 Connect Channel 1 of your oscilloscope at point J (vin) and
Channel 2 to point O (voy). Adjust your oscilloscope to the
following approximate settings:
Channel 1: 10 mV/division, ac coupling
Channel 2: 1 V/division, ac coupling
Time base: 0.2 ms/division
From Equation 9 given in the “Useful Formulas” section of this
experiment, determine the value of the load resistor R; that
gives a centered Q point on the ac load line. Adjust the 5-kQ
potentiometer load as closely as you can to that value.
Connect the signal generator to the breadboard, and adjust the
sine wave output level of the generator at 30 mV peak-to-peak
at a frequency of 5 kHz. If your signal generator cannot be
adjusted to 30 mV peak-to-peak, any value higher than this
can be used as long as the output signal is not clipped. You
should observe that the peak-to-peak output voltage is much
larger than the input, in addition to having a phase shift of
180°. Slowly increase the output level of the signal generator.
What eventually happens to the output waveform?
After a point, the peak-to-peak output voltage no longer
increases. In fact, the positive and negative peaks become flat-
tened, or clipped. Note that if the Q point is placed very near
the center of the ac load line, both peaks become clipped at
approximately the same time. Consequently, the transistor
reaches cutoff and saturation at the same input level.
Now reduce the input signal level to zero, and replace the
potentiometer with a 220-Q resistor. Slowly increase the input
signal level so that one peak slips off much earlier than the
other, as shown in Figure 17-2.

Input

Output

156 FIGURE 17-2

 You should observe that only the positive peaks are clipped.
This condition is characteristic of cutoff clipping because the
Q point is closer to the ac load line’s collector-emitter cutoff
voltage than to the collector saturation current. Confirm this
situation by drawing the ac load line with the Q point on the
graph page provided.
8. Now reduce the input signal level to zero, and replace the
220-Q resistor with a 100-kQ resistor. Slowly increase the in-
put signal level so that one peak clips off much earlier than
the other, as shown in Figure 17-3.

Input

Output

FIGURE 17-3

You should observe that now only the negative peaks are
clipped. This condition is characteristic of saturation clipping
because the Q point is closer to the ac load line’s collector sat-
uration current than to the collector-emitter’s cutoff voltage.
Confirm this situation by drawing the ac load line with the Q
point on the graph page provided. You should have a different
load line than that of Step 7.
9. As in Step 5, again adjust the 5-kM potentiometer to the re-
sistance that centers the Q point on the ac load line, replacing
the 100-k© resistor with it.
10. Now carefully increase the peak-to-peak input signal just be-
fore both output peaks clip off. With your VOM or DMM mea-
sure the rms voltage across the load resistor, V, (rms), and
compute the rms output power of the amplifier (Equation 10).
Record these results in Table 17-2.
11. Using Equation 11 given in the “Useful Formulas” section of
the experiment, calculate the dc power supplied, recording this
value in Table 17-2. 157
 12. Finally, compute the percent efficiency (%n) of your amplifier
(Equation 12), and compare it with the theoretical maximum of
25%. Record your result in Table 17-2. If you calculate a value
greater than 25%, then repeat Steps 9, 10, and 11, trying to
determine the source of your error.

WHAT YOU HAVE DONE

This experiment demonstrated the operation and characteristics of

Class A common-emitter power amplifier. Here, it was shown how
the location of the amplifier Q point affects the type of clipping ob-
served on the output signal when the amplifier circuit is overdriven.
If the Q point was closer to saturation, then the negative peak was
clipped first. The opposite was found to be true if biased closer to
cutoff. In addition, the efficiency of the amplifier was determined.

158
Name Date

THE CLASS A COMMON-EMITTER POWER AMPLIFIER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 159

 Name Date

DATA FOR EXPERIMENT 17

TABLE 17-1 Class A amplifier bias parameters.

Parameter Measured Value Expected Value % Error

Vp

Ve

Vore

Ice

TABLE 17-2 Class A amplifier efficiency.

Parameter Measured Value

V, (rms)

Parameter Calculated Value

JE, (Geng)

Tea

7on

160 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

DATA FOR EXPERIMENT 17

© 1996 Prentice-Hall, Inc. A | rights reserved. 161

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 17

1. For the circuit of Figure 17-1, the value of R,; that centers the
Q point is approximately
(a) 500 Q (b) 750 Q (c) 1 kQ (d) 10 kQ ( )
2. For the best performance, the Q point should be centered on
(a) the de load line (b) the ac load line
(c) both the ac and de load lines ( )
3. If the negative peaks of the output waveform are clipped as
shown in Figure 17-8, this condition represents
(a) cutoff clipping (b) saturation clipping
(c) nonlinear distortion ( )
4. Making R; much larger than 1 kQ would result in
(a) cutoff clipping of the output signal
(b) saturation clipping of the output signal
(c) nonlinear distortion of the output signal ( )
5. For the Class A amplifier of Figure 17-1, the maximum peak-to-
peak output voltage that can be obtained without clipping with
a 500-Q load is approximately
(a) 5 V (b) 7.5. V (coe OmV (d) 15 V ( )

162 © 1996 Prentice-Hall, Inc. All rights reserved.

 THE CLASS B PUSH-PULL
18
EMITTER-FOLLOWER
POWER AMPLIFIER

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the design and

operation of a Class B push-pull emitter-follower power amplifier.
The Class B push-pull amplifier has a pair of complementary (npn
and pnp) transistors, each of which is biased at cutoff (that is, no
collector current). Consequently, collector current in each transistor
flows only for alternate half-cycles of the input signal. Since both
transistors are biased at cutoff, the input signal must be sufficient
to forward bias each transistor on the appropriate half-cycle of the
input waveform. As a result, crossover distortion occurs.
To eliminate crossover distortion, both transistors should, un-
der quiescent conditions, be slightly forward biased so that each
transistor is actually biased slightly before cutoff, resulting in a
small amount of current called the trickle current. Since we now
have neither true Class A nor true Class B operation, but rather
something in between, this operation is referred to as Class AB op-
eration, although the term “Class B” is frequently used to describe
this situation. Despite its complexity, a Class B push-pull ampli-
fier can achieve efficiencies up to approximately 78%, which is more
than three times better than can be obtained with a similar Class
A amplifier without transformer coupling.
Text Reference: 7-2, Class B and AB Push-Pull Amplifiers.
163
 REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): LJ Two 1N914 (or 1N4148)

e000) silicon diodes
LC) Three 1 kQ 2N3904 npn silicon transistor
[|] Two 10 kQ [] 2N3906 pnp silicon transistor
L] 5-kQ potentiometer, or _] 0-15 V dc power supply
10-turn “trimpot” VOM or DMM (preferred)
Capacitors (25 V): [| Signal generator
L] Two 2.2 pF _] Dual trace oscilloscope
[} 100 pF _] Breadboarding socket

USEFUL FORMULAS

Quiescent dc collector current (diode bias)

CW) thes = ie Gf Vaz1 = Vee2)

rms output power

[V,(rms)]?
2) Perms) =
Rr
dc supply power supplied to amplifier
(3) Pac = Veclcc
Amplifier percent efficiency
= P,(rms)
(4) Yn x 100%
de

PROCEDURE

1. Wire the circuit shown in Figure 18—1A. Connect Channel 1 of

your oscilloscope at point J(v;,) and Channel 2 to point O(v,,,).
Adjust your oscilloscope to the following approximate settings:
Channels 1 and 2: 1 V/division, ac coupling
Time base: 0.2 ms/division
2. Apply power to the breadboard and adjust the sine wave out-
put level of the generator at 6 V peak-to-peak at a frequency
of 1 kHz. You should observe amplifier input and output wave-
forms similar to those shown in Figure 18—2. Notice that the
output waveform is distorted in the vicinity of zero volts. This
condition, referred to as crossover distortion, results when the
164 base-emitter diodes of both transistors are not forward biased
 CH 2
Oscilloscope
CHI

Two 1N914

4 2N3906

C.

FIGURE 18-1 Schematic diagram of circuits.

until the input signal exceeds approximately 0.7 V in both

directions.
Using Figure 18-3 as a guide, measure the base-to-emit-
ter voltages required for both transistors to become for-
ward biased, recording these values in Table 18-1.
Note that the peak-to-peak output voltage is slightly
smaller than the input, a difference approximately equal to
two base-emitter voltage drops. In addition, since each half of
the push-pull circuit is itself an emitter-follower, there is no
phase shift between the input and output signals.
3. Disconnect the power and signal generator leads from the
breadboard, and replace the series resistance Ry + R3 with a
5-kQ potentiometer in series with 100-Q resistor, as shown in
Figure 18-1B. Again connect the power and signal generator
leads to the breadboard. 165
 SEE
RD
Qe
we Input
y
*
eewe
#

Output

FIGURE 18-2

4, With the signal generator set at 6 V peak-to-peak at 1 kHz,

carefully adjust the potentiometer so that the crossover distor-
tion just disappears. Notice that the output voltage very nearly
equals the input, so the voltage gain is essentially equal to 1.
5. Again disconnect the power and signal generator leads from
the breadboard, and replace the potentiometer and 100-Q re-
sistor with two 1N914 (or 1N4148) compensating diodes in se-
ries between the two transistor base leads, as shown in Figure
18-1C. Again connect the power and signal generator to the
breadboard.
6. With the signal generator set at 6 V peak-to-peak at 1 kHz,
how does the output signal compare with that seen in Step 4,
after the potentiometer is adjusted?

FIGURE 18-3
166
 You should find that there is virtually no crossover distor-
tion. The voltage required to forward bias both transistors is
now supplied by the voltage drops of the two silicon diodes,
which are also forward biased.
With a VOM or DMM, individually measure the transistor de
base 1, base 2, and emitter voltages with respect to ground,
recording your results in Table 18-2.
Now carefully increase the peak-to-peak input signal so that
the output peaks just clip off. With your VOM or DMM, mea-
sure the rms voltage across the 1-kQ load resistor [V,(rms)],
and compute the rms output power of the amplifier (Equation
2). Record these results in Table 18-3.
In order to measure the de power supplied to the amplifier
while amplifying an input signal, use your VOM or DMM to
measure the de collector current Jc¢c of either transistor. Com-
pute the de power supplied (Equation 3), recording your
results in Table 18-3.
10. Finally, compute the percent efficiency (%n) of your amplifier,
and compare it with the theoretical maximum of 78.5% of a
Class B amplifier. Record your result in Table 18-3. If you
calculate a value greater than 78.5%, then repeat steps 8 and
9, trying to determine the source of your error.

WHAT YOU HAVE DONE

This experiment demonstrated the design and operation of a Class

B push-pull emitter-follower power amplifier and how it compared
with that of a Class A amplifier circuit. The circuit required a com-
plementary pair of transistors (one each pnp and npn) have almost
identical characteristics. The causes of crossover distortion were
demonstrated and possible methods to eliminate it were investi-
gated. The most effective of these methods was current-mirror bias-
ing using a pair of diodes. In addition, the efficiency of the amplifier
was determined and compared with that of a Class A amplifier.

167
 NOTES

168
Name Date

THE CLASS B PUSH-PULL EMITTER-FOLLOWER

POWER AMPLIFIER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 169

 Nai Ces
eeeaes ee Date

DATA FOR EXPERIMENT 18

TABLE 18-1 Voltage-divider bias with TABLE 18-2 Diode (current mirror)
no crossover distortion. bias with no crossover distortion.

Parameter Measured Value Parameter Measured Value |

|
Vp2

TABLE 18-3 Class B amplifier efficiency.

Parameter Measured Value

V, (rms)

Ice

Parameter Calculated Value

170 © 1996 Prentice-Hall, Inc. All rights reserved.

(Nae. a ee ee ee a Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 18

1 The output distortion shown in Figure 18-2 is called

(a) harmonic distortion (b) nonlinear distortion
(c) crossover distortion (d) amplitude distortion
For the Class B amplifier circuit of Figure 18—1, crossover dis-
tortion generally occurs when
(a) both transistors are biased at cutoff
(b) the base-emitter junctions of both transistors are not for-
ward biased
(c) both (a) and (b)
Elimination of crossover distortion for the circuit of Figure 18-1
can be achieved by
(a) adding compensation diodes that forward bias the base-
emitter junction of both transistors
(b) increasing the supply voltage
(c) adjusting resistors R,, Ry, Rs, and Ry to forward bias the
base-emitter junction of both transistors
(d) all of the above
If crossover distortion is eliminated, then the amplifier opera-
tion of Figure 18—1 is more correctly termed
(a) Class A (b) Class AB (c) Class B (d) Class C
The efficiency of a Class B amplifier cannot be greater than
approximately
(a) 25% (b) 50% (c) 75% (d) 100%

© 1996 Prentice-Hall, Inc. All rights reserved. 171

 NOTES

172
 THE JFET DRAIN CURVE
i,

PURPOSE AND BACKGROUND

The purpose of this experiment is to use the oscilloscope to dis-

play the drain curve for the MPF102 JFET. This curve shows the
variation of drain current as a function of drain-to-source voltage
with a constant gate-to-source voltage. Thus, with the special case
of having zero gate-to-source voltage, it is possible to estimate JFET
parameters such as drain current with gate shorted to source, Inss,
as well as gate-to-source cutoff voltage, Vesiorn.
Text Reference: 8-2, JFET Characteristics and Parameters.

REQUIRED PARTS AND EQUIPMENT

100-© resistor, 1/4 W 12.6-V rms secondary
MPF102 n-channel JFET transformer
[] 1N4001 silicon rectifier Dual trace oscilloscope
diode Breadboarding socket

173
 PROCEDURE
Horizontal input (Vps)

117 VAC

Oscilloscope

Vertical input
Up) =

FIGURE 19-1 Schematic diagram of circuit.

MPF102
(bottom view)

FIGURE 19-2 Pin configuration of MPF102 JFET.

1. Wire the circuit shown in the schematic diagram of Figure 19-1.

In this part, the oscilloscope is set up to function as an X-Y plot-
ter. Set the oscilloscope’s controls to the following approximate
settings:
Vertical (or Y) input sensitivity: 0.2 V/division,
de coupling
Horizontal (or X) input sensitivity: 1 V/division,
de coupling
2. After the oscilloscope has warmed up, move the trace dot to the
upper left-hand corner of the oscilloscope’s screen so that it is
centered on the intersecting scale divisions of the display. Now
connect the transformer’s primary to the 117-V ac power line.
The oscilloscope display should be similar to that shown in Fig-
ure 19-8. Ifit is not, the oscilloscope leads may be interchanged
or there may be a wiring error.
The “horizontal input” measures the JFET’s instantaneous
drain-to-source voltage (Vps). The diode allows only positive

174
FIGURE 19-3

voltage variations, from 0 V to about 18 V, which serves as the

instantaneous drain-to-source voltage. The “vertical input” mea-
sures the voltage drop across the 100-0 resistor. As shown on
the display, the vertical axis increases downward, which is dis-
played inverted from the normal sense. Using Ohm’s law, we can
make the vertical input read the JFET’s instantaneous drain
current (Ip). If, for example, the vertical sensitivity is 0.2 V/divi-
sion, then, in terms of the current through the 100-0 resistor
(which is the same as the drain current),
0.2 V/division
Vertical sensitivity =
100
= 2 mA/division
3. As shown in the schematic diagram of Figure 19-1, both the
gate and source leads are grounded, and thus Vaz is zero. Con-
sequently, the maximum drain current (Ipss) occurs when the
curve flattens out. The pinch-off region of the drain curve is for
drain-to-source voltages greater than the JFET’s pinch-off volt-
age, V,. This also occurs when the drain current just begins
to flatten out. Numerically, the pinch-off voltage is equal to the
JFET’s gate-to-source cutoff voltage, Vosior. Using Figure 19-4
as a guide, estimate from the oscilloscope’s display both [pss
and Vosior) for the MPF102 JFET you are using. Record these
values in Table 19-1.

175
 FIGURE 19-4

WHAT YOU HAVE DONE

This experiment demonstrated the shape of the drain curve of a

MPF102 JFET whose gate-to-source voltage is zero. Using an os-
cilloscope as a simple curve tracer, the drain characteristic shows
the variation of the JFET’s drain current as a function of drain-to-
source voltage. This curve then allowed the determination of JFET
parameters such as [pgs and Vesiorp).

176
Name Date

THE JFET DRAIN CURVE

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. wae

 Name Date

DATA FOR EXPERIMENT 19

TABLE 19-1 MPF102 drain curve.

Vos = 0

Ipss

Va scoff

178 © 1996 Prentice-Hall, Inc. All rights reserved,

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 19

ib. For the circuit of Figure 19-1, if the vertical sensitivity of the
oscilloscope is set at 50 mV/division, the vertical axis is then
calibrated to read
(a) 0.5 mA/division (b) 5 mA/division
(c) 50 mA/division (d) 0.5 A/division
The curve of Figure 19-1 is called a
(a) JFET forward transconductance curve
(b) JFET drain curve
(c) JFET source curve
(d) JFET gate curve
The point at which the curve of Figure 19-3 starts to flatten out
determines
(a) Toss (b) V, (c) Vascorn (d) all of the above
Which of the following does not apply to the curve of Figure
19-3?
(a) valid for Ves greater than 0 V(b) can determine V,
(c) can determine Vosorr) (d) can determine [pss
The JFET pinch-off voltage can be taken to be equal to
(a) Ves _ (b) —Ves (c) Vesior (@) —Vescorn

© 1996 Prentice-Hall, Inc. All rights reserved.

 NOTES

180
 THE JFET TRANSFER
20
CHARACTERISTIC CURVE

PURPOSE AND BACKGROUND

The purpose of this experiment is to use the oscilloscope to display

the transfer characteristic curve for the MPF102 JFET. This curve
shows the parabolic, or square-law, variation of the drain current
as a function of the gate-to-source voltage. From such a curve it is
possible to estimate JFET parameters such as the drain current
with gate shorted to source, pss; the gate-to-source cutoff voltage,
Vosior; and the forward transconductance, 8,9. The values of these
parameters are used in performing Experiments 21, 25, and 26.
Text Reference: 8-2, JFET Characteristics and Parameters.

REQUIRED PARTS AND EQUIPMENT

100-2 resistor, 1/4 W 0-15 V de power supply
MPF 102 n-channel JFET Signal generator
1N914 silicon rectifier Dual trace oscilloscope
diode Breadboarding socket

181
 USEFUL FORMULA

JFET forward transconductance at Ves = 0

Beez ss
aie \Vosvorn|

PROCEDURE

Horizontal input (V¢s )

Oscilloscope

Vertical input
Hees (Ip)
If

FIGURE 20-1 Schematic diagram of circuit.

MPF102
(bottom view)

FIGURE 20-2 Pin configuration of MPF 102 JFET.

Wire the circuit shown in the schematic diagram of Figure

20-1. In this part, the oscilloscope is set up to function as an
X-Y plotter. Set the oscilloscope’s controls to the following ap-
proximate settings:
Vertical (or Y) input sensitivity: 0.2 V/division,
de coupling
Horizontal (or X) input sensitivity: 1 V/division,
de coupling
After the oscilloscope has warmed up, move the trace dot to the
upper right-hand corner of the oscilloscope’s screen so that it is
centered on the intersecting scale divisions of the display. Now
apply power and the signal generator to the breadboard.

182
3. Adjust the frequency of the signal generator to 500 Hz and at
a signal level sufficient to produce a display similar to that
shown in Figure 20-3. If you do not obtain this curve, the os-
cilloscope leads may be interchanged or there may be wiring
error.
The “horizontal input” measures the JFET’s instantaneous
gate-to-source voltage (Vgsg ). The diode allows only negative volt-
age variations, which serve as the drain-to-source voltage. The
“vertical input” measures the voltage drop across the 100-2
resistor. As shown on the display, the vertical axis increases
downward, which is inverted from the normal sense. Using
Ohm’s law, we can make the vertical input read the JFET’s in-
stantaneous drain current ([pss). If the vertical sensitivity is
0.2 V/division, then, in terms of the current through the 100-2
resistors (which is the same as the drain current),
0.2 V/division
Vertical sensitivity =
100 ©
= 2 mA/division

FIGURE 20-3

4. Using Figure 20-4 as a guide, estimate from the oscilloscope’s

display both Ipsg and Vosior for the MPF102 JFET you are
using. Record these values in Table 20-1. If you also performed
Experiment 19, now compare these values with those obtained
in that experiment. If you used the same MPF 102 JFET in both
experiments, your results should closely agree.

183
 V
GS (off)
Vas 0

IDSS

Ip

FIGURE 20-4

5. From the values for [pss and Vaso) Measured in Step 4, calcu-
late the MPF102 JFET forward transconductance at zero gate-
to-source voltage, g,,o, and record this value in Table 20-1.
These values are used in performing Experiments 21, 25, and
26.

WHAT YOU HAVE DONE

This experiment demonstrated the shape of the transfer character-

istic, or transconductance curve of an MPF102 JFET. Using an os-
cilloscope as a simple curve tracer, the transfer characteristic curve
resembled a parabola showing the nonlinear variation of the JFET’s
drain current as a function of gate-to-source voltage. From this
curve, it was then possible to estimate JFET parameters such as
£mo,/pss, and Vosior), Which would be needed for several later ex-
periments.

184
Name Date

THE JFET TRANSFER CHARACTERISTIC CURVE

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 185

 Name Date

DATA FOR EXPERIMENT 20

TABLE 20-1 MPF 102 transfer characteristic curve.

Ipss

Vasiofh)

§mo

186 © 1996 Prentice-Hall, Inc. Alll rights reserved.

NaC ee eee ee ea Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 20

ihe The point at which the curve of Figure 20-3 intersects the ver-
tical axis is
(a) 2mo (b) RV, (c) [pss (d) Vasior
The point at which the curve of Figure 20-3 intersects the hor-
izontal axis is
(a) Zmo (b) Vos (c) Ipss (d) Vasworn
The diode in the test circuit of Figure 20-1 is used to
(a) limit the peak drain current
(b) forward bias the gate-to-source junction
(c) reverse bias the gate-to-source junction
(d) protect the JFET from excessive gate voltages
From the curve of Figure 20—8, one is able to determine
(a) Ings (b) Vesiorn (c) Zmo (d) all of the above
If g,,9 = 5000 uS and Vesiorm = —3 V, then Ipss is
(a) 0.6 mA (b) 1.2 mA (c) 7.5 mA (d) 15 mA

© 1996 Prentice-Hall, Inc. All rights reserved. 187

 NOTES

188
 JFET SELF-BIAS
rail

PURPOSE AND BACKGROUND

The purpose of this experiment is to verify the voltages and cur-

rents in a JFET circuit using self-bias. A JFET requires that the
gate-to-source voltage always be less negative than the pinch-off
or gate-to-source cutoff voltage, but less than zero. Since virtually
no gate current flows due to the JFET’s high input impedance,
the gate voltage is essentially at ground reference. Consequently,
using only a drain-supply voltage, the required negative quiescent
gate-to-source voltage is developed by the voltage drop across the
source resistor of the self-bias circuit. This experiment uses the
JFET parameters measured in Experiment 20 to confirm mea-
sured values.
Text Reference: 8-3, JFET Biasing.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): LJ 0-15 V de power supply

Two 1 kO [] VOM or DMM (preferred)
LJ 100 kD L) Breadboarding socket
[] MPF102 n-channel JFET
189
 USEFUL FORMULAS

JFET dc gate-to-source cutoff voltage

_ 2Ipss
(1) Vesiorm =
8mo

Quiescent de drain (source) current

R m Sli 1 a (2R Sm = Wile
(2a) lp eel pss (His 8mo sé 2
(Rs8mo)”

2
(2b) = Ipss il = Vas
GS (off)

Quiescent dc gate-to-source voltage

(3) Ve = IpRs
= —Voes so that Ve =a)

Quiescent drain voltage

(4) Vp = Vop — Iphp
Quiescent dc drain-to-source voltage
(5) Vos = Vop — Ip(Rp + Rs)
JFET forward transconductance at Q point

Vos
(6) Em = Smo 1- —~*
Vascott)

PROCEDURE

715 V

100 kQ.

190 FIGURE 21-1 Schematic diagram of circuit.

Wire the circuit shown in the schematic diagram of Figure
21-1, and apply power to the breadboard. For the same JFET
used in Experiment 20, record the measured values for Ipgs,
Veasior, and G,,o in Table 21-1.
Using your VOM or DMM as an ammeter, measure the quiescent
drain current (Jp) and record this value in Table 21-2.
Using the values of g,,9 and Ipss that you determined in Ex-
periment 20, determine the quiescent drain current (either
graphically or Equation 2a), and compare this value with that
measured in Step 2. Your results should agree within 10 percent.
With your VOM or DMM, individually measure the following
quiescent dc voltages: gate (Vg), source (Vs), drain (Vp), and
drain-to-source (Vps). Record your values in Table 21-2, and
compare these values with the expected values calculated using
Equations 3, 4, and 5 given in the “Useful Formulas’ section of
this experiment. Your results should agree within 10 percent.
You should have measured essentially no gate voltage, since the
gate current is very small due to the very high input impedance
of the JFET.
Now measure the quiescent de gate-to-source voltage (Vcs ). How
does this value compare with the source voltage measured in
Step 4?
These two voltages should be essentially the same, except
that Ves is a negative voltage while the source voltage is positive
with respect to ground. In a self-biased circuit, the gate receives
its bias voltage solely from the voltage developed across the
source resistor. In addition, the JFET’s quiescent gate-to-source
voltage will always be negative unless the gate and source leads
are shorted together.
With Equation 2b and the values of Ipgs and Vesior) found in
Experiment 20, plot on the blank graph provided for the transfer
characteristic (transconductance) curve for the JFET you are
using.
For the quiescent values of Jp and Vgs measured in Steps 2
and 5, plot the Q point on the graph. You should find that the
Q point lies essentially on the characteristic curve.
Replace the 1-kQ source resistors (Rs) with a 5-kQ potentiome-
ter. Connect your VOM and DMM as a voltmeter across the
JFET’s gate and source leads. Now vary the potentiometer
slowly so that you can obtain approximately five simultaneous
values for Jp and Vas, recording them in Table 21-3.
Plot the data obtained in Step 8 on the graph. You should find
that all the points lie essentially on the nonlinear, square-law
transfer characteristic curve. This happens because the curve
describes all the possible combinations of Jp and Ves as Ip
varies from zero to Ipgs while Ves varies from zero to Veésior).
Furthermore, you should notice that changing Rs changes the
191
 location of the Q point on the transconductance curve even
though the supply voltage, Ipss, and Vosiorr) remain the same
throughout.

WHAT YOU HAVE DONE

This experiment verified the voltages and currents in a JFET self-

bias circuit. The gate-source voltage must be negative, but more
positive than the JFET’s gate-to-source cutoff voltage. The gate-to-
source voltage is set up solely by the voltage drop of the circuit’s
source resistor. By varying the source resistor, a nonlinear square-
law characteristic curve was obtained.

192
Name Date

JFET SELF-BIAS

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 193

 Name Date

DATA FOR EXPERIMENT 21

TABLE 21-1

From Experiment 20

Ipss mA

Vesioff) Vi

Smo LS

TABLE 21-2
=
Parameter Measured Value Expected Value % Wrror
+
Ip

Va

Vs

194 © 1996 Prentice-Hall, Inc. All rights reserved.

INSih Gee ee eee ee Date
TABLE 21-3

Vas Ip

© 1996 Prentice-Hall, Inc. All rights reserved. 195

 NOTES

196
Name Date

DATA FOR EXPERIMENT 21

Hit
al
| al
see ‘au ay ia HHH rH
ae a
HH

Ci peeeee

i a

ii cE
|

HHH} =

© 1996 Prentice-Hall, Inc. All rights res erved. 197

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 21

1. For an n-channel JFET used in a self-biased circuit,

(a) the drain is more positive than the source
(b) the source is more positive than the gate
(c) the gate-to-source voltage is less negative than the Ve@siorp
of the JFET
(d) all of the above ( )
2. For the self-biased circuit of Figure 21-1 with pss = 10 mA
and g,,,9 = 5000 uS, the source current 1s approximately
(a) 1mA (b) 2 mA (c) 5mA (d) 10 mA ( )
3. For the self-biased circuit of Figure 21-1 with Ipss = 10 mA
and g,,9 = 5000 uS, the gate-to-source voltage is approximately
(a) 1V (b) 2V (c) -1 V (d) -2 V ( )
4. For the self-biased circuit of Figure 21-1 with Ipss = 10 mA
and g,,9 = 5000 uS, the JFET forward transconductance g,,, at
the Q point 1s approximately
(a) 1000 uS (b) 2500 uS (ce) 4000 US (d) 5000 uS ( )
5. For the self-biased circuit of Figure 21-1 with Ipss = 10 mA
and g,,9 = 5000 uS, the drain-to-source voltage is approximately
(a) 2V (b) 3V (c) 5V (d) 10 V ( )

198 © 1996 Prentice-Hall, Inc. All rights reserved.

 THE DEPLETION-MODE
22
MOSFET

PURPOSE AND BACKGROUND

The purpose of this experiment is to plot the transfer characteristics

of a depletion-mode metal-oxide semiconductor field-effect transis-
tor (MOSFET). The D-type MOSFET is sometimes called a normally-
on or depletion-enhancement MOSFET as it can be operated with
negative as well as positive gate-to-source voltages. Like the JFET,
the D-mode MOSFET conducts drain current for Ves between Vesiorp
and 0 and can be biased in the same manner as a JFET. Because
of the insulating layer between the gate and the channel, the MOS-
FET has a much higher input impedance than a JFET. Also because
of this extremely high input impedance (> 10! 1), MOSFETs are
subject to destruction by static discharge and care must be taken
when handling them.
Text References: 8-4, The Metal Oxide Semiconductor FET
(MOSFET); 8-5, MOSFET Characteristics and Parameters;
8-6 MOSFET Biasing.

199
 REQUIRED PARTS AND EQUIPMENT
Two 10-k© resistors, 1/4 W Two 0-15 V de power
5-kQ potentiometer supplies
et
50-kQ. potentiometer Two DMMs (preferred) or
40673 n-channel MOSFET, VOMs
or equivalent _] Breadboarding socket

USEFUL FORMULAS

Forward transconductance (at Ves = 0)

_ 2Ipss
(1) SO =
Vosioff)
Quiescent dc drain current
2
(2) Ip = Ipss 1- Vas
Vas(off)

PROCEDURE

1. Wire the circuit shown in the schematic diagram of Figure 22-1.

Be very careful in handling the MOSFET. Manufacturers nor-
mally package MOSFETs with all leads shorted together with a
piece of wire or metal ring and the leads pressed into black con-
ducting foam material. First insert the MOSFET on the bread-
board and wire the remaining components. Then unwrap the
shorting wire from all the leads. Never insert a MOSFET to or
remove a MOSFET from a circuit when the power is still on.
Once you have removed the shorting wire or ring and checked
the circuit for accuracy, apply power to the breadboard. Adjust
the 5-kQ potentiometer so that Vps = 10 V.
Now adjust the 10-kQ2 potentiometer so that Vag = -10 V. Mea-
sure the corresponding drain current (J) and record this value
in Table 22-1.
The drain current may be zero as the gate-to-source voltage
is more negative than Vogior) for your particular MOSFET.
Adjust the 10-kQ potentiometer for the remaining values of Vos
listed in Table 22—1. For each value of Vgs, measure the drain
current and record its value.
From the data of Table 22-1, plot the characteristic, or transcon-
ductance curve (/p vs. Vas) for the MOSFET you are using on
the blank graph provided for this purpose.

200
 +15V

5 kQ adjust for
Vos — 10 V

10 kQ ‘| +

40673
50 kQ eens or equivalent

10ka S
| =
-15V

FIGURE 22-1 Schematic diagram of circuit.

6. From the graph, determine [pss for your MOSFET at the point
where Vos = 0. Record its value in Table 22-2.
7. From the graph, determine Vosior) for your MOSFET at the
point where Jp = 0. Record its value in Table 22-2.
8. Using Equation 1 given in the “Useful Formulas” section of this
experiment, determine the forward transconductance of your
MOSFET, recording its value in Table 22-2.
9. When you are finished, first turn off the power to the bread-
board. Then short all three leads of the MOSFET by wrapping
them with a piece of wire before removing the MOSFET from
the circuit.

WHAT YOU HAVE DONE

In this experiment you determined the transfer characteristic curve

for a depletion-mode MOSFET. You were able to have gate-to-source
voltages that were negative as well as positive. Once the curve was
drawn, you determined the following parameters for your particu-
lar MOSFET: Ipnss, Vesior), and Zmo. In addition, you learned how
to properly connect a MOSFET to and remove a MOSFET from a
circuit without damaging it.

201
 NOTES

202
Name _ Date

THE DEPLETION-MODE MOSFET

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 203

 Name Date

DATA FOR EXPERIMENT 22

TABLE 22-1

Vos ali) V

Vas Ip (mA)

| tov
= 8 Vi

On

=4V

=2V

— 1 V)

0V

1V

2V

4V

6V

TABLE 22-2

Parameter Measured Value

Ipss mA

Vosiotn V

Em 0 ms

204 © 1996 Prentice-Hall, Inc. All rights reserved.

INS Ge ee ee RS OO Date

DATA FOR EXPERIMENT 22

© 1996 Prentice-Hall, Inc. All rights reserved. 205

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 22

1. For an n-channel depletion-mode MOSFET to be properly bi-

ased, the gate-to-source voltage must be
(a) negative
(b) positive
(c) zero
(d) all of the above
2. Handling a MOSFET requires that
(a) the shorting wire around all the leads must be removed
before the device is connected to the circuit.
(b) the MOSFET is never inserted or removed from a circuit
when the power is on.
Sh abe Vas —— DNV wien Ip = 0, and Ip = 10 mA when Ves = 0,
the forward transconductance is
(a) 2mS (b) 0.5 mS (c) 4mS (d) 1 mS
4, For the circuit of Figure 22-1 if Veg =1 V, Vesim =—4 V, and
Ipnss = 8 mA, the drain current is
(a) 0.6 mA (b) 8mA (c) 10 mA (d) 12.5 mA ( )

206 © 1996 Prentice-Hall, Inc. All rights reserved.

 THE ENHANCEMENT-MODE
23
MOSFET

PURPOSE AND BACKGROUND

The purpose of this experiment is to plot the transfer characteris-

tics of an enhancement-mode metal-oxide semiconductor field-effect
transistor (MOSFET), which is sometimes called a normally-off
MOSFET. When the gate-to-source voltage exceeds its threshold
voltage, the MOSFET conducts and drain current flows. Because
of the insulating layer between the gate and the channel, the en-
hancement-mode MOSFET has a much higher input impedance
then a JFET. Also because of this extremely high input impedance
(> 10!2 0), MOSFET are subject to destruction by static discharge
and care must be taken when handling them.
Text References: 8-4, The Metal Oxide Semiconductor FET
(MOSFET); 8-5, MOSFET Characteristics and Parameters; 8-6
MOSFET Biasing.

207
 REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 0-15 V de power supply

Pe) Two DMMs (preferred) or
100 kO VOMs
1-MQ potentiometer |] Breadboarding socket
NTE 465 n-channel
MOSFET, or equivalent

USEFUL FORMULAS

Quiescent dc drain current

if
(1) Ip = K [Ves — Vesctn)
where K depends on the particular MOSFET and is determined
from the data sheet.

PROCEDURE

1. Wire the circuit shown in the schematic diagram of Figure 238-1.

Be very careful in handling the MOSFET. Manufacturers nor-
mally package MOSFETs with all leads shorted together with
a piece of wire or metal ring and the leads pressed into black

+15 V

1kQ
100
kQ au

NTE 465
1MQ or equivalent

a -

FIGURE 23-1 Schematic diagram of circuit.

208
 conducting foam material. First insert the MOSFET on the
breadboard and wire the remaining components. Then unwrap
the shorting wire from all the leads. Never insert a MOSFET to
or remove a MOSFET from a circuit when the power is still on.
2. Once you have removed the shorting wire or ring and checked
the circuit for accuracy, apply power to the breadboard.
3. Now adjust the 1-MQ potentiometer so that the gate-to-source
voltage (Vc¢s) is zero. Slowly adjust this potentiometer and stop
at the point where drain current (/p) just starts to flow. Measure
the gate-to-source voltage and record its value in Table 23-1.
The gate-to-source voltage is the threshold voltage Vosith).-
4. Adjust the 1-mQ potentiometer so that the gate-to-source voltage
increases in 1-V steps up to 10 V. For each value of Vjs, measure
the drain current and record both values in Table 23-1.
5. From the data of Table 23-1, plot the characteristic, or transcon-
ductance, curve Up vs. Vos) for the enhancement-mode MOS-
FET you are using on the blank graph provided for this purpose.
6. When you are finished, first turn off the power to the bread-
board. Then short all three leads of the MOSFET by wrapping
them with a piece of wire before removing the MOSFET from
the circuit.

WHAT YOU HAVE DONE

In this experiment you determined the transfer characteristic curve

for an enhancement-mode MOSFET. Drain current conducts when
the gate-to-source voltage exceeds its threshold voltage and in-
creases in a parabolic (square law) fashion. In addition, you learned
how to properly connect a MOSFET to and remove a MOSFET from
a circuit without damaging it.

209
 NOTES

210
ING
1 Gy eee Date

THE ENHANCEMENT-MODE MOSFET

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 211

 Name Date

DATA FOR EXPERIMENT 23

TABLE 23-1

Vas Ip (mA)

212 © 1996 Prentice-Hall, Inc. All rights reserved.

INET Cee ei ee ee Es Date

DATA FOR EXPERIMENT 23

© 1996 Prentice-Hall, Inc. All rights reserved. 213

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 23

1. For an n-channel depletion-mode MOSFET to be properly bi-

ased, the gate-to-source voltage must be
(a) negative
(b) positive
(c) zero
(d) more positive than its threshold voltage
2. Handling a MOSFET requires that
(a) the shorting wire around all the leads must be removed
before the device is connected to the circuit.
(b) the MOSFET is never inserted or removed from a circuit
when the power is on.
3. If Ip = 3 mA when Veg = 5 V and Vosin) = 2 V, the drain
current when Vos = 7 V is
(a) 5mA (b) 8.3 mA (c) 7mA (d) 3mA
4, If Ip = 4 mA when Ves = 4 V and Vosan) = 3 V, the drain
current when Vcs = 2 V is
(a) 2mA (b) 3mA (c) 4mA (d) 0 mA ( )

214 © 1996 Prentice-Hall, Inc. All rights reserved.

 VMOSFET RELAY DRIVER
24

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the use of a
VMOSFET as a driver interface for a 12-V relay, providing isola-
tion between one circuit and another. Because of its construction,
the VMOSFET is sometimes called a power MOSFET and is ca-
pable of handling higher currents than regular enhancement-mode
MOSFETs. Like other MOSFETs, the VMOSFET has a much higher
input impedance than a JFET. Also because of this extremely high
input impedance (> 10! 0), VMOSFETs are subject to destruction
by static discharge, so care must be taken when handling them.
Text References: 8-4, The Metal Oxide Semiconductor FET
(MOSFET); 8-5, MOSFET Characteristics and Parameters;
8-6 MOSFET Biasing.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/2 W): O 0-15 V de power supply

LJ) 100 kQ L] 12-V relay
Pete MO; (4 SPDT switch
[) VK67AK n-channel iz DMM (preferred) or VOM
MOSFET, or equivalent C Breadboarding socket 215
 PROCEDURE

1; Wire the circuit shown in the schematic diagram of Figure 24-1.

Be very careful in handling the VMOSFET. Manufacturers nor-
mally package VMOSFETs with all leads shorted together with
a piece of wire or metal ring and the leads pressed into black
conducting foam material. First insert the VMOSFET on the
breadboard and wire the remaining components. Then unwrap
the shorting wire from all the leads. Never insert a VMOSFET
to or remove a VMOSFET from a circuit when the power is still
on.
+12 V

100 kQ 12-V
pone S05 PDT
| Contacts

OO)
VKG7AK
~ or equivalent

1MQ

FIGURE 24-1 Schematic diagram of circuit.

2. Once you have removed the shorting wire or ring and checked
the circuit for accuracy, apply power to the breadboard.
3. First place the switch in position 1. Measure Vag and Vpg, record-
ing both values in Table 24-1.
Since Ves = 0, the VMOSFET is cutoff, such that Ves <
Vasith). Since Ip = 0, there is no voltage drop across the relay
coil and the relay armature is not energized.
Then place the switch in position 2. Measure Ves and Vps,
recording both values in Table 24—1.
Since Veg > Vesith), the VMOSFET conducts. The relay ar-
mature pulls in. The relay contacts are then able to control the
switching of another circuit and is electrically isolated.
When you are finished, first turn off the power to the bread-
board. Then short all three leads of the VMOSFET by wrapping
them with a piece of wire before removing the VMOSFET from
216 the circuit.
WHAT YOU HAVE DONE

In this experiment you controlled a relay using a VMOSFET inter-

face driver. When the VMOSFET is cutoff, the relay is not energized.
When a positive voltage is applied to the gate lead, the relay arma-
ture pulls in.

217
 NOTES

218
Name Date

VMOSFET RELAY DRIVER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 219

 Name Date

DATA FOR EXPERIMENT 24

TABLE 24-1

Switch Position Vas Vos Relay Energized? |

nee |
ac Sree |

220 © 1996 Prentice-Hall, Inc. All rights reserved,

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 24

1. Handling a VMOSFET requires that

(a) the shorting wire around all the leads must be removed
before the device is connected to the circuit.
(b) the VMOSFET is never inserted or removed from a circuit
when the power is on.
2. For the relay driver circuit of Figure 24-1, when the switch is
in position 1, the VMOSFET is at
(a) saturation (b) cutoff
3. For the relay driver circuit of Figure 24-1, when the switch is
in position 1, the relay armature is
(a) energized (b) not energized
4. When the relay is energized in the circuit of Figure 24-1,
(a) Vos > Vasith) (b) Vas < Vestn)

© 1996 Prentice-Hall, Inc. All rights reserved.

 NOTES

222
 THE COMMON-SOURCE
29
AMPLIFIER

PURPOSE AND BACKGROUND

The purposes of this experiment are (1) to demonstrate the oper-

ation and characteristics of a self-biased common-source amplifier
and (2) to investigate what influences its voltage gain by using the
JFET parameters measured in Experiment 20. The common-source
amplifier is characterized by application of the amplifier input sig-
nal to the gate lead while its output is taken from the drain, a
condition that always gives a 180° phase shift.
Text References: 9-3, Common-Source Amplifiers.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): [] MPF102 n-channel JFET

L] Two 1 kO | 0-15 V de power supply
Diary ko [] Signal generator
CL) 100 kQ [] VOM or DMM (preferred)
Capacitors (25 V): L] Dual trace oscilloscope
L) Two 2.2 pF |] Breadboarding socket
CJ 100 pF.

223
 USEFUL FORMULAS

Voltage gain

Gh ee
Vin

CAA t mao lt (source resistor bypassed)

(3) Ay = _Emita__ (source resistor not bypassed)

1+ Enis

where ia = Rp||Rr

JFET dc gate-to-source cutoff voltage

2T ps:
(4) Vesioth = — DSS
§m0

Quiescent de drain (source) current

(2Rs mo 4p 1)1/2
(Rs mo + 1)-
(5) Ip = 2Ipss
(eee

Quiescent dc gate-to-source voltage

(6) Vs = IpRs
(7) = —Vos so that Ve = 0
Quiescent dc drain-to-source voltage
(8) Vos = Vop — Ip(Rp + Rs)
JFET forward transconductance at Q point

Vas
(9) Em = &m0 Wes
VGsioff)

PROCEDURE

Hip Wire the circuit shown in Figure 25-1, omitting the signal gen-
erator and the power supply. Enter the values of Ings, Vasiom,
and g,,9 obtained in Experiment 14 in Table 25-1.
After you have checked all connections, apply only the 15-V sup-
ply voltage to the breadboard. With your VOM or DMM, mea-
sure the JFET’s quiescent drain current J, and gate-to-source
voltage Vas, recording your values in Table 25-2. Based on the
values for g,,9 and Ipgg that you measured for the JFET in
Experiment 20, calculate the JFET’s transconductance g,,, at
this quiescent point, and record your result in Table 25-2. In
all cases, compare your measured values with what you would
expect to measure.

224
 ap iS)W

Ro
100 kQ

CH 2
Oscilloscope
CH 1

FIGURE 25-1 Schematic diagram of circuit.

3. Connect Channel 1 of your oscilloscope at the input to the am-

plifier (v;,) and Channel 2 to the 1-kQ load resistor (v,y;). Then
connect the signal generator to the circuit as shown in Figure
25-1, and adjust the sine wave output level of the generator at
0.5 V peak-to-peak at a frequency level of 5 kHz.
Note that the output signal level (Vout) is greater than the
input level (vi,). In addition, voyt is inverted, or 180° out-of-
phase, with respect to the input. These points are two major
characteristics of a common-source amplifier. In order to observe
the phase shift, you must display both signals simultaneously
on the oscilloscope; otherwise, you will not see any phase shift.
4, With an oscilloscope, measure the ac peak-to-peak voltage at
the JFET’s source lead. Even at the oscilloscope’s highest input
sensitivity, you should measure virtually no ac voltage at this
point. The 100-uF bypass capacitor, in parallel with Rs, serves
essentially as a short circuit path to ground, since its reactance
at 5 kHz is very small compared with the 1-kO resistance. Con-
sequently, the source lead is effectively at ac ground.
5. Calculate the expected voltage gain from Equation 2 using the
transconductance value determined in Step 2, and record the
value in Table 25-2. Now measure the actual circuit voltage
gain by dividing the peak-to-peak output voltage v4, by the
peak-to-peak input voltage v;,, recording your result in Table
25-2.

225
 6. Now remove R,. You should observe that the output voltage
level increases. It does so because the load resistance affects the
voltage gain of the amplifier stage. As in Step 5, experimentally
determine the voltage gain by measuring v,,; and Vin, comparing
your measured result with the expected value (Equation 2, with
R= Rp). Record your results in Table 25-2.
7. In this final step, also remove the 100-uF source bypass ca-
pacitor from the circuit. Note that the output voltage decreases
tremendously from that of Step 6. As in the previous two steps,
experimentally determine the voltage gain by measuring V,ut
and v;,, comparing your results with the expected value (Equa-
tion 3, with Ry = Rp). Record your results in Table 25-2.
From the results in Table 25-2, you should now understand
how both the source and load resistances affect the voltage gain
of a common-source amplifier.

WHAT YOU HAVE DONE

This experiment demonstrated the operation and characteristics of

a self-biased common-source amplifier, which has 180° phase shift.
Here, the input signal is applied to the JFET’s gate lead, while the
output signal is taken from the drain lead. The experiment also
showed how both the load resistance and emitter bypass capacitor
influenced the circuit’s voltage gain.

226
INemae at oe eee Date

THE COMMON-SOURCE AMPLIFIER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 227

 Name Date
DATA FOR EXPERIMENT 25

TABLE 25-1

From Experiment 20:

§m0 = Ipss =a

Parameter Measured Value Expected Value % Error

TABLE 25-2

Measured Expected
Condition Vin Went Gain Gain % Error

Normal circuit
(Step 5)

No load
(Step 6)

No bypass
capacitor and
no load
(Step 7)

228 © 1996 Prentice-Hall, Inc. All rights reserved.

(INA) Cpe
ee Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 25

1. For the circuit of Figure 25-1 with Ipgg = 10 mA and gyn, =

5000 uS, the voltage gain from gate to drain is approximately
(a) 0.6 (b) 0.7 (c) 2 (d) 4
The signal at the drain is out-of-phase with the gate by
(a) 0° (b) 45° (c) 90° (d) 180°
If the source bypass capacitor in Figure 25-1 is removed, the
voltage gain will
(a) increase (b) decrease
(c) remain essentially the same
If the load resistor R,; in the circuit of Figure 25-1 is increased,
the voltage gain will
(a) increase (b) decrease
(c) remain essentially the same
The common-source amplifier of Figure 25—1 is similar in oper-
ation to a bipolar transistor
(a) common-base amplifier (b) common-collector amplifier
(c) common-emitter amplifier (d) emitter-follower

© 1996 Prentice-Hall, Inc. All rights reserved.

 NOTES

230
 THE COMMON-DRAIN
26
AMPLIFIER
(SOURCE-FOLLOWER)

PURPOSE AND BACKGROUND

The purposes of this experiment are (1) to demonstrate the opera-

tion and characteristics of a self-biased common-drain amplifier,
and (2) using the JFET parameters measured in Experiment 20,
to investigate what influences its voltage gain. The common-drain
amplifier, often referred to as a source-follower, is characterized by
application of the input signal to the gate lead while the output
is taken from the source. The output signal is never larger than
the input but is always in-phase with the input. Consequently, the
output follows the input.
Text Reference: 9-4, Common-Drain Amplifiers.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 0-15 V de power supply

LJ Two 1 kQO [] Signal generator
100 kO [] VOM or DMM (preferred)
L] Two 2.2-uF capacitors, 25 V Dual trace oscilloscope
L] MPF102 n-channel JFET |] Breadboarding socket

231
 USEFUL FORMULAS

Voltage gain

Ong = 2
Vin

(yA, Sante
odes ae Al
where R, = Rg||Rz
JFET dc gate-to-source cutoff voltage
Dali
(3) Vesom = —?==
&m0

Quiescent dc drain (source) current

(2Rs mo aie 11/2
(Rs 8mo + 1)-
(4) Ip = 2Ipss
(Rsgmo)”
Quiescent dc gate-to source voltage
(5) Vs = Ips
(6) = — Vac so that Ve = 0
Quiescent dc drain-to-source voltage
CON Vises Vp pie piis
JFET forward transconductance at Q point

Vas
(8) Em = &mo 1- — >
| f,|

PROCEDURE

1. Wire the circuit shown in Figure 26-1, omitting the signal gen-
erator and the power supply.
2. After you have checked all connections, apply only the 15-V sup-
ply voltage to the breadboard. With your VOM and DMM, mea-
sure the JFET’s quiescent drain current Jp and gate-to-source
voltage Vas, recording your values in Table 26-1. Based on the
values for g,,9 and Ipgg that you measured for the same JFET
in Experiment 20, calculate the JFET’s transconductance g,,, at
this quiescent point, and record your result in Table 26—1. In
all cases, compare your measured values with what you would
expect to measure.

232
3. Connect Channel 1 of your oscilloscope to the amplifier’s input
(vin) and Channel 2 to the 1-kQ load resistor (v,,,,). Then connect
the signal generator to the circuit as shown in Figure 26-1, and
adjust the sine wave output level of the generator at 1 V peak-
to-peak at a frequency of 5 kHz.

aplls)W

MPF102
2.2 uF

CH2
Oscilloscope
CH 1

FIGURE 26-1 Schematic diagram of circuit.

Note that the output signal level (v,,;) is less than the in-
put level (v;,,). In addition, v,,; is in-phase with the input. These
points are two major characteristics of a common-drain ampli-
fier.
4. Calculate the voltage gain (Equation 2) using the transconduc-
tance value determined in Step 2, and record the value in Table
26-2. Now measure the actual circuit voltage gain by dividing
the peak-to-peak output voltage v,,4 by the peak-to-peak input
voltage v;, (Equation 1), recording your result in Table 26-2.
5. Now remove R,;. Observe that the output voltage level increases
somewhat. It does so because the load resistance affects the
voltage gain of the amplifier stage. As in Step 4, experimentally
determine the voltage gain by measuring v,,; and v;,, compar-
ing your measured result with the expected value. In this case,
R, = Rg. Record your results in Table 26-2.
From the results in Table 26—2, you should now understand
how the load resistance affects the voltage gain of a common-
drain amplifier.

233
 WHAT YOU HAVE DONE

This experiment demonstrated the operation and characteristics of

a self-biased common-drain amplifier, or source follower, which has
no phase shift. Here, the input signal is applied to the JFET’s gate
lead, while the output signal is taken from the source lead. The
experiment also showed how the load resistance influenced the cir-
cuit’s voltage gain.

234
IN2) Ce ——— ceria
ee aS Date

THE COMMON-DRAIN AMPLIFIER

(SOURCE-FOLLOWER)

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 235

 INA Ge
eeee ee Date

DATA FOR EXPERIMENT 26

TABLE 26-1

From Experiment 20: |

§m0 = Ipss =

Parameter | Measured Value | Expected Value % Error

i Ip
L

TABLE 26-2
[

hire Expected
Condition Vin Vout Gain Gain % Error

Normal circuit
(Step 4)

No load (Step 5)

236 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 26

1. For the circuit of Figure 26-1 with Ipss = 10 mA and g,,0 =

5000 uS, the voltage gain from gate to source is approximately
(a) 0.56 (b) 0.71 (c) 0.83 (d) 1
The signal at the source is out-of-phase with the gate by
(a) 0° (b) 45° (cjro0y (d) 180°
If the JFET forward transconductance in the circuit of Figure
26-1 is increased, the voltage gain will
(a) increase (b) decrease
(c) remain essentially the same
If the load resistor R,, in the circuit of Figure 26—1 is decreased,
the voltage gain will
(a) increase (b) decrease
(c) remain essentially the same
The common-drain amplifier is similar in operation to a bipolar
transistor
(a) common-base amplifier (b) common-collector amplifier
(c) common-emitter amplifier

© 1996 Prentice-Hall, Inc. All rights reserved. 237

 NOTES

238
 AMPLIFIER LOW-FREQUENCY
RESPONSE

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the factors that

contribute to the low-frequency response of a common-emitter tran-
sistor amplifier. The low-frequency response of a typical common-
emitter amplifier is determined in part by the input and output
coupling capacitors and the emitter bypass capacitor. The result is
essentially a combination of three high-pass filter networks that al-
low signals having frequencies greater than the cutoff frequency of
the dominant network to pass through while attenuating all others.
Although the cutoff frequencies associated with these three paths
can be made equal, such is rarely the case.
This experiment examines individually the effect of each capac-
itor on the common-emitter amplifier’s low-frequency response. In
all cases, the values of the capacitors are intentionally made abnor-
mally small in order to allow the frequency response to be easily
measured.
Text References: 10-1, General Concepts; 10-2, Decibels;
10-3, Low-Frequency Amplifier Response; 10-6 Total Amplifier
Response.

239
 REQUIRED PARTS AND EQUIPMENT
Resistors (1/4 W): 2N3904 npn silicon
15 OO) transistor
mii wo 2:7kO 0-15 V dc power supply
rs 2 KO (J VOM or DMM (preferred)
47 kQ, CI Signal generator
100 kO _] Dual trace oscilloscope
Capacitors: Breadboarding socket
L) Two 0.033 pF
ek
Two 2s2eu Be 25s Vi
iO) fanNae, BAS) Ni

USEFUL FORMULAS

Quiescent dc base voltage

(DE Vee= E na JV
1 2
Quiescent dc emitter voltage
(aie Vee Ven
Quiescent de emitter current

Ce
Ri + Ree
Transistor ac emitter resistance (at normal room temperature)
Chee 25 mV
Iz
Amplifier ac input impedance
(5) Rin = R, ||Ro ||Bre + Re)

(6A, =o
Vin

(7) A, = Rel:
Rr +r.
Decibel voltage gain
(8). dB = 20slog (A)
Frequency response due to input coupling capacitor C,
if
Onin —
27C1(Rin + Ra)

240
Frequency response due to emitter bypass capacitor C»

Gowen = il

27Co (Azle
S |Re + Rpt re) Reo|

Frequency response due to output coupling capacitor C3

1
(11) fs =
27C3(Rc + Ry)

PROCEDURE
+15 V

CH 2
Oscilloscope
CH 1

FIGURE 27-1 Schematic diagram of circuit.

1. Wire the circuit shown in Figure 27—1, omitting the signal gen-
erator and the power supply.
2. After you have checked all connections, apply the 15-V supply
voltage to the breadboard. With a VOM or DMM, measure the
transistor’s quiescent de emitter voltage with respect to ground.
From this value, determine the transistor’s ac internal emitter
resistance r, (Equation 4). Then determine the expected mid-
band voltage gain of the amplifier in decibels (Equations 7 and
8). Record these values in Table 27-1.
3. Connect Channel 1 of your oscilloscope to point J (vj,) and Chan-
nel 2 to point O (Voy). Then connect the signal generator to the
circuit as shown in Figure 27-1, and adjust the sine wave out-
put level of the generator at a frequency of 50 kHz so that the

241
 peak-to-peak output voltage of the amplifier spans 7.1 vertical
divisions when Channel 2 is set at a sensitivity of 0.5 V/division.
Measure the peak-to-peak input voltage level, and determine
the amplifier’s dB voltage gain (Equation 8). Record this value
in Table 27-1.
In order to determine the amplifier’s low-frequency 3-dB point
due solely to the effects of the input coupling capacitor C1, re-
place C; (2.2 uF) with a 0.033-uF capacitor. Adjust the sine
wave output level of the generator at a frequency of 50 kHz so
that the peak-to-peak output voltage of the amplifier spans 7.1
vertical divisions when Channel 2 is set at a sensitivity of 0.5
V/division. Then slowly reduce the input frequency until the
peak-to-peak output voltage drops to 5 vertical divisions. This
reduction in output voltage is 5/7.1, or 0.707, which is equiva-
lent to —3 dB. Using your oscilloscope, measure the frequency at
which this value occurs, and record this frequency (f;) in Table
27-2 along with the expected value (Equation 9) for compari-
son, assuming a typical beta of 150 for the 2N3904 transistors.
Then replace C; with a 2.2-uF capacitor. You should observe
that the output signal becomes smaller as the input frequency
is reduced.”
In order to determine the amplifier’s low-frequency 3-dB point
due solely to the effects of the emitter bypass capacitor Cg, re-
place Cy (10 wF)with a 1-uF capacitor. Again adjust the sine
wave output level of the generator at a frequency of 50 kHz
so that the peak-to-peak output voltage of the amplifier spans
7.1 vertical divisions when Channel 2 is set at a sensitivity of
0.5 V/division. Then reduce the input frequency until the peak-
to-peak output voltage drops to 5 vertical divisions. From your
oscilloscope, measure the frequency at which this value occurs
(f2), and record this frequency in Table 27—2 along with the ex-
pected value for comparison (Equation 10). Again assume that
beta is typically 150. Then replace Cy with a 10-uF capaci-
tor. You should again observe that the output signal becomes
smaller as in the input frequency is reduced.
In order to determine the amplifier’s low-frequency 3-dB point
due solely to the effects of the output coupling capacitor C3, re-
place C3 (2.2 wF) with a 0.033-4F capacitor. Again adjust the
sine wave output level of the generator at a frequency of 50 kHz
so that the peak-to-peak output voltage of the amplifier spans
7.1 vertical divisions when Channel 2 is set at a sensitivity of
0.5 V/division. Then reduce the input frequency until the peak-
to-peak output voltage drops to 5 vertical divisions. From your

“For most laboratory signal generators, Rg = 50 Q. If you are not sure of yours,
consult the generator’s user manual or ask your instructor.

242
 oscilloscope, measure the frequency at which this value occurs
(f3), and record this frequency in Table 27-2 along with the
expected value for comparison (Equation 11). You should observe
that the output signal becomes smaller as the input frequency
is reduced.

WHAT YOU HAVE DONE

This experiment demonstrated the factors that control the low-

frequency response of a small-signal, common-emitter amplifier. You
determined the amplifier’s midband voltage gain, the critical fre-
quencies of the input Re circuit, the emitter bypass circuit, and the
output Re circuit.

243
 NOTES

244
Nain =e
ee Date

AMPLIFIER LOW-FREQUENCY RESPONSE

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

245
© 1996 Prentice-Hall, Inc. All rights reserved.
 Name Date

DATA FOR EXPERIMENT 27

TABLE 27-1 Amplifier midband response.

if Parameter

Vr (measured)

r. (measured)

Ay(dB) (measured)

Cm |
TABLE 27-2 Amplifier low-frequency response (critical
frequencies).

Frequency Measured Expected % Error

fi

fe

fs

246 © 1996 Prentice-Hall, Inc. All rights reserved.

INA TC een eee es ee ee ee Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 27

13 The midband decibel gain for the circuit of Figure 27-1 is ap-
proximately
(a) 9.5 dB (b) 19.5 dB (c) 23.6 dB (d) 27.4 dB
The low-frequency response of the amplifier of Figure 27-1 is
controlled by
(a) capacitor C; (b) capacitor C2
(c) capacitor C3 (d) all of the above
Assuming a signal source impedance of 50 2 and a B of 100 for
the circuit for Figure 27-1, the critical frequency due solely to
C, is approximately
(a) 1 Hz (b) 3 Hz (c) 6 Hz (d) 43 Hz
Assuming a signal source impedance of 50 2 and a B of 100 for
the circuit of Figure 27-1, the critical frequency due solely to
C2 is approximately
(a) 2 Hz (b) 6 Hz (c) 50 Hz (d) 100 Hz
Assuming a signal source impedance of 50 2 and a B of 100 for
the circuit of Figure 27-1, the critical frequency due solely to
C3 is approximately
(a) 11 Hz. (b) 19 Hz (c)227 Hz (d) 45 Hz

© 1996 Prentice-Hall, Inc. All rights reserved. 247

 NOTES

248
 THE SILICON-CONTROLLED
RECTIFIER

PURPOSE AND BACKGROUND

The purposes of this experiment are to demonstrate (1) how to test

a silicon-controlled rectifier (SCR) with an ohmmeter and (2) how to
use an SCR to create a half-wave, variable-resistance, phase-control
circuit. Essentially the equivalent of a pnp and an npn transistor
connected together, the SCR is a special type of diode that will not
conduct current from anode to cathode unless a sufficient amount
of current is applied to its gate terminal. Once an SCR has been
turned on by such a gate pulse, it continues to conduct even if the
gate pulse is removed. The only way to turn off an SCR is to remove
the voltage from the anode (that is, zero volts).
This experiment demonstrates how an SCR is used to vary the
power dissipated by a resistive load by varying the SCR’s conduction
angle between 0° and 90°. Such a circuit can be used as a light
dimmer or a variable-speed control for an electric motor, such as a
hand drill.
Text References: 11—2, The Silicon-Controlled Rectifier (SCR);
11-3, SCR Applications.

249
 REQUIRED PARTS AND EQUIPMENT

Resistors: [|] 2N6397 SCR, 200 V,5 A

ll 470 O, 1/4W 12.6-V rms secondary
m2 2 kO 2 Wi transformer
L] 5-kQ potentiometer, or Dual trace oscilloscope
10-turn “trimpot” VOM or DMM (preferred)
_] 1N4001 silicon rectifier diode J) Breadboarding socket

USEFUL FORMULA

rms power dissipated by a resistor

es: 2

PROCEDURE

A
Anode

G
. AG Galena

Cathode Gate Cathode

A. Anode p. K

FIGURE 28-1 Pin configuration and diode junction representation of SCR.

GH
Oscilloscope

117 VAC

12.6 V rms

250 FIGURE 28-2 Schematic diagram of circuit.

 As with diodes and transistors (see Experiments 1 and 8), a
VOM can be used to check quickly whether an SCR is good
or bad. Unless they have a specific function for this purpose,
DMMs are not able to perform this test properly. Refer to Ex-
periment 8 and reread how to determine the polarity of your
ohmmeter’s leads.
Using a 2N6397 or equivalent SCR, whose pin diagram and
diode junction representation are shown in Figure 28-1, con-
nect the ohmmeter’s positive lead to the SCR’s anode lead,
while the ohmmeter’s negative lead is connected to the cathode
lead. Measure the resistance, recording this value in
Table 28-1.
Reverse the meter’s leads so that the positive lead is connected
to the cathode while the ohmmeter’s negative lead is connected
to the anode lead. Measure the resistance and record this value
in Table 28-1.
The meter readings in both cases should be about the
same.
Now connect the meter’s positive lead to the gate lead, and the
negative lead to the cathode lead. Measure the resistance and
record this value in Table 28-1.
Reverse the meter leads. Measure the resistance and record
this value in Table 28-1.
Again connect the meter’s positive lead to the gate lead, but
now connect the meter’s negative lead to the anode. Measure
the resistance and record this value in Table 28-1.
Reverse the meter leads. Measure the resistance and record
this value in Table 28-1.
In Steps 2, 3, 6, and 7, the measured resistance is generally
greater than 1 MQ. In Step 4, you forward biased the gate-
cathode junction, while this junction was reverse biased in
Step 5. Consequently, the resistance reading obtained in Step
4 should be less than in Step 5, similar to that of an ordinary
diode.
Wire the circuit shown in the schematic diagram of Figure
28-2. Initially set the 5-kOQ potentiometer to approximately
2 kQ. In addition, set your oscillscope to the following approx-
imate settings:
Channel 1: 10 V/division, de coupling
Channel 2: 20 V/division, de coupling
Time base: 5 ms/division
The ground lead of the oscilloscope probe should be connected
to the anode terminal of the SCR.
10. Apply power to the breadboard. On Channels 1 and 2 you
should see approximately three cycles of the voltage across
the 2.2-kQ load resistor and a cathode-to-anode voltage wave-
form like that shown in Figure 28-3. Because of the manner in 251
 which the oscilloscope probes are connected to the circuit, the
voltage across the SCR (Channel 2) is displayed inverted from
what you would normally expect to see.
11. Change the oscilloscope’s time base to 1 ms/division. Using the
voltage waveforms shown in Figure 28—4 as a guide, measure
the SCR’s conduction angle for various settings of the 5-kO
potentiometer. Based on the time divisions in Figure 28—4, the
SCR’s conduction angle (a) in degrees is computed as

ie as 603
2to

For each setting of the potentiometer, measure t,; and fg. Also,
use an ac voltmeter to measure the rms voltage across the

FIGURE 28-3

252 FIGURE 28-4

 2.2-kQ load resistor. Calculate the power dissipated by the load
at each setting. You should attempt about 10 different settings.
Record your values in Table 28-2.
12. On the blank graph provided for this purpose, plot the rms
power dissipated by the load versus the SCR’s conduction an-
gle. What do you conclude from the graph?
From your graph, you should see that the load’s dissipated
power decreases with increasing conduction angle.

WHAT YOU HAVE DONE

This experiment demonstrated how to properly test a silicon-con-

trolled rectifier (SCR) with an ohmmeter. In addition, this experi-
ment demonstrated the operation of a half-wave phase-control cir-
cuit whose SCR’s conduction angle is controlled from 0° to 90°
by a variable resistor. Data was taken so that a graph of the power
dissipated by the load vs. the SCR’s conduction angle could be
made.

253
 NOTES

254
Name Date

THE SILICON-CONTROLLED RECTIFIER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 255

 Name Date

DATA FOR EXPERIMENT 28

TABLE 28-1 SCR resistance tests.

Ohmmeter Leads
Step
Number + = Saco
—s

2 anode cathode

3 cathode anode

4 gate cathode

5 cathode gate

6 gate anode

7 anode gate |

256 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

TABLE 28-2 SCR variable phase control

V,, (rms) Load Power

© 1996 Prentice-Hall, Inc. All rights reserved. 257

 NOTES

258
INA Coe eee ee ee ee Date

DATA FOR EXPERIMENT 28

i| ied Gonteata
{ | it t { ia
1 = ia
| LH Tac I
i

ne
|
| H
ia cet Talay

useee
+—t+ +—+ + ft —t it

ae ‘| { iE [
ttt ==" al ela |

4 al se
He H Lp LI HH :
= + ttt ol! a t lt
+ += +— + - ie ic +

4 i 1 = EE
i es Ey

L HH FH 4
Cot

is HH Pee eect mi i.
Titel = a ai
meal +4 sed ial
=e Bi silt | il

ia eae Coo och

HH

— + +

© 1996 Prentice-Hall, Inc. All rights reserved. 259

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 28

1. The equivalent circuit representation for an SCR uses

(a) an npn transistor and a diode
(b) a pnp transistor and a diode
(c) two transistors of the same type
(d) an npn and a pnp transistor ( )
2. Ifthe ohmmeter’s positive lead is connected to the SCR’s anode
while the negative lead is connected to the cathode, for a “good”
SCR the ohmmeter will read
(a) 0
(b) a very low resistance
(c) typically several thousand ohms
(d) a nearly infinite resistance ( )
3. If the ohmmeter’s positive lead is connected to the SCR’s anode
while the negative lead is connected to the gate, for a “good”
SCR the ohmmeter will read
(a) 0
(b) a very low resistance
(c) typically several thousand ohms
(d) a nearly infinite resistance ( )
4. For the circuit of Figure 28-1, once the SCR conducts, the way
to turn off the SCR is to
(a) reverse bias the gate
(b) forward bias the gate
(c) remove, or ground, the anode voltage
(d) ground the gate lead ( )
5. As the SCR’s conduction angle is increased from 0° to 90° in the
circuit of Figure 28-1, the power dissipated by the load resistor ( )
(a) decreases (b) increases (c) remains the same
260
© 1996 Prentice-Hall, Inc. All rights reserved,
 THE UNIJUNCTION
TRANSISTOR

PURPOSE AND BACKGROUND

The purposes of this experiment are (1) to demonstrate how to test a

unijunction transistor (UJT) with an ohmmeter and (2) to describe
the operation of a relaxation oscillator. The UJT is a three-terminal
switching device used primarily as an oscillator. Although it uses the
name transistor and its schematic symbol closely resembles that of
an n-channel FET, the UJT, unlike other transistors, cannot be used
as an amplifier.
Text Reference: 11-6, The Unijunction Transistor (UJT).

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 0-15 V de power supply

[] 68 kO VOM or DMM (preferred)
1 kO Dual trace oscilloscope
LJ] 47 kO Breadboarding socket
0.01-uF capacitor
2N2646 unijunction transistor
(HEP 310, MU020, or
equivalent)
261
 USEFUL FORMULAS

Approximate output frequency

Cyt fo = : (Hz)
RC In| y
Len
where 7 = intrinsic standoff ratio
Peak capacitor voltage
(2) Vp = nVpBB aR WM

where Vgp = UJT interbase voltage (Vg2 — Vp1)

Von = UJT emitter-base diode voltage
Base 2 dc voltage
By), = rBB Vcc
EB Beas R, + Ro

Base 1 dc voltage

A) Ven
RiVec
a rep +R, + Re

PROCEDURE

As with diodes and transistors (see Experiments 1 and 8),

VOMs can be used to check quickly whether a UJT is good
or bad. Unless they have a specific function for this purpose,
DMM<s are usually not able to perform this test properly. Refer
to Experiment 8 to determine the polarity of your ohmmeter’s
leads.
Using a 2N2646 UJT, whose pin diagram and diode junction
representation are shown in Figure 29-1, connect the ohmme-
ter’s positive lead to the transistor’s base 1 (B1) lead while the
ohmmeter’s negative lead is connected to the base 2 (B2) lead.
Measure the resistance and record this value in Table 29-1.
Reverse the meter’s leads so that the positive lead is connected
to the B2 lead while the ohmmeter’s negative lead is connected
to the B1 lead. Measure the resistance and record this value
in Table 29-1.
The meter readings in both cases should be the same. This
resistance, called the base-to-base resistance rpg, is typically
4kQ to 10 kQ.
Now connect the meter’s positive lead to the emitter lead (E),
and the negative lead to the B1 lead. Measure the resistance
and record this value in Table 29-1.
262
 2N2646
(top view)

B2

a9)

E eB

TB
UJT equivalent
circuit

Bl

FIGURE 29-1 Pin diagram and diode junction representation

of 2N2646 UJT.

+15 V

Oscilloscope
CH 1

FIGURE 29-2 Schematic diagram of circuit.

5. Reverse the meter leads. Measure the resistance and record

this value in Table 29-1.
6. Again connect the meter’s positive lead to the emitter lead,
but now.connect the meter’s negative lead to B2. Measure the
resistance and record this value in Table 29-1.
263
 Reverse the meter leads. Measure the resistance and record
this value in Table 29-1.
In Steps 4 and 6, you separately forward biased both emitter-
base junctions. In Steps 5 and 7, these junctions were reverse
biased. Consequently, the resistance reading obtained in Step
4 should be less than in Step 5, and the reading in Step 6
should be less than in Step 7. In general, one of the emitter-
base resistance readings will be lower than the other. Usually
the emitter-B2 junction exhibits the lower resistance.
When you are not sure which leads of a UJT are the emit-
ter, B1, and B2 leads, you should be able to identify the two
base leads quickly since they measure the same resistance with
either meter polarity (Steps 2 and 3).
Wire the circuit shown in the schematic diagram of Figure
29-2. Initially, leave the 47-kQ timing resistor disconnected
from the circuit. In addition, set your oscilloscope to the fol-
lowing approximate settings:
Channel 1: 5 V/division, de coupling
Channel 2: 2 V/division, de coupling
Time base: 0.2 ms/division
10. Apply power to the breadboard. First measure the de voltages
at B1 and B2 with respect to ground, and then take the differ-
ence, Vg2 — Vp1, to obtain the interbase voltage Vgg. Do this for
both the measured and the expected values, and record them
in Table 29-2. Using the experimental value you measured in
Steps 2 and 3 for the interbase resistance rgg and Equations
3 and 4 given in the “Useful Formulas” section, compare the
values for Vg; and Vgg with their expected values.
11. Now add the 47-k©) timing resistor to the circuit as shown in
Figure 29-2. On Channel 1, you should now see displayed a ca-
pacitor charge-discharge “sawtooth” waveform like that shown
in Figure 29-3. Using your oscilloscope, measure the frequency
(f,) of this waveform, and record this value in Table 29-2.
12. Using the capacitor voltage waveform shown in Figure 29—4
as a guide, measure the maximum voltage (V,,) and the mini-
mum voltage (V,) with respect to ground, and record your re-
sults in Table 29-2. Using the experimental value for V,, and
assuming a diode voltage Vp of 0.7 V, determine the UJT’s in-
trinsic standoff ratio ()) from Equation 2. Record this value in
Table 29-2.
13. Using the value for the intrinsic standoff ratio found in Step
12, as well as timing resistor R and capacitor C, calculate
the expected output frequency of the UJT relaxation oscillator
(Equation 1), recording this value in Table 29-2. Compare this
value with that measured in Step 11.
14. Now notice the positive-going waveform on Channel 2, which
264 is the voltage across resistor R;. Using the waveform shown in
 UJT emitter

UST base 1

FIGURE 29-3

V,

Vo

Vix
OV
FIGURE 29-4 Capacitor voltage waveform.

Figure 29-5 as a guide, measure the maximum voltage (V,) and

the minimum voltage (V2) with respect to ground, and record
your values in Table 29-2. You should find that the minimum
voltage is approximately equal to the base 1 de voltage mea-
sured in Table 29-1.

OV

FIGURE 29-5 UJT base 1 voltage waveform.

15. Now connect the Channel 2 probe to B2 of the UJT. You should
observe a negative-going waveform on Channel 2, which is the
voltage across resistor R2. Using the waveform shown in Figure
29-6 as a guide, measure the maximum voltage (V3) and the 265
 V;

FIGURE 29-6 UJT base 2 voltage waveform.

minimum voltage (V;) with respect to ground, and record your

values in Table 29-2. You should find that the maximum volt-
age is approximately equal to the base 2 de voltage measured
in Table 29-1, while the minimum voltage is approximately
equal to the valley voltage, V,.
Consequently, we are able to obtain three separate wave-
forms from the UJT relaxation oscillator.

WHAT YOU HAVE DONE

This experiment demonstrated how to properly test a unijunction

transistor (UJT) with an ohmmeter. In addition, this experiment
demonstrated the operation of a relaxation oscillator, identifying the
waveforms present at all three terminals of the UJT. In addition,
the intrinsic standoff ratio (7) of a UJT was determined.

266
Name Date

THE UNIJUNCTION TRANSISTOR

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 267

 Name Date

DATA FOR EXPERMIMENT 29

TABLE 29-1 UJT resistance tests.

=

Ohmmeter Leads
Step
Number = = Resistance

2 base 1 base 2

3 base 2 base 1

4 emitter base 1

Is) base 1 emitter

6 emitter base 2
Rca(een are

a base 2 emitter
=

268 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

TABLE 29-2 UJT relaxation oscillator.

sa
Measured Expected op
Parameter Value Value Error

Vp2

=|,
V3

Vs

© 1996 Prentice-Hall, Inc. All rights reserved. 269

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 29

1. If the intrinsic standoff ratio for the UJT used in the circuit
of Figure 29-2 is 0.75, the output frequency of the relaxation
oscillator is approximately
(a) 670 Hz (b) 1120 Hz (c) 15380 Hz (di) 2127 Hz ( )
2. Ifthe intrinsic standoff ratio for the UJT used in the circuit of
Figure 29-2 increases, the output frequency of the relaxation
oscillator
(a) decreases (b) increases
(c) remains essentially the same ( )
3. Ifthe UJT interbase resistance is 6 kQ, the base 2 voltage for
the circuit the Figure 29-2 is approximately
(a) OSV (b) 2 V (Ome aaN (d) 14.85 V ( )
4. The waveform at the base 2 lead of a UJT oscillator is a
(a) sawtooth
(b) positive-going spike
(c) negative-going spike
(d) square wave ( )
5. The waveform at the emitter lead of a UJT oscillator is a
(a) sawtooth
(b) positive-going spike
(c) negative-going spike
(d) square wave ( )

270 © 1996 Prentice-Hall, Inc. All rights reserved.

 OP-AMP SLEW RATE

PURPOSE AND BACKGROUND

The purpose of this experiment is to measure the slew rate of a

741 operational amplifier. The slew rate, a large-signal parameter,
is defined as the maximum time rate of change of the output voltage
of an op-amp in response to a step input voltage. Expressed in units
of volts per microsecond (V/ys), the slew rate is dependent upon
the frequency response of the internal stages of the op-amp. Thus,
the higher the slew rate, the better the frequency response of the
amplifier.
The measurement of the operational amplifier’s slew rate is
always accomplished with a large-signal amplifier having wnity gain
with a high input frequency signal.
Text Reference: 12-3, Op-Amp Parameters.

REQUIRED PARTS AND EQUIPMENT

Two 10-k© resistors, 1/4 W Signal generator

[] 741 op-amp (8-pin mini-DIP) Dual trace oscilloscope
Two 0-15 V de power Breadboarding socket
supplies
271
 PROCEDURE
10k

GHZ
Oscilloscope
CHE

FIGURE 30-2 Pin diagram of 741 op-amp.

1. Wire the circuit shown in the schematic diagram of Figure 30-1,

and set your oscilloscope for the following approximate settings:
Channel 1: 5 V/division, ac coupling
Channel 2: 1 V/division, ac coupling
Time base: 10 ys/division
2. Apply power to the breadboard, and adjust the square-wave in-
put signal at 5 V peak-to-peak with a frequency of 10 kHz.
The output signal should have a trapezoidal shape, as shown in
Figure 30-8. If the operational amplifier were ideal (that is, in-
finite slew rate), the output signal would look exactly the same
as the input at very high frequencies. In reality, it takes a finite
amount of time for the large-signal amplifier to switch from one
voltage extreme to the other.
3. Measure the peak-to-peak output voltage, AV, and record your
result in Table 30-1.
4. Measure At, the time in microseconds that it takes the output
voltage to swing from its minimum to its maximum value, or
vice versa, and record this value in Table 30-1.
5. From the measurements in Steps 3 and 4, calculate the slew
rate, AV/At, for your 741 amplifier, and record your result in
272 Table 30-1.
 Input

Output

FIGURE 30-3

For the 741 operational amplifier, the typical slew rate is

0.5 V/s. Other op-amps, such as the LM318, are faster, having
a typical slew rate of 70 V/us. This is 140 times better than that
of the 741 op-amp.

WHAT YOU HAVE DONE

This experiment demonstrated how to measure the slew rate, or

time rate of change of the output voltage of a 741 operational am-
plifier. It is a large-signal parameter and is measured using a closed-
loop gain of 1.

273
 NOTES

274
Name Date

OP-AMP SLEW RATE

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 275

 Name Date

DATA FOR EXPERIMENT 30

TABLE 30-1

AV Vv

At MS

Slew Rate V/s

276 © 1996 Prentice-Hall, Inc. All rights reserved.

ING Cee
= eee = ee Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 30

1. For the circuit of Figure 30-1, using a +15 V supply, the maxi-
mum possible output voltage swing is approximately
(a) 5V (b) 15 V (c) 20 V (d) 30 V
The maximum time rate of change of the output voltage of the
circuit of Figure 30-1 in response to a step input is termed the
(a) gain-bandwidth product
(b) slew rate
(c) output voltage swing
(d) common-mode rejection ratio
The slew rate is usually specified in units of
(a) V/s (b) V/us (c) dB (d) MHz
For an operational amplifier, the slew rate limits the
(a) input impedance (b) common-mode rejection
(c) voltage gain (d) frequency response
For the circuit of Figure 30-1, if the output voltage swings from
+5V to —10V in 0.5 ps, the slew rate is
(a) 5 V/us (b) 15 V/us (c) 20 V/us (d) 30 V/us

© 1996 Prentice-Hall, Inc. All rights reserved. 277

 NOTES

278
 OP-AMP COMMON-MODE
3T
REJECTION

PURPOSE AND BACKGROUND

The purpose of this experiment is to measure the common-mode re-

jection of a 741 operational amplifier. If the same signal is applied
simultaneously to both inputs, called the common-mode input, then
the output voltage of an ideal op-amp should be zero. Since oper-
ational amplifiers are not ideal devices, a small but finite output
voltage will be present when both the input voltages are the same.
The ratio of the common-mode input voltage to the generated out-
put voltage is termed the common-mode rejection, or CMR, and is
expressed in decibels. The higher the CMR, the better the rejection
and the smaller the output voltage.
Text References: 12-2, The Differential Amplifier; 12-3,
Op-Amp Parameters.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 741 op-amp (8-pin mini-DIP)

Two 100 Two 0-15 V de power supplies
10 kO VOM or DMM (preferred)
Two 100 kD Signal generator
100-kQ potentiometer, or Dual trace oscilloscope
10-turn trim-pot [] Breadboarding socket 279
 USEFUL FORMULAS

Differential amplifier voltage gain

hey (where Ry = Ry and Re = Ra)

Ry
Common-mode voltage gain
(2) Ae = VoutCen)

Vinten

dB common-mode rejection
Aya)
(3) CMR (dB) = 20 log |——
cm

PROCEDURE

Vout( cm)
©

CGH
Oscilloscope
CHa

FIGURE 31-1 Schematic diagram ofcircuit.

1. Wire the circuit shown in the schematic diagram of Figure 31-1,

and set your oscilloscope for the following approximate settings:
Channel 1: 2 V/division, ac coupling
Channel 2: 0.02 V/division, ac coupling
Time base: 5 ms/division
2. Apply power to the breadboard. Adjust the input voltage, called
the common-mode input voltage, Viyiem), to 10 V peak-to-peak
at a frequency of approximately 60 Hz. You should make this
voltage setting as accurate as possible.
280
OFFSET NULL (+) ®@

FIGURE 31-2 Pin diagram of 741 op-amp.

3. Using a VOM or DMM, now measure the rms common-mode

input and output voltages, recording your results in Table 31-1.
From the common-mode input and output voltages, calculate the
common-mode voltage gain, A.,, (Equation 2), recording this
result in Table 31-1.
4. This circuit is called a difference, or differential amplifier, and
the differential voltage gain, A,,,), is based upon all four resis-
tors, as given in the “Useful Formulas” section of this experi-
ment (Equation 1). First calculate the differential voltage gain,
and then use it to calculate the common-mode rejection (in deci-
bels) for your 741 operational amplifier. Record your result in
Table 31-1.
Most manufacturers of the 741 op-amp cite a minimum
CMR of 70 dB, although a value of 90 dB is typical.
5. In some instances, the CMR may be improved by trimming one
or more resistors of the circuit of Figure 31—1. Disconnect the
signal generator and dc power to the circuit. Replace R4 witha
series connection of a 100-kQ potentiometer and a 10-k) resis-
tor.
6. Apply power to the breadboard and again adjust the common-
mode input voltage to 10 V peak-to-peak at a frequency of 60
Tz
7. Using the oscilloscope to observe the output of the operational
amplifier at pin 6, adjust the 100-kQ potentiometer for a mini-
mum output voltage.
8. Repeat Steps 3 and 4 using a differential gain of 1000. Record
your results in Table 31—2. Do you see an improvement in the
CMR?

WHAT YOU HAVE DONE

This experiment demonstrated how to measure the common-mode

rejection (CMR) of a 741 operational amplifier and how to maximize
the CMR of a difference amplifier. For an ideal operational amplifier,
the common-mode output voltage should be zero, giving an infinite
281
 value for the CMR. The ratio of the common-mode input voltage
to the generated output voltage is termed the common-mode rejec-
tion ratio, or CMRR. When expressed in decibels, it is called the
common-mode rejection (CMR). The higher the CMR, the better the
rejection, resulting in a smaller output voltage.

282
Name Date

OP-AMP COMMON-MODE REJECTION

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. Alll rights reserved. 283

 Namé< 3-4
SS eee Date

DATA FOR EXPERIMENT 31

TABLE 31-1

[ Measured common-mode input voltage, Viniem)

Measured common-mode output voltage, Vouticm)

res common-mode voltage gain, A.»,

Calculated differential voltage gain, A,,q)

Calculated common-mode rejection, CMR

TABLE 31-2

Measured common-mode input voltage, Vincm)

Measured common-mode output voltage, Vouticm)

Calculated common-mode voltage gain, A.»

Calculated differential voltage gain, A,,q)

Calculated common-mode rejection, CMR

284 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 31

1. In a differential amplifier, the signal applied simultaneously to

both inputs is the
(a) differential input (b) noninverting input
(c) inverting input (d) common-mode input
An increase in common-mode rejection means an increase in
the amplifier’s
(a) input impedance (b) frequency response
(c) voltage gain (d) noise immunity
Differential-amplifier common-mode rejection is measured in
(a) V (b) V/s (c) dB (d) V/mV
If the differential voltage gain is 100 and the common-mode
voltage gain is 0.001, the common-mode rejection is
(a) 40 db (b) 60 db (c) 80 db (d) 100 db
For the circuit of Figure 31-1, if the common-mode rejection
ratio is 100,000 : 1 and the input voltage is 10 V peak-to-peak,
the peak-to-peak output voltage is
(a) 0.001 _.V (b) 0.01 V (c) 0.1 V (d) 1V

© 1996 Prentice-Hall, Inc. All rights reserved. 285

 NOTES

286
 OP-AMP INVERTING AND
NONINVERTING AMPLIFIERS

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation of

both inverting and noninverting amplifier circuits using a 741 op-
erational amplifier. Both circuits operate in the closed-loop mode.
The inverting amplifier’s closed-loop voltage gain can be less than,
equal to, or greater than 1. As its name implies, its output signal
is always inverted with respect to its input signal. On the other
hand, the non-inverting amplifier’s closed-loop voltage gain is al-
ways greater than 1, while the input and output signals are always
in-phase.
Text Reference: 12-5, Op-Amp Configurations with Negative
Feedback.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 741 op-amp

eleiskO (8-pin mini-DIP)
(457 kO Two 0-15 V de power
L] Two 10 kO supplies
m2 2 kOe: Signal generator
miraTeko) Dual trace oscilloscope
[J] 100 kO Breadboarding socket 287
 USEFUL FORMULAS

Inverting amplifier closed-loop voltage gain

(a) A, ==—

Noninverting amplifier closed-loop voltage gain

PROCEDURE

1. Wire the inverting amplifier circuit shown in the schematic dia-

gram of Figure 32-1A, and set your oscilloscope for the following
approximate settings:
Channels 1 and 2: 0.5 V/division, ac coupling
Time base: 1 ms/division

CH 2
Oscilloscope
GHut

CH 1
Oscilloscope
CH 2

288 FIGURE 32-1 Schematic diagram of circuits.

OFFSET NULL o. et 5
— INPUT © (~) +Vec
+ INPUT (») (©) OUTPUT
Vee (#4) (4) OFFSET NULL
Pore
FIGURE 32-2 Pin diagram of 741 op-amp.

2. Apply power to the breadboard, and adjust the input voltage to 1

V peak-to-peak and the frequency at 500 Hz. Position the input
voltage above the output voltage on the oscilloscope’s display.
What is the difference between the two signals?
Notice that the output signal is of opposite form, or is in-
verted, compared to the input signal, as shown in Figure 32-3.
The output voltage is then said to be inverted from, or 180° out-
of-phase with, the input, since the positive peak of the output
signal occurs when the input’s peak is negative.
3. Measure the peak-to-peak output voltage. Then determine the
voltage gain and compare it to the expected value, recording
your results in Table 32-1.
The peak-to-peak output voltage should be the same as the
input (1 V), so that the voltage gain is —1. The minus sign
indicates that the output is inverted with respect to the input.
4. Keeping the input signal at 1 V peak-to-peak, change resistor
Ry according to Table 32-1, recording your results as in Step 3.
Each time, disconnect the power supplies and signal generator
before you change the resistor. Do your results agree with those
obtained from the equation for the inverting amplifier voltage
gain (Equation 1)?

Input

Output

FIGURE 32-3 289

 As the results of Table 32-1 indicate, the voltage gain of an
inverting amplifier can be made to be less than 1, equal to 1, or
greater than 1.
Now wire the noninverting amplifier circuit shown in the sche-
matic diagram of Figure 32-1B. Apply power to the breadboard
and adjust the input voltage to 1 V peak-to-peak and the fre-
quency at 400 Hz. Again position the input voltage above the
output voltage on the oscilloscope’s display. What is the differ-
ence between the two signals?
The only difference is that the output signal is /arger than
the input signal, as shown in Figure 32-4. Both signals are
said to be in-phase, since the output signal goes positive exactly
when the input does.

Input

Output

FIGURE 32-4

Measure the peak-to-peak output voltage. Then determine the

voltage gain and compare it to the expected value, recording
your results in Table 32-2.
The peak-to-peak output voltage should be approximately
2 V, so that the voltage gain is 2.
Keeping the input signal at 1 V peak-to-peak, change resistor
Ry according to Table 32-2, recording your results as in Step
6. Each time, disconnect the power supplies and signal gener-
ator before you change the resistor. Do your results agree with
those obtained from the equation for the noninverting amplifier
voltage gain (Equation 2)?
As the results of Table 32-2 indicate, the voltage gain of a
noninverting amplifier can never be less than 1 or equal to 1. It
290 will always be greater than 1.
WHAT YOU HAVE DONE

This experiment demonstrated and compared the operation of the

noninverting and inverting amplifier circuits using the 741 opera-
tional amplifier. Both circuits are termed linear amplifiers, as the
output signal is linearly proportional to its input signal. The invert-
ing amplifier’s closed-loop voltage gain can be less than, equal to, or
greater than 1 and its output signal is always of the opposite polar-
ity, or inverted with respect to its input signal giving a phase shift
of 180°. On the other hand, the noninverting amplifier’s closed-loop
voltage gain is always greater than 1, while the input and output
signals are always in phase.

291
 NOTES

292
INA Neg eS
eee es Date

OP-AMP INVERTING AND NONINVERTING AMPLIFIERS

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 293

 Name Date

DATA FOR EXPERIMENT 32

TABLE 32-1 Inverting amplifier.

Measured Measured Expected Jo

Ry Vea Gain Gain

10 kO

22 kO

TABLE 32-2 Noninverting amplifier.

Measured Measured Expected Yo

Rr View Gain Gain Error

10 kO

22 kD 4

47 kQ

100 kQ

4.7kO
|— Ml
hee |
Le

294 © 1996 Prentice-Hall, Inc. All rights reserved,

NAT Ceo
es ee eS Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 32

1 The circuit of Figure 32—1A is

(a) an inverting amplifier (b) a noninverting amplifier
(c) a differential amplifier (d) a voltage follower
The voltage gain of an inverting amplifier can be
(a) less than 1 (b) equal to 1
(c) greater than 1 (d) all of the above
The output signal of an inverting amplifier is out-of-phase with
its input signal by
(a) 0° (b) 90° (c) 180° (d) 270°
The voltage gain of a noninverting amplifier can be
(a) less than 1 (b) equal to 1
(c) greater than 1 (d) all of the above
The output signal of a noninverting amplifier is out-of-phase
with its input signal by
(a)EOn ee(bye 90> (c) 180° (d) 270°

© 1996 Prentice-Hall, Inc. All rights reserved. 295

 NOTES

296
 OP-AMP COMPARATORS

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation of

noninverting and inverting comparator circuits using a 741 opera-
tional amplifier. A comparator determines whether an input voltage
is greater than a predetermined reference level. Since a compara-
tor operates in an open-loop mode, the output voltage approaches
either its positive or its negative supply voltage.
Text Reference: 14—1, Comparators.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 1N914 (or 1N4148) diode

Two 1 kO LED
A Telce) 2N3904 npn transistor
L] Two 10 kO Two 0-15 V de power
L) 47 kO supplies
100 kQ Signal generator
[] 100-kQD potentiometer Dual trace oscilloscope
741 op-amp (8-pin mini-DIP) Breadboarding socket

297
 USEFUL FORMULAS
Noninverting comparator output

(1) Vout = +Voear when Vin > VRrer

(2) Vout = — Veat when Vin < VRrer
Inverting comparator output
(3) Vout = + Vsar when Vin < Vrer
(4) Vout = —Vsar when Vi, > Vrer

PROCEDURE

+15 V

CH 2
Oscilloscope
Chad

FIGURE 33-1 Schematic diagram of circuits.

298
1. Wire the circuit shown in the schematic diagram of Figure
33—1A, and set your oscilloscope for the following approximate
settings:
Channel 1: 1 V/division, de coupling
Channel 2: 10 V/division, de coupling
Time base: 1 ms/division

OFFSET NULL 2 vey 3

— INPUT S (~) +Vec
+ INPUT (3) OUTPUT
OFFSET NULL

FIGURE 33-2 Pin diagram of 741 op-amp.

2. Apply power to the breadboard, and adjust the input voltage at

3 V peak-to-peak and the frequency at 300 Hz. What is the po-
larity of the output voltage when the input signal goes positive?
When the input goes negative?
When the input signal Vi, is applied to the op-amp’s non-
inverting input, the output signal’s polarity will be the same as
that of the input, so that this circuit is a noninverting compara-
tor. In this case, the reference voltage Vgpr is zero (the inverting
input is grounded). Because of the high open-loop gain of the

Input

FIGURE 33-3

299
 op-amp, the output immediately goes positive when Vj, is
greater than zero volts (Vemr), and vice versa, as shown in
Figure 33-3. This circuit is also referred to as a noninverting
zero-level detector since it detects the polarity of the input
signal.
The maximum output (saturation) voltage, Vsar, for the 741
op-amp is typically 12 V to 14 V when using a 15-V supply.
Disconnect the power and signal leads to the breadboard, and
reverse the input connections to the op-amp so that the input
signal is now connected to the inverting input while the nonin-
verting input is grounded, as shown in Figure 33—1B.
Again apply both the power and signal leads to the breadboard.
Now what is the difference between the operation of this circuit
and that of the circuit used earlier?
Notice that the output of this comparator circuit has a po-
larity that is inverted with respect to the input signal. Such
a circuit is called an inverting comparator. Furthermore, since
the reference voltage (the voltage at the noninverting input) is
zero, this circuit is also referred to as an inverting zero-level
detector. When the polarity of the input signal is positive, the
output voltage equals —Vgar, and vice versa, as shown in Figure
33—4. As can be seen, both circuits are useful in converting sine
waves into square waves.

Input

Output

FIGURE 33-4

Disconnect the power and signal leads from the breadboard, and
wire the circuit shown in Figure 33-1C. Make sure that you have
the 1N914 diode and LED, as well as the npn transistor, wired
correctly.
300
6. Apply power to the breadboard. Depending on the setting of the
potentiometer, the LED may or may not be lit when you connect
the power. If the LED is on, turn the potentiometer past the
point at which the LED is off.
7. With your oscilloscope, measure the voltage at the op-amp’s in-
verting terminal (pin 2), which is the reference voltage Vprp for
the comparator, and record the value in Table 33-1.
8. Now connect the oscilloscope to the op-amp’s noninverting input
(pin 2). While watching the LED, vary the potentiometer just
until the LED lights up. Measure this voltage at pin 3, Vinvon),
and record your result in Table 33-1. How does this value com-
pare with the one you determined in Step 7?
These two values should be nearly the same. When the in-
put voltage V;, at the noninverting input exceeds the compara-
tor’s reference voltage at the inverting input, the op-amp com-
parator’s output switches from its negative saturation voltage
to its positive saturation voltage. This circuit is a noninverting
comparator whose nonzero reference voltage is set by the 10-kQ
and 1-kQ resistors connected as a simple voltage divider. The
transistor-LED circuit connected to the output of the compara-
tor allows you to determine visually whether the input voltage
is greater or less than the reference voltage. If the input voltage
exceeds the reference, the LED is lit.
9. Disconnect the power to the breadboard. Verify the operation of
this noninverting comparator by varying voltage-divider resistor
R, and repeating Steps 6, 7, and 8, according to Table 33-2.

WHAT YOU HAVE DONE

This experiment demonstrated the operation of noninverting and

inverting comparator circuits using a 741 operational amplifier. It
was shown that the basic comparator determines if an input voltage
is greater than a predetermined reference level. Since comparators
detect whether or not its input signal either exceeds or drops below
a given voltage level, they are also referred to as level detectors.
Comparators operate in the open-loop mode, and as a consequence,
the output voltage always approaches either its positive or negative
supply voltage level.

301
 NOTES

302
Name Date

OP-AMP COMPARATORS

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 303

 Naiié= =e ae Se ee eee Date

DATA FOR EXPERIMENT 33

TABLE 33-1 Inverting comparator.

R, Measured Vrrr Measured Vynon)

ae
TABLE 33-2 Noninverting comparator.

Measured Vprr Measured Vion)

304
© 1996 Prentice-Hall, Inc. All rights reserved,
ING Cea
ee ee Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 33

1. The circuit of Figure 33-1A is

(a) an inverting comparator
(b) a noninverting comparator
The reference voltage for the comparator of Figure 33-1A is
(a) OV (b) -15 V
(Cyr Loa. (d) none of the above
For the circuit of Figure 33—1B, if the input voltage is greater
than the reference voltage, the output voltage is approximately
(aje—13 V (b) -3 V (c) +3 V (d) +13 V
For the circuit of Figure 33-1B, if the input signal is a sine
wave, the output signal looks like a
(a) sine wave
(b) sine wave, but inverted with respect to the input
(c) square wave
(d) square wave, but inverted with respect to the input
For the circuit of Figure 33-1C, if R, and Rz are 10 kf), the
LED is lit when the input voltage is
(a) less than —7.5 V
(b) 0V
(c) greater than 7.5 V
(d) any voltage between —7.5 V and +7.5 V

© 1996 Prentice-Hall, Inc. All rights reserved. 305

 NOTES

306
 OP-AMP DIFFERENTIATOR
AND INTEGRATOR

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation of

both a differentiator and an integrator using an op-amp. A differ-
entiator is a circuit that calculates the instantaneous slope of the
line at every point on a waveform. On the other hand, an integrator
computes the area underneath the curve of a given waveform. Dif-
ferentiation and integration are paired mathematical operations in
that one has the opposite effect of the other. For example, if you in-
tegrate a waveform and then differentiate it, you obtain the original
waveform.
Text Reference: 14—3, The Integrator and Differentiator.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 741 op-amp (8-pin mini-DIP)

Ple2-2 kG) [] Two 0-15 V de power
[] Two 10 kO supplies
22 kO Function generator
[] 100 kO [] Dual trace oscilloscope
Capacitors: . Breadboarding socket
[1] 0.0022 pF
0.0047 uF 307
 USEFUL FORMULAS

Differentiator
Output voltage:

a V.= Rec (“Ha

dt
Low-frequency response:
i!
(2) fe =
27RsC
When fin < fc, the circuit acts as a differentiator.
When fin > f:, the circuit approaches an inverting amplifier
with a voltage gain of —Rr/Rs.
Integrator
Output voltage:
1 ie

(3 ) Vont se. Ric

eee |p Vine

Low-frequency response:
Ht
A) a
f 27RsC
When fin > f-, the circuit acts as an integrator.
When fin < fc, the circuit approaches an inverting amplifier
with a voltage gain of —Rs/R}.
For minimum output offset due to input bias currents:

PROCEDURE

1. Wire the differentiator circuit shown in the schematic diagram

of Figure 34—1A, and set your oscilloscope to the following ap-
proximate settings:
Channel 1: 0.5 V/division, de coupling
Channel 2: 0.05 V/division, de coupling
Time base: 0.5 ms/division
Apply power to the breadboard, and adjust the peak-to-peak
voltage of the input triangle wave at 1 V and the frequency at
400 Hz. As shown in Figure 34—3, the output signal is a square
wave that is 180° out-of-phase with the input signal.
Temporarily remove the probe connected to Channel 2 of the os-
308 cilloscope, and adjust the resulting straight line (ground level)
 Oscilloscope
CH 1

Oscilloscope
CH 1

(tr) + Vee

OUTPUT

OFFSET NULL

FIGURE 34-2 Pin diagram of 741 op-amp.

at some convenient position on the screen. Reconnect the probe

to the output of the differentiator, and measure the negative
peak voltage (with respect to ground) of the square wave, re-
cording your result in Table 34-1.
4. Now measure the time duration for which the square-wave sig-
nal is negative (t,). The peak voltage of a square wave that
results from differentiating a triangle waveform having a peak
voltage V,, is given by
2hrC Vu
Vour(peak) = —
ty 309
 Input

Output

FIGURE 34-3

Compute the expected value of the negative peak voltage, and

compare it with the measured value above. Record your results
in Table 34-1.
Change the time base to 0.2 ms/division and Channel 2 to 0.1
V/division. Then adjust the input frequency at 1 kHz. Repeat
Steps 3 and 4. You should find that the peak output voltage
increases.
Now change the input frequency to 30 kHz. Adjust the time
base to 10 ws/division and Channel 2 to 2 V/division. What
does the output signal look like?
Notice that the output signal looks like a triangle wave
with a phase shift of 180°. Why?
Above approximately 15.4 kHz, the circuit ceases to act as
a differentiator since the reactance of the 0.0047-uF capacitor
is now less than that of the 2.2-kQ resistor (Rs). Above this fre-
quency, the circuit functions like that of an inverting amplifier
having a voltage gain of —Rr/Rs.
Measure the peak-to-peak output voltage and determine the
voltage gain, recording your values in Table 34—1. How does
the voltage gain compare to that of an inverting amplifier?
Wire the integrator circuit shown in the schematic diagram of
Figure 34-1B, and set your oscilloscope to the following ap-
proximate settings:
Channels 1 and 2: 0.5 V/division, de coupling
Time base: 20 ps/division
Apply power to the breadboard, and adjust the peak-to-peak
voltage of the input square wave at 1 V and the frequency
310
 at 10 kHz. As shown in Figure 34—4, the output signal is a
triangle wave that is 180° out-of-phase with the input signal.

Input

Output

FIGURE 34-4

10. Temporarily remove the probe connected to Channel 2 of the

oscilloscope, and adjust the resulting straight line (ground
level) at some convenient position on the screen. Reconnect
the probe to the output of the integrator, and measure the
negative peak voltage (with respect to ground) of the triangle
wave, recording your result in Table 34-2.
i b- Now measure the time duration for which the triangle-wave
signal is negative (t,). The peak voltage of a triangle wave
that results from integrating a square waveform having a peak
voltage V,, is given by
= Viatl
Vout(peak) =
RiC
Compute the expected value of the negative peak voltage, and
compare it with the measured value above. Record your results
in Table 34-2.
12. Change the time base to 50 ws/division and Channel 2 to 1
V/division. Then adjust the input frequency to 4 kHz. Repeat
Steps 10 and 11. You should find that the peak output voltage
increases.
13. Now change the input frequency to 100 Hz. Adjust the time
base to 2 ms/division and Channel 2 to 5 V/division. What
does the output signal look like?
Notice that the output signal looks like a square wave with
a phase shift of 180°. Why?
311
 Below approximately 724 Hz, the circuit ceases to act as
an integrator since the reactance of the 0.0022-yF capacitor
is now greater than that of the 100-kQ resistor (Rs). Below
this frequency, the circuit functions like that of an inverting
amplifier having a voltage gain of —Rg/R}.
14. Measure the peak-to-peak output voltage and determine the
voltage gain, recording your values in Table 34-2. How does
the voltage gain compare to that of an inverting amplifier?

WHAT YOU HAVE DONE

This experiment demonstrated the operation of the differentiator

and integrator using 741 operational amplifiers. The differentia-
tor is a circuit that calculates the instantaneous slope of the line
at every point on a waveform. On the other hand, the integrator
generates a signal that is proportional to the accumulative “area
underneath the curve” of a given waveform. Besides these mathe-
matical operations, differentiators and integrators are often used
as signal processing circuits because of their ability to change the
shapes of their input signals.

312
Name Date

OP-AMP DIFFERENTIATOR AND INTEGRATOR

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 313

 Name Date

DATA FOR EXPERIMENT 34

TABLE 34-1 Op-amp differentiator.

Input Measured Peak Expected Peak %

Frequency Output Output Error

>in

TABLE 34-2 Op-amp integrator.

Input Measured Peak Expected Peak Jo

Frequency Output Output Error

314 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 34

1. The maximum frequency below which the circuit of Figure

34-1A acts as a differentiator is approximately
(a) 3 kHz (b) 3.3 kHz (c) 3.6 kHz (d) 15 kHz
When the circuit of Figure 34—-1A is acting as an amplifier, the
voltage gain is
(a) —10 (b) ek (Cyn. (d) 10
The minimum frequency above which the circuit of Figure
34-1B acts as an integrator is approximately
(ade 720iiz (b) 3 kHz (co) ie khiz (d) 3.4 kHz
A 2-kHz triangle waveform is applied to the circuit of Figure
34-1A. The output signal then looks like a
(a) triangle waveform with 0° phase shift
(b) triang!e waveform with 180° phase shift
(ce) square wave with 0° phase shift
(d) square wave with 180° phase shift
A 2-kHz square wave is applied to the circuit of Figure 34—1B.
The output signal then looks like a
(a) triangle waveform with 0° phase. shift
(b) tric-cle ~aveform with 180° phase shift
(ce) squece vave with 0° phase shift
(d) square wave with 180° phase shift

© 1996 Prentice-Hall, Inc. All rights reserved. 315

 NOTES

316
 THE BUTTERWORTH
39
2ND-ORDER
LOW-PASS ACTIVE FILTER

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation and

characteristics of a Butterworth Sallen and Key 2nd-order low-pass
active filter. A Butterworth low-pass filter passes all signals with
frequencies below its cutoff frequency with a constant, or maximally
flat, passband gain. The cutoff frequency is also referred to as the
critical corner, break, or 3-dB frequency. Above this frequency, the
input signal is attenuated at a rate of —12 dB/octave, a rate that is
equivalent to —40 dB/decade for such a 2nd-order filter. Because of
the component values used in this experiment, the passband voltage
gain is ideally fixed at 1.586 (4 dB), although other arrangements
allowing other higher passband gains are possible. In addition, for
input frequencies well below the cutoff frequency, there is no phase
shift between input and output signals.
Text Reference: 16—3, Active Low-Pass Filters.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 741 op-amp (8-pin mini-DIP)

Two 6.8 kO [| Two 0-15 V de power supplies
ail KE) Signal generator
fa.47-kO [] Dual trace oscilloscope
Two 0.033-uF capacitors Breadboarding socket 317
 USEFUL FORMULAS

(1) Ry = Ro and Cr = Co

(2) Rp = 0.586 Ra
Cutoff frequency
iE
3
i 27R1C,

dB frequency response

Vout
(4) Aap 20 log (ee

1.586
ee
(5) Aap = 20 log
b+(F
Le
(2) |

PROCEDURE

1. Wire the circuit shown in the schematic diagram of Figure 35-1.

2. Set your oscilloscope for the following approximate settings:
Channels 1 and 2: 0.2 V/division, ac coupling
Time base: 1 ms/division
3. Apply power to the breadboard, and adjust the input signal volt-
age to 1V peak-to-peak at a frequency of 100 Hz. You should
make this voltage setting as accurate as possible.
4. With the resistor and capacitor values used in this circuit, what
do you expect the cutoff frequency to be?
From the formula for cutoff frequency, the cutoff frequency
is approximately 710 Hz.
5. With the input frequency set at 100 Hz, what is the peak-to-
peak output voltage?
You should find that the output voltage is larger than the
input. You should also observe that both the input and output
signals are essentially in-phase.
6. Now vary the generator’s frequency ( f;,), keeping the input volt-
age constant at 1 V peak-to-peak in order to complete the re-
quired data in Table 35-1. At the higher frequencies, you may
have to increase the input voltage to obtain a measurable out-
put level. Using the dB frequency response formula (Equation
5), calculate the expected dB response using a cutoff frequency
of 710 Hz. Then plot both your experimental and your expected
results on the blank graph provided for this purpose.
318
 Cy

0.033 uF

CH1
Oscilloscope

— INPUT +Vee
im
+ INPUT (‘-)OUTPUT
Vee (1) OFFSET NULL

FIGURE 35-2 Pin diagram of 741 op-amp.

th From your plotted results, you should find that both are parallel.
How closely they are parallel will depend on how close the actual
resistor and capacitor values are to the values shown in the
schematic diagram.
Notice that the filter’s gain at low frequencies is essentially con-
stant up to some point (that is, the passband), after which it
decreases at a linear rate with increasing input frequency. This
linear decrease in gain as a function of frequency is termed the
roll-off. To determine the roll-off of your filter, you must deter-
mine the slope of a line. Using the data in Table 35-1, subtract
the decibel gain measured at 1 kHz from that measured at 10
kHz. The frequency difference from 1 kHz to 10 kHz is one
decade (that is, a factor of 10). Consequently, the roll-off is the
difference
in the decibel gain over a one-decade frequency range.
From your measurements, what is the filter’s roll-off, and how
319
 does it compare with what you should expect for a Butterworth
2nd-order low-pass filter?
You should find that the low-pass filter’s roll-off is nearly
—40 dB/decade, or —12 dB/octave.
9. The filter’s cutoff frequency is the frequency at which the dB
frequency response is 3 dB less than the dB passband gain. This
value is equivalent to an output voltage that is 0.707 times the
input voltage of the filter. From your graph, estimate the filter’s
cutoff frequency, and compare it with the value calculated in
Step 4.
You should have estimated a critical frequency of approxi-
mately 710 Hz. In this case, the passband gain is 1.586, or 4 dB,
so the critical frequency occurs when the filter’s dB response is
alls) 3) Colley, oir ath Gilby,

WHAT YOU HAVE DONE

This experiment demonstrated operation and characteristics of a

Butterworth Sallen and Key 2nd-order low-pass active filter. This
filter passed all signals with frequencies below its critical frequency
with a relatively constant passband gain. Above the critical fre-
quency, the input signal is attenuated at a linear rate. In this ex-
periment, the following parameters were measured: passband gain,
critical frequency, and roll-off. The filter’s frequency response was
graphed from the measured data.

320
et eee a Date

THE BUTTERWORTH 2ND-ORDER LOW-PASS

ACTIVE FILTER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 321

 Name Date

DATA FOR EXPERIMENT 35

TABLE 35-1

Input
Frequency Experimental Expected
(Hz) Vin Vout Vout/ Vin dB Gain dB Gain*
sl
100
ea
200

300

400

500

600

800
oa

1000
=|
|
2000
ery fae eal

4000

5000 Gives
6000

al
8000
a
10,000
eels
“Using a cutoff frequency of 710 kHz, for simplicity.

322 © 1996 Prentice-Hall, Inc. All rights reserved.

 Date

S555 5255525 22522522552 5522===2=22===

S5555555SSssls==s=====2=s2===========
SSSs
S5e5sl22=222=225=222=22=52=2z==2:
Ses Sesssssess 2558 See S335
: ssffrsits EStiocsnsstesscecttects
Sogaeeassesassassees=22=22==2==e=st=2==
Se = a: I a Pa

SSE Tiere SSSSneensscseessseee

‘ SGccnsscessscsseacesescersesteees
ple uniates SE5S=S=S52=:52=:
= === =
: =S== ai ze
aesEEGE oe
re FE Secs Se eesnessesseesaeeeee

a
YI

9 325:2=:2::222=22=!£222z2==5=2=2=2=22=2====2==2==2==S=2=22 SSSS55
8 SSSSS555= S5SS225222=5222=5225==== =a Gsssessesseec== S2=22=
; s£55:55:55:05:05:0::Gcse:sssss:sstissstisteeilsSanes=2s2s252522=52
S5555] 5=s===55205752==55522202 22550500057 ===e=seeeS8E=Se=eeesees
SEPSitrsrsrses zeSete ft a edna a alia
pd SS==sPEPESCEEHEERECESLESEEESCEsteH eecnattsiteeeststet erste
S55552 5522252225752 =5==22=52==2==eS=See=eeeseeseeessaseeszesaee=
DS SEEEEECozorsrshe)
arererersBees eed
Sefeceeet2 HScEEE teesreeet tice
SEES ue So ccersscessssassasesseresseeeeeserszeer2

“ros
sa HH
iM HIit
Mu

oe sce

a So eeeee
Bug UuGBSSREEEEESEESTEEEEELUEEEESS tee seceUUSUUEGUGEUGIGGEE
ciate eae sBESESERSUGUSHRSLOGEREOUOGICIGE
SarseniceSerer
© on Prentice-Hall, Inc. All rights reserved. 323
Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 35

1. For the low-pass filter circuit of Figure 35-1, if R, and R,

are 10 kQ, the critical frequency is approximately
(a) 240 Hz (b) 340 Hz (c) 480 Hz (d) 600 Hz
2. Within the filter’s passband, the voltage gain is approximately
(a) 1 (b) 1.5 (C)Eo (d) 10
3. Within the filter’s passband, the output signal is out-of-phase
with the input signal by approximately
(a) 0° (b) 45° (cye90" (d) 180°
4. Beyond the filter’s cutoff frequency, the response varies linearly
at a rate of
(a) —6 dB/octave (b) —12 dB/octave
(c) —18 dB/octave (d) —20 dB/decade
5. If the cutoff frequency is 500 Hz and the input signal to the
filter has a frequency of 3000 Hz, the dB response is
(a) —3 dB (b) —16 dB (cop Pay celle) (d) —62 dB ( )

324 © 1996 Prentice-Hall, Inc. All rights reserved.

 THE BUTTERWORTH
36
2ND-ORDER
HIGH-PASS ACTIVE FILTER

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation and

characteristics of aButterworth 2nd-order Sallen and Key high-pass
active filter. A Butterworth high-pass filter has an operation that is
opposite that of a low-pass filter. That is, a high-pass filter passes all
signals with frequencies above its cutoff frequency with a constant,
or maximally flat, passband gain. Below this frequency, the input
signal is attenuated at a rate of 12 dB/octave, or 40 dB/decade for
such a 2nd-order filter. Because of the component values used in
this experiment, the passband voltage gain is fixed at 1.586 (4 dB),
although arrangements allowing other higher passband gains are
possible. In addition, for frequencies well above the cutoff frequency,
there is no phase shift between input and output signals.
Text Reference: 16—4, Active High-Pass Filters.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 741 op-amp (8-pin mini-DIP)
[] Two 6.8 kOD Two 0-15 V de power supplies
26k0 am |] Signal generator
LJ) 47 kO Dual trace oscilloscope
CL) Two 0.0047-F capacitors Breadboarding socket 325
 USEFUL FORMULAS

(1) R, = Ro and Gi = Co

(2) Rg = 0.586 Ra
Cutoff frequency
1
Li SS
i 27R1Cy

dB frequency response

Vous
(JAN ep,
dB DAWIog (]
ee

1.586
41/2
(5) Aap = 20 log (L |
1+ fe

PROCEDURE

Wire the circuit shown in the schematic diagram of Figure 36-1.

Set your oscilloscope for the following approximate settings:
Channels 1 and 2: 0.2 V/division, ac coupling
Time base: 0.2 ms/division

Apply power to the breadboard, and adjust the input signal volt-
age to 1 V peak-to-peak at a frequency of 10 kHz. You should
make this voltage setting as accurate as possible.
With the resistor and capacitor values used in this circuit, what
do you expect the cutoff frequency to be?
From the formula for the cutoff frequency, the cutoff fre-
quency is approximately 5 kHz.
With the input frequency set at 10 kHz, what is the peak-to-
peak output voltage?
You should find that the output voltage is larger than the
input. You should also observe that both the input and output
signals are essentially in-phase.
Now vary the generator’s frequency (f;,,), Keeping the input volt-
age constant at 1 V peak-to-peak in order to complete the re-
quired data in Table 36-1. You may have to increase the input
voltage at the lower frequencies in order to obtain a measurable
output level. Using the dB frequency response formula (Equa-
tion 5), calculate the expected dB response using a cutoff fre-
quency of 5 kHz. Then plot both your experimental and your
326 expected results on the blank graph provided for this purpose.
 6.8 kQ

C, Cy +15 V

Oscilloscope

FIGURE 36-2 Pin diagram of 741 op-amp.

7. From your plotted results, you should find that both are parallel.
How closely they are parallel will depend on how close the actual
resistor and capacitor values are to the values shown in the
schematic diagram.
8. Notice that the filter’s gain at high frequencies is essentially
constant from some point (that is, the passband), before which
it increases at a linear rate with increasing input frequency.
This linear increase in gain as a function of frequency is termed
the roll-off. To determine the roll-off of your filter, you must
determine the slope of a line. Using the data in Table 36-1,
subtract the dB gain measured at 100Hz from that measured
at 1 kHz. The frequency difference from 100 Hz to 10 kHz is
one decade (that is, a factor of 10). Consequently, the roll-off is
the difference in the dB gain over a one-decade frequency range.
From your measurements, what is the filter’s roll-off, and how
does it compare with what you should expect for a Butterworth
2nd-order high-pass filter? 327
 You should find that the high-pass filter’s roll-off is nearly
40 dB/decade, or 12 dB/octave.
9. The filter’s cutoff frequency is the frequency at which the dB
frequency response is 3 dB less than the dB passband gain. This
value is equivalent to an output voltage that is 0.707 times the
input voltage of the filter. From your graph, estimate the filter’s
cutoff frequency, and compare it with the value calculated in
Step 4.
You should have estimated a critical frequency of approx-
imately 5 kHz. In this case, the ideal passband gain is 1.586,
or 4 dB, so the critical frequency occurs when the filter’s dB
response is 4 dB — 3 dB, or +1 dB.

WHAT YOU HAVE DONE

This experiment demonstrated operation and characteristics of a

Butterworth Sallen and Key 2nd-order high-pass active filter. This
filter passed all signals with frequencies above its critical frequency
with a relatively constant passband gain. Below the critical fre-
quency, the input signal is attenuated at a linear rate. In this ex-
periment, the following parameters were measured: passband gain,
critical frequency, and roll-off. The filter’s frequency response was
graphed from the measured data.

328
Name Date

THE BUTTERWORTH 2ND-ORDER HIGH-PASS

ACTIVE FILTER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

329
© 1996 Prentice-Hall, Inc. All rights reserved.
 Name

DATA FOR EXPERIMENT 36

TABLE 36-1
—
Input
Frequency Experimental Expected
(Hz) Vian Vent Vout / Vin dB Gain dB Gain*

100 15,

200

300

400

500

600

800 |

pe 1000

2000

4000
moe —|
5000

6000

8000

10,000 |

“Using a cutoff frequency of 5 kHz, for simplicity.

330 © 1996 Prentice-Hall, Inc. All rights reserved.

INS Te ee ee ae Date

DATA FOR EXPERIMEN

re
COO
YY
DW
A

oo taeoo
i _
Se
a po ST es SETHE
Soe L
saan
CET
A
oo
~
n

os

i)

© ce Prentice-Hall, Inc. All rights reserved. 331

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 36

1. For the high-pass filter circuit of Figure 36-1, if C; and Cy» are
0.001 uF, the critical frequency is approximately
(a) 8 kHz (b) 12 kHz (c) 16 kHz (d) 23 kHz
2. Within the filter’s passband, the voltage gain is approximately
(a) 1 (b) 1.5 (c) 5 (d) 10
3. Within the filter’s passband, the output signal is out-of-phase
with the input signal by approximately
(a) 0° (b) 45° (c) 90° (d) 180°
4. Below the filter’s cutoff frequency, the response varies linearly
at a rate of
(a) 6 dB/octave (b) 20 dB/decade
(c) 40 dB/decade (d) 60 dB/decade
5. If the cutoff frequency is 2000 Hz and the input signal to the
filter has a frequency of 100 Hz, the dB response is
(a) —3 dB (b) —22 dB (c) —52 dB (d) —104 dB ( )

332 © 1996 Prentice-Hall, Inc. All rights reserved.

 THE ACTIVE BAND-PASS
3/
FILTER

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation and

characteristics of amultiple-feedback active band-pass filter. Band-
pass filters pass all input signal frequencies within a given range,
called the bandwidth, while rejecting those frequencies outside this
range. The bandwidth encloses a single frequency at which the out-
put voltage is a maximum, called the center frequency.
The multiple-feedback band-pass filter is only one of a number
of possible band-pass filter circuits which, unlike the “twin-T” band-
pass filter, enable one to specify individually the center frequency
(fio), gain (A,), and quality factor (Q). Because of its simplicity, it
is limited for Qs less than 10.
Text Reference: 16—5, Active Band-Pass Filters.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): |] 741 op-amp (8-pin mini-DIP)

Py 1) KO Two 0-15 V de power supphes
20K Signal generator
[1 68 kO . Dual trace oscilloscope
180 kO |] Breadboarding socket
_] Two 0.0J-uF capacitors 333
 USEFUL FORMULAS

Center frequency

Cfo = cass eee

ae i
© OnC \ Ri RRs

here
where Ry
1 =
Q
——~+—
Dn PANG

R — Q
“Ir foC(2Q2 — Go)
Q
tae
R —

Center frequency voltage gain

(2) ) Aj R3
Ao = —
OR,

where Ay must be less than 2Q?

Shifting the center frequency with constant center frequency gain
and bandwidth
2
(3) Ri = Ra( |
0

Center frequency from upper and lower 3-dB frequencies

(A) fo = fern
Quality factor
fo
(OQ) eames
[eyo

PROCEDURE

1. Wire the circuit shown in the schematic diagram of Figure

37-1, and set your oscilloscope for the following approximate
settings:

Channels 1 and 2: 0.2 V/division, ac coupling

Time base: 0.2 ms/division
2. Apply power to the breadboard, and adjust the output of the
signal generator at 1 V peak-to-peak at a frequency of 1 kHz.
3. Now vary the signal generator’s frequency to the point at which
the output voltage of the filter, as displayed on Channel 2 of
the oscilloscope, reaches its maximum peak-to-peak amplitude.
Measure this peak-to-peak output voltage, and then determine
334 the center frequency voltage gain Viut/ Vin, recording your data
 HZ
Oscilloscope
CH

OUTPUT

OFFSET NULL

FIGURE 37-2 Pin diagram of 741 op-amp.

in Table 37-1. How does the measured voltage gain compare

with the expected value (Equation 2)?
The measured center frequency voltage gain, which is
based on resistors R; and R3, should be about 1.32. If your
value is 10% or more off from this value, either you are not
at the filter’s center frequency, as evidenced by a maximum
output voltage, or the resistors you are using are significantly
different from their rated values. You should also observe that
the input and output waveforms are exactly 180° out-of-phase
at this center frequency. Such is the case because the input
signal eventually is connected to the op-amp’s inverting input
so that the output signal will be inverted from, or 180° out-of-
phase with, the input signal.
4. Using your oscilloscope, determine the filter’s output fre-
quency without disturbing the frequency setting of the signal
generator, recording your result in Table 37-1. How does this
value compare with the expected value (Equation 1)? 335
 The band-pass filter’s center frequency is based on the val-
ues of both capacitors and all three resistors, and it should be
near 737 Hz.
Now determine the filter’s bandwidth by measuring both the
upper and lower 3-dB frequencies at which the peak-to-peak
output voltage drops to 0.707 times the value at the center
frequency. To do this easily, you should set the signal generator
first to the filter’s center frequency. Then, without changing the
output frequency, adjust the signal generator’s output voltage
so that the output voltage of the filter is 1.0 V. Make this setting
as accurate as possible.
Then decrease the signal generator’s frequency, and stop
at the point at which the output voltage drops to 0.71 V peak-
to-peak (1.0 V x 0.707 = 0.71). Determine the frequency at
this point, called the lower 3-dB frequency (f,), and record
your result in Table 37-2.
Continue to decrease the input frequency. Does the output volt-
age increase or decrease?
Notice that the peak-to-peak output voltage of the band-
pass filter decreases as the input frequency moves away from
the filter’s center frequency.
Now increase the signal generator’s frequency beyond the cen-
ter frequency, and stop at the point at which the filter’s peak-to-
peak output voltage is again 0.71 V. Determine the frequency
at this point, called the upper 3-dB frequency (fy), and record
this result in Table 37-2.
Subtract the lower 3-dB frequency from the upper 3-dB fre-
quency, obtaining the 3-dB bandwidth of the filter. Record your
result in Table 37—2. Using this bandwidth and the center fre-
quency experimentally found in Step 4, calculate the filter’s Q,
or quality factor, and record your result in Table 37-2.
Within 10%, you should determine a filter Q of 4.17. If not,
repeat Steps 3 through 7, carefully measuring the voltages and
frequencies.
From the two measured 3-dB frequencies, you can determine
the filter’s center frequency by taking the geometric average:
fo = fat ae
How does your result obtained from this equation compare with
the value you determined in Step 4?
10. Disconnect both the power and the signal leads from the bread-
board, and replace the 2.7-kO resistor (R2) with a 1.5-kQ resis-
tor. Connect the power and signal generator to the breadboard.
i Repeat steps 3 through 9 to determine the filter’s center fre-
quency voltage gain (Ao), center frequency (fo), bandwidth,
and Q. Record your results in Table 37-3.

336
12. When the value of Resistor Ry is changed, how does the new
center frequency that you determined in Table 37-3 compare
with the expected value obtained from Equation 3 in the “Use-
ful Formulas” section of this experiment?
If you have performed this experiment correctly, you should
find that when resistor Ry is changed, the bandwidth and the
center frequency gain remain the same, while the filter’s cen-
ter frequency is inversely proportional to the value of Ry. For
example, if Rg changes from 2.7 kO to 1.5 kQ, the new center
frequency should be

2.7 kO
1/2
fo = (7387 He) = 988 Hz
1.5 kO
Since the center frequency changes, @ also changes.
13. Set the input voltage to the filter at 1 V peak-to-peak, and
vary the signal generator’s frequency according to Table 37-4.
Then plot the dB gain response for all measured frequencies on
the blank graph provided for this purpose. From this graph,
you should be able to estimate the filter’s center frequency,
bandwidth, and Q, and these values should compare favorably
with those in Table 37-3.

WHAT YOU HAVE DONE

This experiment demonstrated operation and characteristics of a

multiple-feedback band-pass active filter. This filter passed all sig-
nals within a given range about the filter’s center frequency while
rejecting those frequencies outside this range. In this experiment,
the following parameters were measured: center frequency gain,
center frequency, bandwidth, and Q. In addition, it was shown how
to vary the filter’s center frequency with a single resistor while keep-
ing the bandwidth and center frequency gain constant. The filter’s
frequency response was graphed from the measured data.

337
 NOTES

338
Name Date

THE ACTIVE BAND-PASS FILTER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 339

 Name Date

DATA FOR EXPERIMENT 37

TABLE 37-1

Input voltage, Vi, V

Output voltage, Vout V

Center frequency voltage gain, Ao

Center frequency, fo Hz

TABLE 37-2

Lower 3-dB frequency, fr, lal

Upper 3-dB frequency, fy Hz

3-dB bandwidth, BW Hz

Quality factor, Q

TABLE 37-3

Input voltage, V;, V

Output voltage, Vou Wi

Center frequency voltage gain, Ay

Center frequency, fo Hz

Lower 38-dB frequency Hz

Upper 3-dB frequency Hz

3-dB bandwidth, BW Hz

Quality factor, Q

340 © 1996 Prentice-Hall, Inc. Alll rights reserved.

Nate ee Date

TABLE 37-4
——
Input
Frequency Measured
(Hz) Vis Vout Vet) Vin dB Gain

1000

it
2000

a
4000

8000

| 10,000 |

© 1996 Prentice-Hall,
Inc. All rights reserved. 341
 NOTES

342
ING Tn Cree ner = Syewe Date

DATA FOR EXPERIMENT 37

1 = SS ee = = = —
98 3522225
=ssse=
5222222222527 /222222=2222==2222==5222=:522
2 ee Zec= 22 o2525222=22 z=
555525 5:s!:!:5r5212r72 S55s22522=====5== SEE
, S55ic2=ss:2====22 S55ESE5c2==55e/ 55508558 S8S0SSeSerse=eree
ere sf5arsuaratifititetetititi: Sosssnaseasssslss2=ses=e==e=aeee2
au SS=SneSessessseeesssee ae Sirsssss joes BEE
4 —SEES ee
S25555502 055555227 ===5527 25555227 25255522 255222 225505 ae
fy == 22 525252=222=2525=5=====2 sr stritis: SESSSEESSEESEESSESSSESSSE
= ese eee Hiltseer ets
Seeeeceeoee ee Be sieeeresssissis

a oe
ii =
222855555222 as
qunsisti siiieuitsre
He Hy
nae
S555ssssss222=22=2==222=2 s5nSEe==:wae

EEE
eoeee
eeoH
aeee
: Ze of:
scsaiitts
see
H a EES
.= sees

sn EERE cea #5:

+ —} tr ro — Ss = -—+—}+—_ + + _+ +++ + + 47
9 =

o BaeSaseae SSSSSSS=S=SS=s= Fugu ===

: SEEE== Zee SSHSSsislisssssssssss=222s2222=====2
Se Seif]ssif0tssddlocsastgcssd ocst#liscaitieststlcts
= = oocstosSo = = SSssse =o oa SS2eee5) tet =e

ag=ie caaeseescez
SES EGSESL BEE EEEotEEE EERE EERE EERE EEE EEE
serie
7zeeeseresseeer
4 === SSSSSSsSSSS=== =2ss22===2===S s===Z=se
==5====
S55:5:==2552=s25==5=5:55=2 a

: Be Gcee2seesass=2ess22=ee==eS2ee==ee=e
seGcssSoceesee lesserseer
cesteese fail
aaa Sescecgeezccsrseerssoccccsseees
tH cy =

2 = cesses

FECES air

co iE
snne Hy H
© 1996 Prentice-Hall, Inc. All rights reserved.
le 343
Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 37

1: The center frequency for the band-pass filter circuit of Figure

37-1 with the components shown is approximately
(a) 350 Hz (b) 500 Hz (c) 625 Hz (d) 740 Hz
The Q for the circuit of Figure 37—1 with the components shown
is approximately
(a) 2 (b) 4 (c) 6 (d) 8
At the filter’s center frequency, the output signal is out-of-phase
with the input by
(a) 0° (b) 45° (c) 90° (d) 180°
If the center frequency is 1000 Hz and the Q is 5, the 3-dB
bandwidth is
(a) 100 Hz (b) 200 Hz (c) 300 Hz (d) 500 Hz
For the circuit of Figure 37-1, if Ry is changed to a lower value,
(a) the center frequency gain increases
(b) the bandwidth decreases
(c) the center frequency increases
(d) all of the above ( )

344 © 1996 Prentice-Hall, Inc. All rights reserved.

 THE ACTIVE
38
BAND-STOP FILTER

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation and

characteristics of an active notch, or band-stop, filter. The operation
of a band-stop filter is opposite that of a band-pass filter in that the
notch filter rejects all input signal frequencies within a given range,
called the bandwidth, while passing those frequencies outside this
range. The bandwidth encloses a single frequency where the output
voltage is a minimum, called the center, notch, or null frequency.
This experiment uses a multiple-feedback band-pass filter with
a two-input summing amplifier to create a band-stop filter. This
filter is only one of a number of possible band-stop filter circuits.
Text Reference: 16—6, Active Band-Stop Filters.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): Two 741 op-amps (8-pin

ae Zak) mini-DIP)
Two 12 kQ _] Two 0-15 V de power supplies
1b kQ Signal generator
El68:kD~. Dual trace oscilloscope
180 kO |] Breadboarding socket
Two 0.01-uF capacitors 345
 USEFUL FORMULAS

Notch frequency
i (Z Ro )
(1) fo =
2rC \ Ri RoR3

where R; =
Q
277 foAoC

Rp = @
OmfyC(2Q2 — Ao)
ene
LS thoC
For unity passband voltage gain

(2) Ao = fis
2R}
where Ru = AoRs and Rg = Rs
Quality factor

@) @ = fo
fi fh

PROCEDURE

1: Wire the circuit shown in the schematic diagram of Figure

38-1, and set your oscilloscope for the following approximate
settings:
Channels 1 and 2: 0.2 V/division, ac coupling
Time base: 0.2 ms/division
Apply power to the breadboard, and adjust the output of the
signal generator at 1 V peak-to-peak at a frequency of 1 kHz.
Now slowly decrease the signal generator’s frequency to the
point at which the output voltage of the filter, as displayed
on Channel 2 of the oscilloscope, reaches its minimum peak-
to-peak amplitude. You will need to increase the sensitivity of
Channel 2 to do this. Measure the peak-to-peak output voltage.
Then determine the center frequency voltage gain Vout/ Vin (in
decibels), sometimes called the notch depth or depth of null,
and record your data in Table 38-1. You should measure a
notch depth of at least —25 dB.
If you do not have a notch depth of at least —25 dB, you
are probably not at the filter’s center frequency, as evidenced
by a minimum output voltage. Also, observe that the input and
346 output waveform are exactly in-phase at this center frequency.
 CH 2
Oscilloscope
CHEE

FIGURE 38-1 Schematic diagram of circuit.

FIGURE 38-2 Pin diagram of 741 op-amp.

4. Using your oscilloscope, determine the filter’s center frequency

without disturbing the frequency setting of the signal genera-
tor, recording your result in Table 38-1. How does this value
compare with the expected value (Equation 1)?
The notch filter’s center frequency is based on the values
of both capacitors and all three resistors, and it should be near
FW x,
5. Continue to decrease the input frequency. Does the output volt-
age increase or decrease?
Notice that the peak-to-peak output voltage of the notch
filter increases as the input frequency moves away from the fil-
ter’s center frequency. Eventually, the output voltage remains
essentially constant (the passband).
6. Set the frequency of the signal generator at 100 Hz and the
oscilloscope’s Channel 2 sensitivity to 0.2 V/division. Measure
the peak-to-peak output voltage of the filter, and determine the
passband voltage gain, recording your results in Table 38—2. 347
 Now determine the filter’s bandwidth by measuring both the
upper and the lower 3-dB frequencies at which the peak-to-
peak output voltage drops to 0.707 times the value of the
output voltage in the filter’s passband. To do this easily, first
you should set the signal generator at 100 Hz. Then, without
changing the output frequency, adjust the signal generator’s
output voltage so that the output voltage of the filter is 1.0 V.
Make this setting as accurate as possible.
Then decrease the signal generator’s frequency, and stop
at the point at which the output voltage drops to 0.71 V peak-
to-peak (1.0 V x 0.707 = 0.71). Determine the frequency at this
point, called the lower 3-dB frequency (f;,), and record your
result in Table 38-2.
Continue to decrease the input frequency. Does the output volt-
age increase or decrease?
Notice that the peak-to-peak output voltage of the notch
filter decreases as the input frequency moves toward the filter’s
center frequency.
Now increase the signal generator’s frequency beyond the cen-
ter frequency, and stop at the point at which the filter’s peak-to-
peak output voltage is again 0.71 V. Determine the frequency
at this point, called the upper 3-dB frequency (f;,), and record
this result in Table 38-2.
10. Subtract the lower 3-dB frequency from the upper 3-dB fre-
quency, obtaining the 3-db bandwidth of the filter. Record your
result in Table 38-2. Using this bandwidth and the center fre-
quency found experimentally in Step 4, calculate the filter’s Q,
or quality factor, and record your result in Table 38-2.
Within 10 percent, you should determine a filter Q of 4.17.
If not, repeat Steps 3 through 9, carefully measuring the volt-
ages and frequencies.
11. From the two measured 3-dB frequencies, you can determine
the filter’s center frequency by taking the geometric average:
fo = (fifa)
How does your result obtained from this equation compare
with the value you determined in Step 4?
12. Vary the signal generator’s frequency according to Table 38-3,
and plot the dB gain for all measured frequencies on the blank
graph provided for this purpose. From this graph, you should
be able to estimate the filter’s center frequency, bandwidth,
and Q.

348
WHAT YOU HAVE DONE

This experiment demonstrated operation and characteristics of a

multiple-feedback band-stop (notch) active filter. This filter rejected
all signals within a given range about the filter’s center frequency
while passing those frequencies outside this range. In this experi-
ment, the following parameters were measured: passband gain, cen-
ter (notch) frequency, bandwidth, and Q. The filter’s frequency re-
sponse was graphed from the measured data.

349
 NOTES

350
Name Date

THE ACTIVE BAND-STOP FILTER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 351

 INA Cpe Se ee ee ee ee eee Date

DATA FOR EXPERIMENT 38

TABLE 38-1

Input voltage, Vin V

__|
Output voltage, Vout V

Notch Depth dB

Center frequency, fo Hz

TABLE 38-2
ee
ee
Pass-band voltage gain, Ao

Lower 3-dB frequency, f, Hz

Upper 3-dB frequency, fx Hz

3-dB bandwidth, BW Hz

Quality factor, Q

352 © 1996 Prentice-Hall, Inc. All rights reserved.

IND Cpe eee ee Pewee ee Date

TABLE 38-3

|
Input
Frequency Measured
(Hz) Vin Vout Vout/ Vin dB Gain

100 EN,

200

400

600
stecwbel
700

750 4

© 1996 Prentice-Hall, Inc. All rights reserved. 353

 NOTES

354
Nan Ceeee ee Date

DATA FOR EXPERIMENT 38

=
=
=

Hin
cee =

a
2 hee as ea

ce
saree
scestiecs____ a seececceseeeess
Seeerreeriiiz
==s5sas=sassssceecce oe
== stat SEES5555552===5 SE5zaee===2
a re HEHE sce
a oo
ee flagoS

|a __
i
1
© 1996 Prentice-Hall, Inc. All rights reserved. 355
Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 38

1. The notch frequency of the filter circuit of Figure 38-1 with the
components shown is approximately
(a) 350 Hz (b) 500 Hz (c) 625 Hz (d) 740 Hz
The Q for the circuit of Figure 38-1 with components shown is
approximately
(a) 2 (b) 4 (c) 6 (d) 8
At the filter’s notch frequency, the output signal is out-of-phase
with the input by
(a) 0° (b) 45° (c) 90° (d) 180°
In the filter’s passband, the voltage gain is approximately
(a) 0 (b) 1 (c) 2 (d) 4
From your filter response curve, the maximum rejection of the
input signal occurs at
(a) frequencies within the passband
(b) the lower 3-dB frequency
(c) the notch frequency
(d) the upper 3-dB frequency ( )

356 © 1996 Prentice-Hall, Inc. All rights reserved.

 THE PHASE-SHIFT
39
OSCILLATOR

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the design and

operation of an op-amp phase-shift oscillator. By providing three
RC networks having a total phase shift of 180° as positive feedback
to the input of an inverting amplifier, oscillation results. The total
phase shift of the amplifier and that of the phase-shift network is
0°, and the loop gain is unity. The sinusoidal output of the oscillator
has a peak-to-peak voltage equal to the difference between the op-
amp positive and negative saturation voltages.
Text Reference: 17-3, Oscillators with RC Feedback Circuits.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 741 op-amp (8-pin mini-DIP)

Three 1 kQ [] Two 0-15 V de power
27 KO supplies
L] 5-kO potentiometer Dual trace oscilloscope
Three 0.1-uF capacitors Breadboarding socket

357
 USEFUL FORMULAS

Output frequency
il
) fg = —————=
f 27RC ./6

For oscillation
)Re/R =

PROCEDURE

Output
O CH1
Oscilloscope

0.1 uF sla eed

fies ie

FIGURE 39-1 Schematic diagram of circuit.

OFFSET NULL 8 ey i
+Vee

FIGURE 39-2 Pin diagram of 741 op-amp.

358
Wire the circuit shown in the schematic diagram of Figure 39-1
and set your oscilloscope to the following approximate settings:
Channel 1: 5 V/division, ac coupling
Time base: 0.5 ms/division
After you have checked all connections, apply the +15-V power
supply connections to the breadboard.
Depending on the setting of the 5-kQ potentiomenter, the cir-
cuit may or may not be oscillating when power is applied. If a
sine wave is not displayed on the oscilloscope, carefully adjust
the 5-kQ potentiometer until a sine wave starts to appear on
the oscilloscope’s display. If you continue to increase the resis-
tance of the potentiometer, you should observe that the peaks
of the sine wave become clipped and that the output frequency
becomes lower. Adjust the potentiometer to the point at which
the circuit just sustains oscillation.
On the other hand, if a sine wave is seen when power is
applied on the breadboard, carefully decrease the resistance of
the potentiometer to obtain the best-looking sine wave.
Using your oscilloscope’s time base set at approximately 0.2
ms/division, measure the output frequency of the phase-shift
oscillator, recording your result in Table 39-1. Compare this
value with the expected frequency found using Equation 1 given
in the Useful Formulas section of this experiment.
Disconnect the power from the breadboard and carefully remove
and measure the total resistance (R,) of the 27-kQ resistor and
of the setting of the series 5-kQ2 potentiometer that produced
oscillation. Record the value in Table 39-1. At the oscillation
frequency set by the three RC networks, 1/29 of the output sig-
nal is fed back to the input of the op-amp. For the loop gain to be
unity, the voltage gain of the inverting amplifier must then be
29, which implies that the feedback resistor Ry must be equal
to 29R. How does the sum of the 27-kQ resistor and setting of
the 5-kQ potentiometer compare with the 1-kQ resistors of the
phase-shift network?

359
 WHAT YOU HAVE DONE

This experiment demonstrated the design and operation of a phase-

shift oscillator using a 741 operational amplifier. This type of oscil-
lator uses three RC networks having a total phase shift of 180° at a
specific frequency as positive feedback to the input of an inverting
amplifier. When the loop gain is 1 by making Ry = 29R, the circuit
then oscillates.

360
Name Date

THE PHASE SHIFT OSCILLATOR

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 361

 Nain ee
eee Ser eee Date

DATA FOR EXPERIMENT 39

TABLE 39-1

Parameter Measured Expected % Error

Output Frequency, f,

Ry 29 kO

362 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 39

AW The RC networks in the oscillator of Figure 39-1 are a form of

(a) positive feedback (b) negative feedback
2. For oscillation, the voltage gain of the amplifier must be
(a) 1/29 (b) 1 (Cee) (d) infinite
The output of the oscillator is a
(a) square wave (b) sine wave (c) triangle wave
(d) sawtooth (e) rectified sine wave
If the values of the three capacitors are increased, the output
frequency will
(a) increase (b) decrease (c) remain the same
If the value of the feedback resistor R; in Figure 39-1 is made
less than 29 kQ,
(a) the circuit continues oscillating at the same frequency
(b) the output frequency increases
(c) the output frequency decreases
(d) the sine wave changes into a square wave
(e) the circuit stops oscillating

© 1996 Prentice-Hall, Inc. All rights reserved 363

 NOTES

364
 THE 555 TIMER ASTABLE
40
MULTIVIBRATOR

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation of

the 555 timer as an astable multivibrator. The 555 timer is an IC
device that allows the formation of an astable multivibrator whose
output frequency and percent duty cycle can be controlled by only
two resistors and a single capacitor. As a practical matter, the output
frequency should be kept less than 200 kHz, while the duty cycle
can range from approximately 50% to 99%.
Text Reference: 17-6, the 555 Timer As an Oscillator.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 555 timer (8-pin mini-DIP)

Ne) 0-15 V de power supply
[| 3.38 kO Dual trace oscilloscope
i aba Breadboarding socket
Capacitors:
0.01 uF
ik ying

365
 USEFUL FORMULAS

Output frequency
1 eee
(1) fo =
(Ry + 2R2)C iF

Percent duty cycle

(22) mp = fate y 190% = | x 100%

R, + 2Ro T

PROCEDURE
425) WY wey Sigha

+5V

FIGURE 40-1 Schematic diagram of circuit.

1. Wire the circuit shown in the schematic diagram of Figure 40-1

using a 5 V supply. Set the oscilloscope to the following approx-
imate settings:
Channel 1: 2 V/division, de coupling
Time base: 0.1 ms/division

GROUND = e ~) + Vee
TRIGGER (wv) ~ DISCHARGE
zt
OUTPUT (~) (©) THRESHOLD
a a
RESET (4) (1) CONTROL VOLTAGE

FIGURE 40-2 Pin diagram of 555 timer.

366
2. Apply power to the breadboard. You should see a waveform that
switches back and forth between ground and the +5-V supply
voltage, similar to that shown in Figure 40-3. Measure the out-
put frequency, and compare it to the value that you would expect
based on the values of R;, Ry, and C (Equation 1). Record your
results in Table 40-1.

555 timer output

Pin 3

FIGURE 40-3 555 timer output, pin 3.

3. Determine the percent duty cycle of the output waveform of the

555 timer astable multivibrator by taking the ratio of the time
that the waveform is at the positive supply voltage to the total
time for one cycle. Then multiply this result by 100%. Compare
your result with the expected value (Equation 2), and record
both in Table 40-1.
4. Disconnect the power from the breadboard, and reverse the 3.3-
kQ and 15-kQ timing resistors so that the 15-kQ resistor is now
R,. Again connect power to the breadboard, and compare the
measured output frequency with the expected value (Equation
1), recording your results in Table 40-1.
5. As in Step 3, measure the percent duty cycle, comparing it to
the expected value (Equation 2), and record your results in
Table 40-1.
Observe that if resistor Rg is much greater than Rj, the
percent duty cycle will approach 50%. On the other hand, if R;
is much larger than Rog, then the percent duty cycle approaches
99%. However, note that when either R; or Rg is changed to
adjust the duty cycle, the output frequency of the 555 timer
also changes. Consequently, the output frequency and the duty
cycle, once set, cannot be adjusted independently.
367
 WHAT YOU HAVE DONE

This experiment demonstrated the operation of the 555 timer as an

astable multivibrator and determined what components controlled
its output frequency and duty cycle.

368
NEL cee ee me ee ne Date

THE 555 TIMER ASTABLE MULTIVIBRATOR

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 369

 Name Date

DATA FOR EXPERIMENT 40

TABLE 40-1

Output Frequency % Duty Cycle

Component
Values Measured | Calculated | % Error |Measured | Calculated | % Error
a Se

Steps 2 and 3:
R, = 3.38 kO

2 = 15 kO

C = O01 jails

Steps 4 and 5:
R, = 15 kQ)

Ro = oe kQ

(CaO, 0B}

370
© 1996 Prentice-Hall, Inc. All rights reserved.
Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 40

ibs For the 555 timer astable multivibrator circuit of Figure 40-1,
the output frequency is approximately
(a) 4.3 kHz (b) 5.5 kHz (c) 6.0 kHz (d) 7.9 kHz
For the 555 timer astable multivibrator circuit of Figure 40-1,
the percent output duty cycle is approximately
(a) 22% (b) 45% (c) 55% (d) 78%
If R, is made much larger than Roz, the percent duty cycle ap-
proaches
(a) 0% (b) 50% (ec) 997%
If Ro is made much larger than Rj, the percent duty cycle ap-
proaches
(a) 0% (b) 50% (c) 99%
When either or both of the timing resistors are changed,
(a) only the output frequency changes
(b) only the percent duty cycle changes
(c) both the frequency and the percent duty cycle change
(d) nothing happens

© 1996 Prentice-Hall, Inc. All rights reserved. 371

 NOTES

372
 THE PHASE DETECTOR
41

PURPOSE AND BACKGROUND

The purposes of this experiment are (1) to demonstrate the oper-

ation and characteristics of a phase detector when both input fre-
quencies are the same (that is, phase lock) and (2) to determine its
conversion gain. The output of a phase detector has a dc voltage,
Vout, that is proportional to the phase difference, Ad, of its two in-
put signals. The ratio of the change of this de output voltage to the
corresponding change in phase is called the conversion gain, Ky, of
the phase detector.
This experiment uses a D-type flip-flop functioning as a phase
detector, which is only one of many possible circuits that may be
used.
Text Reference: 17—7, The Phase-Locked Loop.

REQUIRED PARTS AND EQUIPMENT

7404 TTL hex inverter [] 5-V de power supply

(] 7442 BCD-to-decimal TTL level signal generator
decoder Dual trace oscilloscope
[] 7474 dual D-type flip-flop [] VOM or DMM (preferred)
] 7490 decade counter Breadboarding socket 373
 USEFUL FORMULA

Phase-detector conversion gain

Ke AVout (volts/radian)
Ad

PROCEDURE

+5V +5V +5 V

Savi (Ie)
1 kHz

wee
Phase detector

eee

A: Phase-shift generator Be

Ad Ko Vout
BAP oS
B.

FIGURE 41-1 Schematic diagram of circuit.

1. Wire the circuit shown in the schematic diagram of Figure 41-1.

The 7490 decade counter and the 7442 decoder make a simple
phase-shift generator having ten fixed phase shifts from 0° to
324° in increments of 36°. The 7404 inverter, along with the
7474 flip-flop, make up the phase detector, which has two inputs
(pin 1 of the 7404 and pin 1 of the 7474) and a single output
(pin 5 of the 7474).
Set your oscilloscope to the following approximate settings:
Channels 1 and 2: 2 V/division, ac coupling
Time base: 0.1 ms/division
2. Initially connect pin 1 of the 7474 flip-flop to pin 1 of the 7442
374 decoder, and apply power to the breadboard. Since both phase-
 1 CLEAR
|1] @ 114] VCC (+5 V)

1 PRESET 7474‘ {11] 2 CLOCK

1Q 10] 2 PRESET
iQ [6] [9] 2Q

FIGURE 41-2 Pin diagram of IC devices.

detector inputs are connected to the same point, the phase shift
is naturally 0°. Adjust the output of the square-wave generator
so that the signal of Channel 1 occupies exactly one cycle for the
ten horizontal divisions (that is, an input frequency of 1 kHz).
On the oscilloscope, the two signals should appear as shown in
Figure 41-3. Measure the de output voltage with your VOM or
DMM, and record your result in Table 41-1.

7442 Pin 1

7474 Pin 2

FIGURE 41-3 0° phase shift. 375

 As directed by Table 41-1, in sequence, connect one input of
the phase detector (pin 1 of the 7474 flip-flop) to the different
7442 decoder outputs, while keeping the remaining input of the
phase detector connected to pin 1 of the 7442 decoder. At each
setting, measure the de output voltage using a VOM or DMM,
and record the results in Table 41-1.
Also, observe the change in phase shift of the two input
signals of the phase detector on the oscilloscope each time you
increase the amount of phase shift. For example, the two sig-
nals having a 72° phase shift are shown in Figure 41—4.

7442 Pin 1

7474 Pin 2

FIGURE 41-4 72° phase shift.

Now plot your data, the de output voltage versus phase shift
in degrees, on the blank graph provided for this purpose. Your
graph should resemble a straight line that increases in voltage
as the phase shift increases.
From your data and the graph, compute the conversion gain,
Ky, in terms of V/radian (that is, the “slope of the line”) for
this phase detector. For example, if the de output voltages are
1.0 V and 4.5 V at phase angles of 0° and 324°, respectively,
the conversion gain is

1) = AVout

Ad
(4.0 = L0V) ‘
=e Weare Qc) 8 /radian)

Ky = 0.619 V/radian
For comparison, when this experiment was performed, the con-
376 version gain was determined to be 0.594 V/radian.
WHAT YOU HAVE DONE

This experiment demonstrated the operation and characteristics of

a simple phase detector. A key component of the phase-locked loop,
the output of the phase detector has a dc or average voltage that
is proportional to the phase difference of its two input signals. The
results of this experiment were graphed and the conversion gain of
the phase detector was determined.

377
 NOTES

378
Name Date

THE PHASE DETECTOR

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 379

 ING Goes ae eee Date

DATA FOR EXPERIMENT 41

TABLE 41-1

Phase-Detector Input de Output

(7442 Output Pin) Voltage

il

2 36°

3 72°

[ 4 108°
7
5 144°

6 180°
——

7 216°

9 252°

F 10 288°

Oh 324°

Phase-detector conversion gain, Ky V/radian

380 © 1996 Prentice-Hall, Inc. All rights reserved.

Nair) Ota
eeeee IANS As, Date

DATA FOR EXPERIMENT 41

© 1996 Prentice-Hall, Inc. All rights reserved. 381

IN 6 ee eee Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 41

1. The dc output voltage of the D-type flip-flop phase-detector cir-

cuit of Figure 41-1
(a) increases linearly with phase shift
(b) decreases linearly with phase shift
(c) depends on the frequencies of the two inputs
(d) does not change with phase shift
For the circuit in Figure 41-1, the input signals to the phase
detector are
(a) equal in frequency (b) two different frequencies
(c) harmonically related (d) none of the above
3. The phase-detector conversion gain relates
(a) output and input voltages
(b) output and input frequencies
(c) output voltage and input phase shift
(d) all of the above
If the conversion gain is 2 V/radian and the phase shift is 90°,
the change in output voltage of the phase detector is approxi-
mately
(a) 0.3 V (b) 0.5 V (c) 1.5 V (d) 3.1V ( )
382 © 1996 Prentice-Hall, Inc. All rights reserved.
 THE 567 PHASE-LOCKED
42
LOOP TONE DECODER

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation of

the 567 phase-locked loop tone decoder. The 567 is an IC phase-
locked loop, requiring a minimum of external components to set
the VCO frequency up to a maximum of 500 kHz as well as its
lock range. It is used primarily to indicate whether a sustained
frequency signal or tone is within the loop’s capture range. A voltage
level equal to the supply voltage indicates that the loop is unlocked,
while a zero voltage level indicates a locked system. This experiment
uses an LED to indicate whether the phase-locked loop system is
locked.
Text Reference: 17—7, The Phase-Locked Loop.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/4 W): 567 phase-locked loop

180 0 tone decoder
pieinky [] LED
[] 15 kO 5-V power supply
Capacitors: Function generator
[|] Two 0.1 uF Dual trace oscilloscope
isa: [] Frequency counter
10 pF (] Breadboarding socket 383
 USEFUL FORMULAS

VCO free-running frequency

1st

(3) C3 > 2C

PROCEDURE
1. Wire the circuit shown in the schematic diagram of Figure
42-1. Set your oscilloscope to the following approximate set-
tings:
Channel 1: 1 V/division, ac coupling
Channel 2: 5 V/division, de coupling
Time base: 0.5 ms/division
Apply power to the breadboard, and adjust the output of the
signal generator at approximately 200 Hz with a peak-to-peak
voltage of 2 V. The output of the 567 tone decoder should read
approximately +5 V, and the LED should be lit, indicating that
the phase-locked loop is unlocked.
Now slowly increase the input frequency until the LED goes
out. The output of the 567 should now be approximately zero
volts. Measure the input frequency at this point (f,), and
record this value in Table 42-1.
Slowly increase the input frequency until the LED is again lit,
at which point the output of the 567 will return to approxi-
mately +5 V. Measure the input frequency at this point (f5),
and record this value in Table 42-1.
Now set the input frequency at 2 kHz. The LEE should be
lit, indicating that the loop is unlocked. Slowly decrease the
input frequency until the LED becomes unlit. Measure the
input frequency at this point (f3;), and record this value in
Table 42-1.
Slowly decrease the input frequency until the LED again is
lit. Measure the input frequency at this point (/;), and record
this value in Table 42-1.
Now set the input frequency at approximately 200 Hz. The
LED should be lit. Measure the frequency at pin 5 of the 567
tone decoder with your oscilloscope or frequency counter.
Since the loop is now unlocked, the frequency at pin 5 is the
free-running VCO frequency (fo). Record this frequency in
384 Table 42-1.
 CH 2
Oscilloscope
CH 1

FIGURE 42-1 Schematic diagram of circuit.

a
= Mees) (4) EXTERNAL VCO R
Beceem
FIGURE 42-2 Pin diagram of 567 tone decoder.

8. From your measurements in Steps 3 through 6, you have de-

termined the range of frequencies at which the 567 tone de-
coder will capture and then lock. On increasing frequencies,
the phase-locked loop will capture and lock at f; and will stay
locked until the input frequency exceeds f2. On decreasing fre-
quencies, lock will occur at f3 and will remain until the input
frequency is less than f4. When the loop is locked, the VCO fre-
quency equals the input frequency. When the loop is unlocked,
the VCO frequency equals its free-running frequency fo, which
is determined by resistor R; and by C;. From the known val-
ues of R; and C,, calculate the expected VCO free-running fre-
quency (Equation 1). Compare it with the value found in Step
7, and record this value in Table 42-1. These two values should
agree within 10 percent. The loop’s lock range is the difference,
fo — fs, and is sometimes referred to as the bandwidth. 385
 Determine the percent bandwidth for the 567 tone decoder
using the following formula:

oF Dandi dthee eee x 100

0

Record your result in terms of frequency and percent in Ta-

ble 42-1. For the 567 tone decoder, the percent bandwidth is
typically 14% if the input signal is greater than 200 mV rms.
10. The loop’s capture range is the difference f, — f,; and is never
ereater than the lock range. From your data, compute the cap-
ture range, and record this value in Table 42-1.
11. Starting with an input frequency of 200 Hz, slowly increase
the input frequency until the LED goes out, which is the fre-
quency you measured in Step 3 (f;). During this time, you
should notice that the VCO frequency (pin 5) remains constant
at its free-running frequency, which you determined in Step 7.
While the LED is lit, the loop is not locked and the VCO runs
at its free-runing frequency.
12. Continue to increase the input frequency while the LED is
unlit (the loop is locked). Observe that the output frequency
now equals the input frequency over the lock range.
13. As an optional exercise, change the resistor between pins 5
and 6 to a different value, for example, 10 kO, and repeat the
experiment. You should be able to determine the VCO free-
running frequency and the lock and capture ranges.

WHAT YOU HAVE DONE

This experiment demonstrated the operation of a phase-locked loop

using a 567 phase-locked loop tone decoder. The circuit uses a LED
to indicate whether or not the phase-locked loop system is locked.
The free-running frequency, lock range, capture range, and percent
bandwidth characteristics were measured.

386
IN a Cy eee OO re Date

THE 567 PHASE-LOCKED LOOP TONE DECODER

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 387

 Nainé e
= ae OE
e Date

DATA FOR EXPERIMENT 42

TABLE 42-1

i Fi Hz

fo Hz

fs Hz

fa ie

Measured fo Hz

Expected fo Hz

| % Bandwidth %o

Lock Range Hz

Capture range Hz

388 © 1996 Prentice-Hall, Inc. All rights reserved.

Nae ee
ee Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 42

hk For the component values shown in Figure 42-1, the VCO free-
running frequency is approximately
(a) 200 Hz (b) 400 Hz (c) 600 Hz (d) 800 Hz
When the 567 phase-locked loop tone decoder is locked, the LED
is
(a) unlit (b) lit (c) flashing
If the LED is lit and the input frequency is 200 Hz, the output
frequency of the VCO is approximately
(a) 200 Hz (b) 400 Hz (c) 500 Hz (d) 700 Hz
If the LED is unlit and the input frequency is 500 Hz, the output
frequency of the VCO is approximately
(a) 300 Hz (b) 400 Hz (c) 500 Hz (d) 600 Hz
The phase-locked loop’s capture range is
(a) always greater than the lock range
(b) always less than the lock range
(c) always equal to the lock range

© 1996 Prentice-Hall, Inc. All rights reserved. 389

 NOTES

390
 THE INTEGRATED-CIRCUIT
VOLTAGE REGULATOR

PURPOSE AND BACKGROUND

The purpose of this experiment is to demonstrate the operation of

an integrated circuit (IC) voltage regulator, both as a simple, fixed
voltage regulator and as an adjustable output voltage regulator.
In Experiment 7 voltage regulation is demonstrated using a
zener diode. However, zener diodes in general do not have the ability
to handle large load currents. On the other hand, IC regulators
offer fixed output voltages with typical load regulation of less than
1 percent, internal thermal overload protection, as well as short-
circuit protection.
Text References: 18-1, Voltage Regulation; 18—5, Integrated
Circuit Voltage Regulators; 18-6, Applications of IC Regulators.

REQUIRED PARTS AND EQUIPMENT

Resistors (1/2 W): 1-uwF capacitor

ea A) 7805 +5 V voltage regulator
L] Two 100 0 [] 0-15 V de power supply
RL OLS [] VOM or DMM (preferred)
e220.) _] Breadboarding socket
391
 USEFUL FORMULA

Adjustable-regulator output voltage

VREG
Vout = Vasc + Re [Zer a
Ry
where Ig = 7mA (typical)

PROCEDURE

FIGURE 43-1 Schematic diagram of circuits.

Input <——— +5 Vout

Ground

FIGURE 43-2 Pin diagram of 7805 voltage regulator.

1. Wire the circuit of the fixed output voltage regulators shown in

the schematic diagram of Figure 43—-1A. Connect the 1-uwF ca-
pacitor as closely as possible to the 7805 regulator, as it greatly
improves the transient response and stability of the internal
circuitry of the 7805 regulator.
2. Apply power to the breadboard, and connect a VOM or DMM
across the output of the regulator. Adjust the dc input voltage
to the regulator, and record your result for each of the input
392 voltages listed in Table 43-1. Plot the measured output voltage
versus the input voltage on the graph provided for this purpose.
Such a plot of output voltage versus input voltage of a voltage
regulator is known as its dropout characteristic curve.
From your measurements, observe that the output voltage
of the regulator remains constant when the input voltage ex-
ceeds a given level. When this experiment is performed using
a 7805 regulator, the dc output voltage remains constant at
+5 V whenever the dc input voltage is greater than +7 V. The
difference between the unregulated input and regulated out-
put voltages of the regulator, termed the output-input voltage
differential, is typically 2 V. On the other hand, the dropout
voltage is that voltage below which the regulator circuit stops
regulation. In general, this value is the sum of the regulated
voltage and the output-input voltage differential. For the 7805
+5-V regulator, therefore, the dropout voltage is typically +7 V.
If a type 7812 (+12 V) regulator were used, the expected drop-
out voltage would be +14 V.
Disconnect the power from the breadboard, and wire the cir-
cuit of the adjustable output voltage regulator shown in Figure
43-1B. For this part, you should use 1/2-W resistors.
Apply power to the breadboard, and set the dc input voltage
to the regulator at +15 V. Then measure the dc output voltage
using a VOM or DMM. From the equation given in the “Use-
ful Formulas” section of this experiment, calculate the output
voltage that you would expect to obtain. The typical quiescent
current for the 7805 regulator is 7 mA. Record both the expected
and the measured output voltages Vour in Table 43-2.
Change the value of Ry according to the values listed in Table
43-2. Disconnect the power from the breadboard each time you
change resistors. As in Step 4, record both the expected and
the measured output voltages for each resistance value in Table
43-2. What happens to the output when resistor R2 is 220 0?
You should find that the regulator output voltage is approx-
imately +15 V, which equals its de input voltage. It should be
obvious that it is impossible to obtain an output voltage greater
than the input voltage to the regulator.

393
 WHAT YOU HAVE DONE

This experiment demonstrated operation characteristics of an 7805

(+5 V) integrated-circuit voltage regulator. The IC regulator was
wired both as a simple fixed output voltage regulator as well as an
adjustable voltage regulator. As long as the input voltage remained
approximately 2 V above its rated dc output, the output voltage re-
mained constant. In addition, the voltage regulator’s dropout char-
acteristic curve was graphed from measured data.

394
Namen eS
ees ee Date

THE INTEGRATED-CIRCUIT VOLTAGE REGULATOR

OBJECTIVES/PURPOSE:

SCHEMATIC DIAGRAM:

© 1996 Prentice-Hall, Inc. All rights reserved. 395

 Nae ee
ae eee Date

DATA FOR EXPERIMENT 43

TABLE 43-1 7805 regulator Dropout characteristics.

Input voltage Measured Output Voltage

=|
LV

2 Vi

396 © 1996 Prentice-Hall, Inc. All rights reserved.

Name Date
TABLE 438-2 Adjustable output voltage regulator.

R, = 100 0 Vin
= 15 V

Measured Expected %
Ro Vout Vour Error

oar
|

© 1996 Prentice-Hall, Inc. All rights reserved. 397

 NOTES

398
Name Date

DATA FOR EXPERIMENT 43

© 1996 Prentice-Hall, Inc. All rights reserved. 399

Name Date

RESULTS AND CONCLUSIONS:

REVIEW QUESTIONS FOR EXPERIMENT 43

1. For the 7805 (+5 V) regulator in the circuit of Figure 43-1A,

the output voltage remains constant for input voltages greater
than approximately
(a) +1V (b) 773°. (G) aeons (d) +7 V
2. Using a 7805 (+5 V) regulator in the circuit of Figure 38-14, if
the de input voltage is less than +5 V, the output voltage is
(a) 0 V
(b) +5 V
(c) equal to the de input voltage
(d) an oscillating sine wave
3. For various load resistances, the output voltage of the regulator
circuit of Figure 43-1A
(a) stays essentially constant
(b) increases with increasing load resistance
(c) decreases with increasing load resistance
(d) oscillates
4. Using the adjustable regulator circuit of Figure 43—1B, if the
de input voltage is +15 V, the quiescent regulator current is
7 mA, RA; = 100 , and Re = 100 Q, the the output voltage
is approximately
(ay Ou pee) ace S VYsane (C) iat IRV (CL) eee oa,
5. If Ry is changed to 270 ( in Question 4, the output voltage of
the regulator is approximately
(a) +5 V (b) +10 V (C)iee Lav (d) +20 V ( )
400 © 1996 Prentice-Hall, Inc. All rights reserved.
 APPENDIX
REQUIRED PARTS
AND EQUIPMENT FOR
THE EXPERIMENTS
TABLE A-1 Resistors (1/4 W minimum; all may be 1/2 W).

Quantity Value Radio Shack P/N

iL 10 0 271-1301
1 68 —
2 100 Q 271-1311
il 150 0 271-1312
1 180 0 =
il 22.09) 271-1313
i} 330 0 271-1315
1 470 QD 271-1317
al 560 © —
1 i 680 © _

4 1kO 271-1321
s) 1.5 kO —
i Vy 40) 271-1325
2 Papi V4@) —
il 3.0 kO 271-1328
2) 3.9 kO —
1 4.7 kO 271-1330
3 6.8 kO 271-1333
Z 10 kQ 271-1335
ye 12 kO —
1 15 kO 271-1337
1 22k, 271-1339
1 27 kD 271-1340
1 47 kO, 271-1342
il 68 kQ 271-1345
2 100 kQ 271-1347
1 180 kO _
il 560 kQ _
401
 TABLE A-2 Resistors (1/2 W).

Quantity Value Radio Shack P/N 1

1 ATO, 271-009
2 100 Q 271-012
| 150 O 271-013
2 220 © 271-015

1 1kQ 271-023
1 72 @ 271-027
1 100 kO =
iL 1 MO -

TABLE A-3 Potentiometers (Single turn).

Quantity lf Value 3 Radio Shack P/N

1 ie 5 kO DTPA
il 10 kO 271-218
il 100 kQ 271-220
1 1 MO 271-229
eee

TABLE A+4 Capacitors.

Quantity F Value Radio Shack P/N

il 0.0022 uF -
Z 0.0047 uF —
2 0.01 uF 271-1051
2 0.033 uF _
2 0.1 uF 271-1058

il (aa 1 nF electrolytic 272-1419

2 2.2 uF electrolytic 272-1420
1 4.7 uF electrolytic 272-1012
1 10 uF electrolytic 272-1018
2 100 «F electrolytic 272-1016
L 1 470 uF electrolytic 272-1018

402
TABLE A-5 Solid state devices.

Quantity Description Radio Shack P/N

1N914 diode 276-1620

1N4001 diode, 50 PIV 276-1101
1N735, 6.2 V, 400 mW zener diode
or 1N4735 (1 W) 276-561
LED (red) 276-041A

2N2646 UJT (or HEP 310) 276-2029

2N3904 npn transistor 276-2016
2N3906 pnp transistor 276-2034
MPF102 n-channel FET 276-2062
40673 n-channel depletion-mode
MOSFET, or equivalent
NTE 465 n-channel enhancement-
mode MOSFET, or equivalent
VK 67AK n-channel enhancement-
mode VMOSFET, or equivalent
200-V, 6-A SCR 276-1067

555 timer (8-pin mini-DIP) 276-1723

567 tone decoder 276-1721
741 op-amp (8-pin mini-DIP) 276-007
7404 TTL hex inverter 276-1802
7442 TTL 1-of-10 decoder
7474 TTL dual D-type flip-flop 276-1818
7490 TTL decade counter 276-1808
er
oe
an
a 7805 +5 V regulator (TO-220 pkg) 276-1770

TABLE A-6 Miscellaneous.

Quantity Description Radio Shack P/N

12.6 VCT transformer 273-1505

Breadboarding socket 276-174
VOM, 50 kQ/V minimum
or digital multimeter 28-4014
Dual trace oscilloscope
Signal Generator
0-15 V de power supplies
Frequency counter
12 V relay (SPDT or DPDT)
SPDT switch

403
 ISBN 0-13-399544-5
90000>

9780133995442" |