CMOS Analog

and Mixed-Signal
Circuit Design
 CMOS Analog
and Mixed-Signal
Circuit Design
Practices and Innovations

Arjuna Marzuki
First edition published 2020
by CRC Press
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Contents
Preface.......................................................................................................................xi
Acknowledgments................................................................................................... xiii
Author....................................................................................................................... xv

Chapter 1 CMOS Analog and Mixed-Signal Circuit Design: An Overview......... 1

1.1 Introduction.................................................................................. 1
1.2 Notation, Symbol, and Terminology............................................ 1
1.3 Technology, Circuit Topology, and Methodology........................ 2
1.4 Analog and Mixed-Signal Integrated Design Concepts.............. 3
1.5 Summary......................................................................................4

Chapter 2 Devices: An Overview.......................................................................... 5

2.1 Introduction.................................................................................. 5
2.2 The PN Junction...........................................................................5
2.2.1 Fermi Level...................................................................... 5
2.2.2 Depletion Layer Capacitance............................................ 5
2.2.3 Storage Capacitance.........................................................5
2.3 Photo Devices...............................................................................8
2.4 FETs............................................................................................. 9
2.4.1 Long Channel Approximation.......................................... 9
2.4.1.1 MOS Structure.................................................. 9
2.4.1.2 MOS with External Bias................................. 10
2.4.1.3 MOS Operation............................................... 13
2.4.1.4 Current-Voltage Characteristics...................... 19
2.4.2 MOSFET Scaling...........................................................28
2.4.2.1 Full Scaling..................................................... 29
2.4.2.2 Constant-Voltage Scaling................................ 30
2.4.3 Weak Inversion............................................................... 31
2.4.4 Short-Channel................................................................. 31
2.4.4.1 Carrier Drift Velocity Models......................... 32
2.4.4.2 VDSAT................................................................ 33
2.4.4.3 Current-Voltage Equation for Short
Channel Transistor..........................................34
2.4.5 MOSFET Capacitor........................................................ 35
2.4.5.1 Oxide-Related Capacitance............................. 36
2.4.5.2 Junction Capacitance....................................... 37
2.4.6 MOSFET Transition Frequency.....................................40
2.4.7 Noise............................................................................... 41
2.4.7.1 Thermal Noise................................................. 41
2.4.7.2 Flicker Noise................................................... 42

v
vi Contents

2.5 Process Fitting Ratio................................................................ 43

2.5.1 150–90 nm Design Transfer.........................................44
2.6 MOSFET Parameter Exercise..................................................46
2.7 SPICE Example........................................................................ 54
2.8 Summary.................................................................................. 58
References........................................................................................... 59

Chapter 3 Amplifiers............................................................................................ 61
3.1 Introduction.............................................................................. 61
3.1.1 CMOS Amplifier.......................................................... 61
3.2 Input Voltage Range................................................................. 61
3.2.1 Theory.......................................................................... 61
3.2.2 Example........................................................................ 62
3.3 Signal Path of CMOS Operational Amplifier..........................64
3.3.1 Overall Signal Path.......................................................64
3.3.2 Load.............................................................................. 65
3.3.3 Cascode Current Source...............................................66
3.3.4 Example........................................................................66
3.4 CMOS Amplifier Parameters................................................... 70
3.4.1 Input Offset................................................................... 70
3.4.2 Common Mode Input Voltage Range........................... 70
3.4.3 Current Consumption................................................... 70
3.4.4 Common Mode Rejection Ratio (CMRR).................... 73
3.4.5 Power Supply Rejection Ratio...................................... 73
3.4.6 Slew Rate and Settling Time........................................ 73
3.4.7 DC Gain, fc, and f T. ...................................................... 75
3.4.8 Noise............................................................................. 75
3.4.9 Distortion...................................................................... 77
3.5 Common Mode Feedback........................................................ 79
3.6 Compensation in Amplifier...................................................... 81
3.6.1 Loop Response............................................................. 81
3.6.2 Pulse Response............................................................. 82
3.7 Wideband Amplifier Technique...............................................84
3.7.1 Source and Load...........................................................84
3.7.2 Stages and Feedback..................................................... 86
3.8 Noises in Amplifiers.................................................................90
3.8.1 Noise in Circuits...........................................................90
3.8.2 Noise in Single-Stage Amplifiers.................................92
3.8.3 Noise in Differential Pairs............................................96
3.8.4 Noise in Amplifier with Resistors in the Feedback......97
3.8.5 Noise Bandwidth.......................................................... 98
3.9 Current Density Design Approach......................................... 100
3.10 Layout Examples.................................................................... 100
3.11 Summary................................................................................ 101
References......................................................................................... 102
Contents vii

Chapter 4 Low Power Amplifier........................................................................ 103

4.1 Introduction............................................................................ 103
4.2 Low Voltage CMOS Amplifier............................................... 103
4.2.1 Body or Bulk Control................................................. 103
4.2.2 Circuit Technique....................................................... 104
4.3 Subthreshold........................................................................... 104
4.4 Current Reuse CMOS Amplifier............................................ 107
4.5 Other Techniques.................................................................... 109
4.5.1 Common-Gate with Gain-Boosting Wideband
Differential LNA........................................................ 110
4.6 Spice Example........................................................................ 111
4.7 Summary................................................................................ 114
References......................................................................................... 115

Chapter 5 Voltage Regulator, References and Biasing...................................... 117

5.1 Introduction............................................................................ 117
5.2 Current Sources...................................................................... 117
5.3 Self-Biased.............................................................................. 119
5.4 CTAT and PTAT.................................................................... 119
5.5 Bandgap Voltage Reference.................................................... 121
5.5.1 Bandgap Reference..................................................... 121
5.6 Diode-Less Voltage Reference............................................... 122
5.7 Cascode Current Source......................................................... 124
5.8 Regulated Power Supply......................................................... 125
5.9 Design Example...................................................................... 127
5.10 Spice Example........................................................................ 129
5.11 Layout Example...................................................................... 133
5.12 Summary................................................................................ 134
Problems............................................................................................ 134
References......................................................................................... 134

Chapter 6 Introduction of Advanced Analog Circuit......................................... 135

6.1 Introduction............................................................................ 135
6.2 MOSFET as a Switch............................................................. 135
6.3 Basic Switched Capacitor....................................................... 136
6.3.1 Switching Capacitor Sensitive to Parasitic
Capacitances............................................................... 136
6.4 Active Integrator..................................................................... 138
6.4.1 Non-inverting Switching Capacitor ­Non-sensitive
to Parasitic Capacitances............................................ 139
6.4.2 Inverting Active Integrator without a Delay............... 141
6.4.3 Inverting the Switching Capacitor with a Delay,
Non-sensitive to Parasitic Capacitances..................... 142
viii Contents

6.4.4 SC Behavior in Discrete Points of Time.................... 142

6.4.5 Non-inverting Active Integrator with a Delay............ 144
6.5 Sample-and-Hold Amplifier................................................... 145
6.6 Programmable Gain Amplifier............................................... 146
6.6.1 Timing........................................................................ 149
6.6.2 Common Mode Feedback.......................................... 149
6.6.2.1 AMP and CMFB......................................... 150
6.7 Chopper Amplifier.................................................................. 152
6.8 Dynamic Element Matching Technique................................. 153
6.9 Resistor-Less Current Reference............................................ 155
6.10 Switch Mode Converter.......................................................... 156
6.11 SPICE Example...................................................................... 158
6.12 Layout Issue............................................................................ 164
6.13 Summary................................................................................ 164
References......................................................................................... 164

Chapter 7 Data Converter.................................................................................. 167

7.1 Introduction............................................................................ 167
7.2 Digital-to-Analog Converter.................................................. 168
7.2.1 Resistor String Topology............................................ 168
7.2.2 Current Steering......................................................... 169
7.2.3 Hybrid Topology......................................................... 169
7.2.4 DAC Trimming or Calibration................................... 173
7.2.5 Glitch.......................................................................... 175
7.3 Analog-to-Digital Converter.................................................. 176
7.3.1 Slope ADC.................................................................. 176
7.3.2 SAR ADC................................................................... 177
7.3.3 Flash ADC.................................................................. 178
7.3.4 Pipelined ADC........................................................... 179
7.3.5 Delta Sigma ADC....................................................... 183
7.4 SPICE Example...................................................................... 186
7.4.1 DAC Example............................................................. 186
7.4.2 ADC Example............................................................ 186
7.5 Layout Examples.................................................................... 190
7.6 Summary................................................................................ 193
References......................................................................................... 193

Chapter 8 CMOS Color and Image Sensor Circuit Design............................... 195

8.1 Introduction............................................................................ 195
8.2 Technology and Methodology................................................ 195
8.2.1 General Comments on Technology or Process
for CMOS Image Sensor............................................ 195
8.2.2 Backside Illumination................................................. 196
Contents ix

8.2.3 Photo Devices............................................................. 197

8.2.4 Design Methodology.................................................. 197
8.3 CMOS Color Sensor............................................................... 198
8.3.1 Transimpedance Amplifier Topology......................... 198
8.3.2 Current to Frequency Topology.................................. 198
8.3.3 Current Integration Topology..................................... 199
8.4 CMOS Image Sensor..............................................................202
8.4.1 CMOS Image Sensor Architecture.............................202
8.4.1.1 Pixel-Level ADC.........................................202
8.4.1.2 Column-Level ADC..................................... 203
8.4.1.3 Chip-Level ADC..........................................204
8.4.2 Analog Pixel Sensor...................................................205
8.4.3 Digital Pixel Sensor....................................................208
8.4.4 Low Power and Low Noise Technique.......................208
8.4.4.1 Low Power Techniques................................208
8.4.4.2 Low Noise Techniques.................................209
8.5 SPICE Example......................................................................209
8.6 Layout..................................................................................... 212
8.7 Summary................................................................................ 213
References......................................................................................... 213

Chapter 9 Peripheral Circuits............................................................................. 217

9.1 Introduction............................................................................ 217
9.2 Oscillator................................................................................ 217
9.2.1 Ring Oscillator........................................................... 217
9.2.2 RC Oscillator.............................................................. 217
9.2.2.1 Ramp Oscillator........................................... 218
9.3 Non-overlapping Generator.................................................... 220
9.4 Interface Circuitry.................................................................. 222
9.4.1 Basic Interface Circuit................................................ 222
9.4.2 I2C..............................................................................224
9.5 I/O Pad.................................................................................... 225
9.6 Schmitt Trigger Circuit........................................................... 226
9.7 Voltage Level Shifters............................................................ 227
9.8 Power on Reset....................................................................... 229
9.9 ESD Circuit............................................................................ 232
9.10 SPICE Example...................................................................... 237
9.11 Layout Example......................................................................244
9.12 Summary................................................................................246
References.........................................................................................246
x Contents

Chapter 10 Layout and Packaging....................................................................... 247

10.1 Introduction............................................................................ 247
10.2 Process.................................................................................... 247
10.2.1 Antenna Rule............................................................ 247
10.2.2 Electromigration and Metal Density........................ 247
10.2.3 Shear Stress.............................................................. 249
10.3 Floor Planning........................................................................ 250
10.4 ESD and I/O Pad Layout........................................................ 251
10.4.1 Low Parasitic Capacitance Pad................................ 251
10.4.2 Seal Ring.................................................................. 251
10.5 Analog Circuit Layout Technique.......................................... 253
10.5.1 Matching................................................................... 253
10.5.2 Guard Ring............................................................... 254
10.5.3 Shielding................................................................... 255
10.5.4 Voltage (IR) Drop..................................................... 255
10.5.5 Metal over Implant................................................... 257
10.5.6 Substrate Tap............................................................ 257
10.6 Digital Circuit Layout Technique........................................... 257
10.6.1 Power Distribution for Mixed-Signal Design........... 257
10.6.2 Clock Distribution.................................................... 258
10.6.3 Latch-up.................................................................... 259
10.7 Packaging...............................................................................260
10.7.1 Die Attach.................................................................260
10.7.2 Package Type............................................................ 261
10.7.3 Package Parasitic...................................................... 263
10.8 Summary................................................................................264
References.........................................................................................264

Index....................................................................................................................... 265
Preface
The purpose of this book is to provide a complete working knowledge of the
Complementary Metal-Oxide Semiconductor (CMOS) analog and mixed-signal
circuit design, which can be applied for System on Chip (SOC) or Application-
Specific Standard Product (ASSP) development. The assumed background of the
reader is knowledge of linear circuits, discrete concepts, microelectronic devices,
and Very Large-Scale Integration (VLSI) systems. The first chapter covers an intro-
duction to CMOS analog and mixed-signal circuit design. This chapter gives an
overview of the subject of analog and mixed-signal circuit design, which is an intro-
duction to analog and digital integrated circuit design concepts. Three-dimensional
factors, such as technology, circuit topology, and methodology are described in this
chapter. The trade-offs concept is also discussed in this chapter.
CMOS technology continues to be the dominant technology for fabricating
integrated circuits. This book will cover basic devices such as the Metal-Oxide
Semiconductor Field-Effect Transistor (MOSFET), with both long and short-channel
operations. This topic is covered in Chapter 2 solely to provide a MOSFET under-
standing to the readers. The understanding of the MOSFET is very crucial in CMOS
circuit design. Photo devices and other related devices are also discussed in this
chapter. A new topic such as the fitting ratio is included to discuss the design “trans-
fer” approach. This approach is useful for practicing engineers.
Seven chapters focus on the CMOS analog and mixed-signal circuit design.
There are amplifiers, low power amplifiers, voltage regulator-reference, data con-
verters, dynamic analog circuits, color and image sensors, and peripheral (oscillators
and Input/Output (I/O)) circuits. Two chapters (Chapters 6 and 7) out of seven
chapters emphasize the mixed-signal circuit design. Chapter 8 focuses on the exam-
ples of CMOS analog and mixed-signal circuit designs, such as color and image
sensors. One chapter is focused on the Integrated Circuit (IC) layout and packaging.
The knowledge of the IC layout and packaging is critical in the development of the
CMOS circuit design, especially for analog and mixed-signal IC products.
One of the aims of this book is to provide a text for an introductory course on
CMOS analog circuit design for senior undergraduates and graduate students.
Many examples and exercises are provided in this book. Some of the circuits are
ready to be simulated using the Electronic Design Automation (EDA) tool such as
Simulation Program with Integrated Circuit Emphasis (SPICE). Chapters 2 and 3
are derived from the analog IC design senior undergraduate course at the Universiti
Sains Malaysia. These two chapters provide a quick and complete understanding of
CMOS analog circuit design.
This book presents practical methods working engineers have encountered in
the design of analog and mixed-signal circuits. Chapters 4–9 have been arranged
with earlier topics for the working engineers, while the remaining topics are for
the graduates or researchers. The principles and concepts discussed should never

xi
xii Preface

become outdated even though technology changes. For researchers, innovation top-
ics, such as the current-reuse technique and subthreshold operation, are important
for low power applications. Diodeless voltage reference and dynamic element match-
ing are also relevant for the researchers. This book surely provides design and layout
examples that will be immediately useful in commercial ICs.
Acknowledgments
I am indebted to those who helped us in bringing this book through the process of
idea to reality.
I also wish to express our appreciation to the School of Electrical and Electronic
Engineering of Universiti Sains Malaysia. Finally, the success of this book would
not have been possible without the kind assistance provided by my graduate students.

xiii
Author
Arjuna Marzuki received his BEng (Hons) in Electronic (Communication) from the
Department of Electronic & Electrical Engineering of the University of Sheffield in
the United Kingdom, MSc from Universiti Sains Malaysia, and PhD from Universiti
Malaysia Perlis.
Arjuna joined Hewlett-Packard as an R&D engineer in Wireless Semiconductor
Division in 1997. His main jobs were to design Radio Frequency (RF) and radio fre-
quency integrated circuit (RFIC) products. Such products were high-frequency tran-
sistors, RF gain blocks, I/Q demodulator, etc. He then later joined IC Microsystems
Sdn. Bhd. in Cyberjaya, Selangor, Malaysia, as IC design staff engineer. In the
company, he involved in designing 12/10/8 bits digital-to-analog converter ICs and
family of RFIC devices. He also managed to secure MYR 3.5 million MGS fund
for RFIC device research and development/commercialization. He later joined
Agilent Technologies as IC design engineer/manager in Optical Product Division.
His main jobs were to lead the analog design group, which was assigned to design
operational amplifiers, band-gap circuits, data-converters, I/Os, power-on reset, etc.
A small contribution by the group was “Industry’s 1st Digital Color Sensor IC with
I/O via 2-wire Serial Interface,” which was released in February 2006 by Avago
Technologies. He has been granted 1 US patent and has developed more than 20 com-
mercial products during his employment with Hewlett-Packard/Agilent Technologies
and IC Microsystems.
Arjuna had gained professional qualification as a professional and chartered engineer
when he was registered with the Board of Engineers Malaysia and Engineering Council
UK, respectively. He is a Fellow of The Institution of Engineering and Technology
(FIET). He was a recipient of the 2010 IETE J C Bose Memorial Award.
Arjuna is currently an associate professor at Universiti Sains Malaysia and
engaged in the teaching of analog integrated circuit courses at the undergraduate
and postgraduate levels. He is also active in supervising PhD students in the area
of microelectronic research. He has served as referees for many journals and con-
ferences. He has so far published more than 60 technical papers in journals and
conferences.

xv
 1 CMOS Analog
and Mixed-Signal
Circuit Design
An Overview

1.1 INTRODUCTION
The analog circuit employs the analog signal, while the digital circuit employs the
signal that is defined only at discrete values of amplitude. A mixed-signal integrated
circuit is a combination of analog and digital integrated circuits. This book proposes
the concept of a signal path idea for circuit design insight. This book covers the prac-
tices and research topics of the analog and mixed-signal integrated circuits.
Design is a process to achieve at least three outputs or objectives, namely, electrical
specification, circuit schematic, and device parameters, such as Width/Length (W/L)
ratio. An analysis of a circuit is required to be done before the circuit is finalized. Using
modern tools in designing a circuit is unavoidable, however, designers need to realize
the modern tools are only used to validate the performance of the circuit. The “novelty”
or “robustness” of the circuit solely depended on the designers themselves.
This book is not about design procedures. This book stresses the concept of
design, and does not stress the mathematical. Nevertheless, the analysis does require
or use mathematical equations, so a balance of concept and equations will be applied
throughout this book.

1.2 NOTATION, SYMBOL, AND TERMINOLOGY

All notations are kept simple for easier understanding. These notations are related
to signals or concept. A signal is any detectable value of voltage or current. A signal
could provide information about the state of the behavior of an integrated circuit.
A small signal symbol uses a lower-case character, while a large signal symbol uses
a capital case character. Figure 1.1 shows the basic transistor symbols used in this
book. An abbreviation is followed with a full name for quick reference. Important
terminology is italic for easier reference.

1
2 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 1.1 Circuit symbols for n-channel and p-channel enhancement type of Metal-
Oxide Semiconductor Field-Effect Transistors (MOSFETs).

1.3 TECHNOLOGY, CIRCUIT TOPOLOGY, AND METHODOLOGY

At least three factors could determine the final design. Figure 1.2 shows the relation-
ship between the final design with technology, topology, and methodology. One can
foresee the “novelty” of the final design by knowing the level of the “maturity” of
these three factors. To “commercialize” an integrated circuit as a product, the level
of maturity should be high. The lack of maturity can be considered as research gaps
for the researchers. One needs to consider the design for test (DFT) or design for
manufacturability (DFM) for the final design.
Normally, standard Complementary Metal-Oxide Semiconductor (CMOS) tech-
nology is only targeted for the digital circuit. The technology does not have multiple

Circuit
Technology
Topology

Final Design

Methodology
(EDA tools)

FIGURE 1.2 Design dimension.

CMOS Analog and Mixed-Signal Circuit Design 3

polysilicon, and there are no dedicated passive components such as MIM capacitor,
high sheet resistance resistor, and inductor. However, many analog circuits have used
standard CMOS technology.
There are also mixed-signal and RF CMOS technology, which are targeted for
the mixed-signal and RF application. The thick metal, which is for inductor design
has been included for the RF CMOS technology. The advanced CMOS technology
such as for Radio Frequency (RF) application is expensive compared to standard
CMOS technology.

1.4 ANALOG AND MIXED-SIGNAL INTEGRATED

DESIGN CONCEPTS
Analog and digital circuits combined in an Integrated Circuit (IC) are considered
mixed-signal designs.
Leakage power and propagation delay are the two major challenges in designing
digital CMOS Very Large-Scale Integration (VLSI) circuits, in deep sub-micron
technology. While for the analog CMOS, voltage swing, noise, and frequency perfor-
mance are three main challenges. Understanding device behavior is very important,
for example, minimum gate length would give the highest speed, thus reducing the
propagation delay. While for analog CMOS, the gate length of at least twice the min-
imum gate length would give the best trade-off of noise, gain, and speed. A trade-off
idea is shown in Figure 1.3. Therefore, for the mixed-signal integrated circuits, dif-
ferent gate lengths are utilized for the best performance. Figure 1.4 shows how we
can arrange the analog and digital circuits in an IC. Signal integrity and EMI have to
be seriously considered for high frequency application.

Noise Linearity

Power
Gain
Dissipation

Input/Output Supply voltage

Impedance

Voltage Swing
Speed

FIGURE 1.3 Trade-off.

4 CMOS Analog and Mixed-Signal Circuit Design

Gutter for routing low-noise signals

Pads
VDD Reference
VDD ground VDD ground VDD ground
GND Reference
Op-amp Op-amp Op-amp
VDD Power with bias with bias with bias
GND Power capacitors capacitors capacitors
clock clock switches switches switches
drivers
GND
V in+
V in-
GND
signals

signals
signals
clk

clk
clk
Analog
domain
Digital
domain
Digital power

GND Comparators Comparators Comparators

VDD and latches and latches and latches
GND Digital correction logic
Out
Out
Out

FIGURE 1.4 Block diagram layout of a pipeline stage.

1.5 SUMMARY
This book focuses on the custom analog and mixed-signal integrated circuits.
This book will not focus on the basic digital circuit design, digital coding-related,
and back-end digital layout tool. Knowledge of the technology or process that is used
in circuit design is very crucial. Good design requires solid knowledge in the process
or technology. This is reflected in Figure 1.2. Chapter 2 details only standard CMOS
because the technology is still practical in the coming years. The rest of the chapters’
design concept is still applicable for different technologies. This book stresses many
figures and curves to describe the operation and behavior of circuitries. Readers are
encouraged to scrutinize the figures and curves for a better understanding of any
given subjects.
 2 An Overview
Devices

2.1 INTRODUCTION
Complementary Metal-Oxide Semiconductor (CMOS) technology continues to be
the dominant technology for fabricating integrated circuits. This book will cover
basic devices such as metal-oxide semiconductor field-effect transistor (MOSFET)
with both long and short-channel operations. This topic is covered in one chapter
solely to provide a MOSFET understanding to the readers. The understanding of
MOSFET is very crucial in CMOS circuit design. Photo devices and other related
devices are also discussed in this chapter. A new topic such as fitting ratio is included
to discuss the “design transfer” approach. This approach is useful for practicing
engineers.

2.2 THE PN JUNCTION

Figure 2.1 depicts the movement of an electron from the valence band to the conduc-
tion band.

2.2.1 Fermi Level

Figure 2.2 shows the intrinsic silicon, p-type silicon, n-type silicon, and a PN-­
junction diode Fermi levels.

2.2.2 Depletion Layer Capacitance

Formation of a PN junction results in a depleted region at the p–n interface. A deple-
tion region is an area depleted of mobile holes or electrons. The movement of holes
across the junction, to the right in Figure 2.3.
Figure 2.4 shows a n-well/p-substrate diode. Figure 2.5 shows the total diode
depletion capacitance against the diode reverse.

2.2.3 Storage Capacitance

Figure 2.6 depicts charge distribution in a forward-biased diode. The diode reverse
recovery test circuit is shown in Figure 2.7.

5
6 CMOS Analog and Mixed-Signal Circuit Design

electron
Ec

Eg

Ev
hole

FIGURE 2.1 An electron moving to the conduction band, leaving behind a hole in the
valence band.

Ec Ec Ec
Ef n
Ei Ei Ei
Ef p
Ev Ev Ev
(a) (b) (c)

Ec
q · Vbi
Ec
Ef
Ev n-type
p-type

Ev
(d)

FIGURE 2.2 The Fermi energy levels in various structures: (a) intrinsic silicon, (b) p-type
silicon, (c) n-type silicon, and (d) A PN-junction diode.

Anode, A Cathode, K

+ VD –

p-type n-type

- - - - + +
- Depletion +
- region
+ +
- - - - + +

Two plates of a capacitor

FIGURE 2.3 Depletion region formation in a PN junction.

Devices 7

+ VD -

n-well

Bottom capacitance Sidewall capacitance

p-substrate

FIGURE 2.4 A PN junction on the bottom and sides of the junction.

Cj, diode depletion capacitance

Cj0, zero-bias depletion capacitance

1.12 pF

VD, diode voltage

0

FIGURE 2.5 Diode depletion capacitance against diode reverse voltage.

Storage or diffusion capacitance

Metal contact
_
+
p-type n-type

_ +

Minority carriers

FIGURE 2.6 Charge distribution in a forward-biased diode.

8 CMOS Analog and Mixed-Signal Circuit Design

Diode current
I
R
VF - 0.7
ts
R
I
VF Diode voltage
0.7
VR t2 time

VR - 0.7 VR
R
trr
t1 t3

FIGURE 2.7 Diode reverse recovery test circuit.

2.3 PHOTO DEVICES

The typical photodetector devices are photodiode and phototransistor. Typical pho-
todiode devices are N+/Psub, P+/N_well, N_well/Psub, and P+/N_well/Psub (back
to back diode) [1]. Phototransistor devices are P+/n_well/Psub (vertical transistor),
P+/N_well/P+ (lateral transistor), and N_well/gate (tied phototransistor) [1].
This standard photo device still requires a microlens and color filter array.
The quantum efficiency of photodiodes in standard CMOS is usually below
0.3 [2].
Figure 2.8 shows the cross-section photo devices. The devices which are normally
developed for the modified CMOS process are a photogate, pinned photodiode, and

(a) (b) (c) (d)

(e) (f) (g)

Psub P+ gate

Nwell N+

FIGURE 2.8 Different pixel architectures: (a) N+/Psub, (b) P+/N_well, (c) N_well/Psub,
(d) combination of two photodiodes (P+/N_well and N_well/Psub), (e) vertical phototransis-
tor (P+/N_well/Psub), (f) lateral phototransistor (P+/N_well/P+), and (g) N_well/gate tied
phototransistors.
Devices 9

an amorphous silicon diode. These devices will improve the sensitivity of CMOS
image sensor (CIS). The pinned photodiode, which has low dark current, offers good
imaging characteristics for CIS [3].

2.4 FETs
2.4.1 Long Channel Approximation
2.4.1.1 MOS Structure
The MOS structure forms a capacitor. The gate and substrate are acting as plates of
a capacitor. The oxide layer is acting as the dielectric of the capacitor. This is shown
in Figure 2.9. The carrier concentration and its local distribution within the semicon-
ductor substrate can be manipulated by the external voltage applied to the gate and
the substrate terminal. The mass action law is:

n ⋅ p = ni 2 (2.1)

n and p denote the mobile carrier concentration, and ni denotes the intrinsic carrier
concentration of silicon. The mass action law gives us the equilibrium concentra-
tion of the mobile carriers in the semiconductor. Assuming the substrate doped uni-
formly with an acceptor concentration NA, Typically, NA is much greater than ni. ni is
approximately equal to 1.45 × 1010 cm−3 at room temperature. NA is typically on the
order to 1015 to 1016 cm−3. So, we can write,

ni 2
Ppo ≅ N A and n po ≅ (2.2)
NA

VG (Gate voltage)

Gate

Oxide
(SiO2 )

Semiconductor Oxide
substrate thickness

0 V (Substrate voltage)
b

FIGURE 2.9 Two terminal MOS structure.

10 CMOS Analog and Mixed-Signal Circuit Design

The equilibrium Fermi level (EF ) within the bandgap is determined by the doping
type and doping concentration. The Fermi potential ∅F, given by Equation 2.3, is a
function of temperature and doping.

E F − Ei
∅F = (2.3)
q

For p-type,

kT n
∅ FP = ln i (2.4)
q NA

For n-type,

kT N D
∅ Fn = ln (2.5)
q ni

The electron affinity of silicon ( qx ) is the potential difference between the conduc-
tion band level and vacuum level (see Figure 2.10). The work function ( q∅ s ) is the
energy required for an electron to move from the Fermi level into free space.

q∅ s = qx + ( EC − E F ) (2.6)

Three separate components of the MOSFET system have different energy band dia-
grams (Figure 2.11). There is a built-in voltage drop due to the work function dif-
ference between the metal and the semiconductor. This built-in voltage drop occurs
across the insulating oxide layer and surface of the semiconductor.

2.4.1.2 MOS with External Bias

If we assume that the substrate of the MOS system is set to 0 V ground (GND),
depending on the polarity and the magnitude of the gate voltage (VG), the MOS
system operates in three different operating regions: accumulation, depletion, and
inversion.

Eo Free space

qx

Ec Conduction Band
Band-gap
energy 1.1 eV
Ei
qϕFp
EFp Fermi Level
Ev Valence band

FIGURE 2.10 Energy band diagram of a p-type silicon substrate.

Devices 11

Ec

Ei

EFm EFp
Ev

Metal (Al) Oxide Semiconductor (Si)

p-type

FIGURE 2.11 Energy band diagram of the combined MOS system.

VG < 0 Metal (Al) Oxide Semiconductor (Si)

p-type

Oxide
Eox Eox
EFm
Ec
qVG
Ei
EFp
Holes accumulated
P-type Si substrate on the surface Ev

VB = 0

FIGURE 2.12 The cross-sectional view and the energy band diagram of the MOS structure
operating in accumulation region.

If a negative voltage is applied to the gate electrode, the holes in the p-type sub-
strate are attracted to the semiconductor-oxide interface: accumulation (Figure 2.12).

• The oxide electric field is directed toward the gate electrode

• The energy bands to bend upward near the surface
• Electron (minority carrier) concentration decrease

If a small positive voltage is applied to the gate electrode, the oxide electric field
is directed toward the substrate: depletion (Figure 2.13)

• The energy bands to bend downward near the surface

• Holes (majority carrier) will be repelled back into the substrate
• A depletion region is created near the surface
12 CMOS Analog and Mixed-Signal Circuit Design

VG > 0
(small) Metal (Al) Oxide Semiconductor (Si)
p-type

Eox Eox Oxide

Ec

Ei
Depletion E Fp
qVG
P-type Si substrate region E Fm Ev

VB = 0

FIGURE 2.13 The cross-sectional view and the energy band diagram of the MOS structure
operating in depletion mode, under small gate bias.

The thickness of the depletion region, (Xd ), on the surface is the function of the
surface potential ∅s.

• Mobile hole charge in a thin horizontal layer parallel to the surface is:

dQ = −q ⋅ N A ⋅ dx (2.7)

• Using the Poisson equation, we can find the surface potential change
required to displace this charge sheet dQ by a distance Xd away from the
surface:

dQ q ⋅N A ⋅ x
d∅ s = − x ⋅ = ⋅ dx (2.8)
ε Si ε Si

• Integrating the previous equation, we can find the thickness of the depletion
region:

∅s xd
q ⋅ NA ⋅ x
∫ ∅F
d∅ s =
∫ 0 ε Si
⋅ dx (2.9)

q ⋅ N A ⋅ xd 2
∅ s −∅ F = (2.10)
2ε Si

2ε Si ⋅ ∅ s −∅ F
xd = (2.11)
q ⋅ NA
Devices 13

• The charge density of the depletion region given by,

Q = −q ⋅ N A ⋅x d = − 2q ⋅ N A ⋅ε Si ⋅ ∅ S − ∅ F (2.12)

If we increase the position gate bias, the mid-gap energy level Ei becomes
smaller than the Fermi level EFP. Then the semiconductor in this region
becomes n-type: surface inversion (Figure 2.14).

• The n-type layer near the surface is called the inversion layer
• The inversion layer will be used for the channel of MOSFET devices

Once the surface is inverted, the thickness of the depletion region does not increase
any more even if the positive gate bias is further increased.
We can find the maximum depletion region depth xdm by using the inversion con-
dition ∅ S = −∅ F .

2 ⋅ε Si ⋅ 2∅ F
xdm = (2.13)
q⋅NA

2.4.1.3 MOS Operation

A MOSFET is a four-terminal device (see Figure 2.15).

• Gate, source, drain, substrate (or body)

• The two n+ regions will be the drain-conducting terminal of this device
(source and drain)
• The conducting channel will be formed by gate voltage

VG > 0 (large) Metal (Al) Oxide Semiconductor (Si)

p-type
Electrons attracted
E ox E ox Oxide to the surface Ec

Ei
qVG EFp
Depletion E Fm Ev
P-type Si substrate region

VB = 0

FIGURE 2.14 The cross-sectional view and the energy band diagram of the MOS structure
in surface inversion, under larger gate bias.
14 CMOS Analog and Mixed-Signal Circuit Design

GATE
S
D
CHANNEL
WIDTH
(W)

SOURCE CHANNEL DRAIN

(n+) LENGTH (n+)

SUBSTRATE (p-Si)

FIGURE 2.15 The physical structure of n-channel enhancement-type MOSFET.

Types of MOSFETs:

• Zero bias channel state

• Enhancement-type
– No conducting channel at zero gate bias
• Depletion-type
– The conducting channel already exists at zero gate bias
• Types of channels:
• N-channel MOSFET
– P-type substrate and with n+ source and the drain region. And with
n-channel
• P-channel MOSFET
– N-type substrate and with p+ source and the drain region. And with
p-channel

Circuits symbols of MOSFETs (see Figure 2.16):

• The source is the n+ (p+) region, which has a lower (higher) potential than
the other n+ (p+) region in an n-channel (p-channel) MOSFET device
• All the terminal voltage of the device is defined with respect to the source
potential

D D D D D D

G B G G G B G G

S S S S S S
4-terminal Simplified Simplified 4-terminal Simplified Simplified
n-channel MOSFET p-channel MOSFET

FIGURE 2.16 Circuit symbols for n-channel and p-channel enhancement type of MOSFETs.
Devices 15

VGS < VTO

VS = 0 GATE VDS = 0

OXIDE

SOURCE DRAIN
(n+) (n+)

SUBSTRATE (p-Si) DEPLETION REGION

VB = 0

FIGURE 2.17 Formation of a depletion region in n-channel enhancement-type MOSFET.

The channel current is controlled by an external bias of four terminals.

The conducting channel has to be formed in order to start the current flow between
the source and drain region.
In Figure 2.17, as the gate-to-source voltage is increased, the majority carriers
(holes) are repelled back into the substrate, and the p-type substrate is depleted.
As surface potential in the channel region reaches −∅ Fp, a conducting n-type
layer is formed between the source and the drain. See Figure 2.18.
The conducting channel provides an electrical connection between the two n+
regions: allows current flows. See Figure 2.19. V T0, threshold voltage, denotes the
value of the gate-to-source voltage required to create a conducting channel.

2.4.1.3.1 Threshold Voltage

The physical components of the threshold voltage of a MOS structure:

• The work function difference between the gate and the channel
• The gate component to change the surface potential

Metal (Al) Oxide Semiconductor (Si)

p-type

Ec

Ei
φF E Fp
|2φ F| -φ F
qVTO
E Fm Ev

FIGURE 2.18 Band diagram of the MOS structure underneath the gate, at surface inversion.
16 CMOS Analog and Mixed-Signal Circuit Design

VGS > VTO

GATE VDS = 0
VS = 0

OXIDE

SOURCE DRAIN
(n+) (n+)
INVERSION LAYER
(CHANNEL)
DEPLETION REGION
SUBSTRATE (p-Si)

VB = 0

FIGURE 2.19 Formation of inversion layer (channel) in n-channel enhancement-type

MOSFET.

• The gate voltage component to offset the depletion region charge

• The voltage component to offset the fixed charges in the gate oxide and in
the silicon-oxide interface

The work function difference ∅ GC between the gate and the channel determines the
built-in potential of the MOS system.

• For metal gate:

∅ GC =∅ F (substrate) −∅ M (2.14)

• For polysilicon gate:

∅ GC =∅ F (substrate) −∅ F (gate) (2.15)

Because of the fixed acceptor ions located in the depletion region near the
surface, the depletion charge exists.

• Depletion region charge:

QB 0 = − 2q ⋅N A ⋅ε Si ⋅ −2∅ F (2.16)

• Consider the voltage bias of the body

QB = − 2q ⋅N A ⋅ε Si ⋅ −2∅ F + VSB (2.17)

Devices 17

−QB
The component that offsets the depletion region charge is equal to .
COX

ε ox
COX = (2.18)
tox

There always exists a fixed positive charge density QOX at the interface between the
gate oxide and the silicon substrate.
The gate voltage component that is necessary to offset this positive charge at the
interface is −QOX .
COX
• For zero substrate bias:

QB0 Qox
VT 0 =∅ GC − 2∅ F − − (2.19)
Cox Cox

• For non-zero substrate bias:

QB Qox
VT =∅GC − 2∅ F − − (2.20)
Cox Cox

We can write the generalized form of the threshold voltage:

QB 0 Qox QB − QB 0 Q − QB 0
VT =∅GC − 2∅ F − − − =VT 0 − B (2.21)
Cox Cox Cox Cox

• The most general expressing of the threshold voltage (Shichman-Hodges

equation):

VT = VT 0 + γ ⋅ ( −2∅ F + VSB − 2∅ F) (2.22)

QB − QB0

Cox

=−
2q ⋅N A ⋅ε Si
Cox
⋅ ( −2∅ F + VSB − 2∅ F ) (2.23)

2q ⋅ N A ⋅ ε Si
γ= (2.24)
Cox

We can use Equation 2.23 for both the n-channel device and the p-channel device.
However, some of the terms and coefficients in Equation 2.23 have different
polarities for the n-channel case and for the p-channel case.
18 CMOS Analog and Mixed-Signal Circuit Design

• The substrate Fermi potential ∅F is negative in nMOS, positive in pMOS

• The depletion region charge density QB0 and QB are negative in nMOS,
positive in pMOS
• The substrate bias coefficient γ is positive in nMOS, negative in pMOS
• The substrate bias voltage VSB is positive in nMOS, negative in pMOS

The threshold voltage can be made negative. The device has a negative threshold
voltage called a depletion-type (or normally-on) n-channel MOSFET. Except for
this negative threshold voltage, the depletion-type MOSFET has the same electrical
behavior as the enhancement-type device.

2.4.1.3.2 Body Effect and Bias

The body effect refers to the change in the transistor V T resulting from a voltage dif-
ference between the transistor source and body.
Since the voltage differences between the source and body affect the V T, the body
can be thought of as a second gate that helps determine how the transistor turns on
and off.
It is represented by gamma and has units of V .
In several digital circuit applications, the condition VSB = 0 cannot be guaran-
teed for all transistors. We will examine in this example how a non-zero source-to-­
substrate voltage VSB affects the threshold voltage of the MOS transistor. Assume the
MOS transistor has a long channel:

• Calculate γ :

1
2 ⋅q ⋅N A ⋅ε Si 2 ⋅1.6 ⋅10 −19 ⋅ 4 ⋅1018 ⋅ 11.7 ⋅8.85 ⋅10 −14
γ= = = 0.52V 2
Cox 2.20 ⋅10 −6

• Compute and plot the threshold voltage:

VT =VT 0 + γ ( −2∅ F + VSB − 2∅ F ) = 0.48 + 0.52⋅( 1.01 + VSB − 1.01 )

Figure 2.20 shows the threshold voltage across the VSB.
The body bias involves connecting the transistor bodies to a bias network in the
circuit layout rather than to power or ground. The body bias can be supplied from an
external (off-chip) source or an internal (on-chip) source.
The body bias helps to adjust the V T of the transistor by creating a potential dif-
ference between the substrate and source.
Devices 19

0.80

0.75

Threshold Voltage VT (V)

0.70

0.65

0.60

0.55

0.50

0.45

0.40
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2
Substrate Bias VSB (V)

FIGURE 2.20 Shows the threshold voltage across the VSB.

2.4.1.4 Current-Voltage Characteristics

Figure 2.21 shows a cross-sectional view of NMOS operating in the linear region,
edge saturation region, and beyond saturation.
For VGS > VT 0 , VDS = 0

• Drain current ID equal to zero

For VGS > VT 0 , 0 <VDS < VDSAT

• Drain current ID proportional to VDS

• Called the linear mode (or linear region)

For VGS > VT 0 , VDS = VDSAT

• Inversion charge at the drain is reduced to zero: pinch-off point

For VGS > VT 0 , VDSAT < VDS

• A depleted surface region forms adjacent to the drain and grows toward the
source
• Called saturation mode (or saturation region)
20 CMOS Analog and Mixed-Signal Circuit Design

VG > V T

VS = 0 VD
small
ID
OXIDE

SOURCE DRAIN
(n+) (n+)
CHANNEL

SUBSTRATE (p-Si ) DEPLETION REGION

(a)
VB = 0
VG > VT

VS = 0 VD = VDST

OXIDE

SOURCE DRAIN
(n+) (n+)
PINCH-OFF
POINT DEPLETION REGION
SUBSTRATE (p-Si )

(b) VB = 0

VG > VT

VS = 0 VD > VDST

OXIDE

SOURCE DRAIN
(n+) (n+)
PINCH-OFF
POINT DEPLETION REGION
SUBSTRATE (p-Si )

(c)
VB = 0

FIGURE 2.21 Cross sectional view of an n-channel (nMOS) transistor, (a) operating in
linear region, (b) operating at the edge of saturation, and (c) operating beyond saturation.
Devices 21

MOSFET operating in saturation region:

• As with the inversion layer near the drain, the effective channel length is
decreased
• The voltage of channel-end remains constant and equal to VDSAT
• Pinched-off area of the channel absorbs most of the excess voltage drop
(VDS − VDSAT )
• A high-field is generated between the channel-end and the drain boundary

Analysis of the actual three-dimensional MOS system is very complex.

We will use the gradual channel approximation for establishing the MOSFET
current-flow problem and subsequently the current-voltage characteristics.
The boundary conditions for the channel voltage VC are:

VC ( y = 0 ) = VS = 0
(2.25)
VC ( y = L ) = VDS

It is assumed that the entire channel region between the source and the drain is
inverted:

VGS ≥VT 0
(2.26)
VGD = VGS − VDS ≥ VT 0

Let QI(y) be the total mobile charge in the surface inversion layer.
This charge can be expressed as follows,

QI ( y ) = − Cox ⋅ VGS − VC ( y ) − VT 0  (2.27)

Figure 2.22 shows the cross-sectional view of an n-channel transistor, operating in

the linear region.
Figure 2.23 depicts a simplified geometry of the surface inversion layer (channel
region).
Assume that all the mobile electrons in the inversion layer have a constant surface
mobility μn, then we can express the incremental resistance as follows,

dy
dR = − (2.28)
W ⋅ µn ⋅ QI ( y )

Assume that the channel current density is uniform across this segment.
22 CMOS Analog and Mixed-Signal Circuit Design

VGS > V TO

VS = 0
ID
OXIDE
VDS

SOURCE DRAIN
(n+) (n+)
x y CHANNEL
y=L
y=0
SUBSTRATE (p-Si) DEPLETION REGION

VB = 0

FIGURE 2.22 Cross-sectional view of an n-channel transistor, operating in linear region.

y=0
Channel length = L y=L

Source end
Channel Width = W

dy Drain end

Inversion layer
(channel)

FIGURE 2.23 Simplified geometry of the surface inversion layer (channel region).

Applying the Ohm’s law for this segment, we can write the voltage drop along
segment dy in the y-direction as follows,

ID
dVC = I D ⋅dR = − ⋅dy (2.29)
W ⋅µn ⋅ QI ( y )
Devices 23

Integrate this equation along the channel.

L VDS

∫ 0
I D ⋅dR = −W ⋅ µn ⋅
∫ 0
QI ( y ) ⋅ dVC (2.30)

We can simplify the left-hand side of Equation 2.30 and replace QI ( y ) with
Equation 2.27.

VDS
I D ⋅L = W ⋅µn ⋅ COX
∫ 0
( VGS − VC − VT 0 ) ⋅ dVC (2.31)

Assuming that the channel voltage VC is only variable, and it depends on the posi-
tion y:

µn ⋅ COX W
ID = ⋅ ⋅ 2 ⋅ ( VGS − VT 0 ) VDS − VDS 2  (2.32)
2 L

k′ W
ID = ⋅ ⋅ 2 ⋅ ( VGS − VT 0 ) VDS − VDS 2  (2.33)
2 L 

k
I D = ⋅ 2 ⋅ ( VGS − VT 0 ) VDS − VDS 2  (2.34)
2

where:

k′ = µn ⋅ COX (2.35)

and

W
k = k′ ⋅ (2.36)
L

We can find out that the drain current Equation 2.32 is not valid beyond the bound-
ary between the linear region and the saturation region, i.e., for,

VDS ≥ VDSAT = VGS − VT 0 (2.37)

And we can see that the drain current remains approximately constant around the
peak value reached for beyond the saturation boundary. This saturation current level
can be found simply as follows,

µn ⋅ COX W 
I D ( sat ) = ⋅ ⋅ 2 (VGS − VT 0 ) ⋅ (VGS −VT 0 ) (VGS − VT 0 ) 
2

2 L  
(2.38)
µ ⋅C W
= n OX ⋅ ⋅ (VGS −VT 0 ) .
2

2 L
24 CMOS Analog and Mixed-Signal Circuit Design

Linear Region
VGS3
Drain Current Saturation Region

VGS2

VGS1

Drain Voltage

FIGURE 2.24 Basic current-voltage characteristics of an n-channel MOS transistor.

D +
V DS
G B
Drain Current

+ S
VGS

VTO

Gate Voltage

FIGURE 2.25 Drain current of the n-channel MOS transistor as a function of the gate-
source voltage VGS, with VDS > VDSAT.

Thus, drain current, beyond the saturation boundary, is a function of VGS only.
Figures 2.24 and 2.25 show the basic current-voltage characteristics.

2.4.1.4.1 Channel Length Modulation

Beyond the saturation boundary, the effective channel length, the length of the inver-
sion layer where gradual channel approximation is still valid, is different from the
channel length, L.
So, we have to examine the mechanisms of channel pinch-off and current flow on
the saturation mode to obtain more exact drain current.
The inversion layer charge at the source end of the channel is,

QI ( y = 0 ) = −COX ⋅ ( VGS − VT 0 ) (2.39)

Devices 25

The inversion layer charge at the drain end of the channel is,

QI ( y = L ) = −COX ⋅ (VGS −VT 0 −VDS ) (2.40)

At the edge of saturation,

VDS = VDSAT =VGS −VT 0 (2.41)

QI ( y = L ) ≈ 0 (2.42)

We can say the channel is pinched-off at the drain:

If the VDS is increased beyond the edge of saturation, more areas of the channel
become pinched-off. See Figure 2.26.
Then the effective channel length is reduced to,

L′ = L − ∆L (2.43)

where ∆L is the length of the channel segment with QI = 0.

As the drain-to-source voltage increases, the pinch-off point moves from the
drain end of the channel to the source.
The channel voltage at the pinch-off point remains equal to V because the inver-
sion layer charge is zero for Lʹ < y < L.

VC ( y = L′ ) = VDSAT (2.44)

We can consider the inverted portion of the surface as a shortened channel.

The gradual channel approximation is valid in this region.

VGS > V TO

VS = 0 V DS > VDST

OXIDE ID
0 y L’ L L
SOURCE DRAIN
(n+) (n+)
CHANNEL
PINCH-OFF
SUBSTRATE (p-Si ) POINT (Q1 = 0) DEPLETION REGION

VB = 0

FIGURE 2.26 Pinch-off condition.

26 CMOS Analog and Mixed-Signal Circuit Design

Then we can find the drain current as follows,

µn ⋅ COX W
I D ( sat ) = ⋅ ⋅ (VGS −VT 0 )
2
(2.45)
2 L′

Equation 2.45 corresponds to a MOSFET with an effective channel length Lʹ, operat-
ing in the saturation region. This phenomenon, shortening of the effective channel, is
called channel length modulation (CLM). As Lʹ decreases with the increasing VDS, the
saturation current ID(sat) will also increase with VDS. We can modify Equation 2.45
to reflect this drain voltage dependence,

1 µ ⋅C W
I D ( sat ) = ⋅ n OX ⋅ ⋅ (VGS −VT 0 )
2
(2.46)
∆L 2 L
1−
L

The channel length shortening ∆L is proportional to the square root of ( VDS − VDSAT ),

∆L ∝ VDS − VDSAT (2.47)

For simplicity, we use the following empirical relation.

λ is called the channel length modulation coefficient:
∆L
1− ≈ 1 − λ ⋅VDS (2.48)
L

Assuming that λ ⋅VDS << 1, the saturation current given in Equation 2.45 can be
written as:

µn ⋅ COX W
I D ( sat ) = ⋅ ⋅ ( VGS − VT 0 ) ⋅ (1 + λ ⋅VDS )
2
(2.49)
2 L

Figure 2.27 shows the effect of CLM. The drain current in the saturation region
increases linearly with VDS instead of remaining constant.

2.4.1.4.2 Substrate Bias Effect

The derivation of linear-mode and saturation-mode current-voltage characteristics in
the previous pages have been done under the condition of:

VSB = 0.

Positive source-to-substrate voltage affects the threshold voltage and consequently

affects the drain current.
The general expression (Equation 2.23) for the threshold voltage already includes
the substrate bias term.

VT ( VSB ) = VT 0 + λ ⋅ ( 2φF + VSB − 2φF ) (2.50)

Devices 27

Linear Region
VGS3
Drain Current
Saturation Region
with channel
length modulation
(λ≠0)
neglecting channel VGS2
length modulation
(λ=0)
VGS1

Drain Voltage

FIGURE 2.27 Effect of CLM.

We can replace the threshold voltage terms with the more general V T (VSB) terms.

µn ⋅ COX W 
I D ( lin ) = ⋅ ⋅ 2 ⋅ ( VGS − VT ( VSB ) ) VDS − V 2 DS  (2.51)
2 L  

µn ⋅ COX W
I D ( lin ) = ⋅ ⋅ ( VGS − VT ( VSB ) ) ⋅ (1 + λ ⋅VDS )
2
(2.52)
2 L

Finally, we arrive at a complete drain current as a non-linear function of the terminal

voltages.

I D = f (VGS ,VDS ,VBS ) . (2.53)

Figure 2.28 depicts the terminal voltages and current of the NMOS and the PMOS.

• Current-voltage equation of the nMOS:

I D = 0 for VGS < VT (2.54)

µn ⋅ COX W
I D ( lin ) = ⋅ ⋅ 2 ⋅ ( VGS − VT ) VDS − V 2 DS for VGS ≥ VT and VDS < VGS − VT (2.55)
2 L

µn ⋅ COX W
I D ( sat ) = ⋅ ⋅ ( VGS − VT ) ⋅ (1 + λ ⋅ VDS ) for VGS ≥ VT andd VDS ≥ VGS − VT (2.56)
2

2 L

• Current-voltage equation of the pMOS:

I D = for VGS > VT (2.57)

28 CMOS Analog and Mixed-Signal Circuit Design

D S
+ V - +
DS
VGS V SB
ID
+ -
G B G B
+ -

VGS V SB ID
- + +
S D VDS
n-channel MOSFET p-channel MOSFET

FIGURE 2.28 Terminal voltages and currents of the nMOS and the pMOS.

µn ⋅ COX W
I D ( lin ) = ⋅ ⋅ 2 ⋅ ( VGS − VT ) VDS − V 2 DS for VGS ≤ VT andd VDS > VGS − VT (2.58)
2 L

µn ⋅ COX W
I D ( sat ) = ⋅ ⋅ ( VGS − VT ) ⋅ (1 + λ ⋅ VDS ) for VGS ≤ VT andd VDS ≤ VGS − VT
2
(2.59)
2 L

2.4.2 MOSFET Scaling
The very large-scale integration (VLSI) technology requires a high packing den-
sity and small transistor size. The reduction of the size is commonly referred to as
scaling. There are two types of scaling strategies: (1) full scaling (constant-field
scaling) and (2) constant-voltage scaling. Primed quantities in Figure 2.29 indicate
the scaled dimensions and doping density. The scaling of all dimensions by a fac-
tor of S > 1 leads to the reduction of the area occupied by the transistor by factor
of S2.

GATE
S
D

W’ = W / S

OXIDE t ox’ = t ox / S

ND’ = ND ND’ = ND
Xj’ = Xj / S
L’ = L / S

SUBSTRATE DOPING NA’ = NA* S

FIGURE 2.29 Scaled dimensions and doping density.

Devices 29

2.4.2.1 Full Scaling

This scaling option attempts to preserve the magnitude of internal electric fields
in the MOSFET. To achieve this goal, potentials must be scaled down propor-
tionally. Potential scaling affects the threshold voltage. Charge densities must be
increased by a factor of S in order to maintain the field condition. This is seen in
Table 2.1.
The gate oxide capacitance per unit area is changed as follows,

ε ox ε
′ =
Cox = S ox = S ⋅Cox (2.60)
′
tox tox

The aspect ratio W/L of the MOSFET will remain unchanged under the scaling.
The transconductance parameter kn will also be scaled by a factor of S.
The linear-mode drain current of the scaled MOSFET can be found as:

kn′
I′D ( lin ) = ⋅ 2 ⋅ ( VGS
′ − VT′ ) ⋅ VDS
′ − V ′DS
2

2  

S ⋅ kn 1
= ⋅ ⋅ 2 ⋅ ( VGS − VT ) ⋅ VDS − V 2 DS 
2 S2 

I D ( lin )
=  (2.61)
S

The saturation-mode drain current is also reduced by the same scaling factor,

kn′
I D′ ( sat ) = ⋅ (VGS
′ −VT′ )
2

S ⋅kn′ 1 I D ( sat )
⋅ 2 ⋅ (VGS −VT ) =
2
= (2.62)
2 S S

TABLE 2.1
Full Scaling of MOSFET Dimensions, Potentials,
and Doping Densities
Quantity Before Scaling After Scaling
Channel length L Lʹ = L/S
Channel width W Wʹ = W/S
Gate oxide thickness tox tʹox = tox /S
Junction depth Xj Xʹj = Xj/S
Power supply voltage VDD VʹDD = VDD/S
Threshold voltage VT0 VʹT0 = VT0/S
Doping density NA NʹA = S ∙ NA
ND NʹD = S ∙ ND
30 CMOS Analog and Mixed-Signal Circuit Design

The power dissipation of the MOSFET before scaling can be written as follows,

P = I D ⋅VDS (2.63)

Full scaling reduces both the current and voltage,

1 P
P′ = I D′ ⋅VDS
′ = ⋅ I D ⋅VDS = 2 (2.64)
S2 S

Scaling of the voltage (full scaling) may not be very practical in many cases.
The effects of full scaling are depicted in Table 2.2.

2.4.2.2 Constant-Voltage Scaling

In constant-voltage scaling, all dimensions of the MOSFET are reduced by a fac-
tor of S. The power supply voltage does not change. The doping densities must be
increased by a factor of S2 in order to preserve the charge-field relation. This is seen
in Table 2.3.
The gate oxide capacitance per unit area COX is increased by a factor of S.
The transconductance parameter is also increased by S. The drain current under the
constant-voltage scaling is given by:

kn′
I′D ( lin ) = ⋅ 2 ⋅ ( VGS
′ − VT′ ) ⋅VDS
′ − V ′DS
2

2  

S ⋅kn
= ⋅ 2 ⋅ ( VGS − VT ) ⋅VDS − V 2 DS  = S ⋅ I D ( lin ) (2.65)
2 

kn′ S ⋅kn
I′D ( sat ) = ⋅ ( VGS
′ − VT′ ) = ⋅ ( VGS − VT ) = S ⋅ I D ( sat )
2 2
(2.66)
2 2

This is seen in Table 2.4. The power dissipation of the MOSFET increases by a fac-
tor of S,

′ = ( S ⋅I D ) ⋅ VDS = S ⋅P
P′ = I′D ⋅ VDS (2.67)

TABLE 2.2
Effects of Full Scaling Upon Key Device Characteristics
Quantity Before Scaling After Scaling
Oxide capacitance COX CʹOX = S ∙ COX
Drain current ID IʹD = ID/S
Power dissipation P Pʹ = P/S²
Power density P/Area Pʹ/Areaʹ = P/Area
Devices 31

TABLE 2.3
Constant-Voltage Scaling of MOSFET Dimensions,
Potentials, and Doping Densities
Quantity Before Scaling After Scaling
Dimensions W, L, tox, Xj Reduced by S
Voltages VDD, VT Remain unchanged
Doping densities NA, ND Increased by S²

TABLE 2.4
Effects of Constant-Voltage Scaling Upon Key Device
Characteristics
Quantity Before Scaling After Scaling
Oxide capacitance Cox CʹOX = S ∙ COX
Drain current ID IʹD = S ∙ ID
Power dissipation P Pʹ = S ∙ P
Power density P/Area Pʹ/Areaʹ = S3 ∙ (P/Area)

2.4.3 Weak Inversion

For an NMOS transistor operating in the subthreshold region, this is analogous to an
npn bipolar transistor, where the silicon substrate acts as the base while the source
and drain terminals represent the emitter and the collector, respectively.
The drain current for subthreshold biasing can be expressed as:

W  V −V    V 
ID = I D 0exp  GS TH  1 − exp  − DS   (2.68)
L  nVT   VT  

where W = gate width, L = gate length, I D0 = drain current when gate-source volt-
age equals threshold voltage, VGS = gate-source voltage, VTH = threshold voltage,
n = ratio of the sum of gate-oxide capacitance and depletion-region capacitance
over gate-oxide capacitance, VT = thermal voltage, and VDS = drain-source voltage.
The drain current plotted from weak to strong inversion is shown in Figure 2.30 [4].

2.4.4 Short-Channel
Short-channel device:

• The channel length is on the same order of magnitude as the depletion

region thickness of the source and drain junction
• Effective channel length is approximately equal to the source and drain
junction depth
32 CMOS Analog and Mixed-Signal Circuit Design

Log I D

Exponential region
of weak inversion
(subthreshold
biasing) Square-law region
of strong inversion

VTH VGS

FIGURE 2.30 Plot of log I D against VGS showing the exponential region of sub­threshold
­biasing and the square-law I D − VGS relationship in strong inversion. (Redrawn from
Razavi, B., Design of Analog CMOS Integrated Circuits, McGraw-Hill Education, New York,
2001.)

• The limitation imposed on the electron drift characteristics in the channel

• The modification of the threshold voltage due to the shortening channel
length
• The dependence of the surface electron mobility on the vertical electric
field can be expressed by the following empirical formula:

µno µno
µn ( eff ) = = (2.69)
1 +Θ ⋅ E x 1 + Θε ox ⋅ V −V y
toxε Si
( GS C ( ) )

where µno is the low-field surface electron mobility, and 𝛩 is an empirical factor.
Equation 2.69 can be approximated by:

µno
µn ( eff ) = (2.70)
1 +η ⋅ (VGS −VT )

The lateral electric field Ey, along with the channel, increases, as the effective chan-
nel length decreases. Drift velocity tends to saturate at high electric fields. This is
seen in Figure 2.31.

2.4.4.1 Carrier Drift Velocity Models

Based on Figure 2.32,

• Model 1: Inconsistent behavior

• Model 2: Requires infinite E field at the drain to have velocity saturation
• Hence, model 3 is preferred
Devices 33

Vsat
7
10

s
Vd (cm/s)

on
ctr
Ele
les
Ho
n

p
=µ

=µ
pe

pe
Slo

Slo

E c,n E c,p
Electric Field Ey ( V/cm)

FIGURE 2.31 Drift velocity.

1.0 7
Vsat
Model1 Model3 10
Model2
0.8 (electrons α = 2)
Vd (cm/s)

ons
Vdrift / Vsat

ctr

0.6
Ele
les

0.4
= µ Ho

Model 2
n

p
=µ

(holes α = 1)
0.2
pe

pe
Slo

Slo

0
0 1 2 3 4 E c,n E c,p
Ey/Ec Electric Field Ey ( V/cm)

FIGURE 2.32 Carrier drift velocity models.

Model 3 is given by:

Ey
vd = µn ( eff ) ⋅ for E y < Ec (2.71)
E 
1+ y 
 Ec 

vd = vsat for E y > Ec (2.72)

2.4.4.2 VDSAT
At the boundary of saturation and linear regions, the drain-source voltage of the
MOS transistor is VDSAT and ID(lin) = ID(sat).
34 CMOS Analog and Mixed-Signal Circuit Design

VDSAT =
( VGS − VT ) ⋅ EC L (2.73)
( VGS − VT ) + EC L
Saturation current equation can be rewritten as:

(VGS −VT )
2

I D ( sat ) = W ⋅ vsat ⋅COX ⋅ (2.74)

(VGS −VT ) + EC L

µ C W EC L ⋅ (VGS −VT )
2

= n OX ⋅ ⋅ (2.75)
2 L (VGS −VT ) + EC L

2.4.4.3 Current-Voltage Equation for Short Channel Transistor

• Current-voltage equation for short channel nMOS transistor:

I D = I leakage ≅ 0, for VGS <VT (2.76)

µn ⋅ COX W 1
I D ( lin ) = ⋅ ⋅ ⋅ 2 ⋅ ( VGS − VT ) ⋅ VDS − V 2 DS  (2.77)
2 L  VDS  
1+  
 EC L 

For VGS ≥ VT and VDS <

( VGS − VT ) ⋅ EC L
( VGS − VT ) + EC L

(VGS −VT ) ⋅ 1 + λ ⋅V
2

I D ( sat ) =W ⋅ vsat , n ⋅COX ⋅ ( DS ) (2.78)

(VGS −VT ) + EC L

For VGS ≥ VT and VDS <

(VGS −VT ) ⋅ EC L
(VGS −VT ) + EC L
• Current-voltage equations for short channel pMOS transistor:

I D = I leakage ≅ 0, for VGS <VT

µ P ⋅ COX W 1
I D ( lin ) =
2
⋅
L
⋅
 VSD  
( )
⋅ 2 ⋅ VSG − VT ⋅ VSD − V 2 SD 

(2.79)
1+  
 EC L 

For VSG ≥ VT and VSD <

(V SG )
− VT ⋅ EC L
(V SS − VT )+E C L
Devices 35

(VSG − VT ) ⋅(1 + λ ⋅V )
2

I D ( sat ) = W ⋅ vsat , p ⋅ COX ⋅ (2.80)

(VSG − VT ) + EC L SD

For VSG ≥ VT and VSD >

(V
SG )
− VT ⋅ EC L
(V
SG − VT )+E
C L

2.4.5 MOSFET Capacitor
As seen in Figure 2.33, the channel length is given by:

L = LM − 2 ⋅ LD (2.81)

Additional p+ region is to prevent the formation of any unwanted (parasitic) chan-

nels between two neighboring n+ diffusion regions.
Parasitic device capacitances can be classified into two major groups:

1. Oxide-related capacitance
2. Junction capacitance

LD LD

GATE
(n +) (n +) W

LM Channel – stop Implant

GATE

tox DRAIN
SOURCE OXIDE

(n +) (n +)
(p +) L Xj (p+)

SUBSTRATE (p-Si )

FIGURE 2.33 View of the NMOS.

36 CMOS Analog and Mixed-Signal Circuit Design

2.4.5.1 Oxide-Related Capacitance

The gate electrode overlaps both the source region and the drain region at the edges.
There are two overlap capacitances that arise as a result of this structural arrange-
ment. The overlap capacitances can be found as:

CGS ( overlap ) = COX ⋅ W ⋅ LD

CGD ( overlap ) = COX ⋅ W ⋅ LD (2.82)

With

ε OX
COX = (2.83).
tOX

Capacitances which result from the interaction between the gate voltage and the chan-
nel charge are Cgs, Cgd, and Cgb. Figure 2.34 shows the representation of MOSFET
oxide capacitances during cut-off, linear and saturation modes.

• Cut-off mode:
• The surface is not inverted
• No conducting channel between source and drain, so Cgs = Cgd = 0
• The gate-to-substrate capacitance can be approximated by:

Cgb = Cox ⋅ W ⋅ L (2.84)

• Linear mode:
• The inverted channel extends across the MOSFET
• Conducting inversion layer shields the substrate from the gate electric
field: Cgb = 0
• The distributed gate-to-channel capacitance (equal S, D):

1
Cgs ≅ Cgd ≅ ⋅ COX ⋅ W ⋅ L (2.85)
2

• Saturation mode:
• The inversion region is pinched off
• The gate-to-drain capacitance component is equal to zero, Cgd = 0
• Source still linked to the conducting channel. Shielding effect still remains:
Cgb = 0
• The distributed gate-to-channel capacitance as seen between the gate and
the source can be approximated by:

2
Cgs ≅ ⋅ COX ⋅ W ⋅ L (2.86)
3
Devices 37

GATE

SOURCE OXIDE DRAIN

(n+) (n+)

(a) SUBSTRATE (p-Si)

GATE

SOURCE DRAIN

(n+) (n+)
CHANNEL

(b) SUBSTRATE (p-Si)

GATE

SOURCE DRAIN

(n+) (n+)

CHANNEL
(c) SUBSTRATE (p-Si)

FIGURE 2.34 MOSFET oxide capacitances during (a) cut-off, (b) linear, and (c) saturation
modes.

Table 2.5 lists a summary of the approximate oxide capacitance values.

We have to combine the distributed Cgs and Cgd values found here with the
relevant overlap capacitance values, in order to calculate the total capacitance
between the external device terminals. Variation of the distributed (gate-to-­
channel) oxide capacitances as a function of the gate-to-source voltage is shown
in Figure 2.35.

2.4.5.2 Junction Capacitance

Consider the voltage-dependent source-substrate and drain-substrate junction capac-
itances: Csb and Cdb.
Csb and Cdb are due to the depletion charge surrounding the respective source or
drain diffusion regions embedded in the substrate. This is seen in Figure 2.36.
38 CMOS Analog and Mixed-Signal Circuit Design

TABLE 2.5
Lists a Summary of the Approximate Oxide Capacitance Values
Capacitance Cut-off Linear Saturation
Cgb (total) COXWL 0 0
Cgd (total) COXWLD 1/2COXWL + COXWLD COXWLD
Cgs (total) COXWLD 1/2COXWL + COXWLD 2/3COXWL + COXWLD

Cut–off Saturation Linear

Normalized Capacitance (C / Cox WL)

1
Cgb

Cgs
2/3

1/2

Cgd

VT VT + VDS
Gate-to-source Voltage (VGS)

FIGURE 2.35 Variation of the distributed (gate-to-channel) oxide capacitances as function

of gate-to-source voltage.

• Both of these junctions are reverse-biased under normal operating conditions

• The amount of junction capacitance is a function of the applied terminal
voltages
• Junction capacitances associated with sidewalls (2,3,4) will be different
from the other junction capacitance

Assuming that the reverse bias voltage is given by V:

• The depletion region thickness can be found as follows:

2 ⋅ ε Si N A + N D
xd = ⋅ ⋅ ( ∅0 − V ) (2.87)
q NA ⋅ ND

• The built-in junction potential is calculated as:

kT N ⋅ N 
∅0 = ⋅ ln  A 2 D  (2.88)
q  ni 
Devices 39

Gate Oxide
Y

2 Xj

1
5 3

Channel 4

Source and
Drain Diffusion
Regions
Junction Area Type
1 W · xj n+ / p
2 Y · xj n+ / p+
3 W · xj n+ / p+
4 Y · xj n+ / p+
5 W · xj n+ / p

FIGURE 2.36 Junction capacitance.

• The junction is forward-biased for positive bias voltage V and reversed-

biased for negative bias voltage
• The depletion region charge stored in this area is:

 N ⋅ ND  NA − ND
Q j = A ⋅ q ⋅ A  ⋅ xd = A 2 ⋅ε Si ⋅ q ⋅ N + N ⋅ ( ∅ 0 − V ) (2.89)
 NA + ND  A D

• The junction capacitance associated with the depletion region is defined as:

dQj
Cj = (2.90)
dV

• By differentiating Equation 2.89, we can obtain the expression for the junc-
tion capacitance as follows,

ε Si ⋅ q  N A ⋅ N D  1
Cj (V ) = A ⋅ ⋅ (2.91)
2  N A + N D  ∅0 − V
40 CMOS Analog and Mixed-Signal Circuit Design

• This expression can be rewritten in a more general form:

A ⋅Cj0
Cj (V ) = m
(2.92)
 V 
1 − ∅ 
 0 

The parameter m is called the grading coefficient

• The zero-bias junction capacitance per unit area Cj0 is defined as:

ε Si ⋅ q  N A ⋅ N D  1
Cj0 = ⋅ ⋅ (2.93)
2  N A + N D  ∅ 0

• The value of the junction capacitance Cj given by Equation 2.92 ultimately

depends on the external bias voltage that is applied across the PN-junction.
• Equivalent large-signal capacitance can be defined as follows:

∆Q Qj ( V2 ) − Qj ( V1 ) 1 V2
Ceq =
∆V
=
V2 − V1
=
V2 − V1
⋅
∫ V1
C j ( V ) ⋅ dV (2.94)

• By substituting Equation 2.92 into 2.94:

2 ⋅ A ⋅ C j 0 ⋅∅ 0  
1− m 1−m
V   V 
Ceq = − ⋅  1 − 2  −  1 − 1   (2.95)
(V2 −V1 ) (1 − m )  ∅0   ∅0  


• For the special case of abrupt PN-junctions, Equation 2.95 becomes,

2 ⋅ A⋅C j 0 ⋅∅ 0  V V 
Ceq = − ⋅ 1− 2 − 1− 1  (2.96)
(V2 −V1 )  ∅0 ∅0 

• This equation can be rewritten in a simpler form by defining a dimension-

less coefficient Keq as follows:

Keq = A ⋅ C j 0 ⋅ Keq (2.97)

Keq = −
2 ∅0
V2 − V1
⋅ ( ∅ 0 − V2 − ∅ 0 − V1 ) (2.98)

Keq is the voltage equivalence factor (0 < Keq < 1).

2.4.6 MOSFET Transition Frequency

The transition frequency of a transistor is the frequency when the current gain is
unity. Generally, it is equal to = 2π g(Cmgs ) if Cgs >>> Cgd . This parameter is considered
Devices 41

as a figure of merit of transistor or technology. If one wants to design an amplifier

with a bandwidth of 100 MHz, the transition frequency should be at least ten times
the amplifier bandwidth, i.e., 1 GHz.

2.4.7 Noise
2.4.7.1 Thermal Noise
Thermal noise is, in general, associated with the random motion of particles in a
force-free environment. Since the mean available energy per degree of freedom
is proportional to temperature, the resulting noise is referred to as thermal noise.
The thermal noise of a resistor is shown in Figure 2.37.

V 2 n = 4kTR ( ∆f )

4kT
I 2n = , if R = 50, T = 300 K, So Vn = 0.91 nV/√ Hz.
R

For MOSFET thermal noise, see Figure 2.38.

The parameter γ is typically 2/3 for a long channel, and as high as 2.5 for submi-
cron devices.
Figure 2.39 shows the Ohmic noise sources.

Sv ( f )

R 4kTR

Noiseless − +
Resistor f

Noiseless
R
Resistor

FIGURE 2.37 Resistor thermal noise.

=4

FIGURE 2.38 MOSFET thermal noise.

42 CMOS Analog and Mixed-Signal Circuit Design

(a) S

+
, -

RD
,
R1
+ -

RS

,
-
+

(b)
D

RG1 RG2 RGN

G

+ +∙∙∙ + =
(c) S

FIGURE 2.39 Ohmic noise of transistor. (a) The layout of a MOSFET indicating gate,
source and drain resistances; (b) circuit model with thermal noises; and (c) distributed gate
resistance.

2.4.7.2 Flicker Noise

Flicker noise is, in general, a phenomenon observed in many systems with an
inverse frequency dependence of the noise spectral density over a wide frequency
regime. In semiconductors, the presence of energy traps (at the interface) can lead
to the generation and recombination of carriers and a corresponding frequency-
dependent noise of the flicker noise type. An interface of MOSFET is shown in
Figure 2.40 and the flicker noise curve of a transistor is depicted in Figure 2.41.

K 1
V 2n =
Cox WL f

2  K 1 K 3
4kT  gm  ≈ gm2 , so f c ≈ gm , app. for long channel.
 3  CoxWL f c CoxWL 8kT
Devices 43

Polysilicon

SiO2

Dangling
Bonds

Silicon
Crystal

FIGURE 2.40 Interface.

20 log

1 Corner

Thermal

f
fC

FIGURE 2.41 Flicker noise curve.

2.5 PROCESS FITTING RATIO

The relationship between the TARGET and ORIGINAL process technology can be
obtained using Equation 2.99.

WT WS K S (VGS , S − VT , S )
= (2.99)
LT LS KT (VGS ,T − VT ,T )

Equation 2.99 can be simplified to Equation 2.100 as follows:

WT WS
= C (2.100)
LT LS
44 CMOS Analog and Mixed-Signal Circuit Design

where:

KS ( VGS,S − VT ,S )
C=
KT ( VGS,T − VT ,T )

KS is the original transconductance parameter in ORIGINAL process technology, KT

is the target transconductance parameter in process technology, VT ,S is the original
threshold voltage of MOS in ORIGINAL process technology, and VT ,T is the target
threshold voltage of MOS in TARGET process technology.

2.5.1 150–90 nm Design Transfer

First of all, the NMOS scale ratio will be discussed as follows. The initial width of
the transistor is set to 6 µm, and the length of the transistor is set to 3 µm. The I D
versus VDS curve with different VGS voltages of 0 V, 1 V, 1.5 V, 2 V, and 3.3 V is plot-
ted by simulation with sweeping VDS from 0 V to 3.3 V. Same as the first method,
the standard source (150 nm) W/L size that is commonly used for the initial process
porting is W = 6 µm and L = 3 µm. Figure 2.42 shows the I D versus VDS curve for the
NMOS transistor with different VGS voltages in the 150 nm process technology with
a NMOS transistor size of W = 6 µm and L = 3 µm.
As the supply rail for the analog circuit design system used is 3.3 V, the gate-
to-source voltage, VGS, is fixed to 1.5 V as a reference to start the fitting, with the
reference size to get to the scale-down ratio between the 90 nm and 150 nm process
technology. In the 90 nm process technology, the length of the NMOS transistor, L,
is fixed to 2 µm, and then the different NMOS transistor width is simulated and plot-
ted with the I D versus VDS curve. Figure 2.43 shows that the I D versus VDS curve with
different transistor width, W, compares to the NMOS transistor size of W = 6 µm and
L = 3 µm in the 150 nm process technology.
Figure 2.43 shows that the W/L size of 2.1/2 is closer to the black line, which is
the W/L size of 6/3. It shows that the NMOS W/L size of 6/3 in the 150 nm process

FIGURE 2.42 I D versus VDS curve for the NMOS transistor with different VGS in the 150 nm.
Devices 45

FIGURE 2.43 Fitting of I D versus VDS curve with different W size in the 90 nm to W/L size
of 6/3 in the 150 nm.

technology has the almost same characteristic with NMOS W/L size of 2.1/2 in the
90 nm process technology.
Next, the PMOS scale-down ratio will be discussed as follows. The initial width
of the transistor is set to 13 µm, and the length of the transistor is set to 3 µm. The I D
versus VDS curve with different VGS voltages of 0 V, 1 V, 1.5 V, 2 V, and 3.3 V is plot-
ted by simulation with sweeping VDS from 0 V to 3.3 V. Same as the first method,
the standard source (150 nm) W/L size that is commonly used for the initial process
porting is W = 13 µm and L = 3 µm. Figure 2.44 shows the I D versus VDS curve for
the PMOS transistor with different VGS in the 150 nm process technology with the
PMOS transistor size of W = 13 µm and L = 3 µm.
In this case, the same as with the NMOS conversion, the PMOS gate-to-source
voltage, VGS, is fixed to 1.5 V as a reference to start the fitting, with the reference size

FIGURE 2.44 I D versus VDS curve for the PMOS transistor with different VGS in the 150 nm.
46 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 2.45 Fitting of I D versus VDS curve with different W size in the 90 nm to W/L size
of 6/3 in 150 nm.

to get to the scale-down ratio between the 90 nm and 150 nm process technology.
In the 90 nm process technology, the length of the PMOS transistor, L, is fixed to
2 µm, and then the different NMOS transistor width is simulated and plotted with
the I D versus VDS curve. Figure 2.45 shows that the I D versus VDS curve with the dif-
ferent transistor width, W, compares to the PMOS transistor size of W = 13 µm and
L = 3 µm in the 150 nm process technology.
Figure 2.45 shows that the W/L size of 3.8/2 is closer to the black line, which is
W/L size of 13/3. It shows that the PMOS W/L size of 13/3 in the 150 nm process
technology has the almost same characteristic with the PMOS W/L size of 3.8/2 in
the 90 nm process technology.

2.6 MOSFET PARAMETER EXERCISE

Even though knowing the device physic is important, the transistor model, such as
BSIM, is also important. These exercises are all about using a transistor model (using
Tables 2.6 and 2.7) with SPICE simulation in order to determine the parameters for
hand calculation (the simplest model or modeling). The outcome of these exercises
is in Tables 2.8 and 2.9.

1. The threshold voltages of both a long-channel and short-channel device

are provided in the model file (Tables 2.6 and 2.7), however, for the short-
channel device, gm vs. Vgs can be used to determine the threshold voltage.
The linear gm can be extrapolated to the x-axis to estimate Vgs when gm is
zero, the Vgs is equal to Vth.
Devices 47

2. The transconductance parameter, KP, is provided in the model file or can

be calculated as KP = µCox. However, this parameter is not useful with the
short-channel device. Other parameters such as oxide thickness are pro-
vided in the model file. As the ε ox is easily known, Cox can be calculated.
Velocity saturation, Vsat, is applicable for short-channel devices. The value
is also available in the model file.

TABLE 2.6
BSIM3 Models for American Microsystem Inc (AMI) Semiconductor’s C5
Process
* BSIM3 models for AMI semiconductor’s C5 process
*
* Don’t forget the options scale=300nm if using drawn lengths
* and the MOSIS SUBM design rules
*
* 2<Ldrawn<500 10<Wdrawn<10000 Vdd=5V
* Note minimum L is 0.6 um while minimum W is 3 um
* Change to level=49 when using HSPICE
.MODEL NMOS_L NMOS ( LEVEL = 8
+VERSION = 3.1 TNOM = 27 TOX = 1.39E-8
+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = 0.6696061
+K1 = 0.8351612 K2 = −0.0839158 K3 = 23.1023856
+K3B = −7.6841108 W0 = 1E-8 NLX = 1E-9
+DVT0W =0 DVT1W =0 DVT2W =0
+DVT0 = 2.9047241 DVT1 = 0.4302695 DVT2 = −0.134857
+U0 = 458.439679 UA = 1E-13 UB = 1.485499E-18
+UC = 1.629939E-11 VSAT = 1.643993E5 A0 = 0.6103537
+AGS = 0.1194608 B0 = 2.674756E-6 B1 = 5E-6
+KETA = −2.640681E-3 A1 = 8.219585E-5 A2 = 0.3564792
+RDSW = 1.387108E3 PRWG = 0.0299916 PRWB = 0.0363981
+WR =1 WINT = 2.472348E-7 LINT = 3.597605E-8
+XL =0 XW =0 DWG = −1.287163E-8
+DWB = 5.306586E-8 VOFF =0 NFACTOR = 0.8365585
+CIT =0 CDSC = 2.4E-4 CDSCD =0
+CDSCB =0 ETA0 = 0.0246738 ETAB = −1.406123E-3
+DSUB = 0.2543458 PCLM = 2.5945188 PDIBLC1 = −0.4282336
+PDIBLC2 = 2.311743E-3 PDIBLCB = −0.0272914 DROUT = 0.7283566
+PSCBE1 = 5.598623E8 PSCBE2 = 5.461645E-5 PVAG =0
+DELTA = 0.01 RSH = 81.8 MOBMOD =1
+PRT = 8.621 UTE = −1 KT1 = −0.2501
+KT1L = −2.58E-9 KT2 =0 UA1 = 5.4E-10
+UB1 = −4.8E-19 UC1 = −7.5E-11 AT = 1E5
+WL =0 WLN =1 WW =0
+WWN =1 WWL =0 LL =0
+LLN =1 LW =0 LWN =1
+LWL =0 CAPMOD = 2 XPART = 0.5
(Continued)
48 CMOS Analog and Mixed-Signal Circuit Design

TABLE 2.6 (Continued)

BSIM3 Models for American Microsystem Inc (AMI) Semiconductor’s C5
Process
+CGDO = 2E-10 CGSO = 2E-10 CGBO = 1E-9
+CJ = 4.197772E-4 PB = 0.99 MJ = 0.4515044
+CJSW = 3.242724E-10 PBSW = 0.1 MJSW = 0.1153991
+CJSWG = 1.64E-10 PBSWG = 0.1 MJSWG = 0.1153991
+CF =0 PVTH0 = 0.0585501 PRDSW = 133.285505
+PK2 = −0.0299638 WKETA = −0.0248758 LKETA = 1.173187E-3
+AF =1 KF = 0)
*
.MODEL PMOS_L PMOS ( LEVEL = 8
+VERSION = 3.1 TNOM = 27 TOX = 1.39E-8
+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = −0.9214347
+K1 = 0.5553722 K2 = 8.763328E-3 K3 = 6.3063558
+K3B = −0.6487362 W0 = 1.280703E-8 NLX = 2.593997E-8
+DVT0W =0 DVT1W =0 DVT2W =0
+DVT0 = 2.5131165 DVT1 = 0.5480536 DVT2 = −0.1186489
+U0 = 212.0166131 UA = 2.807115E-9 UB = 1E-21
+UC = −5.82128E-11 VSAT = 1.713601E5 A0 = 0.8430019
+AGS = 0.1328608 B0 = 7.117912E-7 B1 = 5E-6
+KETA = −3.674859E-3 A1 = 4.77502E-5 A2 = 0.3
+RDSW = 2.837206E3 PRWG = −0.0363908 PRWB = −1.016722E-5
+WR =1 WINT = 2.838038E-7 LINT = 5.528807E-8
+XL =0 XW =0 DWG = −1.606385E-8
+DWB = 2.266386E-8 VOFF = −0.0558512 NFACTOR = 0.9342488
+CIT =0 CDSC = 2.4E-4 CDSCD =0
+CDSCB =0 ETA0 = 0.3251882 ETAB = −0.0580325
+DSUB =1 PCLM = 2.2409567 PDIBLC1 = 0.0411445
+PDIBLC2 = 3.355575E-3 PDIBLCB = −0.0551797 DROUT = 0.2036901
+PSCBE1 = 6.44809E9 PSCBE2 = 6.300848E-10 PVAG =0
+DELTA = 0.01 RSH = 101.6 MOBMOD =1
+PRT = 59.494 UTE = −1 KT1 = −0.2942
+KT1L = 1.68E-9 KT2 =0 UA1 = 4.5E-9
+UB1 = −6.3E-18 UC1 = −1E-10 AT = 1E3
+WL =0 WLN =1 WW =0
+WWN =1 WWL =0 LL =0
+LLN =1 LW =0 LWN =1
+LWL =0 CAPMOD = 2 XPART = 0.5
+CGDO = 2.9E-10 CGSO = 2.9E-10 CGBO = 1E-9
+CJ = 7.235528E-4 PB = 0.9527355 MJ = 0.4955293
+CJSW = 2.692786E-10 PBSW = 0.99 MJSW = 0.2958392
+CJSWG = 6.4E-11 PBSWG = 0.99 MJSWG = 0.2958392
+CF =0 PVTH0 = 5.98016E-3 PRDSW = 14.8598424
+PK2 = 3.73981E-3 WKETA = 5.292165E-3 LKETA = −4.205905E-3
+AF =1 KF = 0)
Devices 49

TABLE 2.7
Customized Predictive Technology Model (PTM) 45 PMOS
* Customized PTM 45 PMOS
.model PMOS_S pmos level = 54
+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1
+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
* parameters related to the technology node
+tnom = 27 epsrox = 3.9
+eta0 = 0.0049 nfactor = 2.1 wint = 5e-09
+cgso = 1.1e-10 cgdo = 1.1e-10 xl = −2e-08
* parameters customized by the user
+toxe = 1.85e-09 toxp = 1.1e-09 toxm = 1.85e-09 toxref = 1.85e-09
+dtox = 7.5e-10 lint = 3.75e-09
+vth0 = −0.423 k1 = 0.491 u0 = 0.00432 vsat = 70000
+rdsw = 155 ndep = 2.54e+18 xj = 1.4e-08
*secondary parameters
+ll =0 wl =0 lln =1 wln =1
+lw =0 ww =0 lwn =1 wwn =1
+lwl =0 wwl =0 xpart =0
+k2 = −0.01 k3 =0
+k3b =0 w0 = 2.5e-006 dvt0 =1 dvt1 =2
+dvt2 = −0.032 dvt0w =0 dvt1w =0 dvt2w =0
+dsub = 0.1 minv = 0.05 voffl =0 dvtp0 = 1e-009
+dvtp1 = 0.05 lpe0 =0 lpeb =0
+ngate = 2e+020 nsd = 2e+020 phin =0
+cdsc = 0.000 cdscb =0 cdscd =0 cit =0
+voff = −0.126 etab =0
+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018
+uc =0 a0 = 1.0 ags = 1e-020
+a1 =0 a2 =1 b0 = −1e-020 b1 =0
+keta = −0.047 dwg =0 dwb =0 pclm = 0.12
+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56
+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007
+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006
+rsh =5 rsw = 85 rdw = 85
+rdswmin = 0 rdwmin =0 rswmin =0 prwg = 3.22e-008
+prwb = 6.8e-011 wr =1 alpha0 = 0.074 alpha1 = 0.005
+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002
+egidl = 0.8
+aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002
+nigbacc =1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004
+eigbinv = 1.1 nigbinv =3 aigc = 0.69 bigc = 0.0012
+cigc = 0.0008 aigsd = 0.0087 bigsd = 0.0012 cigsd = 0.0008
+nigc =1 poxedge =1 pigcd =1 ntox =1
(Continued)
50 CMOS Analog and Mixed-Signal Circuit Design

TABLE 2.7 (Continued)

Customized Predictive Technology Model (PTM) 45 PMOS
+xrcrg1 = 12 xrcrg2 =5
+cgbo = 2.56e-011 cgdl = 2.653e-10
+cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde =1
+moin = 15 noff = 0.9 voffcv = 0.02

+kt1 = −0.11 kt1l =0 kt2 = 0.022 ute = −1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = −5.6e-011 prt =0
+at = 33000
+fnoimod = 1 tnoimod = 0
+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs =1
+ijthsfwd = 0.01 ijthsrev = 0.001 bvs = 10 xjbvs =1
+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd =1
+ijthdfwd = 0.01 ijthdrev = 0.001 bvd = 10 xjbvd =1
+pbs =1 cjs = 0.0005 mjs = 0.5 pbsws =1
+cjsws = 5e-010 mjsws = 0.33 pbswgs =1 cjswgs = 3e-010
+mjswgs = 0.33 pbd =1 cjd = 0.0005 mjd = 0.5
+pbswd =1 cjswd = 5e-010 mjswd = 0.33 pbswgd =1
+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001
+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001
+xtis =3 xtid =3
+dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007
+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008
+rshg = 0.4 gbmin = 1e-010 rbpb =5 rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15 ngcon =1
* Customized PTM 45 NMOS
.model NMOS_S nmos level = 54
+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1
+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
* parameters related to the technology node
+tnom = 27 epsrox = 3.9
+eta0 = 0.0049 nfactor = 2.1 wint = 5e-09
+cgso = 1.1e-10 cgdo = 1.1e-10 xl = −2e-08
* parameters customized by the user
+toxe = 1.75e-09 toxp = 1.1e-09 toxm = 1.75e-09 toxref = 1.75e-09
+dtox = 6.5e-10 lint = 3.75e-09
+vth0 = 0.471 k1 = 0.53 u0 = 0.04359 vsat = 147390
+rdsw = 155 ndep = 3.3e+18 xj = 1.4e-08
* secondary parameters
+ll =0 wl =0 lln =1 wln =1
+lw =0 ww =0 lwn =1 wwn =1
+lwl =0 wwl =0 xpart =0
+k2 = 0.01 k3 =0
+k3b =0 w0 = 2.5e-006 dvt0 =1 dvt1 =2
(Continued)
Devices 51

TABLE 2.7 (Continued)

Customized Predictive Technology Model (PTM) 45 PMOS
+dvt2 = −0.032 dvt0w =0 dvt1w =0 dvt2w =0
+dsub = 0.1 minv = 0.05 voffl =0 dvtp0 = 1.0e-009
+dvtp1 = 0.1 lpe0 =0 lpeb =0
+ngate = 2e+020 nsd = 2e+020 phin =0
+cdsc = 0.000 cdscb =0 cdscd =0 cit =0
+voff = −0.13 etab =0
+vfb = −0.55 ua = 6e-010 ub = 1.2e-018
+uc =0 a0 = 1.0 ags = 1e-020
+a1 =0 a2 = 1.0 b0 =0 b1 =0
+keta = 0.04 dwg =0 dwb =0 pclm = 0.04
+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = −0.005 drout = 0.5
+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007
+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006
+rsh =5 rsw = 85 rdw = 85
+rdswmin =0 rdwmin =0 rswmin =0 prwg =0
+prwb = 6.8e-011 wr =1 alpha0 = 0.074 alpha1 = 0.005
+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002
+egidl = 0.8
+aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002
+nigbacc =1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004
+eigbinv = 1.1 nigbinv =3 aigc = 0.012 bigc = 0.0028
+cigc = 0.002 aigsd = 0.012 bigsd = 0.0028 cigsd = 0.002
+nigc =1 poxedge =1 pigcd =1 ntox =1
+xrcrg1 = 12 xrcrg2 =5
+cgbo = 2.56e-011 cgdl = 2.653e-10
+cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde =1
+moin = 15 noff = 0.9 voffcv = 0.02
+kt1 = −0.11 kt1l =0 kt2 = 0.022 ute = −1.5
+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = −5.6e-011 prt =0
+at = 33000
+fnoimod = 1 tnoimod = 0
+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs =1
+ijthsfwd = 0.01 ijthsrev = 0.001 bvs = 10 xjbvs =1
+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd =1
+ijthdfwd = 0.01 ijthdrev = 0.001 bvd = 10 xjbvd =1
+pbs =1 cjs = 0.0005 mjs = 0.5 pbsws =1
+cjsws = 5e-010 mjsws = 0.33 pbswgs =1 cjswgs = 3e-010
+mjswgs = 0.33 pbd =1 cjd = 0.0005 mjd = 0.5
+pbswd =1 cjswd = 5e-010 mjswd = 0.33 pbswgd =1
+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001
+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001
+xtis =3 xtid = 3
+dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007
+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008
+rshg = 0.4 gbmin = 1e-010 rbpb =5 rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15 ngcon =1
 52

TABLE 2.8
Summary of Device Characteristics for the Long-Channel CMOS Process
Supply Voltage (VDD) = 5 V Minimum L = 0.5 μm NMOS in Inversion (Saturation):

KPn W
Parameter NMOS PMOS Notes ID = (VGS − VTHN )2 (1 + λ nVds )
2 L
W W
VTHN and VTHP 700 mV 900 mV Typical gm = KPn (VGS − VTHN ) = 2 KPn ID
L L
1
KPn and KPp 100 μA/V2 45 μA/V2 tox = 139 A ro =
λ n I DSAT
ε ox ε ox
′
= Cox 2.5 fF/μm2 2.5 fF/μm2 Cox = WL ⋅ (scale)2
tox tox

λn and λp 0.02 V−1 0.02 V−1 At L = 2 μm.

Note: VSG = 1.25 V, PMOS W/L = 20/2, VGS = 1.01 V, NMOS W/L = 10/2, Id = 20 μA.
CMOS Analog and Mixed-Signal Circuit Design
 Devices

TABLE 2.9
Summary of Device Characteristics for the Short-Channel CMOS Process
NMOS in Inversion (Saturation):
VDD = 1 V Minimum L = 45 nm Overdrive voltage, Vov = VGS − VTHN

Parameter NMOS PMOS Notes I D = vsatnWCox

′ (VGS − VTHN − VDSsatn )

VTHN and VTHP 330 mV 390 mV Typical (lower than the model parameter) ′
gm = vsatnWCox
1
vsatn and vsatp 147 × 103 m/s 70 × 103 m/s PTM Model ro =
λ n I DSAT
ε ox 20 fF/μm2 19 fF/μm2 ε ox 2
′
= Cox Cox = WL ⋅ ( scale )
tox tox = 17.5 A tox = 18.5 A tox
λn and λp 0.25 V−1 0.25 V−1 At L = 100 nm
VDSsatn and VDSsatp 50 mV 50 mV Vov = VGS − VTHN [VGS = 400 mV]
Vovn and Vovp 70 mV 70 mV

Note: VSG = 0.46 V, PMOS W/L = 5 μm/100 nm, VSG = 0.4 V, NMOS W/L = 2.5 μm/100 nm, Id = 10 μA.
Overdrive is ~5%VDD (1 V).
53
54 CMOS Analog and Mixed-Signal Circuit Design

3. λ is called the channel length modulation coefficient. λ = ro ⋅I DSAT

1
. The out-
put resistance, ro, is found by simulation of a transistor with the model file
(Tables 2.6 and 2.7).
4. For the short-channel device, the off current/width with Vgs = 0 V is
I
I off = leakage .
W ⋅ Scale

2.7 SPICE EXAMPLE

The example of current-voltage (IV) curves in Figures 2.46 and 2.47 shows the
threshold voltage and body effect. The schematics of the simulation circuits are
shown in Figures 2.48 and 2.49.

3.0x10-3

2.5x10-3

2.0x10-3
Id (A)

1.5x10-3

1.0x10-3

5.0x10-4

0.0
0 2 4
(a) Vds (V)

2.0x10-4

0.0

-2.0x10-4

-4.0x10-4

-6.0x10-4
Id (A)

-8.0x10-4

-1.0x10-3

-1.2x10-3

-1.4x10-3

-1.6x10-3
0 2 4
(b) Vsd (V)

FIGURE 2.46 IV curves: (a) NMOS 0.5 μm, (b) PMOS 0.5 μm. (Continued)
Devices 55

-4
5.5x10
-4
5.0x10
-4
4.5x10
-4
4.0x10
-4
3.5x10
Id (A)

-4
3.0x10
-4
2.5x10
-4
2.0x10
-4
1.5x10
-4
1.0x10
-5
5.0x10
0.0
-5
-5.0x10
0.0 0.5 1.0
(c) Vds (V)

-6
5.0x10
0.0
-6
-5.0x10
-5
-1.0x10
-5
-1.5x10
-5
-2.0x10
-5
-2.5x10
-5
-3.0x10
-5
-3.5x10
Id (A)

-5
-4.0x10
-5
-4.5x10
-5
-5.0x10
-5
-5.5x10
-5
-6.0x10
-5
-6.5x10
-5
-7.0x10
-5
-7.5x10
-5
-8.0x10
-5
-8.5x10
-5
-9.0x10
0.0 0.5 1.0
(d) Vsd (V)

FIGURE 2.46 (Continued) IV curves: (c) NMOS 45 nm, and (d) PMOS 45 nm.
56 CMOS Analog and Mixed-Signal Circuit Design

-4
4.0x10
Id (A)

-4
2.0x10

0.0
0.0 0.5 1.0 1.5
(a) Vgs (V)

0.0
Id (A)

-4
-1.0x10

-4
-2.0x10

0 1 2
(b) VSG (V)

FIGURE 2.47 Threshold and body effect: (a) NMOS 0.5 μm, (b) PMOS 0.5 μm.
 (Continued)
Devices 57

-4
3.0x10

-4
2.0x10
Id (A)

-4
1.0x10

0.0
0.0 0.2 0.4 0.6 0.8

(c) Vgs (V)

0.0
Id (A)

-5
-2.0x10

-5
-4.0x10

0.0 0.2 0.4 0.6 0.8

(d) VSG (V)

FIGURE 2.47 (Continued) Threshold and body effect: (c) NMOS 45 nm, and (d) PMOS
45 nm.
58 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 2.48 Schematic a simulation of the IV curve.

FIGURE 2.49 Body effect simulation schematic.

Using Tables 2.8 and 2.9, the current can be estimated. From Figure 2.46c and d,
the on current for the NMOS is = 500 µA/(W · scale) = 500 µA/µm, and for PMOS
is = 80 µA/(W · scale) = 80 µA/µm.

2.8 SUMMARY
The understanding of the devices is essentially important in circuit design. Even
though this chapter focuses only on CMOS devices, such as MOSFET and photo
devices, it should be treated as a method to understand a device. Photo devices are
considered “sensor” devices, which in the future, other devices could be integrated
into the standard CMOS process or technology. A simple exercise on how to deter-
mine the MOSFET parameter is also explained in this chapter. Knowing both device
physic and modeling is undeniable crucial for the next chapters. Without a thorough
understanding of the device, one may find difficulties in designing a circuit.
Devices 59

REFERENCES
1. Ardeshirpour, Y., Deen, M. J., and Shirani, S. (2004). 2-D CMOS based image sensor
system for fluorescent detection. Canadian Conference on Electrical and Computer
Engineering, IEEE (pp. 1441–1444).
2. Scheffer, D., Dierickx, B., and Meynants, G. (1997). Random addressable 2048 × 2048
active pixel image sensor. IEEE Transactions on Electron Devices, 44(10), 1716–1720.
3. Lulé, T., Benthien, S., Keller, H., Mütze, F., Rieve, P., Seibel, K., and Böhm, M. (2000).
Sensitivity of CMOS based imagers and scaling perspectives. IEEE Transactions on
Electron Devices, 47(11), 2110–2122.
4. Razavi, B. (2001). Design of Analog CMOS Integrated Circuits. New York: McGraw-
Hill Education.
 3 Amplifiers

3.1 INTRODUCTION
This chapter provides a brief introduction to the basic complementary metal-oxide
semiconductor (CMOS) amplifier, in particular, the two-stage CMOS amplifier.
This chapter use the signal path as design insight. A new technique called the cur-
rent density approach is also discussed in the last part of this chapter.

3.1.1 CMOS Amplifier

Figure 3.1 shows a two-stage operational amplifier. Reference current Iref is
­generated/sourced from a voltage reference circuit. The input stage together with
M12 and M14 forms a folded cascade configuration. M15 and M16 act as an active load
for the first-stage amplifier. The output stage is a common source amplifier with a
compensation capacitor. M18 acts as a load. Important parameters describing the
behavior of the CMOS amplifier are: input voltage range, frequency response, noise,
current consumption, and numerous others. These parameters are discussed in the
next sections.

3.2 INPUT VOLTAGE RANGE

The range describes the “allowable” input voltage which will produce a linear, non-
distorted output signal.

3.2.1 Theory
The maximum input voltage must not make the input transistor, as in Figure 3.2,
move into a linear region mode.

VDS > VGS − VT (3.1)

VG is the input voltage, VD is VDD − VDSAT ( PMOS ).

From the given topology, the input voltage is able to swing slightly above VDD.
M15 and M16 are configured to oppose to that current flowing out of M14. (i.e., the M16
current will mirror current of M15). However, VDM12 is not equal to VDM14.

61
62 CMOS Analog and Mixed-Signal Circuit Design

M11 M13
30/5 30/5 30/5 30/5
90/5
M18
100/2 100/2 100/2 100/2
40/2 40/2 M12 M14

Current mirror 1 Current mirror 3

100/2 100/2 50/25
Iref M17

M16
10/5 10/5 M15 20/3
Current mirror as 20/3
ac ve load
Current mirror 2

FIGURE 3.1 Two-stage CMOS amplifier.

VDD VDD

IN+
IN -

M12 M14

M15
M16

FIGURE 3.2 Input stage of CMOS amplifier.

3.2.2 Example
For the circuit as shown in Figure 3.3, if VI1 is varied from 0 to 1.8 V (VI2 is fixed
at 0.9 V), the drain current of both transistors is shown in Figure 3.4. The character-
istics of the drain current have indicated that there is a working range of differential
voltage for the differential amplifier. Ideally, both transistors should turn ON when
Amplifiers 63

VDD

VI1 M1 M2 VI2

ISS

FIGURE 3.3 Basic differential amplifier.

they are working as a differential amplifier; therefore, the limit of the range of the
differential amplifier is the applied input voltage, which would turn OFF one of the
transistor pair.
If that is the case, when one of the transistors is OFF, the applied Vgs is therefore
either very high of I ds = 2WL Cox µn (Vgs − Vt )2, so Vgs = Vt + WC2oxLµn I ds , or if the input
(
differential voltage is Vid = Vgs1 − Vgs 2, then we have Vid = WC2oxLµn I ds1 − I ds 2 . )
The maximum input differential voltage is found by setting Ids1 = Iss and Ids2 = 0 ,
therefore:

2 LI ss 2 LI ss
Vidmax = or (3.2)
WCox µn WKPn

Exercise:
Given KPn is 120 μA/V2
Based on Figure 3.3, calculate, VI1min and VI1max.
If both P-type metal-oxide semiconductor (PMOS) folded and N-type metal-
oxide semiconductor (NMOS) folded are employed at the input, what will be the
input voltage range?
64 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 3.4 The drain current vs. input voltage.

3.3 SIGNAL PATH OF CMOS OPERATIONAL AMPLIFIER

The signal path is considered the path of “signal flow” from the input to the output.
The signal path can be used to analyze the frequency response, stability, and numer-
ous others.

3.3.1 Overall Signal Path

Figure 3.5 shows the signal path, with arrows indicating the “signal phase.” The cir-
cuit, a folded cascode with its gain = 1, reduces the Miller effect at high frequency.
From Figure 3.5, the output signal is a 180-degree phase shift of the input signal.

-IN
OUT

Signal Phase

FIGURE 3.5 Signal path of the CMOS amplifier (based on Figure 3.1).
Amplifiers 65

As the standard CS amplifier has high gain, the Miller effect will increase the total
input capacitance. Any capacitance between output and input can be seen as capaci-
tance at the input to the ground with the multiplication of (1 + Gain).

3.3.2 Load
There are basically two types of active load: diode-connected MOS or current source
MOS.
Figure 3.6 shows the output stage with a current source as the load.
Figure 3.7 shows the curve of the active load and M1 IV curve. Due to Vgs of the
active load is fixed, thus we have only one curve.
The current source load small signal resistance value is ro = 1/λId, where Id is drain
current. While the diode-connected load small signal resistance is 1/gm.
The low frequency or direct current (DC) gain,

AV = gmn ( roM16 / / rocasp ) gM17 ( roM18 / / roM17 ) (3.3)

Typical load problem:

• Buffer configuration is a severe test for instability (you need to have a big-
ger compensation capacitor)
• It cannot drive a small load resistor.

Output resistance and capacitance typically will affect the output stage. The f3dB,
dominant pole.

1
f3dB = (3.4)
2π ( roM18 / / roM17 ) CL

M1

FIGURE 3.6 Output stage of the CMOS amplifier.

66 CMOS Analog and Mixed-Signal Circuit Design

IDS
I vs V (M1)

Active load

Linear of active load

(a) VDS

IDS I vs V (active
load)

VDS

(b)

FIGURE 3.7 Curve of the (a) active load and (b) M1 IV curve.

While, the transition frequency,

gmn
fT = (3.5)
2π C L

Gain enhancement techniques, such as regulating the drain node, which can increase
the output resistance can be used to increase the gain [1].
The pole is similar to a simple RC pole, each node would have a pole.

3.3.3 Cascode Current Source

Figure 3.8 shows the cascode current source.
The lower devices (M2 and M4) are dimensioned so that the gate voltage has the
required value for cascode biasing. The top devices (M1 and M3) are made wide
enough to leave a comfortable margin between their source potential and of the bot-
tom devices.

3.3.4 Example
Figure 3.9 depicts the amplifier with a simple current source as the load.
Figures 3.10–3.12 show the simulation results of the amplifier with a simple cur-
rent source as the load.
Figure 3.13 shows the amplifier with a cascode current source as the load.
Amplifiers 67

M1 M3
100/2 100/2

0.4

M2 M4
10/5 0.7V 10/5

FIGURE 3.8 Cascode current source.

VDD

M14 V1 V1 M12
M13 V1 V1 M1

Vbias2
Vin+ M2 M3 Vin- M16 M15

Vbias3
M6 M4

M11 M9

Vbias4
M7 M5

FIGURE 3.9 Amplifier with simple current source as a load.

68 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 3.10 Output resistance.

FIGURE 3.11 Output voltage.

FIGURE 3.12 Drain current of M2 and M3.

Amplifiers 69

VDD

M14 V1 V1 M12
M13 V1 V1 M1

Vbias2
Vin+ M2 M3 Vin- M16 M15

Vout
Vbias3
M6 M4 M8 M10

Vbias4
M7 M5 M11 M9

FIGURE 3.13 Amplifier with load (cascode current source).

Figure 3.14 describes the output resistance of the simulated amplifier. The output
resistance is higher than the simple current source’s resistance.
If the differential amplifier is a single-ended drive of signal (transient), the output
currents of both outputs are sometimes not the same. For the current source, Iss, M1
and M2 play significant roles.

FIGURE 3.14 Output resistance of cascode-load.

70 CMOS Analog and Mixed-Signal Circuit Design

3.4 CMOS AMPLIFIER PARAMETERS

3.4.1 Input Offset

The offset voltage is Vref − VI (3.6)

The offset voltage of the amplifier, shown in Equation 3.6, resulting from mis-
matches in threshold voltage, load resistance, etc., see Figure 3.15a and b.

3.4.2 Common Mode Input Voltage Range

Input voltage range simulation configuration is shown in Figure 3.16a. Figure 3.16b
shows the input voltage range simulation result.
Figure 3.17 shows a folded CMOS amplifier with an input voltage range
configuration.
V1, which set the main current source, plays a significant role in the input voltage
range.
Exercise: KCL of the current sources.
Figure 3.18 shows the input voltage range simulation results.

3.4.3 Current Consumption

See Figure 3.19a and b.

+ Vout
-

Vin
Vref

(a)

Vout

Vin
(b) VI Vref

FIGURE 3.15 (a) Input offset simulation configuration and (b) input offset simulation
results.
Amplifiers 71

+
Vout
-

Vin

(a)

Vout

Vin
(b)
Input voltage range

FIGURE 3.16 (a) Input voltage range simulation configuration and (b) input voltage range
simulation result.

VDD

M14 V1 V1 M12
M13 V1 V1 M1

Vin+ M16 Vbias2

M2 M3 M15
Vout

Vbias3
M6 M4 M8 M10

Vbias4
M11
M7 M5 M9

FIGURE 3.17 Folded CMOS amplifier with input voltage range configuration.
72 CMOS Analog and Mixed-Signal Circuit Design

I(vdd)

-0.00013

-0.00014

I(A)
-0.00015

-0.00016

V(vout)
0.6

0.5

0.4

0.3

0.2
V(V)

V(vin)
1.0

0.5

0.0
0.0 0.5 1.0
vp (V)

FIGURE 3.18 Input voltage range simulation results.

Vcc

A I

+
-

Vin

(a)
Vin
I

Icc

o
(b) Vin

FIGURE 3.19 (a) Current consumption simulation configuration and (b) current consump-
tion simulation result.
Amplifiers 73

3.4.4 Common Mode Rejection Ratio (CMRR)

CMRR is the ratio of differential gain over the common mode gain. See Figure 3.20a
and b.

3.4.5 Power Supply Rejection Ratio

Power supply rejection ratio is the ratio of Vout over Vin (signal at power supply). It can
be defined as how well the amplifier can reject noise or changes on the VDD and
ground power buses.
A typical approach to increase the power supply rejection ratio is by using a cas-
code current source or sink (this is due to its high output resistance). See Figure 3.21a
and b.

3.4.6 Slew Rate and Settling Time

• High slew rate
• Small compensation capacitor
• Increase the operating current

See Figure 3.22a and b.

Settling time is equal to Tsettling.

Vout − 90% − Vout −10%

Slew rate = Vidmax = (3.7)
Slew − Time

Product of 1/f T and low frequency gain is approximately equal to settling time [1].
R2

R1
+
Vout(ac)
-
R3
Vin ac ~
R4

Vac

(a) o

CMRR
(dB) Very bad due to
high frequency
-90 effect
(b) freq

FIGURE 3.20 (a) CMRR simulation configuration and (b) CMRR simulation result.
74 CMOS Analog and Mixed-Signal Circuit Design

~ ac input (Vin)

Vcc
+ Vout
– Vcc

DC Vref

(a) 0

( )
Vout
Vin
PSSR
(dB)

-90

(b) freq (ac input)

FIGURE 3.21 (a) PSSR simulation configuration and (b) PSSR simulation result.

+
Vout
Vin = -

Big
signal

(a)

Vout

90%
Vout

10% Vin

Slew
Rate TSettling
(b) Time

FIGURE 3.22 (a) Slew rate and settling time simulation configuration and (b) slew rate and
settling time simulation result.
Amplifiers 75

3.4.7 DC Gain, fc, and fT

fc is the frequency when the gain drops by 3 dB. f T is the transition frequency or unity
gain. DC gain is a low frequency gain. See Figure 3.23a and b.
f T is also a product of low frequency gain and fc (3 dB).
Figure 3.24 shows an example of the open loop response of the CMOS amplifier.
Figure 3.25 shows the open loop response simulation result of the CMOS amplifier.
What is the effect of reducing the gate length to gain-bandwidth (GB) or unity gain?

3.4.8 Noise
For 1 μA, 7.8 × 1012 electrons passing every second will create a 7800 GHz ripple
(noise).

1. Use a larger input transistor to reduce noise

2. Increase operating current
3. White noise/short noise – flat/constant the entire operation
4. Flicker noise

+
V out
-
VI

1MH

1F

~ ac

(a)

or -180°
Phase

180°

DC gain

80 dB 3 dB

0 dB

100 Hz fc fT Freq
(b)

FIGURE 3.23 (a) DC gain, fc (3 dB) and f T configuration and (b) DC gain, fc (3 dB) and f T
simulation result.
76 CMOS Analog and Mixed-Signal Circuit Design

VDD

M14 V1 V1 M12

M13 V1 V1 M1

Vin+ Vbias2
M3 M16 M15

R1

C1

Vout
Vbias3
M6 M4 M8 M10

M7 Vbias4 M5 M11 M9

FIGURE 3.24 Example of open loop response of the CMOS amplifier.

____ I(vdd)(dB)
-------I(vdd)(°)
-70
0
I(vdd) (dB)

I(vdd) (°)

-72
-50

-74 -100

103 104 105 106 107 108 109

V(vout)(dB)
30 -------V(vout)(°)
0
25
V(vout) (dB)

20
V(vout) (°)

-50
15
10 -100
5
-150
0

103 104 105 106 107 108 109 1010

10 V(vin) 1.0

5 0.5
V(vin) (dB)

V(vin)(°)

0 0.0

-5 -0.5

-10 -1.0
103 104 105 106 107 108 109
Frequency (Hz)

FIGURE 3.25 Open loop response simulation result of the CMOS amplifier.
Amplifiers 77

+
-

~
(a)

Output noise = input noise

12n

10 100 1000 Freq

(b)

FIGURE 3.26 (a) Noise simulation configuration and (b) noise simulation results.

See Figure 3.26a and b.

An example of the noise calculation between 100–1000 Hz,

) )
noise(V/ Hz ) × frequency (Hz), 12 nV/ Hz ) × 900 = 360 nVrms

Figure 3.27 shows an example of the noise simulation configuration.

Figure 3.28 shows noise simulation results.

3.4.9 Distortion
Figure 3.29a and b describes the output signal in the time domain and frequency
domain, respectively. To convert the time domain to the frequency domain, an algo-
rithm called fast Fourier transform (FFT) or discrete Fourier transform (DFT) can
be used.

Harmonic = 2nd 2 + 3rd 2 + 4th2 + 5th2 (3.8)

Fundamental = 550 mV. Using Equation 3.8, Harmonic is 42 mV.

78 CMOS Analog and Mixed-Signal Circuit Design

VDD

M14 V1 V1 M12

M13 V1 V1 M1

Vin+ Vbias2
M3 M16 M15

Vout
Vbias3
M6 M4 M8 M10

Vbias4 M11
M7 M5 M9

FIGURE 3.27 Example of noise simulation configuration.

1.5x10-6 V(onoise)

1.0x10-6

5.0x10-7

0.0

1.5x10-6 V(inoise)

1.0x10-6

5.0x10-7

0.0
103 104 105 106
Frequency (Hz)

FIGURE 3.28 Noise simulation results.

Amplifiers 79

waveform is not
sinusoidal-it is distorted

(a)

550 mV

2 nd

5 th

(b) 25 kHz

FIGURE 3.29 (a) Distorted output signal and (b) distorted output signal in frequency
domain.

Harmonic
Therefore, Distortion = = 0.07 or 7%.
Fundamental
CAUTION -> Watch out with the FFT setting. Please do a test case.

3.5 COMMON MODE FEEDBACK

The amplifier in Figure 3.30 has the advantage of a larger input common mode
range because M3 is no longer connected in a diode connection configuration.
IBIAS sets the current in M3, M4, and M5. It is likely that these currents will not be
exactly equal.
Figure 3.31 shows how a feedback circuit is used to stabilize the common mode
output voltages V3 and V4. In this circuit, the arrange value of V3 and V4 is adjusted
until the average of V3 and V4 is equal to common-mode voltage (VCM). The resis-
tors RCM1 and RCM2 must be large enough so as not to degrade the performance in
the differential signal.
80 CMOS Analog and Mixed-Signal Circuit Design

M3 M4
M7

V3 V4

V1 V2
M1 M2

IBIAS

M6 M5

FIGURE 3.30 Differential amplifier with load (current source).

MC3
M3 M4
MC4

V3 V4
IBIAS RCM1
Vcm V1
MC1 MC2 RCM2 M1 M2

MB MC5 M5

Common Mode Feedback Circuit

FIGURE 3.31 Differential amplifier with the CMFB circuit.

Amplifiers 81

3.6 COMPENSATION IN AMPLIFIER

Compensation is required to ensure stability in opamp. A loop gain and phase are
normally used to indicate the stability of the opamp. For an application, the opamp
is normally configured in a closed-loop configuration for the loop gain and phase
analysis.

3.6.1 Loop Response

Figure 3.32 shows a two-stage CMOS amplifier with the open loop frequency
response.

VDD

M3 M4

VDD

Rz
M7

Vin- Vin+
M1 M2 Cc

Vout

R1 C3

C1
Vbias 3 M6T Vbias 3 M8T

Vbias 4 M6B Vbias 4 M8B

FIGURE 3.32 Two-stage CMOS amplifier with open loop frequency response.
82 CMOS Analog and Mixed-Signal Circuit Design

V(vout)(°)
V(vout)(dB)
0

60 -20

-40

40 -60

-80
V(vout) (dB)

V(vout) (°)
20 -100

-120

0 -140

-160

-20 -180

-200

-40 -220
103 104 105 106 107 108 109
Frequency (Hz)

FIGURE 3.33 The open loop frequency response.

The feedback capacitor, C1, and resistor, R1, form a time constant, so that none of
the Alternating Current (AC) output is fed back to the inverting input. Nevertheless,
the DC bias level is fed back, so that the input stage of the amplifier is properly
biased. Cc is the compensation capacitor used to “split” the lower frequency pole and
higher frequency pole further apart. While Miller-zero Cancellation Resistor (Rz) is
used to eliminate zero.
From Figure 3.33, the phase shifts when the gain in unity is −88°, so taking the
difference between this value and 180° gives a phase margin of 92°. The gain margin
is approximately 25 dB. The phase margin should be >60° to ensure stability, this is
to cater to process variation and so on. It is advisable to run some statistical analyses
to ensure the phase margin is “good” in all conditions.
Figure 3.34 shows an example of a simple bipolar opamp, which employs three-
stage design. Cc is the compensation capacitor.
Figure 3.35 shows another simulation of the loop gain and phase with closed-
loop gain determined by R1 and R2 (non-inventing amplifier). C1 and L1 are used to
“break” the closed-loop for the loop gain and phase analysis.
Based on Figure 3.35, without L and C what would happen, and what about the
DC biasing voltage?
Figure 3.36 shows loop analysis greater than phase margin (PM) with “suitable” Cc.

3.6.2 Pulse Response
Pulse response is another method that also can be used to study stability in the
opamp.
Amplifiers 83

VCC

Iref

Cc
IN – IN +
Out

VEE

FIGURE 3.34 Simple bipolar opamp.

+ Out
–

R2 R1
L1, (1MH)

CI (1F)

~ Vac

FIGURE 3.35 Simulation of the loop gain and phase.

Phase

Phase Gain
( dB )
-180° or 180°

PM = 60°

60°
Larger
40 dB
CC
Loop gain
PM

0° 0 dB

0 1K 10K 100K 1M 10M Freq ( Hz )

FIGURE 3.36 Loop analysis shows greater PM with “suitable” Cc.

84 CMOS Analog and Mixed-Signal Circuit Design

+ Out
-

R1

R2

(a)

-1

(b) Time ( s )

FIGURE 3.37 (a) Simulation of the pulse response and (b) output pulse response of the
circuit in Figure 3.37a.

Figure 3.37a shows a simulation of the pulse response.

Figure 3.37b shows the output pulse response of the circuit in Figure 3.37a.
The stability is achieved by ensuring fewer than four peaks are in the damped
oscillation.

3.7 WIDEBAND AMPLIFIER TECHNIQUE

3.7.1 Source and Load
To eliminate amplification loss on the dividers in the output stages, it is essential that
the optimal combination of output and load impedances should be formed.
A simplified equivalent circuit for voltage amplifier and current-to-voltage con-
verter circuits looks as follows:
The output stage for voltage amplifier and current-to-voltage converter and cur-
rent amplification circuits or voltage-to-current converters is as follows:
See Figure 3.38a and b.
To increase the gain, it is advantageous to make:

Z L / ( Zout + Z L ) → 1,

or Zout/ZL << 1, we shall achieve a high output voltage then,

Yout = 1 / Zout
Amplifiers 85

AU, T
Jout = Uout/Zout
Zout
ZL
Uout UL

(a)

A I, S
Iout
Yout
ZL
Jout

(b)

FIGURE 3.38 (a) Output stage of voltage amplifier and current-to-voltage converter and (b)
output stage of current amplifier and voltage-to-current converter.

We can obtain a high gain by making:

Z L / Zout << 1.

For amplifiers and current and voltage converters, respectively, one should keep the
following ratios of input signal generator impedances and input impedances of asso-
ciated circuits:
See Figure 3.39a and b.

Z in → 1 Z g >> 1 ( a),
Z g + Z in Z in

Zg
<< 1 (b).
Z in

AU , S AI , T
Iin

Zg Zg
Zin Zin
Ug Jg

(a) (b)

FIGURE 3.39 (a) Input as voltage source and (b) input as current source.
86 CMOS Analog and Mixed-Signal Circuit Design

3.7.2 Stages and Feedback

The gain decrease at lower frequencies depends on the properties of the external
circuit elements, and at higher frequencies, it depends on the parameters of the cir-
cuit itself. The Miller effect results in amplifier bandwidth reducing. To control this
effect, i.e., to widen the bandwidth, it is necessary to “isolate” the amplifier output
from its input. Cascode connections are most commonly used for this purpose. See
Figures 3.40 and 3.41.
Figure 3.42 shows the trade-off between gain and bandwidth. Two scenarios are
shown in Figures 3.43 and 3.44.
The non-inverting opamp and inverting opamp feedback are shown in Figures 3.45
and 3.46.
The local feedback such as series-parallel, series or parallel feedback are nor-
mally in a block design. This local feedback is shown in Figure 3.47.
Figure 3.48 shows the impedance conditioning of different local feedbacks.

UPS RL

Uout

UB = const

Uin

FIGURE 3.40 Cascode amplifier (CE-CB).

T2
RL
CL
T1

FIGURE 3.41 Simplified cascade circuit.

Amplifiers 87

Trade-off between Closed-loop Gain and

Bandwidth: What do we do if we want
both to be large

( ) ( )
+
_
+

(1 + )

FIGURE 3.42 Trade-off between gain and bandwidth.

f3-db = 10 Mhz
Time constant is the inverse of the -3db frequency:
Av = 100

Vin Vout Time constant τ ≈ 1/ (2πf3db) = 16ns

Rise time and fall time are each a few time constants.
Vin

Vout t ≈ 16 ns

FIGURE 3.43 One-stage solution.

88 CMOS Analog and Mixed-Signal Circuit Design

f3-db = 100 Mhz f3-db = 100 Mhz

Av = 10 Av = 10

Vin Vout

Use feedback to convert the amplifier from

gain of 100 and bandwidth of 10MHz to a gain of
Vin
10 and bandwidth of 100MHz.

Use two such amplifiers in cascade.

Time constant reduces by a factor of 10!

t ≈ 16 ns
Vout

FIGURE 3.44 Two-stage solution.

R2

R1
V- -

V+ +
Vin

FIGURE 3.45 Non-inverting opamp topology.

R2

R1
V- -
Vin

V+
+

FIGURE 3.46 Inverting opamp topology.

While building wide-band amplifiers, local feedbacks (FBs) are used, and the
bandwidth of each cell is optimized.
Figure 3.49 shows example wide-band circuits of voltage amplifiers.
In the high frequency region, paraphrase circuits with source couplings are advan-
tageous, and transistors are used in Common Drain (CD) and Common Gate (CG)
Amplifiers 89

(a) (b)

FIGURE 3.47 Local feedbacks (a) of a series type and (b) of a parallel type.

Zout1 Zin2 = ZL1

1)
Iin

2)

ZL1 ≈ Zin2(2) << Zin2(1) for current amplification

3)

ZL1= Zin2(3) > Zin2(1) ωт decreases in comparison with circuit (1)

4)

ZL1= Zin2(4) < Zin2(1) frequency characteristics are better than in (3)

FIGURE 3.48 Recommendations for design Zin, Z L in stages of different amplifiers.

Examples 1–4.
90 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 3.49 Example wide-band circuits of voltage amplifiers.

+U

I1 Ro I2

Uout

Rg
Uin T1 T2

I0
-U

FIGURE 3.50 High frequency amplifier.

circuits (Т1) and (Т2). This is a special case of differential stages, the main difference
here is an asymmetrical circuit. In this circuit, the drain capacitance in the input arm
is minimized, and connecting the CG transistor converts current amplification into
voltage amplification. This is shown in Figure 3.50.

3.8 NOISES IN AMPLIFIERS

3.8.1 Noise in Circuits
Figure 3.51a and b shows the common source stage. If we assume the noise param-
eter is uncorrelated, we can simply add the noises [2]. Here, we set the input to zero
and calculate the total noise at the output.
 2 K 1 2 4kT  2
V 2 n,out =  4kT gm + g m+ R D (3.9)
 3 Cox WL f RD 
Amplifiers 91

FIGURE 3.51 (a) Common source stage and (b) common source with including noise
sources.

Noisy Circuit Noiseless Circuit

,

- +
- + , ,
+
-

(a) (b)

FIGURE 3.52 Determination of input referred noise voltage: (a) noisy circuit and (b) noise-
less circuit.

Equation (3.10) is a combination of M1 thermal noise, M1 flicker noise

and RD thermal noise.

The equation indicates noise in 1 Hz at a frequency f. The total output noise can be
obtained by integration over the bandwidth of interest.
Input referred noise is a fictitious quantity (that cannot be measured at input) that
allows comparisons between different circuits, see Figure 3.52. The input referred noise
voltage in this simple case is given by the output noise voltage divided by the gain.

V 2 n,out V 2 n,out
=
V 2 n,in =
A2 v g 2 m R2 D

 2 K 1 2 4kT  2 1
V 2 n,in =  4kT gm + g m+ R D 2 2
 3 C oxWL f RD  g m RD

2 K 1 4kT
= ⋅4kT + + 2 (3.10)
3gm CoxWL f g m RD

Due to finite input impedance, modeling the input referred noise by merely a voltage
source is not accurate. Modeling input referred noise by both a series voltage source
and a parallel current source would be more accurate, see Figure 3.53.
92 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 3.53 Input referred noise voltage and current.

A noise source can be transformed from a drain-source current to a gate series

voltage for arbitary Zs. This is described in Equation (3.11).

I 2 n,drain −source
V 2 n,gate = (3.11)
g2 m

3.8.2 Noise in Single-Stage Amplifiers

Figure 3.54 shows a common source stage with noise representation:

 2 1  K 1
V 2 n,in = 4kT  + 2 + (3.12)
 3gm g m RD  Cox WL f

FIGURE 3.54 Common source stage with noise representation.

Amplifiers 93

1   2 1  K 1
I 2 n,in =  4kT  + 2 +  (3.13)
Z 2in  3
 mg g R
m D  Cox WL f 

I 2 n,in ≈ 0 for low frequencies.

Figure 3.55a–d shows the CG stage input referred noise. The common gate with
large output resistance, ro, is shown in Figure 3.56.

FIGURE 3.55 (a–d) Calculation of input referred noise of CG.

94 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 3.56 Common gate (ro large).

 2g 1  2
 R D =V n,in ( gm + gmb ) R D , ∴
2 2
4kT  m + 2

 3 RD 

 2g 1 
4kT  m +
 3 RD 
V 2 n,in = (3.14)
( gm + gmb )
2

4kT
I 2 n,in = (3.15)
RD

While noise together with bias is shown in Figure 3.57. To reduce the noise compo-
nent, we must minimize gm2, but this degrades active-region voltage swing.
Flicker noise effect on the CG stage is shown in Figure 3.58.

1  g 2 m1K N g 2 m3 K p 
V 2 n,out =  +  ( ro1 ro3 )
2
(3.16)
fCox  (WL)1 (WL)3 

FIGURE 3.57 CG with biasing.

Amplifiers 95

FIGURE 3.58 CG with flicker noise.

1  g 2 m1K N g 2 m3 K p  1
V 2 n,in =  +  (3.17)
fCox  (WL)1 (WL)3  ( gm1 + gmb1 )2

1  g 2 m 2 K N g 2 m3 K p  2
I 2 n,in =  +  R out (3.18)
fCox  (WL )2 (WL )3 

1  g2 m 2 K N g2 m3 K p 
I 2 n,in =  +  (3.19)
fCox  ( WL ) ( WL )3 
 2

Figure 3.59 shows a source follower stage.

FIGURE 3.59 Source follower noise.

96 CMOS Analog and Mixed-Signal Circuit Design

2 2
=I 2 n 2 4=
kT gm 2 , I 2 n1 4kT gm1
3 3

Using Equation 3.11, the source follower noise voltage is:

2 1 g 
V 2 n,in = 4kT  + 2m 2  (3.20)
3  gm1 g m1 

Figure 3.60 shows the cascode noise circuit.

The noise voltage is:

 2 1 
V 2 n,in |M 1, RD = 4kT  + 2  , low freq. (3.21)
 3gm g m RD 

Vn,out − RD
= , significant at high freq. (3.22)
Vn2 1 1
+
gm2 sC x

3.8.3 Noise in Differential Pairs

Figure 3.61a shows the differential pair, while Figure 3.61b depicts noise sources.
For low frequency, the current noise is negligible.
Figure 3.62 shows the method of calculating the input referred noise.
The single transistor noise is:

2 K 1
V 2 n1 = 4kT + (3.23)
3gm Cox WL f

FIGURE 3.60 Cascade amplifier noise.

Amplifiers 97

FIGURE 3.61 (a) Differential pair and (b) differential pair with noise source.

The input referred noise voltage is:

 2 1  K 1
V 2 n,in = 8kT  + 2 + (3.24)
3
 mg g R
m D  Cox WL f

I 2 n,in ≈ 0 for low frequencies

3.8.4 Noise in Amplifier with Resistors in the Feedback

See Figure 3.63a and b.

• Total output noise (assume A is large)

2
 − Rf  2
v 2 nout( tot ) ≈   e n Rs + e n R f
2

 Rs 

• Total output noise due to source (assume A is large)

2
 − Rf  2
v 2 nout(in ) ≈   e n Rs
 Rs 

• Noise factor
2 2
 R  e2 R  R  4kTR f R
F ≈ 1+  s  n f = 1+ s  = 1+ s
 R f  e n Rs  R f  4kTRs Rf
2
98 CMOS Analog and Mixed-Signal Circuit Design

3.8.5 Noise Bandwidth
Figure 3.64a and b shows the output noise spectrum of a circuit and concept of noise
bandwidth.
It is meaningful to represent the noise as:

V 2 0 ⋅ Bn ,
where the bandwidth Bn is chosen so that:
∞
V 2 0 ⋅ Bn =
∫
0
V 2 n, out df (3.25)

FIGURE 3.62 Method to calculate input referred noise: (a) Output noise with inputs short
together, (b) effect each source individually, (c) contribution of In1. (Continued)
Amplifiers 99

FIGURE 3.62 (Continued) Method to calculate input referred noise: (d) method to calcu-
late input-referred noise.

FIGURE 3.63 (a) Opamp with feedback resistor and (b) noise source with feedback resistor.

FIGURE 3.64 (a) Noise bandwidth 1 and (b) noise bandwidth 2.

100 CMOS Analog and Mixed-Signal Circuit Design

3.9 CURRENT DENSITY DESIGN APPROACH

As the name implies, the information of the current with respect to density, i.e., the
size of a transistor can be used as an approach in the circuit design. The approach
is more or less to determine the optimized size of a transistor for a given perfor-
mance. This approach would undoubtedly lead to a less mathematical equation-
based design, and therefore suitable for low power application and technology- or
process-independent. gm/Id vs. current density and Vdsat vs. current density are two
common parameters that are used in this circuit design approach. The modified
Equation 3.3 is now:
1
AV = gm . (3.26)
λ Id
Obviously, gm/Id is now clearly can be used in the Equation 3.26. The relation of the
gm/Id ratio with the transistor operating mode can be observed from the fact that this
ratio is equal to the derivative of the logarithmic of ID with respect to Vgs. The gm/Id
ratio is also size-independent [3].
Once a pair of values among gm/Id, gm, and ID has been derived, the width/length
(W/L) of the transistor can be determined unambiguously. Another related approach
is the inversion coefficient approach [4].

3.10 LAYOUT EXAMPLES

Figure 3.65 shows the schematic and Figure 3.66 shows the layout of the single-
ended output opamp.

FIGURE 3.65 Opamp schematic.

Amplifiers 101

FIGURE 3.66 Opamp layout.

3.11 SUMMARY
This chapter discusses the CMOS amplifier design with most of the amplifier speci-
fications or requirements. The technique can be used for many applications, such
as a high gain amplifier, high frequency, and low noise amplifier. This chapter is
very useful for a beginner in analog integrated circuit design. The niche low power
CMOS amplifier is discussed in the next chapter.
102 CMOS Analog and Mixed-Signal Circuit Design

REFERENCES
1. Baker, R. J. (2010). CMOS: Circuit Design, Layout, and Simulation (3rd ed.). Wiley-
IEEE Press. doi:10.1002/9780470891179.
2. Razavi, B. (2001). Design of Analog CMOS Integrated Circuits. New York: McGraw-
Hill Publisher, p. 261.
3. Silveira, F., Flandre, D., and Jespers, P. G. A. (1996). A gm/ID based methodology for
the design of CMOS analog circuits and its application to the synthesis of a silicon-on-
insulator. IEEE Journal of Solid-State Circuits, 31(9), 1314–1319.
4. Enz, C., Chalkiadaki, M.-A., and Mangla, A. (2015). Low-power analog/RF circuit
design based on the inversion coefficient. European Solid-State Circuits Conference
(ESSCIRC), 2, 202–208.
 4 Low Power Amplifier

4.1 INTRODUCTION
Various circuit techniques have been employed and demonstrated by these amplifiers
to achieve low-power operation without compromising too much on the gain, noise,
linearity, and size. Most of the time, it is impossible to win everything, thus, some
trade-offs will have to be made. But in the end, what really matters is getting the
right balance among all the parameters of the amplifier.

4.2 LOW VOLTAGE CMOS AMPLIFIER

When designing analog circuits for operation at reduced supply voltages, careful
attention must be paid to the signal swing and noise level. Folded cascode is one of
the popular techniques, however, using a low-voltage supply process could also ease
the design.

4.2.1 Body or Bulk Control

The conventional metal-oxide semiconductor (MOS) transistor is actually a four-­
terminal device. Depending on the type of used complementary metal-oxide semi-
conductor (CMOS) technology (i.e., N-, P-well, or twin-tub), the bulk-terminal
is usually connected either to a negative/positive supply voltage for the N-type
­metal-oxide-semiconductor (NMOS) or P-type metal-oxide-semiconductor (PMOS)
transistor, respectively, or to the related source terminal. The device bulk or
p-­substrate body connection to a positive voltage source can reduce V TH, thus achieve
low voltage for low power consumption. Recall the equation in Section 2.4,

VT =VT 0 + γ ( −2∅ F + VSB − 2∅ F ) (4.1)

If the body voltage is higher than the source voltage, V T is low.

The bulk-terminal can also be used as a signal input instead of connecting it to
one of the supply voltages or source terminal. In such a way, the threshold voltage
requirement is removed from the signal path. Although the bulk-driven techniques
are used in a variety of low-voltage, low-power applications, yet, they still suffer
from low transconductance value compared to the conventional one.

103
104 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 4.1 New cascode amplifier.

4.2.2 Circuit Technique

A modified cascode or cascade circuit can be used in low-supply voltage applica-
tion. The circuit is shown in Figure 4.1. The figure shows a high frequency ampli-
fier. NMOS transistors M1 and M2 use the same supply voltage, but a separate path.
The supply voltage can be as low as a normal common-source amplifier supply volt-
age [1]. Employing a coupling capacitor, C2 has eased the gate-biasing voltage for
the M1 and M2. T1–T3 are used for radio frequency (RF) matching purposes with a
T-type network topology.

4.3 SUBTHRESHOLD
This is a popular low-power design technique and is also known as weak inversion.
The use of this technique in design could obtain very low power consumption, thus
prolonging battery life. Subthreshold biasing occurs when the gate-source voltage,
Low Power Amplifier 105

VGS , of the MOS transistor is less than the extrapolated threshold voltage, VTH , of the
device, but sufficient enough to cause the formation of a depletion region at the sur-
face of the silicon substrate adjacent to the drain-source channel. The drain current
for subthreshold biasing is caused by the flow of a diffusion current due to the minor-
ity charge carrier concentration gradient, rather than the drift of majority charge
carriers in the channel, which is negligible. For an NMOS transistor operating in the
subthreshold region, this is analogous to a negative-positive-negative (npn) bipolar
transistor, where the silicon substrate acts as the base, while the source and drain
terminals represent the emitter and the collector, respectively.
The drain current for subthreshold biasing can be expressed as:

W  V −V   VDS 
ID = I D 0exp  GS TH  1 − exp  − V  , (4.2)
L  nVT   T 

where W = gate width, L = gate length, I D0 = drain current when the gate-source
voltage equals the threshold voltage, VGS = gate-source voltage, VTH = threshold volt-
age, n = ratio of sum of gate-oxide capacitance and depletion-region capacitance
over gate-oxide capacitance, VT = thermal voltage, and VDS = drain-source voltage.
Figure 4.2 [2] depicts the plot of log I D against VGS , where the straight line around
the region VGS < VTH represents Equation 4.2 and is known as the subthreshold expo-
nential region.
Also from Equation 4.2, as VDS increases to more than approximately 3 VT , the drain
current becomes almost constant because the last term in the equation approaches
unity. This is illustrated in Figure 4.3 [3].
It implies that for subthreshold biasing, the MOS transistor merely needs around
0.1 V of drain-source voltage to operate in its saturation region, as VT is only about
25 mV at room temperature. This very low minimum saturation VDS for MOS transis-
tors is therefore very appealing for low-power analog circuits, as less supply voltage
is needed to power up the devices.

FIGURE 4.2 Plot of log against showing the exponential region of subthreshold biasing and
the square-law–relationship in strong inversion.
106 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 4.3 Plots ID of versus VDS with varying subthreshold biasing.

The transconductance for subthreshold biasing can be obtained by differentiating

Equation 4.2 with respect to VGS and can be further simplified to be:

ID I Cox
gm = = D (4.3)
nVT VT C js + Cox

where Cox = gate-oxide capacitance per unit area, and C js = depletion-region capaci-
tance per unit area. From Equation 4.3, the ratio of transconductance to drain current
in subthreshold biasing is given by:

gm 1 1 Cox
= = (4.4)
I D nVT VT C js + Cox

In subthreshold biasing, the ratio of gm over I D is significantly higher than that for
strong inversion. Amplifiers imply that for the same amount of drain current, sub-
threshold biasing produces a greater transconductance, thus giving better current
efficiency. However, to increase the current in subthreshold biasing while main-
taining the same VGS in the subthreshold region, the width of the MOS transistor
will need to be increased as given by Equation 4.2. This eventually will result in
a much larger MOS device size, hence, a larger total size of the integrated circuit
(IC) layout.
The use of the subthreshold biasing technique for low-power applications is
restricted only to those with relatively low operating frequencies. This is due to a
very small transition frequency, fT , for subthreshold biasing that renders it unsuitable
for higher frequencies, especially those beyond 1 GHz. The transition frequency, fT ,
is defined as the frequency at which the MOS transistor’s current gain falls to unity.
However, as CMOS technology becomes smaller, the transition frequency has been
found to be increasing [4].
Low Power Amplifier 107

4.4 CURRENT REUSE CMOS AMPLIFIER

The main objective of this technique is to obtain a much larger transconductance of
the low noise amplifier (LNA), without further increasing the total current drawn.
Another way of looking at it is to reduce the total current drawn, while approxi-
mately maintaining the same amount of transconductance of the LNA. Figure 4.4
helps to illustrate this technique.
Figure 4.4a is a typical common-source amplifier that is made up of a driving
transistor, NMOS1, and resistive load, R1, with a current, I D , passing through the
resistor and transistor. The low-frequency, small-signal voltage gain of this amplifier
is simply given by:

Av = − gm _ NMOS1. ( R1  ro _ NMOS1 ) (4.5)

In Figure 4.4b, the resistive load is being replaced with an active load, PMOS1.
The current, I D , passing through this PMOS1 is therefore being reused by NMOS1.
With the current passing through both NMOS1 and PMOS1 still being I D , the low-
frequency, small-signal voltage gain now is given by:

Av = − gm _ NMOS1. ( ro _ PMOS1  ro _ NMOS1 ) (4.6)

When the input signal is also being driven by PMOS1 in addition to NMOS1, as
depicted by Figure 4.4c, with the same current, I D , passing through both transistors,
the low-frequency, small-signal voltage gain can now be expressed as:

Av = − ( gm _ PMOS1 + gm _ NMOS1 ) . ( ro _ PMOS1  ro _ NMOS1 ) (4.7)

FIGURE 4.4 (a) Typical CS amplifier, (b) CS amplifier with active load, and (c) current
reuse concept.
108 CMOS Analog and Mixed-Signal Circuit Design

Now, the effective transconductance of this amplifier has increased from a mere
gm _ NMOS1 to ( gm _ PMOS1 + gm _ NMOS1 ), with the drawn current remaining unchanged.
All in all, this shows how the current-reuse technique can help the circuit to be more
economical in terms of total current drawn and the effective transconductance it
produces. Conversely, the total current drawn can be reduced without reducing the
initial effective transconductance.
This current-reuse technique has been implemented through a number of different
ways by various authors [5–12], most commonly by stacking a PMOS transistor on top
of an NMOS transistor in the same direct current (DC) current path, as shown previously
by Figure 4.4c. With both PMOS and NMOS transistors in the same DC current path,
one can opt for either a complementary common-source current-reuse or complemen-
tary common-gate current-reuse configuration, as illustrated in Figures 4.5 and 4.6.

FIGURE 4.5 Complementary common-source current-reuse configuration.

FIGURE 4.6 Complementary common-gate current-reuse configuration.

Low Power Amplifier 109

For both configurations, the effective transconductance can be almost double to

that with only an NMOS transistor and a load in the same DC current path while
drawing the same current. It is not going to be exactly doubled since the transcon-
ductance of the PMOS transistor is slightly lower than that of the NMOS transistor
due to lower mobility of the main charge carrier in the PMOS transistor.
Works from [5,10,11] utilize complementary common-source current-reuse con-
figurations for their LNAs [10]; however, use this configuration in a slightly dif-
ferent way, where the NMOS transistor is stacked on top of the PMOS transistor
instead of the other way around as described above. This is so that both the NMOS
and PMOS portions of the common-source, current-reuse LNA can share the same
source degeneration inductor. However, with this slightly different configuration,
a load (either active or passive) is needed at the drain of each transistor unlike in
the usual complementary common-source current-reuse configuration, where both
the NMOS and PMOS transistors also function as active loads, as well as driving the
input signal. This is the same for the work by [12], with their slightly different com-
plementary common-gate current-reuse configuration, where the NMOS transistor
is stacked on top of the PMOS transistor. As a result, they need to include additional
passive loads at the drains of the transistors.

4.5 OTHER TECHNIQUES

Some authors have gone a step further by combining both complementary common-
gate and common-source current-reuse configurations through the capacitive cross-
coupling technique in a differential LNA topology [7–9]. This configuration is more
widely known as common-gate current-reuse with a capacitive cross-coupling con-
figuration and is depicted in Figure 4.7.
This capacitive cross-coupling is viable with differential topology since the output
of a common-source amplifier is 180° out-of-phase, while that of a common-gate
amplifier is in-phase. With the transistors being utilized as both common-gate and

FIGURE 4.7 Common-gate current-reuse with capacitive cross-coupling configuration.

110 CMOS Analog and Mixed-Signal Circuit Design

common-source amplifiers simultaneously, the resulting gain will be doubled for

each half-circuit. This capacitive cross-coupling technique applied to a complemen-
tary common-gate current-reuse configuration, therefore, is a type of gm-boosting
technique. By adding up both half-circuits of the differential LNA, the gain will
therefore be quadrupled, but, of course, with the total drawn current being twice
larger to supply both half-circuits.
The downside of this current-reuse technique is that it compromises the linear-
ity of the LNA as a result of the high gain it produces. It also has a tighter voltage
headroom [13]. This technique, therefore, is less suitable for applications with high
input power at the receiver.

4.5.1 Common-Gate with Gain-Boosting Wideband Differential LNA

An inductorless common-gate with gain-boosting wideband differential LNA was
reported in [14]. This LNA is actually intended for 2.45 GHz industrial, scientific and
medical (ISM) band applications. It does, however, exhibit very good performance
around 0.4 GHz, hence, it might be suitable for low power applications. It was imple-
mented in STMicroelectronics 0.13-µm CMOS technology and took up an area of
0.007 mm2. On measurements at MedRadio frequencies, it achieves a gain of 25 dB,
input return loss (RL) of 12 dB and noise figure (NF) of 4.0 dB, while dissipating
power of 1.32 mW. The circuit schematic of this LNA is depicted in Figure 4.8.
As illustrated in Figure 4.8, this wideband differential LNA basically employs
a common-gate topology with some cross-couplings that result in the overall

FIGURE 4.8 Common-gate with gain-boosting wideband differential LNA circuit sche-
matic proposed by Belmas et al. (Redrawn from Belmas, F. et al., IEEE J. Solid State Circ.,
47, 1094–1103, 2012.)
Low Power Amplifier 111

gm-­boosting of the LNA. NMOS transistor M1 together with resistor R1 form the
main common-gate amplifier. This main common-gate amplifier is being gm-boosted
by the output from another common-gate amplifier (formed from NMOS transistor
M3 and resistor R3) and also from the capacitive cross-coupling (through capacitor
C4) of the output from the main common-gate amplifier of the opposite half-circuit.
The common-gate amplifier formed from M3 and R3 is also gm-boosted, and this is
by the cross-coupling of the input signal from the opposite half-circuit to the gate of
M3. PMOS transistor M4 acts as an active load to prevent a large DC voltage drop
across R3. The gate of M4 is connected to the gate of M4 of the opposite half-circuit
to create a dynamic ground. The main advantage of this LNA seems to be its small
size of 0.007 mm2 due to its inductorless topology. However, its differential topology
and some cross-couplings (to attain gm-boosting) necessitate the use of four DC volt-
age rails to supply all the common-gate amplifiers, thus resulting in high total power
consumption of 1.32 mW.

4.6 SPICE EXAMPLE

Figure 4.9 shows the simulation schematic of the current reuse. The NMOS tran-
sistor is biased through a feedback resistor. The input signal is coupled to both
transistors via capacitors. Figure 4.10 shows the simulation results. The input sig-
nal amplitude is 4 mV peak to peak. From the figure, the gain of the amplifier is
approximately 5.
The common gate (CG) amplifier simulation schematic is shown in Figure 4.11.
Figure 4.12 shows the cross-CG amplifier simulation results. From the figure, the
gain is approximately 1. Figure 4.13 shows the cross-coupling concept of the CG
amplifier. Figure 4.14 shows the simulation results. The input difference is 2 mVp,
while the output signal is 20 mVp. Therefore, the gain of the cross-coupling CG

FIGURE 4.9 Basic current reuse simulation schematic.

112 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 4.10 Simulation results.

FIGURE 4.11 Common gate simulation circuit.

Low Power Amplifier 113

FIGURE 4.12 CG simulation results.

FIGURE 4.13 Cross-coupling amplifier.

114 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 4.14 Simulation results of cross-coupling CG amplifier.

amplifier is 10. It is a big increase of gain, if two out-of-phase signals are applied to
the gate and source of M1 simultaneously.

4.7 SUMMARY
Current-reuse is a low-power design technique that can boost the effective transcon-
ductance of a LNA without further increasing the drawn current, hence, the total
power consumption. The most common ways of implementing this technique are
through complementary common-source and common-gate current-reuse topolo-
gies and differential common-gate current-reuse with capacitive cross-coupling
topology.
Subthreshold biasing or weak inversion is another low-power design technique,
where the gate-source voltage applied to a MOS transistor is slightly lower than the
transistor’s threshold voltage. As a result of subthreshold biasing, the MOS transis-
tor only needs a relatively very low drain-source voltage to operate in its saturation
region. Also, the ratio of gm over I D in subthreshold biasing is significantly higher,
which implies that this technique gives better current efficiency.
Low Power Amplifier 115

REFERENCES
1. Lee, S.‐G., and Lee, J.‐W. (2011). A Q‐band CMOS low‐noise amplifier using a low‐
voltage cascode in 0.13‐μm CMOS technology. Microwave and Optical Technology
Letters, 53, 2985–2988.
2. Razavi, B. (2001). Design of Analog CMOS Integrated Circuits. New York: McGraw-
Hill Education.
3. Gray, P. R., Hurst, P. J., Lewis, S. H., and Meyer, R. (2010). Analysis and Design of
Analog Integrated Circuits, 5th ed. New York: Wiley, pp. 811–821.
4. Yang, J., Tran, N., Bai, S., Fu, M., Skafidas, E., Halpern, M., Ng, D. C., and Mareels, I.
(2011). A subthreshold down converter optimized for super-low-power applications in
MICS band. 2011 IEEE Biomedical Circuits and Systems Conference, BioCAS 2011,
2, 189–192.
5. Khoshroo, P., Elmi, M., and Naimi, H. M. (2016). A low-power current-reuse
­resistive-feedback LNA in 90 nm CMOS. 2016 24th Iranian Conference on Electrical
Engineering, ICEE 2016 (pp. 917–920).
6. Reddy, K. V. (2017). A 280 µW sub-threshold Balun LNA for medical radio using
current re-use technique. PhD Research in Microelectronics and Electronics Latin
America (PRIME-LA), pp. 1–4.
7. Pan, Z., Qin, C., Ye, Z., and Wang, Y. (2017). A low power inductorless wideband
LNA with Gm enhancement and noise cancellation. IEEE Microwave and Wireless
Components Letters, 27(1), 58–60.
8. Salimath, A., Karamcheti, P., and Halder, A. (2014). A 1 V, sub-mW CMOS LNA for low-
power 1 GHz wide-band wireless applications. Proceedings of the IEEE International
Conference on VLSI Design, (c) (pp. 460–465).
9. Cruz, H., Huang, H. Y., Lee, S. Y., and Luo, C. H. (2015). A 1.3 mW low-IF, c­ urrent-reuse,
and current-bleeding RF front-end for the MICS band with sensitivity of −97 dbm.
IEEE Transactions on Circuits and Systems I: Regular Papers, 62(6), 1627–1636.
10. Cha, H. K., Raja, M. K., Yuan, X., and Je, M. (2011). A CMOS MedRadio receiver RF
front-end with a complementary current-reuse LNA. IEEE Transactions on Microwave
Theory and Techniques, 59(7), 1846–1854.
11. Choi, C., Kwon, K., and Nam, I. (2016). A 370 µm CMOS MedRadio receiver front-end
with inverter-based complementary switching mixer. IEEE Microwave and Wireless
Components Letters, 26(1), 73–75.
12. Parvizi, M., Allidina, K., and El-Gamal, M. N. (2016). An ultra-low-power wideband
inductorless CMOS LNA with tunable active shunt-feedback. IEEE Transactions on
Microwave Theory and Techniques, 64(6), 1843–1853.
13. Wang, S. B. T., Niknejad, A. M., and Brodersen, R. W. (2006). Design of a sub-mW 960-
MHz UWB CMOS LNA. IEEE Journal of Solid-State Circuits, 41(11), 2449–2456.
14. Belmas, F., Hameau, F., and Fournier, J. M. (2012). A low power inductorless LNA with
double Gm enhancement in 130 nm CMOS. IEEE Journal of Solid-State Circuits,
47(5), 1094–1103.
 5 Voltage Regulator,
References and Biasing

5.1 INTRODUCTION
The main sub-blocks of analog and mixed-signal integrated circuits, such as ampli-
fiers, oscillators, and data converters require biasing circuitries to bias their tran-
sistors. The circuit designated to provide biasing voltages to these transistors is
generally known as biasing circuitry. The basic element in the biasing circuitries is a
current source and current mirror. The concept of current mirror/source is if we can
set both VGS and VDS, we can attain the drain current, ID, or if we can set the ID and
VGS, then we can attain the VDS.
Voltage reference or current reference circuits are specifically designed circuits
to provide constant voltage or current across the process, voltage, and temperature
(PVT). The voltage reference is typically a combination of current sources.

5.2 CURRENT SOURCES

Fortunately, the complementary metal-oxide semiconductor (CMOS) transistor is
a current source. If we simply apply a constant voltage to the gate (such as a refer-
ence voltage), we can tailor the width and length of the device to give us a certain
current. A basic current mirror is shown in Figure 5.1. How current mirrors are
ratioed is shown in Figure 5.2. Current flows in M1 as a result of VGS1. If M2 is in
saturation, and if M2 gate width/gate length (W2/L2) = W1/L1, then drain current of
M2, Id2 will be equal to Id1. In MOS technology, scaling of currents is easily accom-
plished by manipulating the W/L ratios of each transistor. However, it is important
to keep all the mirror devices operating in the saturation region to maintain proper
operation.
The minimum voltage across the mirror transistor is Vdsat. Under these conditions, the
output resistance of the current mirror is the output resistance of the mirror transistor:

1
Ro = (5.1)
λn I DSAT

where λ is the channel length modulation parameter. Five variables are available as
design parameters: W1, L1, W2, L2, and VGS. Normally, the values of L and VGS are
picked first to simplify the design process. For example, making all values of L equal
reduces the current ratio equation to a ratio of transistor widths:

I D2 W2
= (5.2)
I D1 W1

117
118 CMOS Analog and Mixed-Signal Circuit Design

VDD VDD

R R

D D

G G
M1 M2

S S

FIGURE 5.1 Basic current mirror.

VDD VDD VDD VDD

M* W/L N* W/L O* W/L

G
W/L

IREF R M* IREF N* IREF O* IREF

Channel-length modulation
is neglected here.

FIGURE 5.2 How current mirrors are ratioed.

Also, making all values of L the same serves to make the effects of process variations
constant from transistor to transistor. Lateral diffusion, etch effects, and photolithog-
raphy errors will then affect the circuit in a “common mode” manner. Errors tend to
cancel under these conditions.
In general, it is a good practice to make L as large as possible for analog designs.
Increasing L reduces the value of λ. Setting L equal to three times the process mini-
mum length is a good rule to start with. This rule can be modified after you have
experience with a particular process. It is also a good practice to design for a specific
VGS that is somewhat larger than Vth. Higher values of VGS allow smaller values of W
to be used, but the value of Vdsat will be increased. Values of VGS that approach Vth
result in physically large transistors.
Voltage Regulator, References and Biasing 119

VDD VDD

Vbias2

+ + w/2 -

w/2
Out

FIGURE 5.3 Self-biased.

5.3 SELF-BIASED
Self-biased is a scheme that saves power and reduces circuit area, and this is
chosen to eliminate the needs of external biasing circuitry by generating bias
voltages from internal nodes of the circuit. The idea is shown in Figure 5.3.
Using this approach in biasing would lead to non-constant current values across
the PVT variation.

5.4 CTAT AND PTAT

There are at least two methods to develop this circuit. The first method is the current
summation method and the second is to generate the current source from a voltage
reference.
For the current summation method, a simple solution is to add complementary
to absolute temperature (CTAT) and proportional to absolute temperature (PTAT)
current sources. Figure 5.4 shows the concept of PTAT and CTAT. Figure 5.5 shows
the CTAT current source which has the negative Tcc. It can be seen that, base-emitter
voltage (VBE) is actually a CTAT source. The Tcc of VBE is approximate –2 mV/°C.
The biggest hurdle to this method is the difficulty to interface to other circuits (e.g.,
voltage-controlled oscillator (VCO) buffer amplifier). It is quite difficult to imple-
ment current sources and mirrors (to the current source of a VCO buffer amplifier)
with different size or ratio, the device mismatch would be the biggest problem.
A PTAT source is typically a delta of VBE or the differences of VBEs. This idea is
discussed in the next section.
An example of a current source from a voltage reference is a circuit based on
the Zener-referenced circuit [1]. The idea is shown in Figure 5.6. The Zener-
referenced circuit is based on the Zener breakdown of a reversed base-emitter junc-
tion. This breakdown phenomenon of between 6–8 V, depending on how the process
120 CMOS Analog and Mixed-Signal Circuit Design

VREF VREF

PTAT reference CTAT reference

T, temperature T, temperature
(a) (b)

FIGURE 5.4 (a) CTAT and (b) PTAT.

Iref
Diode
voltage
Diode voltage

Change = -1.6 mV/C

Temp, °C

FIGURE 5.5 CTAT source.

VCC

M1 M2

M3

+ ZENER R IOUT
VZ
-
M4 M5

GND

FIGURE 5.6 Zener-based current source.

Voltage Regulator, References and Biasing 121

works as a voltage reference or a source with a Tcc near zero. The current reference,
Iout = Vz/R, this circuit depends on the Tcc of R. The disadvantages of this circuit are
the supply voltage needs to be more than the Zener breakdown voltage and a noisy
Zener diode.

5.5 BANDGAP VOLTAGE REFERENCE

If you plot the diode voltage (VBE) over the temperature, you will notice that it
points to the bandgap potential (1.2 V for silicon technology) at absolute zero (zero
Kelvin). The bandgap voltage at zero K, by the way, is strictly a theoretical concept;
at that temperature there are no semiconductors. Delta-VBE is a truly straight line,
pointing to zero at zero K, but it is relatively small.

5.5.1 Bandgap Reference
The bandgap circuit as shown in Figure 5.7 is tentatively an essential analog circuit
to generate reference voltages or currents that exhibit little dependence on tempera-
ture. Vertical parasitic pnp bipolar junction transistors are normally used as diodes.
In general,

Vbg = α1V1 + α 2V2 (5.3)

R5 R4
VOUT

+
-

R7

Q1 Q2

VSD

FIGURE 5.7 Bandgap circuit.

122 CMOS Analog and Mixed-Signal Circuit Design

where V1 has positive Tcc, and V2 has negative Tcc (varying in opposite directions with
temperature).
Choosing α1 and α2 so that α1 δV1/δT + α2 δV2/δT = 0. Hence, the reference band-
gap voltage obtained will be zero Tcc.
For a bipolar device, Ic = Is exp (VBE/V T ), where V T = kT/q.
Therefore, VBE = V T ln (Ic/Is). Hence, in Equation 5.3, the bandgap voltage is
now defined as below:

Vbg = α1VBE + α 2∆VBE (5.4)

where VBE = base emitter voltage of bipolar transistors (forward voltage of a

­positive-negative (pn) junction diode exhibits a negative Tcc), and ∆VBE = the dif-
ference between two bipolar transistors base-emitter voltages operating at unequal
current densities (exhibits positive Tcc).
∆VBE = VBE1 − VBE 2 = VT ln ( n ). Transistor Q2 is 10 times of Transistor Q1.
(Assumption to be made: Assume Ib negligible.)
This bandgap circuit is simply incorporated by three series base emitter voltages.
With the operational amplifier, inputs of Vinm and Vinp are forced to be equal.

Vinm = Vinp

Hence,

Vbe1 = Vbe 2 + I ref R (5.5)

and

I ref R = VT ln 10 or R = (VT ln 10 ) / I ref

Lastly, the bandgap voltage is:

Vbg = I ref ( R5 ) + Vbe1 (5.6)

The assumption is the current into transistors is similar or equal to Iref. For large
voltage application, this bandgap circuit can be incorporated by multiple series base
emitter voltages instead of one base emitter, as in the above example.

5.6 DIODE-LESS VOLTAGE REFERENCE

Figures 5.8 and 5.9 show two circuits [2] which do not employ diodes. Figure 5.8
shows the new voltage reference generator proposed here is based on the well known
circuit which uses MOSFETs and one resistor only [3], which works as a PTAT cur-
rent and voltage source. The simplified schematic of a PTAT is shown in Figure 5.9.
The current mirrors Ml and M2, and M3–M4 form a closed loop gain greater than
Voltage Regulator, References and Biasing 123

vdd

M1 M2

I1
I2

M4 M3

IR R VGS

gnd

FIGURE 5.8 Beta multiplier circuit.

unity. If one assumes that M3 and M4 operate in the weak inversion region, and the
supply voltage (VDD) is high enough to ensure the saturation of M1 and M2, then
delta gate source voltage (VGS ) can be expressed as follows:

∆VGS = VT ln ( k ) (5.7)

where V T = kT/q is the thermal voltage, k = (S1/S2)*(S3/S4), and S1, S2, S3, and S4 are
W/L aspect ratios of the respective MOSFETs. Notice that delta VGS does not depend
on the current level, as long as M3 and M4 are in weak inversion. The current IR is
defined by R and can be reproduced by further current mirrors.
The presence of a resistor is a drawback. If a low current is required, a high value
resistance is needed, which costs a large silicon area. The accurate resistance in
not guaranteed by some foundries and can vary with technology. In the proposed
voltage reference source, the resistor R is replaced by negative-type metal-oxide
semiconductor field-effect transistors (n-MOSFETs) M5 and M6, which work in the
linear region of weak inversion. Both of those MOSFETs are biased by stable out-
put reference voltage (VREF) to assure that the drain-source resistance, rds of the
MOSFET resistors M5 and M6 varies only with process and temperature, not with
supply voltage. This behavior modifies the generated currents 19 and IR with the
process and temperature variations in the opposite way to process and temperature
fluctuations in the output load circuit built with M7 and M8. This concept is depicted
in Figure 5.9.
124 CMOS Analog and Mixed-Signal Circuit Design

vdd

M1 M2 M9

M10

I1 M7
I2

M8
M4 M3

IR
M5

Istart
VGS

M11
M6 VREF

gnd

FIGURE 5.9 Diodeless voltage reference circuit.

The final equation of VREF is:

VREF = ∆VGS +VDS 7 + VDS 8 (5.8)

As ∆VGS is considered as the PTAT source, then the VDS of M7 and M8 behaves as
the CTAT source.

5.7 CASCODE CURRENT SOURCE

The cascode current source provides quite an exact current across voltage at the out-
put or between the output and ground. The only thing which should be done is to find
the condition providing the operation of the cascode current source transistors in the
saturation region. The lower devices (M2 and M4) are dimensioned so that the gate
voltage has the required value for cascode biasing. The top devices (M1 and M3)
are made wide enough to leave a comfortable margin between their source potential
and VDSAT of the bottom devices. This is shown in Figure 5.10. This is a much lower
current of the cascode current source. The output resistance of the cascode current
source is actually the total resistance of M3 and M4. The resistance is:
Voltage Regulator, References and Biasing 125

M1 M3
100/2 100/2

0.4

M2 M4
10/5 10/5
0.7 V

FIGURE 5.10 Cascode current source.

Ro = ( 2 + gm 3ro3 ) ro3 ≅ gm 3ro32 (5.9)

as vgs4 = 0 (from the small signal point of view), the equation is left without M4
parameters.

5.8 REGULATED POWER SUPPLY

Figure 5.11 depicts the block diagram of the voltage regulator. A high voltage n-type
MOS is utilized as a pass transistor. The error amplifier, the feedback resistor,
and the pass transistor form a negative feedback loop. The output voltage can be
expressed as out:

 R 
Vo = Vref .  1 + 1  (5.10)
 R2 

A high temperature linear voltage regulator requires a high-performance error

amplifier. A temperature stable biasing current will prevent the power consumption
of the error amplifier from increasing needlessly over temperature, and preserve its
126 CMOS Analog and Mixed-Signal Circuit Design

Pass transistor
Unregulated ro VO
DC M1
+ VC
+− R1 RL I
− Vin L
AV
+ VO'
Vi –

Vref +

VO R2

FIGURE 5.11 Regulated power supply 1.

stability. The design of a high-performance wide temperature range error amplifier

depends on the availability of a stable current reference [4].
A series regulator is one type of linear regulator that relies upon the variable
conductivity of an active electronic device to drop the voltage from an unregulated
direct current (DC) input voltage to a regulated output voltage.
The simple series voltage regulator using a power transistor (350V HV-DMOS)
and a Zener diode is shown in Figure 5.12.
This circuit is called a series regulator because the drain and source terminals of
the transistor are in a series with the load resistor, R2. This circuit is also called a
source follower voltage regulator because double diffused metal-oxide semiconduc-
tor (DMOS) is connected in the source follower configuration. Here, the DMOS is
termed a series-pass transistor. The current in the Zener diode is small because of
the current amplifying property of the DMOS. Hence, there is a little voltage drop
across the diode resistance, and the Zener approximates an ideal constant voltage
source.

R = R3 + R1 (5.11)

where R0 and R1 are the total resistance, R of the high voltage resistor.
The current through resistor R is the sum of the Zener current, IZ, and the transis-
tor gate current IG (=ID/β ≡ IOUT/β), where β is the current gain of the transistor.

IR = IZ + IG (5.12)

The DC input voltage, VIN, is fed to the input terminals, and the regulated output voltage,
Vout, is obtained across the load resistor, R2. The diode provides the reference voltage,
VZ, and the DMOS acts as a variable resistor, whose resistance varies with the gate cur-
rent, IG. The principle of the operation of such a regulator is based on the fact that a large
proportion of the change in the input voltage appears across the transistor. Therefore, the
output voltage tends to remain constant. The polarities of different voltages are,

Vout = Vz − VGS (5.13)

Voltage Regulator, References and Biasing 127

vin

R3

R1

out

Zener R2
diode Zener
diode

vssa

FIGURE 5.12 Regulated power supply 2.

The gate-source voltage, VGS, of the transistor remains almost constant, being equal to
that across the Zener diode, Vz. For the operation of the series regulator, the increased
VGS causes the DMOS to conduct more if the VOUT decreases, thereby raising the out-
put voltage and maintaining the output constant. If the VOUT increases, the decrease
of VGS causes the DMOS to conduct less, thereby reducing the output voltage and
maintaining the output constant. The resistor R2 is calculated using an equation,

R2 = VOUT /I OUT (5.14)

The second diode, D1 at the output stage, is to clamp the overshoot voltage.
The key principle in this type of circuit, such as “Low drop regulator” is achieved
by finding a low drop pass element/transistor. Nevertheless, switching regulators
could improve the efficiency of a regulator, but with an increase in noise.

5.9 DESIGN EXAMPLE

Two designs examples are shown in Figures 5.13 and 5.14. Both designs are using
the same concept, which is regulated voltage or constant-transconductance (gm).
Figure 5.13 shows the complete concept of the voltage reference and biasing
128 CMOS Analog and Mixed-Signal Circuit Design

Vdd

M7 M10

R1 12k R2 24k
Vbg
U1
+
- M8 M8 M9
OPAMP
R3 4k Bandgap amp R4 5k Out1

d 1X d 18X
R5 5k
Vbg/2 U2
M3 M4
+
-

OPAMP
R6 5k
Current amp

˜ Vbg/2
R7 5k R8 5k

R9 5k

Current Generator
R11 5k
2

R10 5k
U3
1

tClose = 0
2

R12 5k

U4
1

tClose = 0

FIGURE 5.13 Design 1.

circuitries. “Vbg” is the bandgap voltage, which the value is constant across the
PVT. It uses the VBE of the diode as a CTAT source, while the ∆ VBE is used as
the PTAT source. The bandgap amp is used to force both voltages at its inputs to be
approximately the same. Figure 5.13 also shows the biasing circuitries for a circuit
that requires good current sources. The second operational amplifier (opamp), called
current amplifier (amp), is used to provide a constant current source or transconduc-
tance. The concept is similar to the circuit in Figure 5.11, with only slight modifica-
tion. The current amp forces the transistors M3 and M4 to produce a constant current
across at least the VDD variation. From the figure, the current is

0.5Vbg1
I D3 = (5.15)
Req

where the equivalent resistor, Req, is the total resistance for the “current generator.”
Obviously, the current is constant across the voltage and temperature variation. This cur-
rent can be reproduced to another circuit by using a simple current mirror concept.
Voltage Regulator, References and Biasing 129

FIGURE 5.14 Design 2.

Figure 5.14 shows the digital-to-analog converter (DAC) Reference generates the
bias voltages necessary for the switchable current sources (Figure 7.3) in the hybrid
DAC (Section 7.2.3). A single stage amplifier is used to impose the reference volt-
age across the 3l unit resistors in the series. At the top of that series resistor, there is
16 unit of current source, one unit of resistor value that is arranged in series is 120 Ω
(to match with the resistor in the binary-weighted resistor string).
The first bias voltage, DACBIAS1, is the voltage required at the gate of the transis-
tor Ml in a switchable current source to maintain a constant current. The second bias
voltage, DACBIAS2, is a cascode bias feeding to increase the output impedance of
the current source. The VREF is needed to maintain the bias voltages because this is
one of the most important factors to provide a constant current throughout the resistor
network. Resistor R and capacitor C in the figure are used for circuit stability. VOUT
and feedback voltage are connected at the top level in order to configure the circuit as a
buffer amplifier. The fourth terminals of the PMOS transistors are connected to VDD,
while the fourth terminal of the NMOS transistors is connected to Ground (GND).
With the target value current, I equals 20 µA, the VOUT is therefore equal to 1.1999 V.

5.10 SPICE EXAMPLE

Based on Figure 5.1, we can simulate the basic current source of 20 µA. Figure 5.15
shows the simulation results of the basic current source and mirror. We can see that
M2 is not a perfect current source. The current does change across VDS.
Figure 5.16 shows how we can provide the basic voltages for biasing transistors,
especially the cascode current source in an opamp (see Chapter 3). The results of
the figure are shown in Figure 5.17. Figure 5.18 shows the beta multiplier refer-
ence circuit. The circuit needs a start-up circuit. Figure 5.19 shows the simulation
130 CMOS Analog and Mixed-Signal Circuit Design

Id (M1)
Id (M2)

2.4x10-5

2.2x10-5

2.0x10-5

1.8x10-5
Id (A)

1.6x10-5

1.4x10-5

1.2x10-5

1.0x10-5
0 2 4
Vo (V)

FIGURE 5.15 Current source simulation results.

VDD

20/2 Vbias1

VDD VDD VDD VDD

20/2 20/2 20/2 20/20 20/2 Vbias2

Vbiasp

10/20 10/2 10/2 10/2 Vbias3

Iref = 20µA
10/2 10/2 10/2 Vbias4

FIGURE 5.16 CASCODE Biasing circuit.

Voltage Regulator, References and Biasing 131

Vbias1
Vbias2
4 Vbias3
Vbias4

3
V (V)

0.0 0.5 1.0

Time (s)

FIGURE 5.17 CASCODE Biasing circuit simulation result.

VDD VDD VDD

60/10 60/10 60/10

Vsu 6/2

6/20
30/10 30/10
Vbiasn

Rbias
6/20 10 KΩ

FIGURE 5.18 BMR circuit.

132 CMOS Analog and Mixed-Signal Circuit Design

Vbiasn

1.0
Vbiasn (V)

0.5

0.0
0 2 4 6
Vdd (V)
FIGURE 5.19 BMR simulation result.

FIGURE 5.20 Bandgap circuit.

Voltage Regulator, References and Biasing 133

1.5

1.0
Vref (V)

0.5

0.0
0 2 4 6
Vdd (V)

FIGURE 5.21 Bandgap circuit simulation result.

result. Figure 5.20 depicts a bandgap circuit, which is a modified beta multiplier ref-
erence (BMR) circuit. Figure 5.21 shows the simulation result of the bandgap circuit.
The output voltage is approximately equal to 1.2 V across the temperature variation.

5.11 LAYOUT EXAMPLE

Figure 5.22 shows the biasing layout based on Figure 5.16. The basic layout plan is
applied for the circuit. Figure 5.23 shows the layout based on Figure 5.18.

FIGURE 5.22 Layout of CASCODE Biasing circuit.

134 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 5.23 Layout of BMR circuit.

5.12 SUMMARY
In this chapter, a bandgap or reference voltage circuit is discussed. These circuits
are normally applicable to practical analog or mixed-signal integrated circuits.
The diodeless circuitry is a new innovation that could be applied to mixed-signal
integrated circuit products if proper investigation about the PVT variation and the
technique to improve is available.

PROBLEMS
Based on Figure 5.1, if the targeted current is 20 µA. W = 6 µm, L = 1.2 µm. Using
Table 2.8 calculate the required Vgs.

REFERENCES
1. Gray, P. R., Hurst, P. J., Lewis, S. H., and Meyer, R. G. (2009). Analysis and Design of
Analog Integrated Circuits, 5th ed. Hoboken, NJ: John Wiley & Sons.
2. Borejko, T., and Pleskacz, W. A. (2008). A resistorless voltage reference source for
90 nm CMOS technology with low sensitivity to process and temperature variations.
11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
(pp. 1–6).
3. Vittoz, E., and Fellrath, J. (1977). CMOS analog integrated circuits based on weak
inversion operations. IEEE Journal of Solid-State Circuits, 12(3), 224–231.
4. Flandre, D., Demeus, L., Dessard, V., Viviani, A., Gentinne, B., and Eggermont,
J.-P. (2002). Design and application of SOI CMOS OTAs for high-temperature envi-
ronments. IEEE Transactions on Circuits and Systems: Analog and Digital Signal
Processing, 49, 449.
 6 Introduction of
Advanced Analog Circuit

6.1 INTRODUCTION
This chapter will be useful in designing a mixed-signal integrated circuit. Many
conventional analog circuits can be replaced with the dynamic analog circuit and
non-linear analog circuit. The dynamic analog circuit employs the fact that charge
or information can be stored on a capacitor or gate capacitance of a metal-oxide
semiconductor field-effect transistor (MOSFET). However, the non-linear circuit
exploits the non-linear characteristics of the device or sub-circuit. The example
of the circuits is an analog multiplier, logarithmic amplifier, etc. Most of the basic
switched-capacitor circuitries are explained in this chapter. A chopper amplifier con-
cept is also introduced in this chapter.

6.2 MOSFET AS A SWITCH

The largest voltage that an N-type metal-oxide semiconductor (NMOS) switch
can pass is Vdd–Vth. While the lowest voltage a P-type metal-oxide semiconductor
(PMOS) switch can pass is Vth. The combination of NMOS and PMOS in parallel
(transmission gate) can remedy this issue. These conditions are valid when the sub-
strates (p- and n-well) are connected to the correct potential.
Recall the expression for the current I ds( lin) in the MOS transistor, as a result, the
expression for the transistor conductance gds = ∂( I ds( lin) ) in the linear mode can be
written in the form of: ∂(Vds )

gds = β × (Vg − Vin − Vth − Vds ) (6.1)

Weff
where β = C0 × µ × .
Leff
Obviously, the MOS transistor switch conductance varies with an input signal.
The conductance of the switch can be made slightly constant by using PMOS and
NMOS transistors connected in parallel.
The charge injection effect can also be decreased by using PMOS and NMOS
transistors connected in parallel in the analog switch. These transistors inject charges
of opposite signs, thus there are prerequisites for their compensation.
The absolute value of a charge in the NMOS transistor inversion layer is:

QN = Cox (WL) N × ∆Von( N ) = Cox (WL) N × (Vck − Vin − VthN ) (6.2)

135
136 CMOS Analog and Mixed-Signal Circuit Design

Here, ∆Von( N ) is a gate overdrive in the NMOS transistor.

The same is true for the PMOS transistor (the input signal value is counted off
from Vss ):

QP = Cox (WL) P × ∆Von( P ) = Cox (WL) P × ( Vin − VthP ) (6.3)

It is obvious that with the common equation LN = LP , compensation can be expected

at WN = WP, i.e., we have (WN LN ) = (WP LP ) ≡ (WL ).
Let us define the difference QN − QP :

QN − QP = C0 ( WL ) × ( Vdd − 2Vin − VthN + VthP ) . (6.4)

It is clear that the equality of QN and QP can be achieved only at the only value of
Vin , close to Vdd .
2

6.3 BASIC SWITCHED CAPACITOR

6.3.1 Switching Capacitor Sensitive to Parasitic Capacitances
A basic switched capacitor is shown in Figure 6.1. First of all, it is assumed for
simplicity of reasoning that, voltage sources that are connected to the switching
capacitor (SC) C is constant, i.e., V1 and V2. Let V1 be >V2.
Clock periods Т1 and Т2 do not overlap, so there is no time overlapping of closed
switch states.
When switch Т1 closes at the beginning of the N-th clock period, the capacitor С1,
as well as parasitic capacitances СР1 and СР2 are charged up to V1. Then the switch
Т1 opens, after a short period of time the switch Т2 closes, and the same capacitors
are charged to V2. The resulting effect of this process is charge transfer equal to
(C + C P1 + C P 2 )(V1 − V2 ) in its absolute value, from the voltage source V1 into the volt-
age source V2.

T1 T2

Sw1 C Sw2

+ +
V1 V2
- Cp1 Cp2 -
Vssa Vssa
Gnda

T1

T2

FIGURE 6.1 Elementary switched capacitor.

Introduction of Advanced Analog Circuit 137

The charge numerically equal to the average current passes between sources V1
and V2 for one second:

(V1 − V2 )
I = (C + C P1 + C P 2 )(V1 − V2 ) × Fs = , (6.5a)
Reff

1
where Reff = is an effective resistance of the SC. (6.5b)
Fs × (C + CP1 + CP 2 )

Let us calculate the effective resistance of the SC.

Let: (C + CP + CP 2 ) = 1 pF; Fs = 100 kHz. Then Reff = 10 MΩ that is the value
achievable only when an advanced technological process is used.
The possibility of obtaining high-value resistors is the first advantage of the SC
method (another main advantage of the SC method will be described below).
Attention should be drawn to the fact, however, that parasitic capacitors СР1 and
СР2 are connected in parallel with С1 and add their charge to the С1 charge. The role
of these capacitors cannot be actually considered with an acceptable accuracy
because of their non-linearity and insufficient repeatability of the chip parameters in
the depleted areas of P–N junctions. The SC types independent on parasitic capaci-
tances are described in next section.
Figure 6.1 is also called a non-inverting SC, as into V2, i.e., to the collector of the
transferred charge, the charge is transferred having a sign, similar to the sign of the
charge passing from V1 to V2 at a simple connection of sources V1 and V2 with a resistor.
Now let the potentials of voltage sources, where the switching capacitor is con-
nected to, change in time.
Let the moment of the clock period Т1 transition from logic zero to logic one, that
is T1 ⇒ 1, be the beginning of the regular clock period. Let the SC (C + CP1 + CP 2 )
become disconnected from the voltage source V1 at the moment T1 ⇒ 0 within
the N − 1-th clock period. As the moment T1 ⇒ 0 is very close to the middle of
the N − 1-th clock period, we shall designate it as a point of time. The instanta-
neous value of the input voltage V1( N − 1 ) at the moment N − 12 is stored on capacitors
2
(C + CP1 + CP 2 ). A little later, actually at the same moment, T2 ⇒ 1, the charge stored
in capacitors (C + C P1 + C P 2 ) × V1( N − 12 ) is also transferred to the voltage source V2. As
real switches have non-zero, i.e., finite channel resistance, the charge from capacitors
to V2 is not transferred instantly, and the time from the moment T2 ⇒ 1 to the moment
T2 ⇒ 0 , equal to nearly the half period, is the time when the capacitor discharges to
the acceptable accuracy. The charge transfer finishes at the moment N . It is clear
from the given reasoning that the SC described performs a half a clock period delay
and is called an SC with a delay. It should be noted, however, that if the value of
V1 changes only on clock period boundaries, i.e., if the previous circuits fulfill the
sample-and-hold function, the SC described performs a whole clock period delay.
It follows from the description of the SC operation that the potential at the SC out-
put node changes with one clock period periodicity, hence, the SC nodes perform the
sample-and-hold function. In most SC circuits, there is only one SC and, namely, the
one on the boundary of the SC-system and the outside analog world where the input
138 CMOS Analog and Mixed-Signal Circuit Design

is continuous in time. In the rest of the SCs, which are quite numerous, the input
signal changes right on the clock boundary, as it is defined by previous SCs. As it is
these SCs that determine mainly the transfer function of the SC-system, it is common
to consider in the SC analysis that the delay in the switching capacitor with a delay
is equal to the whole clock period, i.e., to one. That the delay is different from one in
the only (as a rule) SC is taken into account separately, however, in most SC-systems
of the high enough order, this is not significant. Summing up what was said above,
we shall note that this SC is called a non-inverting SC with a delay.
It can be written that the charge passing from V1 to V2 conforms with the follow-
ing expression:

Q2( N ) = (C + C P1 + C P 2 ) × V1( N −1) (6.6)

6.4 ACTIVE INTEGRATOR

Let us assume for simplicity that the opamp included in the integrator on the SC has
an indefinitely big, i.e., infinite differential amplification, and the potential of the
voltage source VIN is positive.
The transfer function of the continuous integrator is:

1 1
H ( s) = − ×
s RC2

Let us replace formally the resistor with its equivalent on the SC in Equation 6.5b:

1
R= .
(C1 + CP1 + CP 2 ) × Fs

F (C + C P1 + C P 2 )
Then: H ( s) = − ss × 1
C2

When the switch Т2 is closed, at the first moment of the total charge on С1, СР1, and
СР2 are distributed between these capacitors and the input capacitor of the OA invert-
ing input, resulting in its changed potential. The sign of the output voltage VOUT change
is opposite, and the charge arriving at the С2 right plate is opposite to the potential
sign at the inverting input. To preserve the total electric neutrality of both plates of the
capacitor С2, a charge is “pushed out” of the С2 left plate into the inverting input circuit.
This charge has a sign similar to that of the charge added to the С2 right plate, but oppo-
site to the sign of the charge, which arrived from the SC to the OA inverting input. As a
result, the charge, which arrived from the SC at the OA inverting input, is compensated.
The compensation process lasts until the inverting input potential becomes zero.
When this result is achieved, the whole charge, which arrived from the SC at the
OA inverting input circuit, is compensated. It turns out here that the charge “pushed
out” of the С2 left plate is of the opposite sign, but is equal in its absolute value to the
Introduction of Advanced Analog Circuit 139

charge which arrived from the SC at the OA inverting input. The result is similar to
the transition of the whole charge, which arrived at the OA inverting input to the C2
integrating capacitor. It is this conclusion that is always meant while analyzing the
active integrator on SC.
Thus, the charge delayed by a clock period and equal in its absolute value to
VIN ( N −1) × (C1 + CP1 + CP 2 ), after passing to the capacitor С2, changes the voltage on it
and, hence, at the integrator SC output, to:

C1 + C P1 + C P 2
∆VOUT ( N ) = −VIN ( N −1) . (6.7)
C2

As a result, if, for example, VIN = const , the voltage at the integrator SC output
changes (to the side opposite to the VIN sign) stepwise (see Figure 6.2), the envelope
of these steps being a straight line as in the continuous integrator.

6.4.1 Non-inverting Switching Capacitor ­Non-sensitive

to Parasitic Capacitances

To eliminate parasitic capacitor influence, another wiring diagram of the switching

capacitor is offered (see Figure 6.3). Here, Сp1 and Сp2 are parasitic capacitances of
switches. Let it be necessary to transfer the charge from voltage source V1 to another
source V2. There is also the third source of constant voltage V3, identical to V2.

C2

T1 T2
I
N C1 A OUT

Cp1 Cp2

Gnda Gnda

N-1 N N+1
T1

T2

Integrator
Output

FIGURE 6.2 Active integrator with elementary SC.

140 CMOS Analog and Mixed-Signal Circuit Design

T2 T2
C
Sw4 Sw3

T1 Sw2 Sw1 T1
+ Cp1 Cp2 +
V1 - - V2
Vssa + Vssa

Gnda V2 = V3 -
Vssa

FIGURE 6.3 Non-inverting SC without a delay, non-sensitive to parasitic.

Let the notes given above while analyzing the SC in Figure 6.1 be true.
Switches Sw1 and Sw2, controlled by the clock signal Т1, are closed, and switches Sw3
and Sw4 are open: T1 ⇒ 1.

When the capacitor С is discharged, both plates have potentials V3 = V2; parasitic
capacitors Сp1 and Сp2 are also charged to the voltage V3 = V2. Charges, which are on
both plates of the capacitor, go to the source V3, as a result, the charge stored on the
capacitor is equal to zero.
Switches Sw3 and Sw4, controlled by the clock signal Т2, are closed, and switches Sw1
and Sw2 are open: T2 ⇒ 1.

When the parasitic capacitor Сp2 is not recharged; the left plate of the capacitor
С is charged to V1, and the right one is charged to V2. Charges on the plates, equal
in absolute values С(V1 − V2) and opposite in sign, come from sources V1 and V2.
A positive charge comes from the source V1, and a negative charge of the same value
comes from V2. We can reason the same in another way: to conserve the electric
neutrality of the capacitor, a positive charge equal to С(V1 − V2) is “pushed out” of
the SC right plate and goes directly to V2. In either method of reasoning, the result-
ing effect is transferring a positive charge of the С(V1 − V2) value to V2 at each clock
period. As can be seen, parasitic capacitors transfer no charge to V2. The parasitic
capacitor Сp1 is certainly recharged at this time, but one should not worry about it,
as it is connected with the input voltage source V1, i.e., with the charge source.
Like the SC in Figure 6.1, the SC in Figure 6.3 being analyzed is a non-inverting
SC, for to V2, i.e., the transferred charge collector, a charge is transferred which has
a sign similar to the sign of the charge passing from V1 to V2 when sources V1 and V2
are simply connected with a resistor.
Let the source of time-variant voltage V1 be on the left in Figure 6.3, just as in the
same name analysis for the SC in Figure 6.1, and the constant voltage source V2 be
on the right. As it is clear from the SC (Figure 6.3) operation description, the nega-
tive charge is transferred from the source V2 to the SC right plate at moments which
coincide with moments of connecting the SC to V1, that is, at moments of transferring
Introduction of Advanced Analog Circuit 141

the positive charge from the source V1 to the SC left plate. There is no delay in charge
transfer from V1 to V2 in this case. These SCs are called non-inverting SCs without
delay. The charge coming from V1 to V2 is:

Q2( N ) = C × V1( N ) (6.8)

If this process is repeated in each clock period with the frequency FS, the average
current I, flowing from V1 to V2 is: I = C × V1 × Fs , and the equivalent resistance is:

1
R= (6.9)
C × Fs

6.4.2 Inverting Active Integrator without a Delay

Let us assume for simplicity that the OA belonging to the SC has an indefinitely big,
i.e., infinite differential amplification, and the voltage source potential VIN is positive.
Switches controlled by the clock signal Т2 are closed: T2 ⇒ 1.

When comparing the non-inverting SC in Figure 6.3 with an active integrator on

its base shown in Figure 6.4, it is obvious that V3 = 0, as the non-inverting OA input
is grounded.
At T2 ⇒ 1, the charge С1VIN is pushed out of the SC right plate, thus the inverting
OA input potential (node A) becomes positive, and the potential change sign VOUT of
the integrator output becomes negative. As a result, a negative charge compensat-
ing the positive charge of node A is pushed out of the left plate of the С2 integrating
capacitor. The movement of the VOUT to the negative side occurs until the whole posi-
tive charge СVIN in node A is compensated. If we take into account the fact that the SC
used in the SC integrator is an SC without delay, the resulting effect will be a change
without a delay of the output voltage to the side, opposite to the input voltage sign:

C1
∆VOUT ( N ) = −VIN ( N ) × (6.10)
C2

C2

T2 C1 T2
IN
Sw4 Sw3 A OUT
T1 Sw2 Sw1 T1
Cp1 Cp2
Gnda

Gnda Gnda

FIGURE 6.4 Inverting active integrator without a delay.

142 CMOS Analog and Mixed-Signal Circuit Design

It is clear that both switches and OAs are lag elements so “without delay” means that
the beginning of VOUT change occurs without delay regarding the point of time when
T2 ⇒ 1. The transition period end point is the beginning of the next clock period.
If the resistor in the active resistor capacitor (ARC) integrator is replaced with
its equivalent formally, Equation 6.9, the transfer function of this integrator is:
H (s) = s ( RC
1
2)
= Fss × CC21 . The second main advantage of the SC method follows from
here: The time constant accuracy of the SC integrator based on SC non-sensitive
to parasitic capacitances does not depend on resistance and capacitance absolute
values (rated values of each of these components range within ±20% from batch to
batch), but on the capacitance ratio C1 , equal to 0.1%–0.2% for most technological
C2
processes.

6.4.3 Inverting the Switching Capacitor with a Delay,

Non-sensitive to Parasitic Capacitances
Let us assume for simplicity, as we did it before, that:
The OA in the SC-based integrator has an indefinitely large, i.e., infinite differ-
ential amplification;
V3 = V2;
V1 voltage source potential is positive regarding V3 and V2.
The SC type considered is the most “capacious” one in terms of the number of
physical effects to be taken into account, and it is convenient to analyze assuming
the voltage source V1, attached to the left plate to be the source of the signal changing
in time. The right plate can be attached to voltage sources V2 and V3 = V2 is constant
in time.
As before, the left and the right SC plates are controlled by non-overlapping
clock signals Т1 and Т2 (see Figure 6.5), that is, switches controlled by clocks with
subscripts 1 and 2 cannot be in the closed state simultaneously. Unlike Figure 6.3,
clock signals Т1d and Т2d, controlling the left plate, have interchanged, firstly, and,
secondly, are delayed (subscripts in Т1d and Т2d are from the word delayed) relative
to clock periods Т1 and Т2.
Let the points of time when T1 ⇒ 1 be the beginnings (and simultaneously the end
points) of clock periods. Let also the time intervals between points T1 ⇒ 1, T1d ⇒ 1,
T2 ⇒ 0 , and T2 d ⇒ 0 be so small compared to the clock signal period that all the
points mentioned in this paragraph are the beginnings (and at the same time end
points) of clock periods. Points T1 ⇒ 0 , T1d ⇒ 0 , T2 ⇒ 1, and T2 d ⇒ 1 are middles of
clock signal periods.

6.4.4 SC Behavior in Discrete Points of Time

Switches Sw1 and Sw2, controlled by clock signals Т1 and Т1d , respectively, are closed,
switches Sw3 and Sw4 are open: T1 ⇒ 1, T1d ⇒ 1.

The SC left plate is charged up to the positive potential V1, the right plate is
charged up to the potential V3, negative respective to the potential V1.
Introduction of Advanced Analog Circuit 143

T1d T2
C
Sw2 Sw3

T2d Sw4 Sw1 T1

V1 + Cp1 Cp2 +
- - V2
Vssa + Vssa

Gnda V2 = V3 -
Vssa

T1

T1d

T2

T2d

N -1 N -1/2 N

FIGURE 6.5 Inverting switching capacitor with a delay, non-sensitive to parasitic

capacitances.

Switch Sw1, controlled by the clock signal Т1, opens. Then switch Sw2, controlled by
the clock Т1d , opens: T1 ⇒ 0 then T1d ⇒ 0 .

Let the clock period T2 be still equal to zero and T1d be still equal to one. The SC
right plate has been floating since the point T1 ⇒ 0 , so there is a charge on the SC which
corresponds to the instantaneous voltage V1 at the point T1 ⇒ 0 . Let this moment be
equal N − 12 and the corresponding charge be:

Q 1 = V 1 ×C (6.11)
1 N −  1 N − 
 2  2

At any number of the point T1 ⇒ 0 , the SC right plate has the same potential equal to
V3, i.e., independent of the value of V1. Thus, the value of the charge injected into the
right plate at the Sw1 switch opening at the point T1 ⇒ 0 does not depend on V1, and,
therefore does not produce non-linear distortion. At the point when T1 ⇒ 0 , the SC
left plate must be connected to the voltage source (with V1 in this case) not to prevent
the charge equal in its absolute value to the charge injected into the left plate from
coming to this plate from the voltage source. If we assume, theoretically, that the
144 CMOS Analog and Mixed-Signal Circuit Design

clock Т1 opens Sw2 which connects the left plates with V1, but not Sw1, the charge
injected into the left plate will depend on the value of V1 at this moment and, as a
result, non-linear distortion will occur. Disconnecting the left plate from V1 after
disconnecting the right one from the ground, i.e., at the point T1d ⇒ 0 , does not bring
any additional charge into the left plate, as the right plate is floating at the moment
and cannot exchange the charge with the voltage source.
Thus, the SC switch opening sequence, when the switch connecting the SC plate
with the constant voltage source opens first, adds no non-linear distortion.
Switches Sw3 and Sw4 close in turn, switches Sw1 and Sw2 are open: T2 ⇒ 1, then T2 d ⇒ 1.

The switch Sw3 connecting the SC right plate with the constant voltage source V2
is the first to close in the N-th clock period at the point T2 ⇒ 1. As for V3 = V2, the
charge state of the SC does not change.
Then, at T2 d ⇒ 1, the left plate potential became more negative by the value of:

V1( N ) = V  1 − V3 . (6.12)
1 N − 
 2

To preserve the total zero charge of the SC, a negative charge of the same value is
pushed out of the right plate into the source V2. It is clear that this charge differs from
Equation 6.12 by a fixed value taking into account the charge injection effect at Sw1
opening, but it produces no non-linear distortion.
Bearing in mind the reasons given above when the elementary SC with a delay
was described, we can write:

Q1( N ) = (V1( N −1) − V3 ) × C (6.13)

It is clear from what is described in the last section that despite the positive sign of V1
relative to V2, a negative charge passes from V1 to V2!!! Due to this property, the SC
shown in Figure 6.5 is called an inverting SC with a delay.

6.4.5 Non-inverting Active Integrator with a Delay

As it follows from the above description of the inverting SC with a delay, a charge
arrives at the output node which has the polarity, opposite to the polarity of the charge
flowing between V1 and V2, when connected with a resistor. For example, with a posi-
tive sign of V1 relative to V2, a negative charge comes to V2 from V1. In the integrator
based on this SC type, the role of V2 is performed by the OA inverting input. Based
on the reasoning given above when the SC integrators were analyzed, the conclusion
follows that the integrator is non-inverting (Figure 6.6) and the potential jump at the
OA output (i.e., at the SC integrator output) at the end of the N-th clock period is
equal to:

C1
∆VOUT ( N ) = VIN ( N −1) × (6.14)
C2
Introduction of Advanced Analog Circuit 145

C2

T1d C1 T2
IN
Sw2 Sw1 A OUT
T2d Sw4 Sw3 T1
Cp1 Cp2
Gnda

Gnda Gnda

FIGURE 6.6 Non-inverting active integrator.

6.5 SAMPLE-AND-HOLD AMPLIFIER

A sample-and-hold (S/H) buffer amplifier as shown in Figure 6.7 consists of an oper-
ational amplifier (Figure 6.8), two capacitors, and switches. Bottom plate sampling
is employed in the design in order to reduce the substrate noise [1].
During the sampling (“phi0” is low) of the differential voltages, the output of the
operational amplifier (as shown in Figure 6.8) is shorted to its input and the Direct
Current (DC) voltage is set at Vcm by a common mode feedback circuit [2] in the opera-
tional amplifier. During the holding phase (phi1 is low), the output is shorted to the left/
bottom plate of the S/H capacitor. By employing the common mode feedback circuit
(CMFB), the output of this S/H buffer amplifier is always re-centered at Vcm. The CMFB
employs the capacitive sensing technique. Two capacitors are used to average out the
differential output voltage, the averaged output is connected to the CMFB amplifier

phi0

phi1

phi1
outp inp
capacitor
phi1 capacitor inm
outn

phi1
phi0

FIGURE 6.7 S/H buffer amplifier.

146 CMOS Analog and Mixed-Signal Circuit Design

VDDA

VSSA D1 D2

D1

D2
In+ In-
ibias out- out+

Vcmp Vcmn Vref

out+ out-

VSSA
Vcmp Vcmn

Vhold
Vsample

Vsample
FIGURE 6.8 Differential input operational amplifier with the CMFB.

input, the CMFB amplifier compares it with Vcm (connected to Vref), and adjusts the bias-
ing current until the averaged output is equal to Vcm. The ibias is supplied by the bandgap
circuit. Vsample is connected to phi1, while Vhold is connected to “phi0.”
Finite gain opamp could give us problem when phi1 high, the Vout = Aol·Vcm/
(Aol + 1) = Vcm , if only Aol is big.

6.6 PROGRAMMABLE GAIN AMPLIFIER

Programmable gain amplifiers (PGAs) are MOS switched-capacitor amplifiers. During
the sample cycle, they place the charge on one plate of a sample capacitor with the
other plate connected to a high impedance input node of the amplifier. The amplifier is
connected in unity gain. The output of the amplifier will provide all the charge neces-
sary at the input node of the amplifier to balance the charge on the sample capacitor.
Once the charge is balanced, the unity gain connection can be opened, and this will trap
the balancing charge on the high impedance input nodes of the amp. Then, during the
hold cycle, a feedback capacitor can be placed from the amplifier’s output to the input
nodes. The plate touching the input node will see the charge trapped there from the
sample cycle. The amplifier’s output then sets up a voltage so that the other plate of the
feedback capacitor will acquire a balancing charge. This output voltage will then be a
function of the original sampled charge, as well as the values of the sample and feed-
back capacitors. See the following two figures that show the sample cycle. Figure 6.9
shows during the sampling, while Figure 6.10 shows after the sampling is completed.
The two figures also depict an offset voltage (Vos) that intends to model the offset
voltage between the nodes of a non-ideal amplifier. This offset voltage would nor-
mally become an error term in the final held output voltage by altering the charge
stored on one of the input nodes during sampling. But the sample cycle includes a
means to cancel its affect.
Introduction of Advanced Analog Circuit 147

Vos
+ - VCM
Cf
Qp=-Cs(vx-Vos) + Cf(Vos)

Vx-Vos Vos
Vx+Vcm + - + - + -
Cs Vcm Vos + Vcm

AMP
Cs Vcm Vcm
Vy+Vcm
+ - - +
Vy

Qn=-Cs(Vy)
Cf
- VCM
+
0V

FIGURE 6.9 During sampling.

Vos
+ - VCM
Cf
Qp=-Cs(vx-Vos) + Cf(Vos)

Vx-Vos Vos
Vx+Vcm + - + - + -
Cs Vcm Vcm
AMP

Cs Vcm Vcm
Vy+Vcm
+ - - +
Vy

Qn=-Cs(Vy)
Cf
- VCM
+
0V

FIGURE 6.10 Sampling completed.

To cancel the offset voltage, during sampling while the amplifier is in unity
gain, the feedback capacitors are also connected between the input nodes of the
amp and the common mode voltage. As shown in Figure 6.10, this allows charge
from any offset voltage Vos to be stored on a feedback capacitor. During the hold
cycle, it can be shown that this offset charge stored on the feedback capacitor will
cancel its equivalent (error charge) that became stored on the amp’s input node.
148 CMOS Analog and Mixed-Signal Circuit Design

Voutn-Vcm
- + VCM
Cf

Qp=Cs(Vos)/2 - Cf(Voutn - Vos - Vcm)

Vos
+ - + -
Cs + Vcm Voutn

AMP
Vos
Cs - Vcm
- + Voutp

Vy

Qn=-Cs(Vos)/2 - Cf(Voutp - Vcm) Cf

- VCM
+
Voutp-Vcm

FIGURE 6.11 Holding.

Figure 6.11 shows the hold cycle with the changes in the node voltages. The charge
on the input nodes of the amp is the same as it was during sampling, but it is
described in terms of the new node voltages.
To find the transfer function, the expression for the charge stored on each amp’s
input node during the sample cycle, needs to be equated with the expression for the
charge during the hold cycle, see Figure 6.11.
For the + input node charge (Qp):

Cs (Vos / 2 ) − C f (Voutn − Vos − Vcm ) = − Cs (Vx − Vos ) + C f (Vos )

C f (Voutn − Vos − Vcm ) = − Cs (Vx − Vos / 2 )
−C (6.15)
Voutn = ( Cs / C f ) (Vx − Vos / 2 ) + Vcm

For the − input node charge (Qn):

−Cs (Vos / 2 ) − C f (Voutp − Vcm ) = − Cs (Vy )

−C f (Voutp − Vcm ) = − Cs (Vy ) + Cs (Vos / 2 ) (6.16)
Voutp = ( Cs / C f )( Vy − Vos / 2 ) + Vcm
Introduction of Advanced Analog Circuit 149

Subtracting Equation 6.15 from Equation 6.16 yields the differential transfer func-
tion for sample and hold:

Voutp – Voutn = ( Cs / C f )(Vy – Vx )

Note that the offset voltage Vos has been cancelled out.

6.6.1 Timing
Note that the gain selection involves choosing different values of Cs and Cf from
arrays of capacitors. These need to be chosen after the hold cycle and before the next
sample cycle so the new values of Cs and Cf for either PGA are latched by the falling
edge of their hold clock. See Figure 6.12.

6.6.2 Common Mode Feedback

To control the common mode level of the amp, the differential outputs are con-
tinuously summed together by capacitors (Csum) that feed the summing node into a
separate common mode feedback amplifier (CMFB). This CMFB amp compares the

HOLD2
Cf
VCM Cf
VCM
HOLD1
FBCL2 FBCL1

SAMP1 SAMP2

HOLD1 HOLD2
Pixel signal
Cs + - Cs + - +
PGA1

PGA2

HOLD2 HOLD1 Voutp-Voutn

Ref signal
Cs
- + Cs
- + -
HOLD1 HOLD2

SAMP1 SAMP2

FBCL2 FBCL1
Cf HOLD1 Cf
VCM VCM
HOLD2

FBCL1

HOLD1

SAMP1

FBCL2

HOLD2

SAMP2

PGA1 Sampling PGA1 Holding

PGA2 Holding PGA2 Sampling

Set Cs and Cf for PGA1 Set Cs and Cf for PGA2 Set Cs and Cf for PGA1

FIGURE 6.12 Timing PGA.

150 CMOS Analog and Mixed-Signal Circuit Design

0V
+ - VCM
Cf

0V
Vcm + - + -
Cs Vcm Vcm
Csum

CMFB
AMP
AMP
SAMP
Csum

Cs Vcm
Vcm
+ - - + Vcm

0V

Cf
- VCM
+
0V

FIGURE 6.13 Top-level CMFB.

summed differential output of the main amp to a common mode reference voltage
(Vcm). The CMFB amp affects the bias point of the main amp’s folded cascode output
to hold the center point of the differential output to the Vcm value.
During any SAMPLE cycle, the Csum caps are cleared. See Figure 6.13.

6.6.2.1 AMP and CMFB

The gain stage used in the programmable amplifier is a standard, folded-cascode
configuration with one small improvement for increasing the gain. The gain stage
is shown in Figure 6.14 with the circuit improvement outlined. The transistors,
M6 and M7, biased to analog supply voltage (AVDD) by transistor M2, isolate the
drains of the input differential pair, M8 and M9, from the folding nodes. This lets
the conductances at the folding nodes be dominated only by the output resistances
of PMOS transistors, M1 and M3, instead of the parallel combinations normally
formed with the input differential pair. The nominal gain increase is between 4 dB
and 7 dB, depending on the process skew. This stage settles to 11-bit accuracy in
less than 200 ns with a nominal DC gain of 73 dB. The unity-gain bandwidth is
about 60 MHz.
The common-mode feedback circuit is shown in Figure 6.15. This common-mode
feedback circuit allows the common-mode level to be set during the sampling phase
at the same time that the amplifier offset is being sampled in unity-gain feedback.
During the sampling phase, the sampling (SAMP) switches are closed and the hold-
ing (HOLD) switch is open. At this time, the common-mode feedback capacitors are
shorted out and the common-mode output level is stabilized with transistors, M7,
Introduction of Advanced Analog Circuit 151

AVDD

Vbias4
M1 M2 M3

Vbias3

M4 M5
M6 M7

VOM VOP
+ M8 M9 –

Vbias2 M10 M11

Vbias1 M12 M13

AGND

FIGURE 6.14 Gain stage.

AVDD

Vbias3
M1 M2 M3 M4
To Gain Stage
Folding Nodes
M5 M6

M7
SAMP HOLD SAMP 2W VREF

M8 M9
VOP VOM
W W
C C

M10
Vbias1

AGND

FIGURE 6.15 CMFB circuit.

152 CMOS Analog and Mixed-Signal Circuit Design

M8, and M9. Transistors M8 and M9 act to average any amplifier offset. They also
act as the differential, composite transistor to M7. During the hold phase, the SAMP
switches open and the HOLD switch closes. Transistors M8 and M9 are now in par-
allel with a composite gate input, which is the average of the output signals positive
output voltage (VOP) and negative output voltage (VOM).

6.7 CHOPPER AMPLIFIER

Traditionally, there are two main approaches to reduce the 1/f noise of an amplifier.
The first method is by increasing the gate area of the input components, which is area
costly and not very effective due to the reason that offset and flicker noise exist at
a low frequency. Another way is to operate the input MOS transistors in the lateral
bipolar mode [3] because the 1/f noise of bipolar junction transistors (BJTs) is lower
than the 1/f noise of MOSFETs as the corner frequency between the intersection of
the 1/f and thermal noise is lower for BJTs. For instance, the corner frequency of a
regular BJT may be in the vicinity of 10 Hz compared to 1000 Hz for the regular
MOS, as stated in [3]. According to Enz [4], the latter approach may provide more
than 40 dB of 1/f noise reduction with an offset comprised between 1 mV and 10 mV.
Recently, there is an increasing demand to achieve lower noise level, which is clari-
fied by the introduction of the chopper implementation technique.
The chopper technique is based on a modulation technique, where it converts the fre-
quency range of an input signal to the higher frequency range of a chopping frequency,
fc, where the dominant noise is white noise. The bandwidth of the amplifier is approxi-
mately ten times larger than the chopping frequency. Thus, in order to chop at high
frequencies, a larger amplifier bandwidth compared to chopping frequency is required
to decrease 1/f noise and to allow the thermal noise to be unchanged. After the amplifi-
cation, demodulation is required to demodulate it back to the baseband. The high-order
low-pass filter is needed to diminish the demodulated noise within a higher frequency
range than the chopper frequency and to achieve a low spurious signal [3,5].
Referring to Figure 6.16, at VB, the undesired signal Vn, VD, which represents
sources of noise or distortion, is added to the spectrum. After the second multiplier,
which refers to the demodulator, the signal is demodulated back to the original one,
and the undesired signal has been modulated. The spectrum of the undesired signal
has been shifted to the odd harmonic frequencies of the chopping square wave.
The spectrum of the vn + vD, Vn + VD(f) has been folded back around the chopping
frequency as shown in Figure 6.16. If the chopper frequency is much higher than the
signal bandwidth, then the amount of undesired signal in the pass-band of the signal
will be greatly reduced. Since the undesired signal will consist of 1/f noise and the
DC offset of the amplifier, the influence of this source of the undesired signal is
mixed out of the desired range of operation.
The modulator and the demodulator have the exact structure seeing that they
have the same role. The common chopper circuit consists of four identical switches
that alternate the polarity each half cycle of the chopper clock, as indicated in
Figure 6.16. The chopper clock that is used is a square wave with a frequency
higher than the signal frequency in which the chopping signals, ɸ1 and ɸ2, are
non-overlapping clocks.
Introduction of Advanced Analog Circuit 153

FIGURE 6.16 Principle of the chopper technique. (Redrawn from Yoshida, T. et al., IEICE
Trans. Electron., E89C, 769–774, 2006.)

6.8 DYNAMIC ELEMENT MATCHING TECHNIQUE

The circuit implement of the dynamic element match is shown in Figure 6.17 [6].
The base–emitter junction area of main transistor, Q1, is 8 A, which uses the parallel
connection of eight uniform transistors with 1 A area and the base–emitter junc-
tion area of Q2 is 1 A. Voltage Vdd is the supply power of the chip and Vbias is the
bias voltage. As PMOS transistors P1–P4 have the same W/L sizes, the proportional-
to-absolute-temperature (PTAT) current equation IPTAT1 = IPTAT2 = IPTAT3 = IPTAT4 is
satisfied. If the chopper amplifier is ideal, then the current that passes the bipolar
transistor is VBE/R and satisfies the equation ∆VBE / R = IPTAT 1. From Figure 6.16, the
following equation can be obtained:

kT  I C 2 AE1  1
I PTAT = ln (6.17)
q  I C1 AE 2  R1

In the figure, for common-base bipolar transistors, the common-base current gain is
approximately the gain of current from emitters to collectors in the forward-active region,
and it can be shown by α = IC/IE. Therefore, Equation 6.17 is further described as:

kT  α 2 I E 2 8  1
I PTAT = ln (6.18)
q  α1I E1 1  R1
154 CMOS Analog and Mixed-Signal Circuit Design

Vdd

IPTAT1 IPTAT2 IPTAT3 IPTAT4

p1 p2 p3 p4

DEM
sp1 sp2 sp3 sp4 sp1 sp4 sp1 sp2 sp4
sp2 sp3 sp4 sp1 sp2 sp3 sp3

p6 p7 p8
p5
Vbias

Chopper VBE
R1 VBE
amplifier
IPTAT3 IPTAT4
Q1 Q2
8A 1A

FIGURE 6.17 Dynamic Element Matching (DEM).

where α1 and α2 are the current gain of transistors Q1 and Q2, and the emitter cur-
rents through transistors Q1 and Q2 are IE1 and IE2, respectively.
As Q1 and Q2 are the same transistors, α1 and α2 are equal. In order to gain
accuracy for the IPTAT current, the ratio of emitter current IE2/IE1 must be accurate.
Dynamic element matching is used to improve the current ratio accuracy. The work
process is shown in Figure 6.17. Four switch signals sp1–sp4 are produced by a
digital logical clock. When the first clock period comes, signal sp1 switches on.
The drain of transistor P1 connects the source of transistor P5. The current IPTAT1
passes the branch of transistor P5 and in the same way, the currents IPTAT2, IPTAT3, and
IPTAT4 flow into the branch of transistors P6–P8, respectively. When different switch
signals are effective, the relationship of conduction connection is shown in Table 6.1.
Using this method, the equation IE2/IE1 = 1 can be accomplished; therefore a current
that is proportional to absolute temperature can be attained.
Introduction of Advanced Analog Circuit 155

TABLE 6.1
Conduction–Connection Relationship During Different Switch Signals
On State Conduction Relationship
sp1 P1 drain–P5 source P2 drain–P6 source P3 drain–P7 source P4 drain–P8 source
sp2 P1 drain–P6 source P2 drain–P5 source P3 drain–P8 source P4 drain–P7 source
sp3 P1 drain–P7 source P2 drain–P8 source P3 drain–P5 source P4 drain–P6 source
sp4 P1 drain–P8 source P2 drain–P7 source P3 drain–P6 source P4 drain–P5 source

6.9 RESISTOR-LESS CURRENT REFERENCE

Figure 6.18 [7] shows the PTAT current generator. The circuit is based on a β multiplier
self-biasing circuit consisting of a switched capacitor instead of an ordinary resistor.
The circuit is operated in the subthreshold region to obtain a PTAT current output.
The switched-capacitor circuit consists of capacitor CS2 and two switches (sw3 and
sw4), driven by an external reference clock with frequency fREF. It operates as a resistor

IPTAT

RSC M2 M1

sw3
clk

sw4
fREF CS2
clk

FIGURE 6.18 Resistor-less current reference.

156 CMOS Analog and Mixed-Signal Circuit Design

with average resistance RSC, which is equal to (CS2 · fREF)−1 between the source node
of transistor M2 and the ground. Therefore, adjusting an external reference clock with
frequency fREF, the resistance of the switched-capacitor resistor RSC can be enlarged.
Consequently, the circuit is operated with an ultra-low current, several hundred nano-
amperes or less, and the transistors M1 and M2 are operated in the subthreshold region.
In the circuit in Figure 6.18, gate-source voltage VGS1 in M1 is equal to the sum of
gate-source voltage VGS2 in M2 and the voltage drop (IPTAT · RSC ) across the switched-
capacitor resistor. The currents in M1 and M2 are equal, so the output current IPTAT of
the PTAT current generator is given by:

ηVT  K 2  η kT  K 2 
I PTAT = ln = f REF CS 2 ln  (6.19)
RSC  K1  q 
 K1 

where K is the aspect ratio (= W/L) of the transistor, V T is the thermal voltage, and η
is the subthreshold slope factor [8].

6.10 SWITCH MODE CONVERTER

A control circuit is part of a light-emitting diode (LED) driver design to control the
LED voltage and current. The standard control circuit includes an input coupled to
receive a DC supply voltage, a pulse width modulator, and a feedback circuit input
operable to indicate the LED current.
As shown in Figure 6.19, the on-chip design is a control circuit block diagram.
The control circuit consists of the error amplifier, pulse width modulator, an oscilla-
tor to generate clock and ramp signal, voltage comparator and SR latch, transistors
for output stages, and low dropout linear regulator with the bandgap.
A pulse width modulator is used to realize the feedback control. The pulse width
modulator is operable to control the pulse width of the modulation (PWM) applied
to the buck converter circuit that controls the LED voltage depending upon the LED
current as it is detected by the feedback signal. In achieving high-power efficiency
and constant current, the PWM technique is often employed in the LED driver.
PWM is a technique in which a series of digital pulses is used to control an analog
circuit. The length and frequency of these pulses determine the total power delivered
to the circuit. PWM signals are most commonly used to control DC motors, but have
many other applications including controlling the brightness of an LED. The PWM
strategy switches modes between PWM and pulse frequency modulation to reduce
the working frequency and improve the power efficiency simultaneously when the
load is changing. The control technique of PWM can achieve a constant output cur-
rent and high-power efficiency, while reducing the complexity and cost.
The current-sense resistor provides feedback to the control circuit. It is used to mea-
sure the current flowing in the LEDs. It should be large enough to generate a reasonable
feedback voltage, VF, but it should also be small enough to limit its power dissipation.
Multiple LEDs should be connected in a series configuration to keep an identical cur-
rent flowing in each LED. Driving LEDs in parallel requires a ballast resistor in each
LED string, which leads to lower efficiency and uneven current matching.
Introduction of Advanced Analog Circuit 157

Vin (5V)

VREF (1.0 V)
Bandgap

Voltage PMOS1
VC
Level Converter 5V
VH
1.7 V
VL
LDO
VSL
PMOS2
Vin – 3.3 V VDD33
VLX
3.3 V Off Chip

0V
Vout (1.8 V)
Overlap
NMOS1 Lo
VDD33
R1
VFB +
Co VEA
3.3 V EA
R2 -
0V NMOS2

VREF (1.0 V)

-
QP QN R CMP
+ VH CP1
Dead-time Q Vramp OSC
S VL RP1
Vclk
Output Stage Pulse-Width Modulator

Off Chip

FIGURE 6.19 Switchmode converter. (Redrawn from Wang, C.C. et al., Microelectron. J.,
42, 1–9, 2011.)

The low dropout linear regulator is a voltage source to supply to the internal
circuitry and the generated reference voltage from the bandgap [3]. This internally
generated reference voltage, VREF, is compared with a feedback voltage, VFB, which
is the output voltage, Vout, divided by R1 and R2. A feedback circuit regulates the
switching in the switching output. The feedback circuit cancels out any errors in
the feedback voltage due to component or timing tolerance, and it adjusts the duty
cycle to compensate for changes in the load current. The result is a self-regulating
step-down buck converter that produces a stable LED voltage over constant currents.
A faster speed of the feedback loop comes along with a more stable load voltage.
The resulting current flow through the LEDs is a DC signal [9].
The error amplifier is used to amplify the difference between VREF and VFB.
The output of the error amplifier, VEA, is compared with Vramp to generate a PWM
control digital signal, Q. Typically, a high-frequency signal will be coupled with
the output voltage in a switched-mode power supply design. The low frequency
gain should be considered in this design with the filtered unwanted high-frequency
signals. Amplifiers with the higher bandwidth will amplify the unwanted control sig-
nal in the high-frequency range to cause the system loop to be unstable. Therefore,
1 MHz bandwidth is more than enough to cope with the switching frequency of the
switched-mode power supply design [10].
158 CMOS Analog and Mixed-Signal Circuit Design

Two non-overlapping signals, QP and QN, are generated from the dead-time
circuit. The voltage level converter [11] shifts the voltage level of QP and sends a
Control Voltage (VC) to be the gate drive of the power transistor (PMOS1).
The switching frequency is dependent on the input voltage and load current.
A higher switching frequency lowers the efficiency due to the increased switching
losses [12]. Input current magnitude can be controlled by the switching frequency.
This can be utilized for controlling the output voltage with the switching frequency.
It should be noted that the increasing switching frequency reduces output voltage and
vice versa [13]. The increase of switching frequency also increases the energy asso-
ciated with capacitive-coupled displacement, but high-frequency switching results
in smaller off-chip reactive components, which can be used, leading to more savings
on the bill-of-material. The bill-of-material can be even further reduced if off-chip
reactive components are eventually integrated. The resistive losses dominate at a low
frequency, while capacitive losses are dominant at high switching frequencies [14].

6.11 SPICE EXAMPLE

See Figure 6.20 for the basic depiction of the S/H circuit. Figure 6.21 shows the
result. Figure 6.22 shows the S/H suitable for the data converter, while Figure 6.23
shows the result. Figure 6.24 shows the single-ended version. Figure 6.25 shows

FIGURE 6.20 Basic S/H simulation circuit.

Introduction of Advanced Analog Circuit 159

V (vinsp)
1.0

0.5

0.0

0.8 V (opm)

0.6
0.4
0.2

0.8 V (opp)

0.6
V (V)

0.4
0.2

0.8 V (vinp)

0.6
0.4
0.2

0.8 V (vinm)

0.6
0.4
0.2
0.0 2.0x10-7 4.0x10-7
Time (s)

FIGURE 6.21 Basic S/H amplifier simulation result.

FIGURE 6.22 S/H suitable for data converter.

160 CMOS Analog and Mixed-Signal Circuit Design

V (outp) - V (voutm)
1

-1

V (vinsm)
V (vinsp)
1.0 V (outm)
0.8 V (outp)
0.6
0.4
0.2
0.0
V (V)

V (vopp)
1.0

0.5

0.0

V (vopm)
1.0

0.5

0.0
0.0 2.0x10-7 4.0x10-7
Time (s)

FIGURE 6.23 S/H suitable for data converter simulation result.

FIGURE 6.24 Single-ended version of S/H buffer.

Introduction of Advanced Analog Circuit 161

V (vinsp)
1.0

0.5

0.0

0.8 V (vopm)

0.6
0.4
0.2

0.8 V (opp)

0.6
V (V)

0.4
0.2

0.8 V (vinp)

0.6
0.4
0.2

0.8 V (vinm)

0.6
0.4
0.2
0.0 2.0x10-7 4.0x10-7
Time (s)

FIGURE 6.25 Single-ended version of S/H buffer simulation result.

the result. The simulation schematic uses the ideal opamp shown in Figure 6.26,
as the ideal opamp uses a voltage-dependent current source for better convergence.
The output voltage of the single-ended output is:

VOUT = 100 Meg ⋅VIN ⋅ R1. (6.20)

FIGURE 6.26 Ideal opamp.

162 CMOS Analog and Mixed-Signal Circuit Design

The ratio of the output voltage to the input voltage, gain, is therefore 100 Meg,
when R1 is 1 Ω. Figure 6.27 shows another S/H amplifier, but now with an opamp
(Chapter 3). Figure 6.28 shows the simulation result. Figure 6.29 shows the basic
residue amplifier for the Analog-to-Digital Converter (ADC). The simulation result
is shown in Figure 6.30.

FIGURE 6.27 S/H amplifier with an opamp.

Introduction of Advanced Analog Circuit 163

0.8 V (voutp)

V (vinsp)

0.6
V (V)

0.4

V (voutm)

V (vinsm)
0.2

0.0
0.0 1.0x10-6 2.0x10-6 3.0x10-6
Time (s)

FIGURE 6.28 S/H amplifier with an opamp simulation result.

FIGURE 6.29 Residue amplifier for ADC.

164 CMOS Analog and Mixed-Signal Circuit Design

1st run
0.5

0.0

-0.5

2nd run
0.5

0.0

-0.5
V(voutp)-V(voutm) (V)

3rd run
0.5

0.0

-0.5

4th run
0.5

0.0

-0.5

5th run
0.5

0.0

-0.5
0.0 1.0x10-6 2.0x10-6
Time (s)

FIGURE 6.30 Residue amplifier for ADC simulation result.

6.12 LAYOUT ISSUE

Capacitor mismatch and switch layout are important for the dynamic analog layout.
Routing parasitic capacitance and resistance should be reduced or eliminated.

6.13 SUMMARY
Resistor-less reference circuitry and Dynamic Element Matching (DEM) circuitry are
normally applicable for new applications or research. The standard S/H amplifier is a
typical practical amplifier for data converters. The chopper amplifier is widely popular
in low frequency application. It can also be applied for new circuitry or research.

REFERENCES
1. Baker, R. J. (2010). CMOS: Circuit Design, Layout, and Simulation (3rd ed.). Wiley-
IEEE Press. doi:10.1002/9780470891179.
2. Gray, P. R., Hurst, P. J., Lewis, S. H., and Meyer, R. (2010). Analysis and Design of
Analog Integrated Circuits, 5th ed. New York: Wiley, pp. 811–821.
3. Allen, P. E., and Holberg, D. R. (2002). CMOS Analog Circuit Design, 2nd ed.
New York: Oxford University Press.
Introduction of Advanced Analog Circuit 165

4. Enz, C. C., Vittoz, E. A., and Krummenacher, F. (1987). A CMOS chopper amplifier.
IEEE Journal of Solid-State Circuits, 22, 335–342.
5. Yoshida, T., Masui, Y., Mashimo, T., Sasaki, M., and Iwata, A. (2006). A 1V low-
noise CMOS amplifier using autozeroing and chopper stabilization technique. IEICE
Transactions on Electronics, E89C, 769–774.
6. Jiang, L., Xu, W., and Yu, Y. (2010). Accurate operation of a CMOS integrated tempera-
ture sensor. Microelectronics Journal, 41(12), 897–905.
7. Ueno, K., Asai, T., and Amemiya, Y. (2011). Low-power temperature-to-frequency con-
verter consisting of subthreshold CMOS circuits for integrated smart temperature sen-
sors. Sensors and Actuators A: Physical, 165(1), 132–137.
8. Wang, A., Calhoun, B. H., and Chandrakasan, A. P. (2006). Sub-threshold Design for
Ultra Low-Power Systems. New York: Springer.
9. Wang, C. C., Chen, C. L., Sung, G. N., and Wang, C. L. (2011). A high efficiency DC-DC
buck converter for sub 2xVDD power supply. Microelectronics Journal, 42, 1–9.
10. Luo, F., and Ma, D. (2010). Design of digital tri-mode adaptive-output buck-boost power
converter for power-efficient integrated systems. IEEE Transactions on Industrial
Electronics, 57(6), 2151–2160.
11. Da Rocha, J. F., Dos Santos, M. B., Dores Costa, J. M., and Lima, F. A. (2008). Level
shifters and DCVSL for a low-voltage CMOS 4.2-V buck converter. IEEE Transactions
on Industrial Electronics, 55(9), 3315–3323.
12. Hogue, M. R., Ahmad, T., McNutt, T. R., Mantooth, H. A., and Mojarradi, M. M.
(2006). A technique to increase the efficiency of high voltage charge pumps. IEEE
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13. Liu Xin, Guo Shu-xu, Chang Yu-chun, Zhu Shun-dong, Wang Shuai. (2009). Simple digi-
tal PWM and PSM controlled DC-DC boost converter for luminance-regulated WLED
driver. The Journal of China Universities of Posts and Telecommunications, 16, 98–102.
14. Emira, A., Carr, F., Elwan, H., and Mekky. R. H. (2009). High voltage tolerant inte-
grated Buck converter in 65 nm 2.5 V CMOS. Proceeding of IEEE International
Symposium on Circuits and Systems (pp. 2405–2408).
 7 Data Converter

7.1 INTRODUCTION
A digital-to-analog converter (DAC) and analog-to-digital converter (ADC) can be
described as a mixed-signal integrated circuit.
Resolution is a term used to describe a minimum voltage or current that an ADC/
DAC can resolve. The fundamental limit is a quantization noise due to the finite
number of bits used in the ADC/DAC. In an N-bit ADC, the minimum incremental
input voltage of Vref /2N can be resolved with a full-scale input range of Vref. That
is, limited 2N digital codes are available to represent the continuous analog input.
Similarly, in an N-bit DAC, 2N input digital codes can generate distinct output levels
separated by Vref /2N with a full-scale output range of Vref . An alternative definition of
the resolution is the effective number of bits (ENOB), which is defined by:

 SNDR − 1.76 
ENOB =   bits (7.1)
 6.02 

where SNDR is signal to noise and distortion ratio.

The input/output ranges of an ideal N-bit ADC/DAC are equally divided into 2N
small units, and one least significant bit (LSB) in the digital code corresponds to the
analog incremental voltage of Vref /2N.
Static ADC/DAC performance is characterized by differential non-linearity
(DNL) and integral nonlinearity (INL). The DNL is a measure of the deviation of
the actual ADC/DAC step from the ideal step for one LSB, and the INL is a measure
of the deviation of the ADC/DAC output from the ideal straight line drawn between
two end points of the transfer characteristic. Both DNL and INL are measured in
the unit of an LSB. In practice, the largest positive and negative numbers are usually
quoted to specify the static performance.
In both the ADC and the DAC, the output should increase over its full range as
the input increases. That is, the negative DNL should be smaller than one LSB for
any ADC/DAC to be monotonic. Monotonicity is critical in most applications, in
particular, digital control or video applications. The source of non-monotonicity is
an inaccuracy in the binary weighting of a DAC.
For example, the most significant bit (MSB) has a weight of half the full range.
If the MSB weight is not accurate, the full range is divided into two non-ideal half
ranges, and a major error occurs at the midpoint of the full scale. The similar non-
monotonicity can take place at the quarter and one-eighth points. In DACs, monoto-
nicity is inherently guaranteed if a DAC uses thermometer decoding. However, it is
impractical to implement high-resolution DACs using thermometer codes since the
number of elements grows exponentially as the number of bits increases.
Therefore, to guarantee monotonicity in practical applications, DACs have been
implemented using a segmented DAC approach.
167
168 CMOS Analog and Mixed-Signal Circuit Design

The other important parameters are of course speed and power consumption.
These issues are presented in later sections.

7.2 DIGITAL-TO-ANALOG CONVERTER

7.2.1 Resistor String Topology
This large resistor ratio problem is alleviated by using a resistor divider known as an
R–2R ladder, as shown in Figure 7.1. The R–2R network consists of series resistors of
value R and shunt resistors of value 2R. The top of each shunt resistor of value 2R has
a single-pole double-throw electronic switch that connects the resistor either to the
ground or to the supply voltage. As the topology is binary, a decoder is not required
to control the switches.
Figure 7.1 is a voltage-mode (5-bit) without an opamp; resistor string. The load is
represented by the CL and R L.

VDD

2R
VOUT

b4
CL RL
R

2R

b3
R

2R

b2
R
2R
b1

2R

b0
2R

FIGURE 7.1 Voltage-mode (5-bit) without an op-amp.

Data Converter 169

VDD
VDD
This simplified to

Bias

b RLL RRL

RLL RRL

Current-source-based cell.

FIGURE 7.2 Current steering.

7.2.2 Current Steering

Regarding the DAC structure, the current-steering solution has been preferred to
the R–2R DAC since it avoids the use of input and output reference voltage buf-
fers, which would increase power consumption. The current steering with current-
source based is useful as the value of the current can be adjusted via a bias voltage
(See Figure 7.2).

7.2.3 Hybrid Topology
DACs are used to provide an interface between the digital data sequence and the
analog signal. Many conventional DAC architectures had been developed to con-
vert a digital data sequence in binary to an analog signal in terms of current or
voltage, including weighted current-steering DAC, binary-weighted resistor DAC,
and thermometer coding DAC. Each of the conventional DAC architecture has its
pros and cons. Therefore, each of the conventional DAC has different limitations
in static and dynamic performance, including linearity, monotonicity, and glitch
energy.
The hybrid DAC architecture is developed in order to achieve most of the advan-
tages and the least of the disadvantages from the conventional DAC architectures.
The switchable current source [1] is made of three P-type metal-oxide semicon-
ductor (PMOS) transistors, and its interconnection is shown in Figure 7.3. With the
lower mobility of holes as compared to that of electrons, the PMOS transistor pro-
vides a lower 1/f-noise, but a higher thermal noise level than the N-type metal-oxide
semiconductor (NMOS) transistor.
170 CMOS Analog and Mixed-Signal Circuit Design

Switchable AVDD
Current Source

VBIAS1 M1
1x
From Bias
Voltage
Generator
VBIAS2 M2
. provide a constant
current I = 20 µA
1x

DVS(2) M3 20µA
1x

AGND IOUT

Switchable Current Source

FIGURE 7.3 Switchable current source. (Redrawn from Ab-Aziz, M.T.S. et al., J. Circ.
Syst. Comput., 20, 709–716, 2011.)

The binary-weighted resistor string is used in the LSB segment of the hybrid
DAC. The value of each resistor is proportional to the weighted digital input bit
value. Figure 7.4 shows an example of a 3-bit LSB structure. When the input is a “0”
or a low logic level, the switchable current source switched ON and a constant cur-
rent with magnitude I flows through the resistor string. Since the value of resistors
increases exponentially as the digital input bit increases, the outputs can be calcu-
lated by using the superposition theorem.
The simplified 3-bit mathematical model is:

( )
Vout = 22 D [ 2] + 21 D [1] + 20 D [ 0 ] ( I × R ) (7.2)

Equation 7.2 above, the mathematical model for 8-bit is:

(
Vout = 27 D [ 7] + 26 D [6] + 25 D [5] + 24 D [ 4 ] + 23 D [3] + 22 D [ 2]
(7.3)
+ 21 D [1] + 20 D [ 0 ] ) ( I × R)
where I is a constant current source, R is the least significant bit resistor, and D is
the input bit, which is “1” for a high level and “0” for a low level. The equivalent
resistance used for the 8-bit binary-weighted resistor for the LSB segment of DAC is:

Req = R + R + 2 R + 4 R + 8 R + 16 R + 32 R + 64 R = 128 R (7.4)

Data Converter 171

For input : DVS [2;0] = 111

Vout = 7 (i x R ) = 7 LSB

DVS(2) i
2R i x 2R

DVS(1) i
R 2i x R

+
DVS(0) i
R 3i x R

AGND

1 LSB – i x R

Simplified 3-bits Binary Weighted Resistor

FIGURE 7.4 3-bit DAC.

Figure 7.5 shows a thermometer coding approach is used in the top or MSB seg-
ment of the hybrid DAC. The thermometer coding is using a 4-to-16 priority coding
scheme, which is converting N-bit of digital input to 2N − 1 number of bits in ther-
mometer code. This results in the conversion of 4-bit MSB digital input to a 15-bit
thermometer code, as shown in Table 7.1. Each of the bits in thermometer code is
connected directly to two switchable current sources. When the bit in thermometer
code is “1” or high logic level, it will turn ON the switchable current sources and the
sum of the currents will flow to the weighted resistor string. The total output cor-
responding to the 4 MSB segment is:

(
Vout = D [11] (16 I × 128R ) + D [10 ] ( 8I × 128R ) + D [9] ( 4 I × 128R )
(7.5)
+ D [8] ( 2II × 128R ) )
or

( )
Vout = 211 D 11 + 210 D 10  + 29 D  9  + 28 D 8 ( I × R ) (7.6)
172 CMOS Analog and Mixed-Signal Circuit Design

VDD 16x Vout

DVS(11)
8x

DVS(10)
4x

DVS(9)
2x
DVS(8)

DVS(7)
64R

DVS(6) 32R

DVS(5) 16R

DVS(4) 8R

DVS(3)
4R

DVS(2)
2R

DVS(1) R

Thermometer
Coding DVS(0)
R
Binary-Weighted
Resistor

GND

FIGURE 7.5 Hybrid DAC.

Data Converter 173

TABLE 7.1
Thermometer Coding for the 4 MSB Segment
D[11] D[10] D[9] D[8] Thermometer Coding
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0
0 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

The completed model of the analog output voltage for the l2-bit hybrid DAC archi-
tecture from Equations 7.3 and 7.6 is:

 211 D [11] + 210 D [10 ] + 29 D [9] + 28 D [8] + 

 
Vout =  2 7 D [ 7 ] + 26 D [ 6 ] + 25 D [ 5 ] + 2 4 D [ 4 ] +  ( I × R ) (7.7)
 
 23 D [3] + 22 D [ 2] + 21 D [1] + 20 D [ 0 ] 
 

7.2.4 DAC Trimming or Calibration

The opamp in a basic opamp based R -2R DAC has an offset voltage which could
shift the DAC’s output.
Figure 7.6 shows a trimming circuit for DAC offset. It modifies the common volt-
age for the op-amp.
Figure 7.7 shows how INL can be seen as an offset error.
174 CMOS Analog and Mixed-Signal Circuit Design

VDD

VDD = VREF+
R

2R Rbig
To op-amp
+ input
b4
R
R

Adjustable
2R voltage

b3
R

2R
Selected large so it doesn’t
b2 load the R-2R ladder and
R so we get a large
2R attenuation to the output

b1

2R

b0
2R

Voltage-mode R-2R DAC

FIGURE 7.6 Trimming DAC offset.

VOUT VOUT

INL error

Ideal curve

(a) Digital input code Digital input code

(b)

FIGURE 7.7 Showing how INL can be seen as an offset error: (a) DAC transfer curves
before calibration and (b) DAC transfer curves after offset calibration.
Data Converter 175

VOUT
VOUT

Ideal gain (slope)

Actual gain

INL

(a) Digital input code

Digital input code

(b)

FIGURE 7.8 Showing gain error and how it can cause problems in an offset calibration: (a)
DAC transfer curves with gain error and (b) DAC transfer curves after offset calibration with
gain error.

Figure 7.8 shows the gain error and how it can cause problems in an offset
calibration.
Obviously, a serious study should be conducted in order to determine the method
of calibration or trimming for a DAC.

7.2.5 Glitch
Among the factors that contribute to the glitch phenomenon are matching errors
in switches and driver circuits, or time skew between switching signals, voltage-
dependent complementary metal-oxide semiconductor (CMOS) switches, etc. For a
short period of time, a false code could appear at the output. For example, for 3-bits
binary code DAC, when the digital input changes from 011 to 100, if the MSB switch
is turned on earlier than the other switches, the intermediate state 111 will appear
during the process of the transformation of the switch signals and at the output ter-
minal a glitch will appear [2].
Glitches can be characterized by measuring the glitch impulse area, some-
times called glitch energy. The term glitch energy is a misnomer, since the unit for
glitch impulse area is volt-seconds (or more probably µV-seconds or pV-seconds).
The peak glitch area is the area of the largest of the positive or negative glitch
areas. The glitch impulse area is the net area under the voltage-versus-time curve
and can be estimated by approximating the waveforms by triangles, computing
the areas, and subtracting the negative area from the positive area, as shown in
Figure 7.9 [3].

Peak glitch impulse area : A1 = (V1 × t1 ) / 2  (7.8)

Net glitch impulse area: A1 − A2 = (V1 × t1 ) / 2  − (V2 × t2 ) / 2  (7.9)

176 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 7.9 Calculating glitch impulse area. (Redrawn from Zumbahlen, H., Linear
Circuit Design Handbook, Analog Devices-Newnes, Boston, MA, 2008.)

7.3 ANALOG-TO-DIGITAL CONVERTER

7.3.1 Slope ADC
Dual-slope ADC has greater noise immunity than the other type ADCs. However, a
single-slope ADC is sensitive to the switching error. A single-slope ADC approach
was used in the backside illumination (BSI) application due to its small area [4].
Another example of a single-slope ADC is in work [5]. This concept is shown in
Figure 7.10. The figure illustrates the per-pixel single-slope ADC conversion tech-
nique used in the chip. The globally distributed voltage ramp is connected to each

FIGURE 7.10 Single-slope ADC topology.

Data Converter 177

pixel’s comparator inverting (“−”) input. The non-inverting (“+”) input on each com-
parator is directly connected to the sense node. The globally distributed gray-coded
counter values, shown as a stepped “digital ramp,” are simultaneously applied to
the per-pixel memory bit lines. At the beginning of the conversion, the ramp volt-
age is lowered to just below the lowest expected sense node voltage, which sets the
comparator output to high. This enables the per-pixel memory to begin loading the
gray code values. The ramp is then swept linearly until it exceeds the reset voltage.
Simultaneously, the gray code counter sweeps across an equivalent set of values
(256 for 8 bits). As the ramp crosses each pixel’s sense node voltage, its comparator
output switches low, and the gray code value present at that moment is latched in the
pixel’s memory. At the end of the conversion, each pixel’s memory contains an 8-bit
gray-coded value that is a digital representation of its input voltage. Although using
a linear ramp is the typical approach, it is possible to use alternative ramp profiles,
such as piecewise linear or exponential curves that compress or expand different
illumination ranges. It is also possible to change the gain of the ADC conversion by
changing the voltage range of the analog ramp. One may also use alternate sequences
for the digital inputs using the auxiliary inputs.

7.3.2 SAR ADC

This is a popular ADC type for column-level ADCs [6], also for chip-level ADCs [7].
A 3-bit Successive Approximation Register (SAR) ADC has been developed for
pixel-level ADCs [8]. The conversion always starts with the MSB decision [9].
The technique is shown in Figure 7.11. An algorithm is also depicted. The SAR
algorithm is important (to control DAC output with progressively dividing the range
by 2). The sampled input is compared with the DAC output by progressively dividing
the range by 2, as explained in the 4-bit example. The conversion starts by sampling
input, and the first MSB decision is made by comparing the sample-and-hold (S/H)
output with Vref /2 by setting the MSB of the DAC to 1. If the input is higher, the
MSB stays as 1. Otherwise, it is reset to 0. In the second bit decision, the input is
compared with 3Vref /4 in this example by setting the second bit to 1. Note that the
previous decision set the MSB to 1. If the input is lower, as in the example shown,

FIGURE 7.11 SAR ADC technique.

178 CMOS Analog and Mixed-Signal Circuit Design

the second bit is set to 0, and the third bit decision is made by comparing the input
with 5Vref /8. This comparison continues until all the bits are decided. Therefore, the
N-bit successive-approximation ADC requires N + 1 clock cycles to complete one
sample conversion.

7.3.3 Flash ADC

This is the most straightforward way of making an ADC. Another improvement of
the flash ADC is the folding ADC. Flash ADC probably loses importance in the
CMOS image sensor since it is limited to 8- or 10-bit [10]. However, this ADC topol-
ogy is suitable for chip-level ADC. The ADC technique is shown in Figure 7.12.
From the figure, divided reference voltages are compared to the input. The binary
encoder is needed because the output of the comparator bank is thermometer-coded.
The resolution is limited both by the accuracy of the divided reference voltages and
by the comparator resolution. In practical implementations, the limit is the expo-
nential growth in the number of comparators and resistors. For example, an N-bit
flash needs 2N – 1 comparators and 2N resistors. Furthermore, for the Nyquist-rate
sampling, the input needs an S/H to freeze the input for comparison. As the number

FIGURE 7.12 Flash ADC technique.

Data Converter 179

of bits grows, the comparator bank presents a significant loading to the input S/H,
diminishing the speed advantage of this architecture. Also, the control of the refer-
ence divider accuracy and the comparator resolution degrades, and the power con-
sumption becomes prohibitively high.

7.3.4 Pipelined ADC
Each bit in a general 1-bit-per-stage-pipelined A/D converter is achieved using the
same algorithm. So, to get an arbitrary number of bits, a number of algorithmic
stages can be cascaded to create an arbitrary number of bits—up to the accuracy of
the circuits and silicon processing, which is usually around 10 bits.
The input range of such a converter can be defined as −VREF to +VREF, where |VREF|
is the reference voltage.
The way a single-bit stage in a pipeline converter works, in the simplest form,
is to compare the input voltage to zero volts. If the input voltage is greater than
zero, then the bit for that stage is a “1,” otherwise, the bit is a “0.” At the same
time, the input voltage is multiplied by 2. If the bit decision had been a “1,” then
a value equal to the reference voltage is subtracted from the multiplication result,
otherwise, if the bit decision had been a “0,” a value equal to the reference voltage
is added to the multiplication result. The analog result from a bit stage is called
the residue and is passed onto the next bit stage. Figure 7.13 shows an example of

FIGURE 7.13 Pipelined algorithm.

180 CMOS Analog and Mixed-Signal Circuit Design

a 1-bit-per-stage pipeline converting 5-bits. Note that the last stage does not need a
residue amplifier in order to make a decision for the last bit. All that is required is a
comparator. Checking the algorithm illustrated by Figure 7.13, we get for the input
voltage ratio, ( 0.3VREF + VREF ) / VREF = 0.65, while for the output digital word ratio,
10100/25=0.625, so the error in LSB is (0.625 – 0.650)/25 = −0.8 LSB.
The explained pipeline algorithm is simple and can be expanded to any number
of bits, however, the comparator used in each stage must be as accurate as the bit
resolution. One way to reduce the accuracy requirement of the comparators is to add
redundancy to the system. A common way to do this is to use an extra comparator
at each stage and make two comparisons around zero rather than one comparison at
zero. This allows each comparator to exhibit large errors, but still allows the overall
pipeline to arrive at the correct analog-to-digital conversion. This is done by tak-
ing the extra information provided by two comparators at each stage and applying
the digital error correction. Using the digital error correction, nominal comparator
decision points are placed at ±¼VREF , as shown in Figure 7.14. Since the comparator
error bands cannot overlap, a comparator error of up to ±¼VREF can be tolerated,
greatly reducing the accuracy requirement of the comparators. Looking intuitively
at the information from the comparators, when neither comparator output is true, the
bit is definitely a zero.
When both comparator outputs are true, the bit is definitely a one. When one com-
parator is true and the other is not true, the input lies somewhere between ±½VREF,
and a bit decision cannot reliably be made. This is because the input signal might
have been above or below zero. To deal with this uncertainty, a bit value of 0.5 is
assigned for input values that lie in the range ±½VREF . Additionally for this case, the
value of VREF is neither added nor subtracted from the multiply-by-2 result. The add
or subtract step can be avoided because, since the input initially lies in the range
±½VREF, the multiply-by-2 step will yield an output that is still within the allowable
±VREF output range of the residue amplifier. In fact, the add or subtract step should be
avoided because no bit decision has yet been made and adding or subtracting a value
of VREF could push output value outside the ±VREF range of the residue amplifier.
Taking again the example of Figure 7.13, except this time with the error correction
algorithm:

FIGURE 7.14 Comparator decision points.

Data Converter 181

FIGURE 7.15 Algorithm with error correction.

As seen in Figure 7.15, the input signal of stage 3 happens to fall between the
comparison levels of ±¼VREF, and an output value of 0.5 was assigned. Also, in
stage 3, a multiply-by-2 was performed, but no addition or subtraction of VREF was
performed. The last stage of the pipeline again has a decision level at exactly zero
in order to properly resolve the least significant bit. Again, this last comparison at
zero needs only to have a resolution of ±¼VREF because any input signal within that
resolution about the zero point will result in a quantization error of at most ±½LSB.
Since each stage has an effective resolution of one and a half bits, there are three
valid digital output levels before the digital error correction:

00: definitely a 0
01: uncertainty around a 0
11: definitely a 1

The digital error correction algorithm applied to the resulting bits is termed “bit-­
overlap correction” because the results from all the stages are simply summed
together by overlapping bits from adjacent stages, as shown in Figure 7.16. Comparing
the final output word of the general pipeline algorithm with that of the pipelined
algorithm with the digital error correction, they are identical.
This ADC topology, as shown in Figure 7.17, is suitable for chip-level ADC [11].
The 1.5-bit stage is normally used in designing pipelined ADCs [12], thus requires
182 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 7.16 Corrected output.

FIGURE 7.17 Pipelined ADC.

only trilevel DACs [9]; this is described in Figure 7.18. Each stage is responsible for
resolving two bits from the digital output code. Each stage is composed of a coarse
flash-ADC, a low-resolution DAC, an S/H circuit, and a residue amplifier. The 2-bit
MSB low-resolution ADC determines the two MSBs. This is the first stage. The
determination of the remaining LSBs is performed in the following steps: (1) The
quantization error is found by reconverting the 2-bit digital to an analog value using
the 2-bit DAC. (2) This value is subtracted from the input signal, generating a resi-
due. This residue is then amplified by a gain of two and passed onto the next stage.
The second stage performs similar operations on the amplified residue, resulting
in a determination of the next most significant bits of the input signal. The stages
Data Converter 183

1.5 bits Flash ADC

VIN VOUT
2X

A if : < -¼ VREF
+
+¼ VREF B if :
- B
Coding 3 A C < -¼ VREF > VIN > +¼ VREF
Logic C if : VIN > +¼ VREF
+
-¼ VREF
- +½ VREF 0 -½ VREF
2
Residue Amplifier
1.5 bits to digital error correction

FIGURE 7.18 1.5-bit stage.

are buffered by switching-capacitors gain blocks that provide an S/H between each
stage, allowing concurrent processing. The digital error correction [13,14] is used to
generate the final correct output code. The use of a digital error correction technique
in conjunction with a low number of bits per stage relaxes the constraints on the
comparator offset voltage.
The pipelined-ADC stage consists of: (1) two comparators with corresponding
threshold voltages Vref /4 and −Vref /4, which, in fact, assemble the coarse flash-ADC,
(2) an analog MUX that actually functions as a DAC, with the three corresponding
reference voltages −Vref, 0, and Vref, and (3) residue gain stage [15,16]. The residue-
gain stage samples the signal input, subtracts it from the relevant reference voltage,
and amplifies the residue by the gain of two. Figure 7.19 shows another circuit of
coarse ADC and DAC for the 1.5-bit stage. MUX is used as the DAC, where the
output of the MUX is either 0, VCM, or 2VCM. This output is connected to the residue
amplifier common mode input. Figure 7.20 shows the transfer curve of the circuit in
Figure 7.19 with a residue amplifier. Figures 7.21 and 7.22 show the complete resi-
due amplifier. The subtraction or addition is done with the VCI inputs to the circuit,
as shown in Figure 7.21. The equation that ideally relates to Vout to Vin in terms of VCI
is given by:

Vout = 2 ( Vin + − Vin − ) − ( VCI + − VCI − ) (7.10)

Further improvement to pipelined-ADC is algorithmic, cyclic, or recursive ADC.

7.3.5 Delta Sigma ADC

Oversampled ADCs have the advantage of filtering temporal noise [17]. The idea
is similar to the synchronous analog voltage to frequency converter. This ADC has
been employed at pixel [18] level and column level [19]. The basic idea of the ADC
is shown in Figure 7.23.
184 CMOS Analog and Mixed-Signal Circuit Design

+ (a) To bottom plate of ( )

+
3 - Out
2 2 ab addr Mux

+ 00 01 11

-
0 2VCM= VDD
2 VCM
VCI+
Vin-
-
Mux
(b) + ab
2 00 01 11

3 0 VCM 2VCM
- ab 11 01 00
4
Vin+ Mux
+

VCI-

FIGURE 7.19 Implementing coarse ADC and DAC for 1.5 bits : (a) Single-ended input and
output and (b) double-ended input.

FIGURE 7.20 Transfer curves for using 1.5-bits per clock cycle: (a) single-ended input and
output and (b) double-ended input and output.
Data Converter 185

Φh
Φa
Φa Φh Φ s
C+ Φs

C+ +∆C+
VCI+ Vin+ - + Vout+

VCI- + - Vout-
Vin- C- +∆C-

C- Φs
Φa
Φh
valid

Sample Sample
Φs

Φa Amplify
Φh
Hold
(average)

valid

FIGURE 7.21 Residue amplifier 1. (Redrawn from Baker, R.J., CMOS: Circuit Design,
Layout, and Simulation, 3rd ed., Wiley-IEEE Press, 2010.)

FIGURE 7.22 Residue amplifier 2. (Redrawn from Baker, R.J., CMOS: Circuit Design,
Layout, and Simulation, 3rd ed., Wiley-IEEE Press, 2010.)
186 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 7.23 Delta sigma ADC.

TABLE 7.2
ADC-Type Performances
Topology Latency Speed Accuracy Area
Flash Low High Low High
SAR Low Low–medium Medium–high Low
Delta-sigma High Low High Medium
Pipeline High Medium–high Medium–high Medium
Slope Low Low High Low

In summary, the column-level ADC topology is a popular choice for the CMOS
image sensor due to good trade-off between readout speed, silicon area, and power
consumption [20].
Table 7.2 shows the ADC-type performances.

7.4 SPICE EXAMPLE

7.4.1 DAC Example
The DAC without opamp is shown in Figure 7.1. While the DAC with opamp is
shown in Figure 7.24, but there is an offset problem, as can be seen in Figure 7.25.
Figure 7.26 shows the hybrid DAC simulation schematic. The result of the hybrid
DAC simulation is in Figure 7.27.

7.4.2 ADC Example
Figure 7.28 shows the 1.5-bit stage simulation schematic. The results are shown in
Figure 7.29.
Data Converter 187

VREF+
R = RF

VDD
0 2R
MSB _
1 VOUT
bN-1
+
R

2R

bN-2

0 VREF+
2R Detail
1
bN-3
To resistor
0 bN-2
2R
1
b1

R VREF-

0 2R
LSB
1
b0
2R

VREF-

FIGURE 7.24 Wide-swing current-mode R-2R DAC.

VOUT
VOUT

DC + VOS

+ VOS
VCM - VOS Digital input code
(a)
(b)

FIGURE 7.25 Showing how an op-amp offset affects the DACs transfer curves: (a) showing
offset voltage in an op-amp and (b) DAC transfer curves showing offset.
188 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 7.26 Hybrid DAC simulation schematic.

Data Converter 189

dacvout

1.0
dacvout (V)

0.5

0.0
0 1x10-5 2x10-5
Time (s)

FIGURE 7.27 Hybrid DAC results.

FIGURE 7.28 1.5-bit simulation schematic.

190 CMOS Analog and Mixed-Signal Circuit Design

V(vinm1)
0.8 V(vinp1)
0.6
0.4
0.2
0.0

V(b1p51)
1.0

0.5

0.0

V(a1p51)
1.0
V (V)

0.5

0.0

V(vinp2)-V(vinm2)
1
0
-1

V(vinm2)
1.0 V(vinp2)

0.5
0.0

0.0 1.0x10-6 2.0x10-6

Time (s)

FIGURE 7.29 1.5-bit simulation result.

7.5 LAYOUT EXAMPLES

Figure 7.30 shows the switchable current source for the hybrid DAC.
Figure 7.31 shows the hybrid DAC. Figure 7.32 shows the 8-bit-pipeline ADC.
The ADC reference uses the Vref from another block. While the clock generator
uses the real clock as its input (normally located in the pad ring). The clock gen-
erator and error correction are considered digital circuits, so they are noisy and
grouped together. The ADC reference is an analog block, and thus is considered a
quiet block. The 1-bit comparator is used to convert the last bit.
Data Converter 191

FIGURE 7.30 Switchable current source.

192 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 7.31 Hybrid DAC.

FIGURE 7.32 ADC: (a) layout and (b) floor plan.

Data Converter 193

7.6 SUMMARY
In this chapter, many examples of DACs and ADCs are presented, which are very
much practical for the mixed-signal integrated circuits. The speed, power consump-
tion, and resolution are parameters that should be improved in any design of data
converters. Floor planning is important for data converters. The noise of the digital
circuit should be contained. A separate power pad between the analog and digital
circuit should be considered. The substrate is considered the analog ground or the
quiet plane. So, the substrate should not be connected to the digital ground. More of
this is discussed in the next chapter.

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current-source resistor-string hybrid DAC. Journal of Circuits, Systems, and Computers
(JCSC), 20(4), 709–716.
2. Cheng, K.-H., Wang, H.-H., and Huang, D.-J. (2008). A 1-V 10-bit 2G sample/s D/A con-
verter based on precision current reference in 90-nm CMOS. 15th IEEE International
Conference on Electronics, Circuits and Systems 2008, ICECS 2008 (pp. 340–343).
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Devices-Newnes.
4. Suzuki, A., Shimamura, N., Kainuma, T., Kawazu, N., Okada, C., Oka, T., and
Wakabayashi, H. (2015). A 1/1.7 inch 20Mpixel back illuminated stacked CMOS image
sensor for new imaging application. ISSCC 2015 (pp. 110–112).
5. Kleinfelder, S., Lim, S., Liu, X., and El Gamal, A. (2001). A 10000 frames/s CMOS
digital pixel sensor. IEEE Journal of Solid-State Circuits, 36(12), 2049–2059.
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Nakamura, J. (2013). A 1-inch optical format, 80fps, 10.8Mpixel CMOS image sensor
operating in a pixel-to-ADC pipelined sequence mode. Proceedings of International
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7. Deguchi, J., Tachibana, F., Morimoto, M., Chiba, M., Miyaba, T., and Tanaka, H.
K. T. (2013). A 187.5 µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with
PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC.
ISSCC (pp. 494–496).
8. Zhao, W., Wang, T., Pham, H., Hu-Guo, C., Dorokhov, A., and Hu, Y. (2014).
Development of CMOS pixel sensors with digital pixel dedicated to future particle
physics experiments. Journal of Instrumentation, 9(2), C02004–C02004.
9. Song, B. (2000). Nyquist-rate ADC and DAC. In VLSI Handbook, E. W. Chen (Ed.).
CRC Press, Florida.
10. Loinaz, M. J., Singh, K. J., Blanksby, A. J., Member, S., Inglis, D. A., Azadet, K., and
Ackland, B. D. (1998). A 200-mW, 3.3-V, CMOS color camera IC producing 352 × 288
24-b video at 30 frames/s. IEEE Journal of Solid-State Circuits, 33(12), 2092–2103.
11. Hamami, S., Fleshel, L., Yadid-pecht, O., and Driver, R. (2004). CMOS Aps Imager
Employing 3.3V 12 bit 6.3 ms/s pipelined ADC. Proceedings of the 2004 International
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12. Abdul Aziz, Z. A., and Marzuki, A. (2010). Residual folding technique adopting
switched capacitor residue amplifiers and folded cascode amplifier with novel PMOS
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194 CMOS Analog and Mixed-Signal Circuit Design

13. Lewis, S. H., Fetterman, H. S., Gross, G. F. Jr., Ramachandran, R., Viswanathan, T. R.,
and Viswanathan, T. R. (1992). 10-b 20-Msample/s analog-to-digital converter. IEEE
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digital converter. IEEE Journal of Solid-State Circuits, 34(5), 599–606.
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17. Norsworthy, S. R., Schreier, R., and Temes, G. C. (Eds.). (1997). Delta-sigma Data
Converters: Theory, Design, and Simulation (Vol. 97). New York: IEEE Press.
18. Mahmoodi, A., and Joseph, D. (2008). Pixel-level delta-sigma ADC with optimized
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Symposium on Circuits and Systems MWSCAS’08 (pp. 41–44).
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 8 CMOS Color and Image
Sensor Circuit Design

8.1 INTRODUCTION
An image sensing optical receiver, such as complementary metal-oxide semiconduc-
tor (CMOS) image sensors (CIS), in general, is comprised of photodiode, analog, and
mixed-signal circuits to amplify small photocurrents into digital signals. The CMOS
image sensors are now the technology of choice for most imaging applications, such
as digital video cameras, scanners, and numerous others. Even though their sensitiv-
ity does not reach one of the best actual charge-coupled device CCD’s (whose fill
factor is about 100%), they are now commonly used because of their multiple func-
tionalities and their easy fabrication.
Three types of the topology of CMOS color sensors are discussed, namely,
the transimpedance amplifier (TIA), light to frequency converter, and light
integrating.

8.2 TECHNOLOGY AND METHODOLOGY

This section describes CMOS technology, backside illumination (BSI) technol-
ogy, and photo devices applicable to the CIS design. This section elaborates on the
concept that has already been discussed in chapter 1.

8.2.1 General Comments on Technology or Process

for CMOS Image Sensor

Generally, four types of processes are used, standard CMOS, analog-mixed-signal

CMOS, digital CMOS, and CMOS image sensor processes. The latter is the process
developed specifically for the CMOS image sensor. There are many foundries avail-
able for the development of a CMOS image sensor. The most obvious difference
between this process and the other processes is the availability of photo devices,
such as a pinned photodiode. The advantages of smaller dimension technology are
smaller pixel, high spatial resolution, and lower power consumption. A technology
lower than 100 nm requires modification to the fabrication process (not following the
digital road map) and pixel architecture [1].
Fundamental parameters such as leakage current (will affect the sensitivity to
the light) and operation voltage (will affect dynamic range, i.e., the saturation, a
pinned photodiode is most likely not going to work at a low voltage [1]) are very

195
196 CMOS Analog and Mixed-Signal Circuit Design

important when a process is selected for CIS development. Because of these limi-
tations, a new circuit technique is introduced:

1. An old circuit, such as a standard pixel circuit cannot be used when using
0.1 micron and lower [2]. This is due to the topology which requires high
voltage; because the maximum supply voltage is now lower.
2. Calibration circuit and cancellation circuit are normally employed to reduce
noises.

In order to increase the resolution into multi-megapixel and hundreds of frame rate,
lower dimension technology is normally chosen. Evidently, it has been reported
that 0.13 micron [3] and 0.18 micron [4] are good enough to achieve good imaging
performance.
These modifications of the CMOS process have started at 0.25 micron and below
to improve their imaging characteristics. As process scaling is going to be much lower
than 0.25 micron and below, several fundamental parameters are degraded, namely,
photo responsivity and dark current. Therefore, the modifications are focused on
mitigating these parameter degradations [2,5]. System requirements (such as supply
voltage and temperature) are also one of the criteria in selecting a suitable process.
The price of tool and development costs will also determine the process selection.
A description of pixel size vs. CIS technology is shown in Figure 8.1 [6].

8.2.2 Backside Illumination
BSI technology eliminates the need to push light through the layers of metal inter-
connections. With this, high quantum efficiency can be achieved. However, this tech-
nology incurs additional costs due to extra processes, such as stacking and through
silicon via. A pixel of 1.1 micron seems to be the tipping point advantage over fron-
tside illumination [7]. A work in [8] uses BSI to improve the resolution through the

FIGURE 8.1 Pixel size vs. CIS technology node.

CMOS Color and Image Sensor Circuit Design 197

pixel size. As the BSI is targeted for very small pixel, process such as 90 nm is pre-
ferred, of course this is a very expensive process, and thus this CMOS image sensor
is meant for expensive application (e.g., high-end camera).

8.2.3 Photo Devices
The typical photo detector devices are photodiode and phototransistor. Typical pho-
todiode devices are N+/Psub, P+/N_well, N_well/Psub, and P+/N_well/Psub (back-
to-back diode) [9]. Phototransistor devices are P+/n_well/Psub (vertical transistor),
P+/N_well/P+ (lateral transistor), and N_well/gate (tied phototransistor) [9].
These standard photo devices still require a micro lens and color filter array.
The quantum efficiency of photodiodes in a standard CMOS is usually below
0.3 [10].
The devices which are normally developed for the modified CMOS process are
a photogate, pinned photodiode, and amorphous silicon diode. These devices will
improve the sensitivity of the CIS. A pinned photodiode, which has a low dark cur-
rent, offers good imaging characteristics for the CIS [11].
The photodevices exhibit the parasitic capacitance, which should be considered
during the design process. An example of the parasitic capacitance of N_well/Psub is:

Cphoto = ( Capacitance per area ) × photodevice area. (8.1)

8.2.4 Design Methodology

The typical design flow of the CMOS image sensor is shown in Figure 8.2.
A wave propagation simulation can be done for optics simulation [12]. The image
systems’ evaluation tools are available to conduct the optics simulation as well as
system simulation [13]. Commercially available technology computer-aided design
tools, such as from Synopsys and Silvaco, can be used to simulate the process/
technology of the photodevices. There is a work, [14], (mixed-mode simulation)

FIGURE 8.2 Design flow of CMOS image sensor.

198 CMOS Analog and Mixed-Signal Circuit Design

that combines the technology computer-aided design and pixel-level simulation.

There are many electronic design automation tools available for pixel electrical
simulation, these electronic design automation tools are similar to any integrated
circuit (IC) design tool, such as spectre, SPICE, Verilog-A, and Verilog. These
tools could be time consuming if the number of pixels is large. Indeed, if large
pixels together with the deep submicron process are required, more capital has to
be provided (cost of tools are more expensive for very deep submicron, especially
below 90 nm).
Even though the CMOS foundry provides the models for supported design tools,
sometimes designers still have to model the sub-block on their own to suit the CIS
specification. This can speed up the pixel electrical simulation time, however, this
will degrade the accuracy. For system simulation, VHDL-AMS, System-C, or
MATLAB can be used to predict the overall function and performance.

8.3 CMOS COLOR SENSOR

8.3.1 Transimpedance Amplifier Topology
A typical light or color sensor uses photodiodes and a TIA. The TIA is used to con-
vert the photodiode current to voltage. This is shown in Figure 8.3. The resistor and
capacitor at the output are used to filter out the high-frequency (unwanted) signal.
The filter will affect the time response of the color sensor. The size of the feed-
back resistor, Rfeedback, is also big, and this consumes the size or area of the silicon.
The output voltage is:

vout = i photo × R feedback (8.2)

The amplifier gain is normally huge, and this will increase the current consumption.

8.3.2 Current to Frequency Topology

Several digital color sensors employ light to frequency technique and photodiodes,
which is similar to other studies [15]. These frequency-based digital sensors require
an advanced processor, such as digital signal processor or personal computer to

FIGURE 8.3 TIA-based color sensor.

CMOS Color and Image Sensor Circuit Design 199

FIGURE 8.4 Light to frequency sensor. (a) schematic diagram and (b) timing diagram.

measure or calculate the frequency [16]. Figure 8.4 shows [15] an example of the
sensor. The time or duration of the ramp signal is:

∆V
∆t = CINT × . (8.3)
i photo

8.3.3 Current Integration Topology

The proposed design as shown in Figure 8.5 is an improved version that is based on
previous works [17–19]. It receives signals from the photodiode array, a programma-
ble setting can be applied to the signals, and it then converts the resulting differen-
tial voltage signal into digital words. The programmable settings are the integration
period, capacitor size, and photodiode active area size. The design can sense pulsat-
ing light without the need for a filter. This is because the design works on the prin-
ciple of integrating the photodiode current.
Five major blocks are shown in Figure 8.5: test multiplexer (TEST_MUX),
REFERENCE, analog to digital computer (ADC), TIMING GENERATOR and
integrator, and sample & hold (INTEG S&H). The TIMING GENERATOR is used
to derive the required control signals (see Figure 8.6). INTGR and PRECHARGE
SIGNALS are the inputs to the TIMING GENERATOR. The INTEG S&H block
is the point of interest and will be explained in detail in this chapter. The Photomux
shown in Figure 8.5 is a simplified idea; its function is to select the photodiode active
area and channel or color. Each switch for CHSEL [2:0] consists of three switches for
200 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 8.5 Current integrating.

FIGURE 8.6 Control signals.

CMOS Color and Image Sensor Circuit Design 201

TABLE 8.1
Description of the I/O of the Proposed Design
Name Type Description
VDDA P Analog supply. Nominal 2.6V
VSSA P Analog ground
PDASZ[3:0] DI Photodiode size
CAPSZ[7:0] DI Capacitor select
CHSEL[2:0] DI Channel select
INTGR DI Integrating control signal
PRECHARGE DI Precharge control signal
EN_SINGLE DI Select 7 bit mode (active high)
CLK_ADC DI ADC clock
ADC_PD DI ADC power down pin (active high)
AMP_PD DI Amplifier power down (active high)
BG_PD DI Bandgap power down (active high)
DARKVCM_SEL DI Select normal Vcm (active high)
ATESTSEL[8:0] DI Analog test control signal (TSTMUX)
Photodiode pins ANA Photodiode connection
ANA1 ANA TEST PIN1
ANA0 ANA TEST PIN2
ADCDATAOUT[7:0] D0 ADC data out

color selection (RGB). The integration of the photocurrent is accomplished by using

an array of capacitors, called integration capacitors, Cint, so, together with switches
(transistor symbol), they form an integrator. Table 8.1 depicts the description of the
input/output (I/O).
The simplified integrator output, Vin is:

I photodiode × Tintegration
Vin = Vprecharge − (8.4)
Cint

where Vprecharge is the voltage across the integration capacitor, Cint. The voltage is
provided by the REFERENCE block. Iphotodiode is the photocurrent, and Tintegration is
the integration time.
From Equation 8.4, when the light incident on the photodiode is pulse width
modulation (PWM) light, the integration phase (see Figure 8.6) is synchronized
to a multiple of the PWM periods, then the voltage, Vin, is inversely proportional
to the PWM duty cycle. A single to differential amplifier (sigdiff ) is then used to
produce the differential voltages for the differential input ADC; these values are
later sampled by the sample/hold (S/H) amplifier. In the single to differential cir-
cuit (sigdiff), a compensated common mode voltage is used for the dark current
cancellation. The sampled values are held for analog to digital conversion. At the
same time, the Cint is charged back to the Vprecharge value. A pipeline ADC with
the 8-bit resolution is used for analog to digital conversion. The ADC can receive
202 CMOS Analog and Mixed-Signal Circuit Design

±1.2 V, i.e., differential input voltages with the nominal voltage (common mode
voltage) of 1.2 V. The relationship of voltages and the ADC output is described
in Equation 8.5:

 ( inp − inm ) + Vref 

ADC Output Decimal ( DEC ) =   × 256 (8.5)
 2Vref
 

where inp is the positive input of the ADC, inm is the negative input of the ADC,
and Vref is the reference voltage. For the output of 0 DEC, the differential voltage is
−1.2 V (e.g., inp = 0. 6 V, inm = 1.8 V), while for the output 256 DEC (28), the dif-
ferential voltage is 1.2 V.
Both Equations 8.4 and 8.5 show that the concept is capable of integrating several
functions (gain stage and LPF) into a single silicon. The REFERENCE block is
used to generate bias voltages (e.g., bandgap voltage (VBG) or Vcm) and bias cur-
rents for internal usage, such as the voltage to precharge the Cint. The design also
includes extensive routing for testability. Each block’s input can be overridden, and
each block’s output can be measured. This allows an efficient means of debugging
the signal chain within the design should the need arise.

8.4 CMOS IMAGE SENSOR

The data converter function is to convert an analog signal into a digital signal.
This will improve signal robustness and provide for further processing. The ADC
is normally a typical circuit used as the data converter. Another type is using the
“oscillator” concept. Table 8.2 is a summary of the ADC choice of location for the
CIS [20].

8.4.1 CMOS Image Sensor Architecture

8.4.1.1 Pixel-Level ADC
A digital pixel sensor (DPS) offers a wide dynamic range [21]. The DPS converts the
analog values to a digital format within the pixel. The processing can also be done
at the pixel level. To achieve wide dynamic range resolution, most of the existing

TABLE 8.2
ADC Choice of Location in CIS
Pixel-Level ADC Column-Level ADC Chip-Level ADC
Power Low [20] Medium [3] High
Area Fill factor low Area medium High
Speed (Frame Rate) Highest Medium Limited by ADC
Noise Elimination of temporal noise [5] Medium Low
CMOS Color and Image Sensor Circuit Design 203

FIGURE 8.7 Pixel-level ADC CIS topology.

sensors acquire multiple pictures using different exposures, and then, off-chip pro-
cessing is done to recombine them in one image. This concept is shown in Figure 8.7.
The topology in Figure 8.7 is similar to memory architecture.

8.4.1.2 Column-Level ADC

This topology is shown in Figure 8.8. A correlated doubled sampling circuit is nor-
mally used to reduce the fixed pattern noises [20]. This circuit is employed prior to
the column ADC. Figure 8.9 shows the BSI topology. Figure 8.10 shows the cross-
section of the BSI topology.

FIGURE 8.8 Column-level ADC CIS topology.

204 CMOS Analog and Mixed-Signal Circuit Design

Bottom part (Logic technology)

Row
TSVs Top part (CIS technology)
Load Tr.s

Row decoders

Row drivers
Pixel
Control

array

Ref
Comparators
Reference
voltage

Counters

Image Output
Column TSVs Processing I/F

FIGURE 8.9 BSI topology.

Newly developed
Stacked BI-CIS

Pixels

Circuits

Logic process
Substrate (Si)

FIGURE 8.10 BSI cross-section.

8.4.1.3 Chip-Level ADC

Chip-level ADC or sometimes matrix-level ADC is depicted in Figure 8.11.
The ADC for this topology has to be very fast [22], this topology would also con-
sume a very high current. The ADC type suitable for the CIS topology is pipe-
lined ADC. However, successive approximation register (SAR) [23] and flash type
ADC [24] have also been reported in the CIS design. The trade-off between power
consumption and speed is therefore necessary.
CMOS Color and Image Sensor Circuit Design 205

FIGURE 8.11 Chip-level ADC CIS topology.

8.4.2 Analog Pixel Sensor

A conversion factor of a basic pixel is:
q
FC = (8.6)
Cint

where q is the charge of an electron and Cint is a capacitor used for light integration.
The noise in the electron rms is:

kT Cint
σ= (8.7)
Cint q

where k is the Boltzmann constant and T is the temperature. The noise is typically
decreased by reducing the integration capacitance.
A typical dynamic range of a pixel is given by:

VOUTMAX − VOUTMIN
DR = (8.8)
FC

where the VOUTMAX − VOUTMIN is the output voltage range of the pixel circuit.
A low fixed pattern noise capacitive TIA (CTIA) for the active pixel CMOS
image sensors with a high switchable gain and low read noise is shown in
Figure 8.12. The low fixed pattern noise CTIA active pixel sensor uses a switched
capacitor voltage divider feedback circuit to achieve a high sensitivity, low gain
fixed pattern noise, and low read noise. The circuit consists of a transconduc-
tance amplifier TA1, a photodiode, a network of feedback capacitors and switches
(Cl, C2, Cf, Ml, and M2), and a bit line select transistor M3. WORD is used to
206 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 8.12 CTIA.

select each row of pixels, BIT is the output bus for each column in the sensor,
RESET and GAIN are used to reset the pixel and control the pixel gain, and VREF
is the pixel bias voltage.
Another circuit is shown in Figure 8.13. The integration capacitor, Cint, is used as
a feedback component. The photocurrent now is coming from Cint, and Vdiode remains
constant throughout the integration period.

FIGURE 8.13 Pixel schematic.

CMOS Color and Image Sensor Circuit Design 207

FIGURE 8.14 Pixel schematic [25].

A pixel image sensor [25], implementing real-time analog image processing is

shown in Figure 8.14. The pixel consists of different functional blocks: Sensing
Block, Computing Unit, Bank of Switches, and Memories. The pixel is capable of
processing edge detection, motion detection, image amplification, and dynamic-
range boosting by means of a highly interconnected pixel architecture based on the
absolute value of the difference among the neighbor pixels.
Another example of processing at a pixel level is the matrix transform imager
architecture [26]. The circuit is shown in Figure 8.15. The photodiode is placed as
a current source for a differential pair; this produces output currents in the form of
the multiplication of photocurrent (Isensor) and input voltages. For the differential pair
operating with subthreshold bias currents (which should always be the case due to the
low-level image sensor currents), we can express the differential output current as:

(
 k V + −V −
I + − I − = I sensortanh 
)  (8.9)
 2VT 
 

FIGURE 8.15 Multiplication of photocurrent and input voltages. (Redrawn from

Bandyopadhyay, A. et al., IEEE J. Solid St. Circ., 41, 663–672, 2006.)
208 CMOS Analog and Mixed-Signal Circuit Design

FIGURE 8.16 Analog circuit of DPS. (Redrawn from Zhang, M. and Bermak, A., IEEE
Trans. Very Large Scale Integr. Syst., 18, 490–500, 2010.)

where k is the gate coupling efficiency into the transistor surface potential (typically
0.6–0.8) and V T is kT/q. If the difference of V + − V − is small, the Equation 8.9 is:

(
 k V+ −V−
I + − I − = Isensor 
)  (8.10)
 2VT 
 

8.4.3 Digital Pixel Sensor

The DPS concept is similar to the solution used in the CMOS neuron-stimulus chip.
The DPS in number is found useful for on-chip compression. Figure 8.16 shows an
example of the DPS [27] used for the comprehensive acquisition concept. The pho-
todiode is used to discharge the input capacitance of the comparator and photodiode
itself. It will be discharged proportionally to the light intensity. When this reaches
the threshold, the output of the comparator will trigger.

8.4.4 Low Power and Low Noise Technique

After the selection of the low power process or technology, below are the methods
that can be used to lower down the power consumption of the CIS.

8.4.4.1 Low Power Techniques

1. Biasing method: The subthreshold region or weak inversion biasing is one
of the approaches to achieve low current consumption [28]. This approach
is discussed in Chapter 4. This technique can be applied to an operational
transconductance amplifier (OTA) or an amplifier for an ADC. Triode
region biasing can also be used to further reduce power consumption [29].
2. Circuit technique: The regenerative latch [28] can be used to reduce the
digital power consumption. Reducing/scaling the capacitors in the pipeline
stages (for ADC) can also reduce the power consumption [30].
3. Advanced power management technique: Another type of biasing or circuit
technique, a “smart” approach, such as harvesting solar energy can also be
CMOS Color and Image Sensor Circuit Design 209

employed to reduce the power consumption [31]. We can also selectively

ON only the required readout circuit. Pixels can also be periodically acti-
vated to reduce the power consumption [32] further.

8.4.4.2 Low Noise Techniques

After the selection of the low noise process or technology, below are the methods
that can be used to lower down the noise of the CIS.

1. At pixel level: The thermal noise can be reduced by correlated double sam-
pling and oversampling. The flicker noise is reduced by using a large device,
periodically biasing the transistor, and proper PMOS substrate voltage bias-
ing [33]. Further discussion of flicker noise is already discussed in Chapter 2.
2. Column level: The off-chip calibration can be used to reduce fixed pattern
noise as discussed in work [4]. The calibration is done to select suitable
capacitor weights in the SAR ADC.
3. ADC level: The kT/C noise is reduced by selecting a suitable value for Cf
and Cs of the S/H circuit and buffer [34]. See more discussion in Chapter 6.
4. Photodiode level: The high conversion gain helps to reduce referred-to-
input noise [35]. This idea is mentioned in Section 8.4.2

8.5 SPICE EXAMPLE

Figure 8.17 shows the TIA simulation schematic. I1 is a pulse current source with a
maximum current of 500 nA. Figure 8.18 shows the simulation result of the TIA, and
the maximum output voltage is 800 mV. Figure 8.19 shows the three-transistor (3-T)
pixel, while Figure 8.20 shows a simulation schematic. Figure 8.21 shows the control
voltages and output voltage.

FIGURE 8.17 TIA simulation schematic.

210 CMOS Analog and Mixed-Signal Circuit Design

Vout

0.8
Vout (V)

0.7

0.6

0.5
0.0 2.0x10-5 4.0x10-5 6.0x10-5
Time (s)

FIGURE 8.18 TIA simulation result.

FIGURE 8.19 3-T pixel.

CMOS Color and Image Sensor Circuit Design 211

FIGURE 8.20 3-T pixel simulation schematic.

6 V (row)

4
2
0

6 V (reset)

4
2
0

V(out)
0.4
0.3
0.2
0.1
0.0

4 V (vphoto)
3
2
1
0

I (iphoto)
1.0x10-6

5.0x10-7
0.0
0.0 5.0x10-8 1.0x10-7
Time (s)

FIGURE 8.21 3-T pixel simulation result.

212 CMOS Analog and Mixed-Signal Circuit Design

8.6 LAYOUT
The floorplan of a color sensor is shown in Figure 8.22.
Figure 8.23 shows the photodiode, and Figure 8.24 shows the layout of dark cur-
rent cancellation.

FIGURE 8.22 Color sensor floor plan.

FIGURE 8.23 Photodiodes.

CMOS Color and Image Sensor Circuit Design 213

FIGURE 8.24 Layout of CMOS color sensor with dark current cancellation: (a) Floorplan,
(b) IC layout, and (c) IC microphotograph.

8.7 SUMMARY
This chapter describes the techniques in the circuit design of the CMOS color and
image sensor. The topology such as TIA and light to frequency are popular topolo-
gies for the practical CMOS color sensor. However, the light integrating technique
has been applied to a digital CMOS color sensor, which is suitable for PWM-ed light.
There is still room for improvement for both color and image sensors, especially on
the dynamic range and power consumption.

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 9 Peripheral Circuits

9.1 INTRODUCTION
Knowledge of the oscillator and interface circuitry is important for a complete cus-
tom analog and mixed-signal integrated circuits. The oscillator can be used in more
advanced oscillatory, such as phase-locked loop. However, the phase-locked loop is
normally required for a very accurate source requirement. A basic built-in oscilla-
tor is normally sufficient for standalone analog or mixed-signal integrated circuits.
The control clock is basically generated from the controller or master controller inte-
grated circuit (IC).

9.2 OSCILLATOR
9.2.1 Ring Oscillator
Figure 9.1 shows a current-starved ring oscillator. The oscillation frequency of a
basic ring oscillator is:

1
fosc = (9.1)
n. ( t PHL + t PLH )

where n is the number of the inverters, and tPHL and tPLH are the intrinsic propagation
delays of an inverter.
Equation 9.1 is easily modified for the current-starved ring oscillator as:

ID
fosc = (9.2)
n. ( CTOTALVDD )

where VDD is the supply voltage, CTOTAL is the total capacitance of an inverter, and ID
is the total of current consumed by an inverter.

9.2.2 RC Oscillator
Figure 9.2 is a basic resistor-capacitor (RC) oscillator. Figure 9.3 shows the simplified
schematic of a waveform generator. It contains three selectable complementary metal-
oxide semiconductor (CMOS) capacitors. When the voltage at X is high, the switch
will turn ON and discharge all the capacitors. I is about 4 times of the current provided
by the oscillator reference (oscRef) block. The current generator and waveform genera-
tor are two major blocks in the RC oscillator. The current generator has a timer resistor-
capacitor start (RC Start). It is high when the current generator is stabled. Therefore,
the oscillator frequency should not warble at the earlier stage.

217
218 CMOS Analog and Mixed-Signal Circuit Design

VDD

M14 M7 M8 M9

M15
M1 M3 M4
out

M16
M2 M5 M6

M13 M10 M11 M12

VIN

GND

FIGURE 9.1 Ring current-starved VCO.

Vout
Vc
Vr C switch
R

Current Generator Wave Generator

FIGURE 9.2 RC oscillator.

The period time of one cycle of the circuit in Figure 9.2 is:

∆Vc
T = RC . (9.3)
Vr

9.2.2.1 Ramp Oscillator

An oscillator charge–discharge circuit of Figure 9.4 is the building block of the ramp
generator, together with the comparators in Figure 9.5 [1]. The current source loads
from transistor M9, M10, and mirrors M8, M6, M3, and transistor M7, M0 sets the
Peripheral Circuits 219

VDD
I
x Amp/buffer

RC start

Switch

S0 S1 S2

L, W = 1.88 L, W = 3.04 L, W = 4.46

FIGURE 9.3 RC oscillator with timer.

vdda5
M9 M7 M0
vbiasp2

Qbar M1
out
vbiasp1 M10 Q
M5 M4
M2
C1

M8 M6
M3
vssa5

FIGURE 9.4 Oscillator charge discharge circuit.

charge and discharge current ratios. Switches M4 and M5 reduce transient on-off
mirror glitches by preventing transistors M0 and M3 from turning off when they are
disconnected from the capacitor, C1. The comparator should toggle when the input
overdrive is at a minimum level, and that is when the ramp barely exceeds the upper
and lower voltage limits VH and VL.
The oscillator charge discharge circuit charges a capacitor with a constant charge
current IChg for the ramping up time of the period, until an upper voltage limit is reached,
and then discharges it with the discharge current IDchg for the remaining ramping down
time, until the lower limit is reached, and then starts a new cycle as in Figure 9.6.
The period of the ramp limits is set with two comparators, as in Equation 9.4.

 1 1 
T = C VH − ( VL − Verror )   +  (9.4)
 Ichg I Dchg 
220 CMOS Analog and Mixed-Signal Circuit Design

Comparison
Charging Circuit
Circuit
IChg

SChg
CMP1
+
Ramp
VH SChg
– R Q
C
SDchg

IDchg VL
+ S Qn
SDchg
Prop. –
CMP2

FIGURE 9.5 Block diagram of ramp generator. (Redrawn from Pooya Forghani-Zadeh, H.,
and Rincon-Mora, G.A., J. Low Power Electron., 2, 1–5, 2006.)

VH
VEA
Ramp
VL Verror

tfall

Pulse

T = Period

FIGURE 9.6 Ramp and pulse signal.

9.3 NON-OVERLAPPING GENERATOR

The overlapping clock signals are generated with a circuit shown in Figure 9.7. Two-
output feedback via the nand gate to the top D-Flip-Flop ensures that only one bit of
input 1 (In1), input 2 (In2), or input 3 (In3) is low at any given time. The outputs of the
circuit change state on the positive edge of the input clock signal. The outputs of this
circuit are connected to the non-overlapping clock circuit depicted in Figure 9.8.
The feedback guarantees that the output does not go high until the previous phase
Peripheral Circuits 221

D Q In1
clk

D Q In2
clk

D Q In3
Clkin
clk

FIGURE 9.7 Overlapping clock generator.

In1
Phase 1

Nonoverlapping clock signal

Phase 2
In2

Phase 3
In3

Overlapping clock signals Delay (inverter buffers, or charge pumps)

FIGURE 9.8 Non-overlapping clock generator.

clk
phi0

phi1

FIGURE 9.9 Non-overlapping clock generator 2.

goes back low. The non-overlap time is set by the delay in series with the output of
the negated or (NOR) gates.
Figure 9.9 shows another example of a non-overlapping circuit. A special delay
is used in the circuit. The delay circuit is depicted in Figure 9.10. Metal-oxide semi-
conductor capacitors (MOSCAPs) are used instead of the conventional capacitor to
reduce the size of the circuit.
222 CMOS Analog and Mixed-Signal Circuit Design

VDD

IN OUT

VSS

FIGURE 9.10 Delay circuit.

9.4 INTERFACE CIRCUITRY

9.4.1 Basic Interface Circuit
This circuit is normally used for data control. There should be “synchronization”
between clock, data, and control/latch. Obviously for output, the parallel configu-
ration is preferred due to its fast operation. However, if the input/output (I/O) is
limited, high-speed serial output, such as low-voltage differential signaling interface
can be used.
An example of three “wire” serial peripheral interface (SPI) control is shown in
Figure 9.11. Table 9.1 describes the terminology of SPI control.
Figure 9.12 shows the basic logic diagram of SPI, the first column of D-Flip-Flop
is configured as a shift register, while the second column of Flip-Flop is configured
as latches. Figure 9.13 shows another idea for the SPI, while parallel to serial inter-
face (PSI) is shown in Figure 9.14.
An interface circuit should cater to the daisy chain concept. This concept eases
multiple chips via a single controller. Both circuits in Figures 9.12 and 9.13 have
serial data out for the daisy chain concept. The serial data out is a first in, first out
(FIFO) concept. The clock for the SPI circuitry is normally derived from the external
controller. The clock is independent of the internal clock. The PSI which is normally

t1

SCK
t3

t2

SDI C3 C2

t5

INPUT
t4

CS
t6

FIGURE 9.11 SPI control timing diagram.

Peripheral Circuits 223

TABLE 9.1
SPI Terminology
Symbol Parameter
t1 Clock cycle time
t2 Data setup time
t3 Data hold time
t4 SCK falling edge to CS rising edge
t5 CS falling edge to SCK rising edge
t6 CS pulse width

13
OE

12
CS

SDI 14
D Q D Q 15
QA
R

D Q D Q 1 QB
R

D Q D Q 2 QC
R

D Q D Q 3 QD
R Parallel Data Output

D Q D Q 4 QE
R

D Q D Q 5 QF
R

D Q D Q 6 QG
R

D Q 7 QH
D Q
SCK 11 R

10
SCLM 9 QG Serial Data Output

FIGURE 9.12 Basic block diagram of SPI.

224 CMOS Analog and Mixed-Signal Circuit Design

reg<5> reg<4> reg<0>

1 1 1
DIN 0 D Q 0 D Q 0 D Q REG_OUT
5 4 0
REG_EN
CLK_INT

FIGURE 9.13 SPI 2.

adc_data<7> adc_data<6> adc_data<0>

1 1
D Q 0 D Q 0 D Q DOUT
7 6 0
SHIFT_EN

CLK_ADC

FIGURE 9.14 PSI.

for an analog-to-digital converter (ADC) uses an internal clock for easier synchro-
nization. Nevertheless, the timing of internal signals and external signals is very
important. Special care must be taken during the interface circuit.

9.4.2 I2C
Both serial data and serial clock are bidirectional lines, connected to a positive sup-
ply voltage via a pull-up resistor (see Figure 9.15). When the bus is free, both lines
are HIGH. The output stages of devices connected to the bus must have an open-
drain or open-collector in order to perform the wired-AND function. Data on the
I2C-bus can be transferred at a rate up to 100 kbit/s in the standard-mode, or up to

+VDD
PULL-UP
Rp Rp
RESISTORS
SDA (SERIAL DATA LINE)
SCL (SERIEL CLOCK LINE)

SCLK SCLK

SCLKN1 DATAN1 SCLKN2 DATAN2

OUT OUT OUT OUT

SCLK DATA SCLK DATA

IN IN IN IN

DEVICE 1 DEVICE 2

FIGURE 9.15 I2C.

Peripheral Circuits 225

400 kbit/s in the fast-mode. The number of interfaces connected to the bus is solely
dependent on the bus capacitance limit of 400 pF.
The I2C-bus supports any IC fabrication process (NMOS, CMOS, bipolar). Two
wires, serial data and serial clock, carry information between the devices connected
to the bus. Each device is recognized by a unique address and can operate as either
a transmitter or receiver, depending on the function of the device. In addition to
transmitters and receivers, devices can also be considered as masters or slaves when
performing data transfers. A master is a device that initiates a data transfer on the
bus and generates the clock signals to permit that transfer. At that time, any device
addressed is considered a slave.

9.5 I/O PAD

A sharing pad (see Figure 9.16) between input and output is common for a pin or an
I/O limited device. This is clearly the case for the I2C. If the OE is low, M1 and M2
are off, thus a pad can be used as an input pad. If the output enable (OE) is high,
M2 and M1 will work as a normal output driver, thus a pad is now configured as an
output pad.
A Schmitt trigger circuit can also be added after the basic protection circuits.
A good foundry would offer very good guidance in implementing the I/O.
An analog pad needs to consider a buffer (opamp). The digital output might
require a simple digital buffer. A lot has to be done if the speed requirement needs
to be increased.

from core
VDD
logic ND1
M1
OE

output
enable
I2 I/O
pad

M2
DATAout

NR1

DATAin
to core
logic I1

FIGURE 9.16 Bidirectional pad.

226 CMOS Analog and Mixed-Signal Circuit Design

9.6 SCHMITT TRIGGER CIRCUIT

An I/O cell could be a very simple circuit with just protection devices [2]. Figure 9.17
shows a slow analog signal which has a slow rise time and is applied to a digital
input, such as TTL or CMOS input without a Schmitt trigger circuit. For a typical
inverter, there is no clear difference between the threshold to indicate high-to-low
and vice versa (They are the same). The output of the inverter can be low or high for
both conditions.
Therefore, the solution is to have the circuit with different threshold voltages for
low-to-high and high-to-low. One of the solutions is the Schmitt trigger circuit [3].
As shown in Figure 9.18, when input is low, ML is on, and the output is low.
Now the voltage at the source of M1 and M2 is approximately equal to R2/R3. When
input is high, M1 is on, and the output is high. Now the voltage at the source of M1
and M2 is approximately equal to R1/R3.

VIH
switching threshold may
be anywhere in this band
Vin
VIL

oscillation while Vin

traverses linear region
Vout
uncertainty of switching point

FIGURE 9.17 Slow analog signal.

+3V

R1 R2 3
20k 10k 2.8 Output

M1 M2 2.6
Input
Output 2.4
2.2
W=3u W=3u 2
L=0.35u L=0.35u Input
1.8
R3 1.6
5k 1.4
1.2
1
0 2 4 6 8 10
Time/μSecs 2μSecs/div

FIGURE 9.18 Simple Schmitt trigger concept.

Peripheral Circuits 227

Vdd

P1

P3

P2

IN OUT

N2 Vdd

N3

N1

FIGURE 9.19 CMOS Schmitt trigger circuit concept.

Another Schmitt trigger circuit [2] is shown in Figure 9.19.

Transistor P3 and transistor N3 force output to settle/approach very fast. By vary-
ing the size of these transistors, it will lead to hysteresis (i.e., different threshold
voltages).

9.7 VOLTAGE LEVEL SHIFTERS

Some applications may require internal supply voltages that are higher than that
provided by V DD, in which case, switches and capacitors can be used to produce
internal boosted supply voltages. Classic boost circuits are simple, as shown in
Figure 9.20.
These circuits use MOS devices like diodes and MOSCAPs as output filters.
In the case of the negative boost circuits, transistor Q1 could actually be a PMOS
device, but it will behave as PNP bipolar. The boost voltages provided by these
228 CMOS Analog and Mixed-Signal Circuit Design

m2

CK NEG_BOOST
m1

CK C1 POS_BOOST
m2

Q1

m3
m2

FIGURE 9.20 Classic boost circuit.

m1
POS_BOOST
m2 m3 m4 m5

C1 C2 C3 C4 m6
CK

CK

FIGURE 9.21 Multistage voltage boosting.

circuits is of course less than V DD x 2, since the devices will suffer a forward volt-
age drop when acting as diodes.
For greater output potentials, two approaches can be taken, both basically differ-
ential in nature. The first is based on the above concept, but expanded to any number
of stages, and is shown in Figure 9.21.
The voltages obtained can be damaging to the thin gate oxide of the devices, and
it is expected that this will be taken into consideration.
Such differential techniques can be used to create outputs much closer to VDD x 2
with a single stage, as shown in Figure 9.22.
Such stages can be cascaded to achieve higher voltages.
These boost circuits can be used at very high frequencies to minimize the require-
ment for large capacitor values. Fifty megahertz is not unreasonable, but the clock
signals should be strong and symmetrical. The currents from such boosted supplies
are usually not intended for high power applications; and these circuits are usually
Peripheral Circuits 229

POS_BOOST

m3 m4
m1 m2

C1 C2

CK

CKN

FIGURE 9.22 Cross-coupled voltage boost.

only used in cases where high voltage is passed at a very low current, as in the pro-
gramming or erase of memory through a tunneling mechanism, where the required
currents are trivial.
When designing boost circuits, be careful to notice conditions that simulation
program with integrated circuit emphasis (SPICE) may not handle well, as in the
overshoot of signals above a well potential may cause current spikes into the body
or substrate.

9.8 POWER ON RESET

The main purpose of the power on reset (POR) design is to ensure that the
design starts at a known address after the initial power-on. With the POR, the
design will only start operating from that known address when three occasions
have occurred; with the power supplies stabilizing at appropriate levels; the
processor’s clock being settled; and lastly, with the internal registers loaded
accordingly.
As shown in Figure 9.23, the POR cell contains two major blocks, the differ-
ential POR block and the RC delay block. For this design, the output POR sig-
nal is active-low and triggers after a precise time, t por, after the input signal
level detection. The differential POR generates a high digital voltage value for the
POR_DIFF signal after a power supply level detection, (detecting the threshold
voltage, V THRES ), and this signal controls the RC delay POR for resetting. With this,
the capacitor in the RC delay POR can be fully discharged initially. This design
also requires the power supply to go to zero and remain at zero for some minimum
specified discharge time.
When the power supply voltage, VDD, is superior to V THRES, the POR_RC output
voltage stays at a 0 V level during the time, t por, needed, and then gets to a high
digital voltage value.
The timing diagram for the signals is as shown in Figure 9.24. See Figures 9.25
and 9.26 for differential and RC delay.
230 CMOS Analog and Mixed-Signal Circuit Design

POWER DOWN

VDD DIFFERENTIAL POR_DIFF

VSS POR

POR OUT

RESET

VDD RC DELAY
VSS POR POR_RC

FIGURE 9.23 Block diagram of power on reset.

POR output
3.0
2.0
(V)

1.0
0.0
-1.0

3.0 VDD ramp up 0.1 μs 2.6 V

(V)

2.0 VTHRES
1.0

3.0
2.0
(V)

t por
1.0
0.0
-1.0

POR_DIFF High after detecting the VTHRES

3.0
2.0
(V)

1.0
0.0
-1.0
40u 50u 60u 70u
time (s)

FIGURE 9.24 Timing diagram.

 vdd
VDD
por o
PORDIFF
Peripheral Circuits

d o POR_DIFF
output
vdd VSSA

Differential
Amplifier
VSSA

Power Down Circuitry

Vref
vdd

VSSA
VSSA
Voltage POR
PWRON
Reference

FIGURE 9.25 POR differential block.

231
232 CMOS Analog and Mixed-Signal Circuit Design

vdd vdd

vdd

vdd
RC
rc
rc
Reset
rc

VSSD PORC
POR_RC output

FIGURE 9.26 POR RC delay for POR.

9.9 ESD CIRCUIT

Among all the semiconductor devices, the p–n junction diode is considered one of
the simple and effective electrostatic discharge (ESD) protection devices. Designers
make full use of their forward bias behavior to handle a large amount of ESD current.
Figure 9.27 shows the I–V characteristic for a forward bias diode that is capable of
carrying a significant current when the applied voltage is greater than Von (0.5–0.7 V
range). At this point, the resistance of the diode is very low (<1 Ω), which results in a
low internal temperature even if under high current conditions. Therefore, a forward
bias diode capable of carrying a very high current is widely used for the ESD protec-
tion application.
Besides the p–n junction diode, a Zener diode is also part of the diode that can
be used in ESD protection circuits. The Zener diode is a reverse-biased diode,
where it allows a current to flow in a reverse direction, and it is designed with
lower triggering voltage. Although it has the low on-voltage value compared to
other regular reverse-biased p–n junction diodes, the Zener diode is still not suit-
able to serve as the main protection device because its on-voltage is still higher

I
ID
p
(NA)
+
Ron
VD −
n
(ND)

Von V
(a) (b)

FIGURE 9.27 Simple forward bias p–n junction diode: (a) schematic and (b) I–V curve.
Peripheral Circuits 233

than the gate-oxide breakdown voltage. In fact, a Zener diode is normally used
as a secondary ESD protection device [4].
Snapback devices have a mechanism in which the device will drive into the break-
down region when the voltage across the device is increased. After the breakdown, the
voltage across the device is dropped and moved to a holding region from the breakdown
region because of the internal positive feedback mechanism. The most important snap-
back devices in CMOS technology are MOSFETs and silicon-controlled rectifiers.
The grounded-gate configuration is one of the simplest forms of MOSFETs in the
ESD protection circuit where the source and gate are grounded. Figure 9.28a illus-
trates the basic structure of a grounded-gate NMOS (GGNMOS), and Figure 9.28b
shows the I–V characteristic for the GGNMOS [4].
Based on the GGNMOS I–V characteristic, the key device parameters are Vt1, Vh,
Vt2, and It2. There are a few requirements that must be met to establish a robust ESD
protection circuit against a ESD event. To protect the gate-oxide, first the triggering
voltage of Vt1 must be smaller than the breakdown voltage of the gate-oxide during
an ESD stress condition. This will result in a turn-on for a GGNMOS device prior to
the gate-oxide breakdown occurring. Secondly, Vt2 must be greater than Vt1 to ensure
a uniform turn-on mechanism happens on this GGNMOS device. This is a very
important element to ensure that each finger turns on spontaneously with respect
to the voltage build-up before the first finger that turned on first reaches the second
breakdown. Thirdly, It2 should be as high as possible, as it determines the ESD pro-
tection device robustness. Finally, the holding voltage (Vh) must be larger than VDD,
or else, the GGNMOS will easily turn on under normal operating conditions.
Gate-length dependence on the failure current has been reported by several
authors. For example, [5] reported the dependence on gate length through three-
dimensional (3-D) conduction non-uniformity. Work in [6] focused on the experi-
mental results of a MOSFET by means of an energy band diagram and current flow
path analysis. Work in [7] focused on the performance of different concentration
structures through hard failure and soft failure. Based on the traditional parasitic
negative-positive-negative (npn) triggering model under ESD conditions, it is gen-
erally accepted that a MOSFET with a shorter channel length has a higher current
gain, which helps give a better ESD performance. However, contrary to the above

Drain IDrain

(Vt2,It2)
n+ n+
Igen

p-sub
Isub (Vh,Ih)
(Vt1,It1)

(a) (b) VDrain

FIGURE 9.28 GGNMOS: (a) basic structure and (b) I–V curve.
234 CMOS Analog and Mixed-Signal Circuit Design

cases, some experimental results indicated a better ESD performance with a long
channel length. Reference [4] proposed that the better ESD capability for a longer-
gate NMOS was the trade-off between melt volume and power dissipation, not just
the above result of parasitic npn triggering.
Gate length in protection circuits has a big influence on the ESD capability.
This includes the trigger voltage (Vt1), on-state resistance (Ron), failure current (It2),
and leakage current (Ileakage). The gate length refers to the base width of the lateral
parasitic npn. The triggering mechanism is defined by the turn-on of the parasitic
npn by impact ionization:

β ( M − 1) ≥ 1, (9.5)

where β is the common-emitter current gain and M is the multiplication factor. As

the gate length governs the base width of parasitic npn, increasing the gate length
will decrease β. The lower carrier mobility of the p-type device also gives rise to a
lower β, which in turn requires a larger avalanche multiplication factor M, and thus a
larger drain voltage to turn on the npn.
Shunt or clamp circuits are shown in Figures 9.29 and 9.30. Zener diodes are a
classic approach of the shunt or clamp circuit for the VDD and VSS protection. Q1 is
used in an enhanced version to further reduce the dynamic impedance between VDD
and VSS. The diode clamp version is suitable for low voltage applications. The tran-
sient or dynamic clamp can provide an additional shunt path for the current during an
ESD event. The capacitor, C1, is used to couple the rapid ESD pulse onto an internal
control node to turn on the active device. The charge at the control node is finally
discharged through R1, and the clamp circuit is shut off.
Examples of ESD protections are shown in Figures 9.31 and 9.32. The ESD struc-
tures should be able to protect the IC against all ESD pulsing mode and direction.
For mixed-signal IC or multi-supplies ESD, devices are also required between power
buses. This is shown in Figure 9.33. The figure shows the pad ring idea. All possible
paths of ESD zapping events (pin to pin, power to ground in bidirections) are fully
covered in the I/O pads and shunts as well. The pad ring consists of many types of

Vcc
Vcc D1

D2
D1
D3

Vcc Q1
D4
R1
D1 D5
Vss
Vss Vss

Zener Enhanced Zener Diode

FIGURE 9.29 Static shunt.

Peripheral Circuits 235

Vcc Vcc Vcc

C1

C1 R1
G1 Q1
Q2

Q1 C1 Q1
R1 R1
R2

Vss Vss Vss

FIGURE 9.30 Dynamic shunt.

Vcc
D1 D3

Sensitive Internal Supply

Pin 1 Pin 2
Circuitry Clamp

D2 D4
Vss

FIGURE 9.31 ESD example 1.

VDD

ESD

In
ESD

ESD

GND

FIGURE 9.32 ESD example 2.

 236

ESD Schematic

DVDD

AVDD

SHUNT

AVSS

DVSS
PAD_XCLKar0 PAD_TDbt0 PAD_VSSAbt0 PAD_VDDAbt0 PAD_VDDbt1 PAD_RCVRbt1 PAD_GNDbt0 PAD_CORNERbt0 PAD_ANbt1
(DIO) (DO) (DO) (AP) (DP) (DI) (AG) (AIO)

FIGURE 9.33 ESD example of mixed-signal circuit.

CMOS Analog and Mixed-Signal Circuit Design
Peripheral Circuits 237

TABLE 9.2
Pad Ring
Pin Name Type Pad Type Description
1 AVDD AP VDDA Power
2 AGND AP GNDA Ground
3 TEST DI PAD_RCVR Not used. Tie to logic low
4 SLEEP DI PAD_RCVR Active-high synchronous sleep enable. Device goes
into power-saving sleep mode
5 SDAPROM DIO PAD_XCLK I2C EEPROM data in out. Tie to external EEPROM’s
SDA pin
6 SCLPROM DO PAD_TD I2C EEPROM clock output. Tie to external EEPROM’s
SCL pin
7 SDASLV DIO PAD_XCLK I2C slave data in out. Tie to master SDA
8 SCLSLV DI PAD_RCVR I2C slave clock input. Tie to master SCL
9 XRST DI PAD_RCVR Active-low asynchronous reset
10 CLKIO DIO PAD_XCLK CLKIO outputs the internal clock signal if CLKSEL=0.
It inputs an external clock signal if CLKSEL=1
11 CLKSEL DI PAD_RCVR Internal clock mode if CLKSEL=0. External clock
mode if CLKSEL=1
12 DVDD DP VDD Power
13 DGND DP VSS Ground
14 PWM DO PAD_TD Digital output signal
17 ANA0 ANA PAD_An General-purpose analog pin
18 ANA1 ANA PAD_An General-purpose analog pin

Abbreviations: DI, digital input; DO, digital output; DIO, digital input/output (input if control signal is
high); ANA, analog I/O; DP, digital power; AP, analog power.

I/O pads and power pads. The oscillator, POR, and THI (time-high) block are added
into the pad ring as well. An example of the pad ring is shown in Table 9.2.
ESD devices cannot be copied directly from one technology to another technol-
ogy because of the change of the device characteristics. However, the general topol-
ogy can still be applied. A major concern for the radio frequency (RF) application is
the big parasitic capacitance associated with the ESD devices or structure; one has
to carefully trade-off between RF and ESD performance.

9.10 SPICE EXAMPLE

Figure 9.34 shows an 11-stage ring oscillator, while Figure 9.35 is the result of the
ring oscillator. Figure 9.36 depicts a non-overlapping clock circuit. Figure 9.37
shows the result of the circuit. A Schmitt trigger circuit is shown in Figure 9.38,
while Figure 9.39 is the result. Figure 9.40 shows a voltage level shifter. The result
is depicted in Figure 9.41. Figure 9.42 shows the bidirectional pad simulation circuit.
Figures 9.43 and 9.44 show the result.
238 CMOS Analog and Mixed-Signal Circuit Design

11-stage ring oscillator (45 nm).

FIGURE 9.34
Peripheral Circuits 239

1.0x100
Vosc (V)

5.0x10-1

0.0

0.0 1.0x10-9 2.0x10-9

Time (s)

FIGURE 9.35 11-stage ring oscillator result.

FIGURE 9.36 Non-overlapping circuit (0.5 micron).

240 CMOS Analog and Mixed-Signal Circuit Design

6 V(net@10)

4
2
0

V(net@12)
6
4
2
0
V (V)

6 V(net@13)

4
2
0

V(net@14)
6
4
2
0

0 1x10-8 2x10-8 3x10-8

Time (s)

FIGURE 9.37 Non-overlapping clock results (P1 = net10, P2 = net 14).

FIGURE 9.38 Schmitt trigger circuit simulation (45 nm).

Peripheral Circuits 241

1.0

V (V)
0.5

0.0

0 1x10-7 2x10-7
Time (s)

FIGURE 9.39 Schmitt trigger circuit simulation results.

FIGURE 9.40 Voltage level shifter circuit (45 nm).

1.5

V(out)
1.0
V (V)

V(a)

0.5

0.0
0.0 5.0x10-7 1.0x10-6
Time (s)

FIGURE 9.41 Voltage level shifter circuit simulation results.

 242

D_InB D_In
En D_Out
dgnd
dvdd

50 oe 50
100 100
12 12 prep 400
pad
oeb oe oeb 50 25

6 6 pren 200
50 50

25 25
dvdd_1
dgnd_1

FIGURE 9.42 Bidirectional pad (0.5 micron) grid scale is 0.3 micron.
CMOS Analog and Mixed-Signal Circuit Design
Peripheral Circuits 243

V(d_inb)
6

-2

V(d_in)
6

4
V (V)

-2

V(in_pad)
6

-2
0 1x10-7 2x10-7
Time (s)

FIGURE 9.43 Input simulation results.

6
V(out_pad)

0
V (V)

6 V(d_out)

0 1x10-7 2x10-7
Time (s)

FIGURE 9.44 Output simulation results.

244 CMOS Analog and Mixed-Signal Circuit Design

9.11 LAYOUT EXAMPLE

The ring oscillator layout is shown in Figure 9.45. Figure 9.46 shows a non-overlapping
layout, while Figure 9.47 depicts the bidirectional pad layout. The buffer to drive
30 pF load layout is depicted in Figure 9.48.

FIGURE 9.45 13-stage ring oscillator layout.

FIGURE 9.46 Non-overlapping layout.

Peripheral Circuits 245

FIGURE 9.47 I/O bidirectional pad (with ESD).

FIGURE 9.48 Buffer_30pF layout.

246 CMOS Analog and Mixed-Signal Circuit Design

9.12 SUMMARY
This chapter discussed the practices of practical analog and mixed-signal integrated
circuits. The interface circuitries are really very applicable to the real implemen-
tation. The ESD circuit is also practical, nevertheless, it can be extended to the
research domain.

REFERENCES
1. Pooya Forghani-Zadeh, H., and Rincon-Mora, G. A. (2006). Low-power CMOS ramp
generator circuit for DC–DC converters. Journal Low Power Electronics, 2, 1–5.
2. Barr, K. (2007). ASIC Design in the Silicon Sandbox: A Complete Guide to Building
Mixed-Signal Integrated Circuits. New York: McGraw Hill Professional.
3. Camenzind, H. (2005). Designing Analog Chips. Charleston, SC: BookSurge
Publishing.
4. Amerasekera, A., and Duvvury, D. (2002). ESD Protection Circuit Design Concepts
and Strategy. New York: John Wiley & Sons, pp. 105–125.
5. Chen, T.-Y., and Ker, M.-D. (2001). Investigation of the gate-driven effect and substrate-
triggered effect on ESD robustness of CMOS devices. IEEE Transactions on Device
and Materials Reliability, 1(4), 190–203.
6. Bock, K., Russ, C., Badenes, G., Groeseneken, G., and Deferm, L. (1998). Influence of
well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS
technology. IEEE Transactions on Components, Packaging, and Manufacturing
Technology: Part C, 21(4), 286–294.
7. Wu, D.-X., Jiang, L.-L., Fan, H., Fang, J., and Zhang, B. (2013). Analysis on the positive
dependence of channel length on ESD failure current of a GGNMOS in a 5 V CMOS.
Journal of Semiconductors, 34(2), 1–5.
 10 Layout and Packaging

10.1 INTRODUCTION
This chapter discusses the layout technique and packaging information. For a spe-
cific circuit, a layout specifies the position and dimension of the different layers of
materials as they would be laid on the silicon wafer. However, the layout description
is only a symbolic representation, which simplifies the description of the actual fab-
rication process. For example, the layout representation does not explicitly indicate
the thickness of the layers, thickness of oxide coating, amount of ionization in the
transistor’s channels, etc., but these factors are implicitly understood in the fabrica-
tion process. Some of the main layers used in any layout description are n-diffusion,
p-diffusion, poly, metal-1, and metal-2. Each of these layers is represented by a poly-
gon of a particular color or pattern.

10.2 PROCESS
Following the rule of complementary metal-oxide semiconductor (CMOS) process
or CMOS technology is essential in designing a working CMOS integrated circuit.

10.2.1 Antenna Rule
Process-induced damage to the thin gate oxide occurs when conductors charge up
during wafer fabrication. Conductor layers that are exposed to a plasma environment
during processing will charge up and cause a current to be passed through any gate-
oxide areas that are electrically connected to the exposed conductor layers through
lower conductor layers. Since the conductor charge collector area must be greater
than the connected gate oxide area, the conductor can effectively act as an antenna
and amplify the induced gate oxide current. This current can damage the gate oxide,
and that may result in degraded circuit yield and reliability. The damage depends
on the total charge passed through the gate oxide that is proportional to the ratio of
the exposed conductor area divided by the electrically connected gate oxide area.
This quantity is called the charge collector ratio.
Although the fabrication process will be engineered to minimize process-induced
damage, designers need to reduce the sensitivity of their layouts to this damage.
The antenna rule is shown in Figure 10.1.

10.2.2 Electromigration and Metal Density

Electromigration failure affects both signal and power lines, but is particularly impor-
tant in power lines because of the constant direction of the current. As the current flows
through an aluminum interconnection, the average force exerted on the metal atoms by

247
248 CMOS Analog and Mixed-Signal Circuit Design

NMOAT
Poly Metal-1
M1
M2

NMOAT
(a) Vulnerable gate oxide
M1
M2

(b) Metal-1 jumper

FIGURE 10.1 Antenna rule: (a) Vulnerable gate oxide and (b) protected gate oxide.

the electrons leads to a slow migration of those atoms in the direction of electron flow,
causing the line to migrate in the direction of the electrons (opposite to the current flow).
In regions of the metal line where discontinuities occur (e.g., at the naturally occurring
grain boundaries), a void can develop, creating an opening in the line. Fortunately, there
is a current density threshold level (about 1 mA/mm) below which electromigration is
insignificant. Notably, copper, in addition to having a lower resistivity than aluminum,
has a greater resistance to electromigration. Worst case electromigration is encountered
at the highest operating temperatures and current densities (that is, maximum current
electrical models). The maximum current allowed in any metal line is given by:
I = I ’× WD (10.1)
where WD is the drawn width and Iʹ (in mA/µm) is the maximum current per micron
of drawn width. Table 10.1 shows an example of the metals current density.

TABLE 10.1
Metal Current Density
Maximum Line Current Density per Drawn Width 0.35 µm
Process
Maximum Current
Density (mA/µm)
85_C 110_C
Metal 1, 2 Unidirectional 2.52 1.20
Bidirectional 3.78 1.81
Metal 3 Unidirectional 3.29 1.58
Bidirectional 4.94 2.36
Layout and Packaging 249

The metal density is a metal coverage area in a layout. The percentage is normally
used to identify the density of any given metal. The minimum density is typically
higher than 60%.

10.2.3 Shear Stress

Silicon is a piezoelectric crystal. Stress affects the electrical parameters. Chips are
packaged at high temperatures using materials having thermal coefficients different
than silicon. When the package cools to room temperature, stress gradients upset
matching. Wafers used in the bipolar process are cut in the {111} plane. The CMOS
process uses wafers cut in the {100} plane. See Figures 10.2 and 10.3 for a bipolar
process technology example.
<211>
Direction

4 5 6 7 8 7 65 4

Poor
Match

{111}
Plane

Good
Match 9
10 11 12
Isostress lines

FIGURE 10.2 Stress 1.

<211>
Direction

Wafer flat
along the
(110) axis

{111}
Plane

FIGURE 10.3 Stress 2.

250 CMOS Analog and Mixed-Signal Circuit Design

10.3 FLOOR PLANNING

A proper layout requires proper floor planning. An example of a mixed-signal design
floor plan is shown in Figure 10.4 [1], while Figure 10.5 shows a decoupling capaci-
tor strategy. N-type metal-oxide semiconductor (NMOS) and metal-oxide semicon-
ductor capacitor (MOSCAP) can be used here. Figure 10.6 shows the logic circuit
layout planning concept. The strategy of mixed-signal layout strategy is shown in
Figure 10.7.

Sensitive analog

Medium- swing analog

High- swing analog

Low- speed digital

High- speed digital

Output drivers

FIGURE 10.4 Example of a mixed-signal floorplan.

Bonding Interconnect
inductance On-chip decoupling capacitor resistance
Pin Pad Pad Pin
Analog circuitry

VDD
Off-chip decoupling capacitor
+ –

Digital circuitry
Pin Pad Pad Pin
On-chip decoupling capacitor for the decoupling circuitry

FIGURE 10.5 Showing how decoupling capacitors are used in a mixed-signal chip.
Layout and Packaging 251

Vdd
Gnd
PMOS

channel
Wiring
A B C
P-type
substrate
Transistor
channel
}
Out Y Vdd A B C Y

NMOS
B Transistor
channel

N-type C
substrate Gnd

Gnd (a) (b)

FIGURE 10.6 Layout planning: (a) Representation without regard to layout and (b) layout
friendly.

Interconnect
considerations Interconnect level
Shielding

Guard rings
Device level
Fully differential design/Matching
Power supply and grounding issues
Floor planning
System level

FIGURE 10.7 Mixed-signal layout strategy.

10.4 ESD AND I/O PAD LAYOUT

10.4.1 Low Parasitic Capacitance Pad
For high frequency application, a low parasitic capacitance pad must be used in the
chip design. Based on Figure 10.8, to reduce parasitic capacitance, only top metals
are utilized. Figure 10.9 shows the concept of electrostatic discharge (ESD) diodes
and pads. In this case, the pad is metal 1. As usual, a simple PN junction diode
is used as an ESD diode (Chapter 9). The power ring, supply voltage (VDD), and
ground line use metal 1 as well.

10.4.2 Seal Ring

Metals are normally used to create the outer line called the seal ring. The seal ring
is used to ensure the structure of the chip remains intact after the sawing process.
Thus, it forms some sort of physical barrier between the saw street and the chip.
Figure 10.10 shows the seal ring of a typical integrated circuit (IC) layout.
252 CMOS Analog and Mixed-Signal Circuit Design

Layout or top view

100 μm (Final size)

Metal 2 Top of the wafer

or die
Cross-sectional view
100 μm (final)

Insulator
Insulator
Insulator
FOX
p-substrate

FIGURE 10.8 Low parasitic capacitance pad.

Pad metal 1

N-well

N-select
P-select

P-select N-select

Vial 1

Connected to VDD pad

Metal 2

Vial 1 Connected to ground pad

Metal 2 connection to the pad

from the chip’s circuitry

FIGURE 10.9 Conceptual layout of a pad ESD protection circuit.

Layout and Packaging 253

* Large Power Busses

Surround Die

* ESD in PADS

* Driver/Logic in
Pads

* Seal Ring

FIGURE 10.10 Pad frame.

10.5 ANALOG CIRCUIT LAYOUT TECHNIQUE

10.5.1 Matching
Matching improves when components are located close together and have the same
orientation. This minimizes mismatch due to lateral process variations. This is
shown in Figure 10.11 [2].
The presence of a power dissipating component on the chip affects matching.
A large resistor or transistor dissipating power causes temperature gradients on the
chip. This is described in Figure 10.12. A cross-coupled quad layout reduces mis-
match (Figure 10.13) in the presence of lateral variations. Breaking a component into
four parts and laying them out so opposites are linked reduces mismatch, as well as
interdigitated devices. This is depicted in Figure 10.14.

(a) (b) (c)

FIGURE 10.11 Orientation: (a) Best match, (b) moderate match, and (c) worst match.
254 CMOS Analog and Mixed-Signal Circuit Design

ISOTHERMAL LINES

HEAT SOURCE

POOR GOOD
MATCH MATCH

FIGURE 10.12 Temperature gradient.

1 2 3 4 5

6
R1 R2
7

Increasing
8
sheet
resistance
9

10
R3 R4
11

FIGURE 10.13 Cross-coupled.

RB
RA

A B A B

FIGURE 10.14 Layout of interdigitated resistors.

10.5.2 Guard Ring
The purpose of a guard ring is to collect carriers. It is obviously needed for PN
junction-based devices. It can reduce the latch-up condition and noise or inter-
ference in the guard ringed device. The guard ring is also used for the n-well
resistor. This is shown in Figure 10.15. A NMOS-based circuit or PMOS-based
circuit can also be guard ringed, see Figure 10.16.
Layout and Packaging 255

N+ P-select

N-well Connected to
ground

P+

FIGURE 10.15 Guard ring n-well resistor.

N+ Guard Ring vdd

P+ Guard Ring

N-well
NMOS PMOS
P+ Diffusion
Circuits Circuits
N+ Diffusion
Contact

vss

FIGURE 10.16 Guard ring NMOS and PMOS.

10.5.3 Shielding
Shielding is an effort to shield the analog path or signal from a noisy signal. This is
shown in Figure 10.17. In this example, metal 1 is used to “shield” the analog signal
(poly1) from a noisy digital signal (metal 2). The metal 1 is connected to the ground.

10.5.4 Voltage (IR) Drop

The concept of an “analog ground” is often misunderstood. It is meant to be a noise-
free point (or hub), a spot either on the circuit board or on the IC which can be
used as a 0-Volt reference. The usual practice designates a pin that carries little or
no current as the analog ground; other pins, intended to be at the same potential,
but carrying current are then connected to this point on the circuit board. There is
another way to achieve this, one which saves a pin and has better performance.
A package pin has low resistance, lower than a trace on a circuit board or a metal
run on the IC. Designate a pin as the analog ground, and then connect not one, but
two neighboring pads to it with separate bonding wires: one carries no current and
serves as the analog reference ground on the IC, the other carries the potentially
256 CMOS Analog and Mixed-Signal Circuit Design

Metal 1 shield (tied to

analog ground)

Top view Digital signal

Analog signal

Cross section Metal 2

Metal 1 Insulator
Poly 1 Insulator

FIGURE 10.17 Shielding.

(a) (b)

FIGURE 10.18 Metal connection: (a) bad for matching devices and (b) good for matching
devices.

polluting currents. Similarly, on the IC, use separate metal runs to connect sensitive
devices. In Figure 10.18, the left-hand connection (Figure 10.18a) can create an error.
Figure 10.18b is for matching device connection.
Assume the runs lead to emitters/sources carrying 1 mA. With, say, 50 squares
of additional aluminum for the upper device, if the resistance is:
L
R = Sheet Resistance × (10.2)
W

where Sheet Resistance is 30 mΩ/sq, L and W are metal length and width, respec-
tively. So, using Equation 10.2, creating a current mismatch of 6% at room tempera-
ture. With the balanced connection on the right, this is avoided.
Layout and Packaging 257

METAL
OXIDE

P TYPE RESISTOR
N TYPE EPI TUB

FIGURE 10.19 Metal over implant.

10.5.5 Metal over Implant

Metal over ion implant resistors form a p-channel MOS transistor with the metal as
a gate. A positive voltage on the metal restricts resistor current flow. This is depicted
in Figure 10.19.

10.5.6 Substrate Tap

All substrate taps which p-substrate for standard CMOS process technology must be
connected to negative-type signals.

10.6 DIGITAL CIRCUIT LAYOUT TECHNIQUE

10.6.1 Power Distribution for Mixed-Signal Design
Another issue in power distribution concerns ground bounce (or simultane-
ous switching noise), which is increasingly problematic as the number of
­application-specific integrated circuit (ASIC) input/output (I/O) data pins
increases. Consider M output lines switching simultaneously to the 1 state, each
of those lines outputting a current transient I(out) within a time t(out). (If M out-
put lines switch simultaneously to the 0 state, then a corresponding input current
transient is produced.)
The net output current M · I(out) is fed through the Vdd pin (returned to the
ground in the case of outputs switching to 0). The transient voltage imposed on
Vdd is:

Iout
V = L× M (10.3)
tout

where L is an inductance associated with the Vdd pin. A similar effect occurs on the
ground connection for outputs switching to 0. With a total output current of 200 mA/
ns and a ground pin inductance of 5 nH, using Equation 8.3, the voltage transient is
about 1 V. The voltage transient propagates through the IC, potentially causing logic
blocks to fail to produce the correct outputs. The transient voltage can be reduced by
reducing the power line inductance L, for example, by replacing the single Vdd and
Gnd pins by multiple Vdd and Gnd pins, with K voltage pins reducing the inductance
by a factor of K. See Figure 10.20 [3].
258 CMOS Analog and Mixed-Signal Circuit Design

Vdd
Gnd

Channel
Wiring
Additional Level of
Distribution Vdd
PMOS Transistors (Pull-up)

NMOS Transistors (Pull-down)

Vdd
Gnd
(a) (b)

FIGURE 10.20 Power and ground distribution (interdigitated lines) with rows and logic
cells and rows of wiring channels: (a) overall power distribution and organization of logic
cells and wiring channels and (b) local region of power distribution network. (Redrawn from
Brewer, J.E. et al., Integrated Circuits: The Electrical Engineering Handbook, R. C. Dorf
(Ed.), CRC Press LLC, Boca Raton, FL, 2000.)

10.6.2 Clock Distribution

The distribution becomes a performance bottleneck for high speed very large‐scale
integration (VLSI). The primary source of the load for the clock signals has shifted
from the logic gates to the interconnect, thereby changing the physical nature of the
load from a lumped capacitance to a distributed resistive-capacitive load.
The distance over which the clock signal can travel before incurring a delay
greater than the clock skew defines isochronous regions within the IC. If the external
clock can be provided to such regions with zero clock skew, then clock routing within
the isochronous region is not critical. Figure 10.21a illustrates the H-tree approach,

(a) (b) (c)

FIGURE 10.21 Clock distribution. (a) Example of single driver and isochronous regions.
(b) Example of distributed drivers. (c) Example of clock distribution with unequal line lengths
but within skew tolerances.
Layout and Packaging 259

whose clock paths have equal lengths to terminal points, ideally delivering clock
pulses to each of the terminal points (leaf nodes) of the tree simultaneously (zero
skew).
In a real circuit, precisely zero clock skew is not achieved since different network
segments encounter different environments of data lines coupled electrically to the
clock line segment.
In Figure 10.21a, a single buffer drives the entire H-tree network, requiring a
large area buffer and wide clock lines toward the connection of the clock line to the
external clock signal. Such a large buffer can account for up to 30% or more of the
total VLSI circuit power dissipation. Figure 10.21b illustrates a distributed buffer
approach, with a given buffer only having to drive those clock line segments to the
next level of buffers. In this case, the buffers can be smaller and the clock lines can
be narrower.
Figure 10.21c, the clock network uses multiple buffers, but allows different path
lengths consistent with clock skew margins. For tight margins, an H-tree can be used
to deliver clock pulses to local regions in which distribution proceeds using a differ-
ent buffered network approach such as that in Figure 10.21c.

10.6.3 Latch-up
Parasitic transistors turn on, producing a low resistance path between power
rails. Large currents flow causing thermal destruction. Processing, layout, and
circuit design techniques, can be properly applied to make latch-up unlikely.
The structure of CMOS creates parasitic transistors that can cause latch-up.
The concept of parasitic devices is shown in Figure 10.22. Figure 10.23 shows
a layout method to avoid latch-up. Well tap is used to connect to either ground
or VDD.

In
NMOS ,M1 PMOS ,M2
Well connection
Substrate connection
VDD
Out

p+ n+ n+ C1 p+ p+ n+
Q2
RW 2 Q1 RW 1
n- well
C2

RS2 RS1

p- substrate

FIGURE 10.22 Cross-sectional view of an inverter showing parasitic bipolar transistors

and resistors.
260 CMOS Analog and Mixed-Signal Circuit Design

VDD

Place PMOS here

n+ well tie-down

VDD

Ground

Place NMOS here

p+ well tie-down

Ground

FIGURE 10.23 Adding an extra implant between NMOS and PMOS to reduce latch-up.

10.7 PACKAGING
Packaging of electronic circuits is the science and the art of establishing intercon-
nections and a suitable operating environment for predominantly electrical cir-
cuits. It supplies the chips with wires to distribute signals and power, removes
the heat generated by the circuits, and provides them with physical support and
environmental protection. It plays an important role in determining the perfor-
mance, cost, and reliability of the system. With the decrease in feature size and the
increase in the scale of integration, the delay in on-chip circuitry is now smaller
than that introduced by the package. Thus, the ideal package would be one that
is compact, and should supply the chips with a required number of signal and
power connections, which have minute capacitance, inductance, and resistance.
The package should remove the heat generated by the circuits. Its thermal proper-
ties should match well with a semiconductor chip to avoid stress-induced cracks
and failures. The package should be reliable, and it should cost much less than the
chips it carries.

10.7.1 Die Attach

Wire bonding (see Figure 10.24) is a method used to connect a fine wire between
an on-chip pad and a substrate pad. This substrate may simply be the ceramic base
of a package or another chip. The common materials used are gold and alumi-
num. The main advantage of wire bonding technology is its low cost; but it can-
not provide large I/O counts, and it needs large bond pads to make connections.
Layout and Packaging 261

WIRE
CHIP ON-CHIP PAD

ADHESIVE
SUBSTRATE
SUBSTRATE ............. PAD
.. .. .. .. .. .. .. .. .. .. .. .. ..

FIGURE 10.24 Wire bonding.

BONDING PAD
CHIP
SOLDER BUMP

SUBSTRATE or CHIP

FIGURE 10.25 Solder bump.

The connections have relatively poor electrical performance. The solder bump is
another approach. This is shown in Figure 10.25. Solder bumps are small spheres
of solder (solder balls) that are bonded to contact areas or pads of semiconductor
devices and subsequently used for face-down bonding. The length of the electrical
connections between the chip and the substrate can be minimized by placing sol-
der bumps on the die, flipping the die over, aligning the solder bumps with the con-
tact pads on the substrate, and re-flowing the solder balls in a furnace to establish
the bonding between the die and the substrate. This technology provides electrical
connections with minute parasitic inductances and capacitances. In addition, the
contact pads are distributed over the entire chip surface rather than being confined
to the periphery. As a result, the silicon area is used more efficiently, the maximum
number of interconnects is increased, and signal interconnections are shortened.
But this technique results in poor thermal conduction, difficult inspection of the
solder bumps, and possible thermal expansion mismatch between the semiconduc-
tor chips and the substrate.

10.7.2 Package Type
The package with leads is shown in Figure 10.26. Figure 10.27 is a leadless package.
Figure 10.28 is chip scale package (CSP). CSPs can be divided into two categories:
the fan-in type and the fan-out type.
Fan-in type CSPs are suitable for memory applications that have relatively low
pin counts. This type is further divided into two types, depending on the location
of bonding pads on the chip surface; these are the center pad type and the periph-
eral pad type. This type of CSP keeps all the solder bumps within the chip area by
arranging bumps in an area array format on the chip surface.
262 CMOS Analog and Mixed-Signal Circuit Design

Packaged chip

Chip lead

Through hole via

PCB

Solder

FIGURE 10.26 Lead package.

Molding compound
Die Gold wire

Lead Lead
Exposed die pad
Down bond Silver epoxy

FIGURE 10.27 Leadless package.

CHIP
SOLDER BUMP

Solder balls

FIGURE 10.28 CSP.

The fan-out CSPs are used mainly for logic applications: because of the die size to
pin count ratio, the solder bumps cannot be designed within the chip area.
Figure 10.29 shows the image/color sensor package. A clear compound is dis-
posed over the IC active area. A transparent glass cover is disposed over the clear
compound on the IC active area. Light may pass through the cover and the clear
compound onto the IC active area.
Layout and Packaging 263

Molding compound Gold wire

Lens/Filter/
Clear
compound
Die
Lead Lead
Exposed die pad
Down bond Silver epoxy

FIGURE 10.29 Color or image package.

10.7.3 Package Parasitic
See Figure 10.30. Typically, the electrical interconnection of a chip in a package
consists of chip-to-substrate interconnect, metal runs on the substrate, and, finally,
pins from the package. Associated with these are the electrical resistance, induc-
tance and capacitance—referred to as package parasitics. The electrical parasitics
are determined by the physical parameters, such as interconnect width, thickness,
length, spacing, and resistivity; by the thickness of the dielectric; and by the dielec-
tric constant.
Resistance refers to both direct current (DC) and alternating current (AC).
The DC resistance of an interconnect is a property of its cross-sectional area, length,
and material resistivity.
In addition, the AC resistance depends on the frequency of the signal and is higher
than the DC resistance because of the skin effect.
Resistance in the power distribution path results in the attenuation of input signals
to the device and output signals from the device. This has the effect of increasing
the path delay.
The capacitance of an interconnect is a property of its area, the thickness of the
dielectric separating it from the reference potential, and the dielectric constant of the

Package

Chip Bond wire Lead frame Board

VDD VDD
Signal pads
Signal pads

Package
Chip capacitor

Chip Board
GND GND

FIGURE 10.30 Parasitic model of package.

264 CMOS Analog and Mixed-Signal Circuit Design

dielectric. It is convenient to consider this as two parts: capacitance with respect to

ground and capacitance with respect to other interconnections.
The capacitance with respect to ground is referred to as the load capacitance.
This is seen as part of the load by the output driver and thus can slow down the rise
time of the driver. Interlead capacitance couples the voltage change on the active
interconnect to the quiet interconnect. This is referred to as crosstalk.
Inductance can be defined only if the complete current path is known. In the
context of component packages, the inductance of an interconnect should be under-
stood as part of a complete current loop. Thus, if the placement of the package in
the system alters the current path in the package, the package inductance will vary.
Total inductance consists of self-inductance and mutual inductance. Mutual induc-
tance between two interconnects generates a voltage in one when there is the current
change in the other.
Inductive effects are the leading concern in the design of a power distribution path
in high-performance packages. They are manifested as “ground bounce” noise and
“simultaneous switching” noise.

10.8 SUMMARY
In this chapter, the fundamental of layout and packaging is introduced. Careful plan-
ning of layout and packaging can lead to a very successful design or product. Even
though no modern tool is introduced in this chapter, the knowledge provided is ben-
eficial for the layout designer. The package information is essential for the circuit
designer.

REFERENCES
1. Baker, R. J. (2010). CMOS: Circuit Design, Layout, and Simulation (3rd ed.). Wiley-
IEEE Press. doi:10.1002/9780470891179.
2. Daly, J. C., and Galipeau, D. P. (1999). Analog BiCMOS Design: Practices & Pitfalls.
Boca Raton, FL: CRC Press.
3. Brewer, J. E., Zargham, M. R., Tragoudas, S., and Tewksbury, S. (2000). Integrated
Circuits: The Electrical Engineering Handbook, R. C. Dorf (Ed.). Boca Raton, FL:
CRC Press LLC.
Index
A oxide, 30–31, 36–38
storage, 5
accumulation, 10–11 carrier drift velocity models, 32–33
active integrator, 138–139, 141 cascode biasing, 66
active load, 61, 65–66, 107, 109, 111 cascode current source, 66, 124–125, 129
ADC example, 186 CCD, see charge-coupled device
aluminum, 247–248, 256, 260 channel
analog CMOS, 3 long, 9, 18, 41–42
analog ground, 193, 255–256 short, 34
analog signal, 255–256 channel length modulation, 24, 26–27, 54, 117
analog-to-digital converter, 167, 176 charge, 5, 7, 12–13, 16–19, 21, 24–25, 29–30, 36–37,
antenna rule, 247–248 39, 105, 109, 135–141, 143–144, 146–
148, 195, 205, 218–219, 221, 234, 247
B injection, 135, 144
charge-coupled device, 195
backside illumination, 176, 195–196 chip design, 251
band chip scale package, 261, 264
conduction, 5–6, 10 chopper amplifier, 135, 152–154, 164
valence, 5–6, 10 circuit design, 1, 4, 259, 264
bandgap voltage reference, 121 clamp, 127, 234–235; see also shunt
bandwidth, 86–88, 91, 98–99, 150, 152, 157 classic boost circuit, 228
base-emitter voltage, 119, 122 CLM, see channel length modulation
basic switched capacitor, 136 clock, 136–144, 149, 152, 154–156
beta multiplier reference, 129 skew, 258–259
bidirectional, 224–225, 237, 242, 244–245 CMOS color sensor, 195, 198, 213
binary-weighted resistor, 169–170, 172 CMOS image sensor architecture, 202
bipolar, 225, 227 CMOS process, 249, 257
process, 249 CMRR, see common mode rejection ratio
transistor, 31, 105, 122, 153 color filter array, 8
BMR, see beta multiplier reference color selection, 201
body effect, 18, 54, 56–58 column-level ADC, 202–203
bonding, 250, 255, 260–261 common mode feedback, 79–80, 145, 149
bond wire, 263 common mode rejection ratio, 73
boost circuits, 227–229 common mode voltage, 147, 201
bottom plate sampling, 145 comparator, 4, 156, 177–180, 183, 190, 204, 208,
breakdown, 119, 121 218–219
voltage, 233 compensation, 61, 65, 73, 81–82
BSI, see backside illumination complementary to absolute temperature, 119
buffer, 219, 221, 225, 244–245 conductance, 135, 150
built-in potential, 16 constant-transconductance, 127
bulk-driven, 103 constant-voltage scaling, 28, 30–31
continuous integrator, 138–139
C controller, 217, 222
control signal, 199–201
calibration, 173–175 control voltage, 158
capacitance conversion factor, 205
depletion layer, 5 copper, 248
junction, 35, 37–40 correlated doubled sampling, 203
overlap, 36–37 coupling capacitor, 104

265
266 Index

cross-coupling/cross-coupled, 109–114, 253–254 differential signal, 79

CSP, see chip scale package differential topology, 109, 111
CTAT, see complementary to absolute differential transfer function, 148
temperature differential voltage(s), 62–63, 201
current amplifier, 85, 128 diffusion current, 105
current consumption, 61, 70, 72 digital buffer, 225
current density, 248 digital CMOS, 3
design approach, 100 digital ground, 193
current efficiency, 106, 114 digital signal(s), 195, 202, 255–256
current gain, 40, 106, 126, 153–154, 233–234 processor, 198
current generator, 128 digital-to-analog converter, 167–168
current integration topology, 199 diode-connected load, 65
current path, 108–109 diode-less voltage reference, 122
current reuse CMOS amplifier, 107 diode(s), 120–122, 126–128, 227–228, 232,
current sources, 117, 119–120, 124–125, 128–130 234, 251
current steering, 169 discharge, 208, 217–219, 229, 232
current to frequency topology, 198 distortion, 77, 79
current-voltage characteristics, 19, 21, 24, 26 distributed resistive-capacitive load, 258
current-voltage equation, short channel distribution
transistor, 34 clock, 258
cut-off, 36–38 power, 257–258, 263–264
DMOS, see double diffused metal-oxide
D semiconductor
DNL, see differential non-linearity
DAC example, 186 doping, 10, 28–31
DAC offset, 173–174 double diffused metal-oxide semiconductor, 126
DAC trimming, 173 dynamic element matching technique, 153
daisy chain, 222 dynamic impedance, 234
dark current, 9, 196, 213 dynamic range, 195, 202, 205, 213
DC Gain, 75
decoder, 168 E
decoupling capacitor, 250
degeneration inductor, 109 effective number of bits, 167
delay, 217, 221–222, 229–230, 232 effective transconductance, 108–109
delta gate source voltage, 123 electromigration, 247–248
delta sigma ADC, 183, 186 electron, 5–6, 10–11, 13, 21, 32–33, 75, 205, 248
depletion, 5–7, 10–18, 20, 22, 25, 31, 37–39, electrostatic discharge, 232, 251–253
105–106 encoder, 178
design, 1–4, 117–118, 125, 127–129 energy band diagram, 10–13, 233
example, 127 ENOB, see effective number of bits
flow, 197 equivalent resistance, 141
insight, 61 error amplifier, 125
for manufacturability, 2 error correction, 180–181, 183, 190
methodology, 197 ESD, see electrostatic discharge
for test, 2 exposures, 203
transfer, 5, 44
D-Flip-Flop, 220, 222 F
die attach, 260
differential amplification, 138, 141 failure
differential amplifier, 62–63, 69, 80 hard, 233
differential circuit, 201 soft, 233
differential common-gate, 114 fc, 75
differential gain, 73 feedback, 220, 233
differential input, 146 capacitor, 146–147, 150, 205
differential non-linearity, 167 control, 156
differential output, 145, 149–150 local, 86, 88–89
differential pair, 96–97, 207 resistor, 111, 125, 198
Index 267

series, 86, 89 interconnection, 247, 261, 263–264

signal, 156 interdigitated devices, 253
voltage, 156 internal node, 119
Fermi level, 5, 10, 13 inversion, 10, 13, 15–16, 19, 21–22, 24–25, 31–32,
Fermi potential, 10, 18 36, 52–53, 135
FETs, 9 inverter, 217, 221, 226, 259
figure of merit, 41 inverting active integrator, 141
fill factor, 195, 202
filter, 152 L
filtering temporal noise, 183
finite gain, 146 latch-up, 254, 259–260
fixed pattern noise, 203, 205, 209 lateral variations, 253
flash ADC, 178, 183 layout, 247, 249–251, 253–254, 257, 259, 264
flicker noise, 152, 209 examples, 100, 133
floor plan/planning, 192–193, 250–251 strategy, 250–251
free space, 10 leadless package, 261–262
frequency response, 61, 64, 81–82 lead package, 262
f T , 75 leakage power, 3
full scaling, 28–30 linearity, 3, 103
linear region, 19–24, 27, 61
G LNA, see low noise amplifier
loop response, 75–76, 81
gain-boosting, 110 low drop regulator, 127
gain enhancement, 66 low noise amplifier, 107
gain margin, 82 low noise technique, 208–209
gate-oxide, 31, 105–106, 233, 247 low power, 100–101
glitches, 169, 175–176, 219 technique, 208
gm-boosting, 110–111 low voltage CMOS amplifier
ground bounce, 257, 264 body/bulk control, 103
guard ring, 251, 254–255 circuit technique, 104
lumped capacitance, 258
H
M
half-circuits, 110–111
harmonic, 77, 79 matching, 249, 251, 253, 256
high frequency amplifier, 104 maturity, 2
hold cycle, 146–149 metal density, 247, 249
holding, 145, 148–149 metal over implant, 257
hybrid topology, 169 metal-oxide semiconductor capacitor, 221, 250
hysteresis, 227 migration, 248
Miller effect, 64–65, 86
I Miller-zero, 82
MIM capacitor, 3
inductance, 250, 257, 260–261, 264 mixed-mode simulation, 197
inductor, 3, 109 mixed-signal, 1, 3–4
inductorless topology, 111 mobility, 21, 32, 109, 169, 234
INL, see integral nonlinearity monotonicity, 167, 169
in-phase, 109 MOSCAP, see metal-oxide semiconductor
input offset, 70 capacitor
input signal, 64, 85 MOS device(s), 106, 227
input transistor, 61, 75 MOSFET, 2, 5, 10, 13–16, 18, 21, 26, 28–31,
input voltage range, 61, 63, 70–72 35–36, 40–42, 46, 58, 122–123, 135,
instability, 65 152, 233
integral nonlinearity, 167 capacitor, 35
integrated circuit, 1–3, 106, 198, 229, 247, 251, 257 parameter, 46, 58
integration period, 199, 206 scaling, 28
integrator, 199, 201 transition frequency, 40
268 Index

MOS operation, 13 P
MOS structure, 9, 11–13, 15
MOS transistor, 18, 24, 31, 33, 105–106, 114, 135, package parasitic, 263
152, 257 pad
most significant bit, 167, 182 analog, 225
MSB, see most significant bit bidirectional, 225, 237, 242, 244–245
multiple Vdd, 257 I/O, 225, 234, 237, 251
multiplication, 65, 179, 207, 234 low parasitic capacitance, 251
multistage, 228 output, 225
parallel, 222–223
parallel to serial interface, 222
N parasitic bipolar transistors, 259
parasitic capacitances, 136, 139, 142–143, 197, 237
NF, see noise figure parasitic npn, 234
NMOS, 19, 27, 31, 35, 44–46, 50, parasitic transistors, 259
52–55, 58 passive loads, 109
noise figure, 110 pass transistor, 125–126
noise(s), 61, 73, 75, 77–78, 90–99, 101 phase margin, 82
in amplifiers, 90 phase shift, 64, 82
in amplifier with resistors in feedback, 97 photocurrent, 195, 201, 206–207
bandwidth, 98–99 photo devices, 5, 8, 197
in circuits, 90 phototransistor, 8, 197
in differential pairs, 96 pinch-off, 19, 20, 24–25
flicker, 42–43 pinned photodiode, 8–9
in single-stage amplifiers, 92 pipelined ADC, 179, 181–182
thermal, 41 pixel-level ADC, 202–203
non-inverting active integrator, 144–145 pixel sensor
non-linear, 27, 135, 144 analog, 205
non-linearity, 137 digital, 202, 208
non-overlapping generator, 220 pixel size, 196–197
novelty, 1–2 plasma environment, 247
PMOS, 45–46, 48–55, 57, 103, 107–109, 111, 129,
135–136, 150, 153, 158, 169, 209, 227,
O
251, 254–255, 258–260
off current, 54 transistor, 45–46, 61, 108–109, 111, 136, 150,
on-chip, 18, 208, 260–261 153, 169
design, 156 PN junction, 5–7
on current, 58 diode, 251
1.5-bit stage, 181, 183, 186 POR, see power on reset
on-state resistance, 234 positive feedback, 233
on-voltage, 232 power consumption, 103–104, 111, 114, 168–169,
operational transconductance amplifier, 208 186, 195, 204, 208–209, 213
oscillator(s), 117, 156 power on reset, 229–230
ramp, 218 power supply rejection ratio, 73
RC, 217–219 precharge, 199, 201–202
ring, 217, 237–239, 244 predictive technology model, 49–51, 53
out-of-phase, 109, 114 process, voltage, and temperature, 117
output impedance, 129 process fitting ratio, 43
output resistance, 65–66, 68–69, 73, 93, 117, process variation, 118
124, 150 programmable gain amplifier, 146
overall signal path, 64 propagation delays, 3, 217
overdrive, 53, 136 proportional to absolute temperature, 119
overlapping clock generator, 221 PSI, see parallel to serial interface
oversampling, 209 PSRR, see power supply rejection ratio
overshoot, 127 PTAT, see proportional to absolute temperature
oxide thickness, 9, 29, 47 PTM, see predictive technology model
Index 269

pulse response, 82 signal path of CMOS operational amplifier,

pulse width modulation, 201 example, 66
PVT, see process, voltage, and temperature signal to noise and distortion ratio, 167
PWM, see pulse width modulation silicon-controlled rectifier, 233
silicon substrate, 10, 17, 31, 105
single-ended, 69, 100, 158, 160–161, 184
Q single-pole double-throw electronic switch, 168
quantum efficiency, 8, 196–197 slew rate, 73–74
slope ADC, 176
small-signal, 107
R snapback, 233
SNDR, see signal to noise and distortion ratio
radio frequency (RF), 3, 104, 237
source follower, 95–96, 126
matching, 104
spatial resolution, 195
signals, 110
speed, 168, 179, 186, 193
ramp, 176–177
SPI, see serial peripheral interface
generator, 218, 220
spice example, 54, 111, 129, 158
signal, 156, 199
stability, 64, 81–82, 84, 125, 129
regenerative latch, 208
stages, 84, 86, 89–90
registers, 229
start-up circuit, 129
regulated power supply, 125–127
strong inversion, 105–106
reliability, 247, 260
substrate tap, 257
residue amplifier, 162–164, 180, 182–183, 185
subthreshold, 207–208
resistor-less current reference, 155
biasing, 104–106, 114
resistor string topology, 168
region, 31, 155–156
resolution, 167, 178–182, 193, 195–196, 201–202
surface potential, 12, 15
switch, 135–136, 138, 143–144, 150, 152,
S 154–156, 164
switchable current source, 129, 169–171, 190–191
sample-and-hold (S/H), 145, 201 switch-mode converter, 156
sample cycle, 146, 148–150 synchronization, 222
sampling, 145–150 system level, 251
SAR ADC, 177
saturation current, 23, 26, 34
saturation region, 19, 21, 23–24, 26–27, 105, 114, T
117, 124
sawing, 251 temperature gradient, 253–254
saw street, 251 temperature variation, 123, 128, 133
Schmitt trigger, 225–227, 237, 240–241 temporal noise, 202
seal ring, 251, 253 thermal coefficients, 249
segmented, 167 thermal noise, 152, 169, 209
self-biasing/self-biased, 119, 155 thermometer code, 167, 171
self-inductance, 264 threshold voltage, 15, 17–19, 26–27, 29, 31–32,
self-regulating, 157 44, 46, 54
sensitivity, 9, 195, 197, 205, 247 through silicon via, 196
serial, 222–225 timer, 217, 219
serial peripheral interface, 222 time response, 198
series regulator, 126–127 timing, 149, 157
settling time, 73–74 trade-off, 3, 86–87, 103, 186, 204, 234, 237
shear stress, 249 transconductance, 103, 106–109
sheet resistance, 254, 256 parameter, 29–30, 44, 47
shielding, 251, 255–256 transient voltage, 257
shift register, 222 transimpedance amplifier topology, 198
shunt, 234–236 transistor model, 46
signal flow, 64 transition frequency, 40–41, 66, 75, 106
signal integrity, 3 trigger voltage, 234
270 Index

U W
unity-gain bandwidth, 150 wafer, 247, 249, 252
weak inversion, 31–32, 104, 114, 123, 208
wideband amplifier technique, 84
V wideband differential LNA, 110–111
work function, 10, 15–16
variable resistor, 126
VBE, see base-emitter voltage
VDD variation, 128 Y
VDSAT, 21, 24, 33 yield, 247
voltage-controlled oscillator, 119
voltage gain, 107 Z
voltage-mode, 168, 174
voltage regulator, 125–126 Zener diode, 121, 126–127