Hardware Description Languages Compared: Verilog and SystemC

Gianfranco Bonanome
Columbia University
Department of Computer Science
New York, NY

Abstract This library encompasses all of the necessary

components required to transform C++ into a
As the complexity of modern digital systems hardware description language. Such additions
increases, engineers are now more than ever include constructs for concurrency, time notion,
integrating component modeling by means of communication, reactivity and hardware data
hardware description languages (HDLs) in the types.
design process. The recent addition of SystemC to As described by Edwards [1], VLSI
an already competitive arena of HDLs dominated verification involves an initial simulation done in
by Verilog and VHDL, calls for a direct C or C++, usually for proof of concept purposes,
comparison to expose potential advantages and followed by translation into an HDL, simulation of
flaws of this newcomer. This paper presents such the model, applying appropriate corrections,
differences and similarities, specifically between hardware synthesization and further iterative
Verilog and SystemC, in effort to better categorize refinement. SystemC is able to shorten this
the scopes of the two languages. Results are based process by combining the first two steps.
on simulation conducted in both languages, for a Consequently, this also decreases time to market
model with equal specifications. for a manufacturer.
Generally a comparison between two
computer languages is based on the number of
Introduction lines of code and execution time required to
achieve a specific task, using the two languages. A
Continuous advances in circuit fabrication number of additional parameters can be observed,
technology have augmented chip density, such as features, existence or absence of constructs
consequently increasing device complexity. This that facilitate coding, availability of optimization
has resulted in a higher degree of design techniques, as well as others. These criteria vary
automation and increase in the number of tools slightly when attempting to compare two HDLs.
available to an integrated chip designer. Recently For instance, HDLs need to have time-handling
there has been an incline toward the usage of constructs, unlike most other computer languages.
Hardware Description Languages [3]. The Comparable “building blocks” may synthesize into
portability of models created with such tools, has different circuitry, depending on the language’s
made them preferable over their corresponding standard.
flow, state and logic diagrams. Other points utilized as a basis for comparison
Various HDLs with diverse properties and include: efficiency of methods and language
objectives have been developed over the years, constructs, signal behavior description, scheduling
giving designers a vast selection in the appropriate semantics and ease of implementation.
modeling instrument. In this paper I will be comparing different
SystemC presents a new approach to the aspects between the Verilog [2] and SystemC [4]
concept of HDLs, as it combines hardware and HDLs, according to the measures mentioned
software descriptions at different levels of above. The code that will be used to base this
abstraction, by extending C++ with a new comparison implements an alarm clock controller.
library.
Related work after, to specify their sizes. SystemC accomplishes
this in one step, but at its own can declare a
Previous work comparing two or more HDLs is function separately from its body, as in C. This
limited to a few papers, usually regarding VHDL property of the language can also be viewed as an
and Verilog. This is mainly due to the fact that advantage, since a module can therefore call
SystemC is a latecomer to this field, but also several different processes. Verilog is only able to
because it is merely an extension of an already carry out a process if found within a module,
existing language. which signifies having to write a module for every
Douglas Smith wrote a tutorial [5] in which he process that needs to be called by external
compares VHDL and Verilog. Smith also describes modules. The absence of a high level construct
the range of modeling capacity possessed by the that replicates structure can often lead into
two languages, exposing VHDL’s lower modeling writing code that may seem repetitive, or difficult
limit: gate level. Interestingly enough, Verilog is to optimize.
one of the few HDLs capable of modeling down to When modeling a process in Verilog, common
transistor level. practice is to have an always construct around the
Few additional papers dealing with two or body of the function to be evaluated. In SystemC,
more HDLs exist, but are generally not meant to the functions are written as members of the
bring forth comparison issues, rather to present module class being designed, allowing the designer
co-design techniques such as Agliada [8]. to more easily integrate additional functionality in
In his paper on co-simulation of VHDL and the same design.
SystemC, Agliada introduces a method to Timing mechanisms vary extensively between
homogenize the system descriptions in order to Verilog and SystemC. The later has a built-in
simulate them together. This approach calls for a clocking mechanism, where such a device and its
VHDL to SystemC translator. In describing such a output signal wave can be described using the
tool, it is unavoidable to compare the two sc_clock() construct. Instead, Verilog uses a more
languages, even if not in detail. general way to create a clock: by defining it as a
module. Although this technique may appear
inefficient, it is actually more natural for a
Fundamental differences in constructs beginning designer, since no new constructs need
to be learned. Figure 2 below, illustrates this
Both Verilog and SystemC utilize modules as point.
design entities While Verilog has the module
keyword build in, SystemC needs to call a Verilog SystemC
construct named sc_module() to declare the body module m555 (clock); sc_clock m555("m555",
output clock; 20, 0.5, 5, true);
of the device at task. The difference in module
reg clock;
declaration syntax can be seen below in figure 1. initial
#5 clock = 1;
always
#50 clock = ~clock;
Verilog SystemC
endmodule
module runner(port names); SC_MODULE(Runner) { Figure 2. Clock declaration syntax.
//port sizes and direction //ports sizes and direction
//body //body
SystemC allows for three types of processes to
endmodule };
//member functions be utilized in the description of a model: methods,
threads and synchronized threads.
Figure 1. Component declaration syntax. According to the SystemC User’s Guide [4],
methods execute when changes occur in signals
Although Verilog may appear slightly more found in their sensitivity list. Upon termination, a
concise at first, it should be pointed out that the method returns control to the simulation kernel.
former requires ports to be listed once in the Threads behave similarly as methods, but they
module declaration line, and again immediately may also be suspended and reactivated at the
occurrence of a specified event. As Edwards [1] wire or tri Simple interconnecting wire
points out, hardware does not exhibit this wor or trior Wired outputs OR together
behavior, but such processes can be useful when wand or triand Wired outputs AND together
designing a test bench. tri0 Pulls down when tri-stated
Synchronous threads are a special case of tri1 Pulls up when tri-stated
threads, where triggering takes place at a specific supply0 Constant logic 0 (supply strength)
edge of a signal. The scheduling of all three supply1 Constant logic 1 (supply strength)
process types takes place at the bottom portion of trireg Stores last value when tri-stated
a SystemC model, by using the sc_ctor() macro (capacitance strength)
(SystemC constructor). In modeling an alarm
clock controller, such a constructor was called for In order to support modeling at different levels
the tick process of type method: of abstraction, from the functional to the register-
transfer level, as well as to support software,
sc_ctor ( Runner ) { SystemC provides programmers with a rich set of
sc_method ( tick ); signal types. This is different from languages like
sensitive_pos ( clock ); Verilog that only support bit-vectors as types.
} SystemC can implement both two-valued and
four-valued signal types, which add practicality to
where Runner is the name of the sc_module that a simulation.
owns the tick process. SystemC’s set of data types is enhanced to
Verilog per se does not differentiate among support multiple design domains and abstraction
processes, but allows flexibility to mimic the levels. The fixed precision types allow for fast
behavior found in the three scenarios described simulation. The arbitrary precision types can be
above. This is achieved by means of timing- used for computations with large numbers and to
oriented constructs such as: model large busses. Such types do not have a
limitation in size.
always @ ( condition ) In addition, this HDL provides a large
selection of overloaded operators, quantization and
Here the condition may be a signal or an overflow modes, as well as type conversion
event, in which case the identifier will be found mechanisms.
between parentheses. By this token, a function SystemC, extends C++ types by utilizing the
can also be edge-triggered: following signal definition syntax:

always @ ( posedge clock ) sc_signal < base_type > signal_name;

As strongly-typed languages, both Verilog and where base_type corresponds to one of C++’s
SystemC support signals as well as variables. They base types, such as integer, real, char, etc.
do differ in the built-in types available to the user. Likewise, ports are declared with the same syntax,
Verilog subdivides its data types into two main but utilize the identifiers sc_in<>, sc_out<> or
categories: registers and nets. A register type sc_inout<>.
involves storage and consists of the following As in C or C++, a SystemC description can
variants: include user-defined libraries containing functions
and data structures, to employ throughout a
reg unsigned variable of any bit size program. Verilog offers no such reusability
integer signed 32-bit variable feature, which in certain cases can be a drawback.
time unsigned 64-bit variable This is mainly due to the language’s interpretive
real double-precision floating point nature.

Nets (or wires) are of a larger variety:

Creating Descriptions
while there are Advance
events Time
Intuitively, Verilog can be very efficient in
structural designs, as the language possesses
moderately uncomplicated port-mapping and
module instantiation techniques. Switching
between layers of abstraction can be confusing at while there are
active events
times, since no dedicated constructs exist to aid
the modeling of larger designs. For this reason, the
structure of the description may appear the same
Inactive events? Activate them
throughout, regardless of component hierarchy.
SystemC introduces a bit more discipline in
large system modeling, by means of special
constructs. The ability of declaring a sc_main() non-blocking Activate them
routine that manages all of the other modules, assign events
clocking and data transfer schemes, is a major
advantage. This also facilitates the debugging
process of the very same descriptions. Activate
monitoring events
At the same time, its object-oriented
sequential origins make SystemC suitable for
behavioral designs. This introduces a new concept
in system design: the co-simulation of a piece of
hardware and its embedded software, using the
same language. It is now possible to implement, while there are
active events
for example, a controller and its driver all under
update the
the same roof. changed object;
Beginners will find Verilog easier to learn, due
to its generalized syntax. It also does not require Update event? schedule any
evaluation
the user to be familiar with other languages that events for
the HDL was based on, as is the case with sensitive
SystemC and C++. processes;

process
evaluation event;
Simulation semantics

Verilog and SystemC adopt different

Figure 3. Verilog Simulation Semantics.
simulation semantics. Verilog utilizes an event-
driven scheduler, which obeys the rules illustrated
by the graph in figure 3. Here we see nested loops
In comparison, SystemC’s cycle-based
executing in zero-time, which translates directly
simulation semantics are much simpler, as
into slower execution times during simulation,
overhead for different types of events is
than those of a cycle-based scheduler. Although
eliminated. Overall scheduling is more efficient, as
proven competent, such a set of semantics is at
timing information is done away with. The graph
times a drawback on performance, as several
adaptation from Mueller [7] illustrates below:
actions are expected to take place in each clock
cycle.
 The first of these two sources of non-
Clock Update Advance
Time deterministic behavior can be attributed to the
fact that an extensive amount of serialization
needs to be implemented by the simulator. This is
because the computer running the simulation is
often not as parallel as the hardware being
Update outputs
of newly
designed. The process of serializing concurrent
triggered sync. events generates a zero-time event queue, in which
processes such events are executed and evaluated. The order
of events inside such a queue may produce non-
deterministic output.
Execute all Execute all The second non-determinism source is the
async.
processes whose triggered possible interleaving of statements in different
inputs just sync.
processes behavioral always and initial blocks. This problem
changed
can be resolved by utilizing non-blocking
Figure 4. SystemC Simulation Semantics. procedural assignments, as stated above.
There are several things designers can do to
control non-determinism when programming in
Language Determinism
SystemC. First of all, the usage of channels such
as hardware signals (sc_signal, etc) and fifos,
The Verilog simulation model pictured above
always results in globally deterministic behavior.
guarantees a certain level of determinism over the
Secondly, there should be a general awareness
scheduling order.
among designers that the order of thread
Statements located within a begin-end block
execution within a particular simulation phase is
are guaranteed to execute sequentially in the order
unspecified and implementation-dependent.
listed inside such a begin-end block. Although a
However, when the same design is simulated
process may very well suspend itself at a certain
multiple times using the same stimulus and the
event and later regain control, its statements will
same version of the simulator, the thread ordering
still be executed in the order listed within the
between different runs will not vary.
begin-end block.
Additionally, designers can use command line
Non-blocking assignments will always be
options in the SystemC simulator to randomize
performed in the order that the statements were
the order of execution of threads within each
to be executed. For example:
simulation phase. This feature is useful for
detecting design flaws resulting from inadequate
initial begin
A <= 0; synchronization within design specifications.
A <= 1;
end
Conclusions
when the above block of Verilog code is executed
there will be two events added to the non-blocking Beginner designers may want to start with
assign update queue. The previous rule requires Verilog (even over VHDL) as it has a much
that they be entered and performed in the same smaller vocabulary, and does not require previous
order as listed in the source. Hence at the end of knowledge of another language. It also has a
time step 1, the variable A will be assigned 0, smaller amount of task-specific constructs to be
then 1. remembered.
Two basic sources of non-determinism surface While Verilog may be considered a weak
when modeling a design in Verilog: arbitrary object oriented language, SystemC is more suited
execution order in zero time, and arbitrary for such programming style, due to its roots.
interleaving of statements from other processes [2]. Designs that require heavy amounts of inter-
module communication may be alternatively
implemented to take advantage of this well
developed feature.
SystemC presents potential for shorter
simulation times, as its scheduling algorithm is
based on process type, avoiding timing overhead.
Shorter simulation times combined with a reduced
verification stage, make SystemC the favorable
out of the two, for very large designs. This is
especially true since Verilog lacks high level
constructs that facilitate such a design process.
In general Verilog is better suited for
structural designs, as it allows for better control of
modules within the same abstraction layers, even
though it lacks component hierarchy management.
SystemC’s nature is behavioral, which can make it
more difficult to synthesize than Verilog.
Verification process in larger designs is shorter
for SystemC, as no C/C++ simulation needs to be
implemented, hence decreasing the time to
market.

References

[1] S. Edwards. Languages for Embedded Systems.

Kluwer 2000.
[2] T. Kropf. The Verilog Hardware Description
Language. Kluwer 1996.
[3] G. DeMicheli. Synthesis and Optimization of
digital circuits. McGraw Hill 1994.
[4] Synopsys. SystemC version 2.0 User’s guide.
2000.
[5] D. Smith. VHDL & Verilog Compared &
Contrasted. Proc. 33rd Design Automation
Conf., 1996.
[6] System-on-Chip Specification and Modeling
Using C++. ICCAD 2000 Roundtable.
[7] W. Mueller. The Simulation Semantics of
SystemC. Proc. Design, Automation, and Test
in Europe (DATE 2001), Munich, Germany,
March 2001.
[8] N. Agliada, A. Fin. F. Fummi M. Martignano.
G. Pravadelli. On the Reuse of VHDL Modules
into SystemC Designs. Proc. IEEE Forum on
Design Languages (FDL), Lyon, France 2001.
[9] S. Swan. An Introduction to System Level
Modeling in SystemC 2.0. Cadence Design
Systems, Inc. May 2001.